Pushing and training integrated SRAM digital in-memory computing architecture

Abstract

The invention provides a pushing and training integrated SRAM (Static Random Access Memory) digital memory computing architecture. The pushing and training integrated SRAM digital memory computing architecture comprises a pushing and training integrated SRAM digital memory computing core module and a WL driving amp, the system comprises a forward-input driving module, a BL driving module, a forward-output module, a reverse-input exchange switch module, a reverse-input driving module, a reverse-output module and a control module. The push-training integrated SRAM digital memory calculation core module consists of a plurality of transposed SRAM digital memory calculation modules, and is used for carrying out matrix multiplication and addition calculation and supporting simultaneous forward calculation and reverse calculation; and the reverse-input exchange switch module is used for exchanging input data and realizing reverse input exchange operation of the corresponding transposed weight matrix. According to the invention, by multiplexing the push-training integrated SRAM digital storage and calculation kernel module, the balance problem of calculation density and storage density of forward and reverse propagation is solved, the efficient switching of training and reasoning is realized, the calculation energy efficiency and area efficiency are optimized, and the training and reasoning efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing technology, and more specifically, to a push-train integrated SRAM digital in-memory computing architecture. Background Technology

[0002] Low-Earth orbit (LEO) satellite constellations carry large-scale remote sensing payloads, placing extremely high demands on onboard computing platforms and requiring real-time processing of massive amounts of remote sensing image data. Currently, AI algorithms are widely used in onboard remote sensing image processing, significantly reducing the amount of data transmitted between satellite and ground through calculations such as target recognition, detection, and classification, thus significantly alleviating communication bandwidth pressure.

[0003] Traditional von Neumann architecture-based AI computing faces significant challenges: most energy consumption is spent on data transfer between storage and computing units, rather than the actual computation process. In-memory computing, by deeply integrating computation and storage, performs AI calculations directly within the storage unit, significantly reducing data transfer overhead. Furthermore, through parallel computing, it can complete multiple multiply-accumulate operations within a single clock cycle, meeting the millisecond-level processing requirements of remote sensing data. In-memory computing architectures efficiently support inference and computation tasks for mainstream AI models such as convolutional neural networks and Transformers, and are widely used.

[0004] Currently, onboard in-memory computing still faces the following challenges: The on-orbit fine-tuning capability of neural network algorithms is crucial. When facing tasks involving the identification, detection, and classification of new data features captured at different times, the computing platform needs to update some weights of the neural network in real-time on-orbit to ensure high accuracy. This requires the satellite to perform on-orbit inference and training. However, backpropagation requires significantly more storage space than forward propagation to store intermediate results and gradient information. The capacity requirements of the in-memory computing array during backpropagation can lead to some array elements being idle during forward propagation. Therefore, a push-train integrated SRAM digital in-memory computing architecture needs to be proposed to achieve on-orbit fine-tuning of the satellite with low hardware overhead.

[0005] Patent application CN118796465A discloses a method, apparatus, device, storage medium, and product for integrating training and inference, relating to the field of data processing technology. The method includes: allocating corresponding runtime and development resources to a target object based on the resource status in a resource pool and the resource requirements of the target object; selecting a matching initial model from a pre-created model library based on the data characteristic information of the target data; adjusting the initial model based on the model performance evaluation results and hardware resource usage to obtain a corresponding target model; and publishing the model service image corresponding to the target model to the runtime resources with one click for inference execution within the runtime resources. However, this patent application cannot completely solve the existing technical problems, nor can it meet the needs of this invention. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the purpose of this invention is to provide an integrated push-train SRAM digital in-memory computing architecture.

[0007] The push-train integrated SRAM digital in-memory computing architecture provided by the present invention includes: a push-train integrated SRAM digital in-memory computing core module, a WL driver & forward-input driver module, a BL driver module, a forward-output module, an inverted-input switching module, an inverted-input driver module, an inverted-output module, and a control module; The push-train integrated SRAM digital memory computing core module is composed of multiple transposed SRAM digital memory computing modules. The push-train integrated SRAM digital memory computing core module receives the forward input signal from the WL driver & forward-input driver module and the reverse input signal from the reverse-input driver module, and outputs the forward output signal to the forward-output module and the reverse output signal to the reverse-output module. At the same time, it outputs the bit line signal to the BL driver module. The output of the WL driver & forward-input driver module is connected to the input of the push-train integrated SRAM digital memory core module, providing word line drive signals and forward input signals to the memory core module; The input of the BL driver module is connected to the output of the push-train integrated SRAM digital memory core module, and receives bit line signals from the memory core module and performs bit line driving. The input of the forward-output module is connected to the output of the push-train integrated SRAM digital storage and computing core module, and receives the forward output signal from the storage and computing core module and outputs the forward multiplication and accumulation calculation result; The inverted-input switching module receives an inverted input signal as its input and outputs a switched inverted input signal to the inverted-input driving module. The input of the inverting-input driving module is connected to the output of the inverting-input switching module, and its output is connected to the input of the push-train integrated SRAM digital memory core module, providing an inverting input signal to the memory core module; The input of the reverse-output module is connected to the output of the integrated push-train SRAM digital storage and computing core module, receives the reverse output signal from the storage and computing core module and outputs the reverse multiplication and accumulation calculation result; The output of the control module is connected to the control terminals of the integrated push-train SRAM digital storage and computing core module, the WL driver & forward-input driver module, the BL driver module, the forward-output module, the reverse-input switching module, the reverse-input driver module, and the reverse-output module, providing control signals to each module to select the operating mode.

[0008] Preferably, the push-train integrated SRAM digital memory computing core module is composed of 128×128 transposed SRAM digital memory computing modules, and each transposed SRAM digital memory computing module includes a transposed SRAM digital memory computing array, a forward addition tree and a reverse addition tree; The transposed SRAM digital memory array receives forward input signals from the WL driver & forward-input driver module and reverse input signals from the reverse-input driver module, and outputs forward output signals to the forward adder tree and reverse output signals to the reverse adder tree. The input of the forward adder tree is connected to the forward output signal of the transposed SRAM digital memory array, and the output is connected to the forward-output module; The input of the inverted adder tree is connected to the inverted output signal of the transposed SRAM digital memory array, and the output is connected to the inverted-output module.

[0009] Preferably, the transposed SRAM digital storage array includes 6T SRAM storage cells and two NOR gate logic circuits; The 6T SRAM memory cell has a word line WL, a bit line BL, a data output Q, and an inverted data output QB; The first input of the first NOR gate receives the forward input inverted signal INB_F, the second input is connected to the inverted data output QB, and the output provides the forward output signal OUT_F; The first input of the second NOR gate receives the inverted input signal INB_B, the second input is connected to the inverted data output QB, and the output provides the inverted output signal OUT_B.

[0010] Preferably, both the forward addition tree and the backward addition tree are implemented using digital addition circuits; The forward addition tree performs addition operations on the forward output signals of the transposed SRAM digital memory array and outputs the forward multiplication and accumulation calculation results. ,in It is the weight matrix of the nth layer. It is the result of the forward multiplication and accumulation calculation of the nth level. It is the first The result of the forward multiplication and accumulation calculation of the layer; The inverse addition tree performs an addition operation on the inverse output signal of the transposed SRAM digital memory array, and outputs the inverse multiplication-accumulation calculation result. ,in It is the matrix transpose symbol. It is the result of the reverse multiplication and accumulation calculation of the (n+1)th level. It is the result of the reverse multiplication and accumulation calculation of the nth layer.

[0011] Preferably, the driving circuit of the WL drive & forward-input drive module is implemented by cascading inverters; The WL driver & forward-input driver module receives forward input data and control signals as input, and outputs word line drive signals and forward input drive signals to the push-train integrated SRAM digital storage and computing core module.

[0012] Preferably, the driving circuit of the BL driving module is implemented by cascading inverters; The input of the BL driver module is connected to the bit line output of the integrated push-train SRAM digital memory core module, and the output provides a bit line drive signal to perform bit line charging and discharging operations.

[0013] Preferably, the switching circuit of the inverting-input switching module includes six NAND gate logic elements; The first input of the inverted-input switching module receives a first inverted input signal IN0, the second input receives a second inverted input signal IN1, and the control input receives a switching control signal C. When the switching control signal C is logic 1, the first output... Output second inverted input signal Second output Output the first inverted input signal ; When the switching control signal C is logic 0, the first output... Output the first inverted input signal Second output Output second inverted input signal .

[0014] Preferably, the driving circuit of the inverting-input driving module is implemented by cascading inverters; The input of the inverting-input drive module is connected to the output of the inverting-input switching module, and the output provides an inverting input drive signal to the integrated SRAM digital storage and computing core module.

[0015] Preferably, the input of the inverse-output module is connected to the inverse output of the integrated training and derivation SRAM digital memory module, and the output provides the inverse multiplication and accumulation calculation result. The output signal is then shifted and spliced, and weight update calculations are performed. ,in This is the updated weight. These are the original weights. It's the learning rate. It is the gradient of the weights.

[0016] Preferably, the output control signal of the control module switches the operating mode of the architecture, including memory read / write mode, inference in-memory computing mode, and inference-training integrated in-memory computing mode; In memory read / write mode, the control module activates the WL driver & forward-input driver module and the BL driver module, and shuts down the forward-output module, the reverse-input driver module and the reverse-output module. In inference memory computing mode, the control module activates the WL driver & forward-input driver module and the forward-output module, and deactivates the BL driver module, the reverse-input driver module and the reverse-output module. In the integrated push-training in-memory computing mode, the control module activates the WL driver & forward-input driver module, the forward-output module, the reverse-input switching module, the reverse-input driver module, and the reverse-output module, and deactivates the BL driver module.

[0017] Compared with the prior art, the present invention has the following beneficial effects: This invention provides an integrated SRAM digital in-memory computing architecture that supports efficient switching between training and inference. By using an integrated SRAM digital in-memory computing core module, it optimizes computational energy efficiency and area efficiency, thereby improving the efficiency of training and inference. Attached Figure Description

[0018] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This invention provides a schematic diagram of an integrated push-train SRAM digital in-memory computing architecture. Figure 2 A schematic diagram of a transposed SRAM digital storage array circuit provided by the present invention; Figure 3 This is a schematic diagram of an inverting-input switching circuit provided by the present invention.

[0019] Reference numerals: SRAM digital memory core module 101, transposed SRAM digital memory calculation module 1011, WL driver & forward-input driver module 102, BL driver module 103, forward-output module 104, inverted-input switching module 105, inverted-input driver module 106, inverted-output module 107, control module 108. Detailed Implementation

[0020] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0021] Example like Figure 1 This is a schematic diagram of an integrated push-train SRAM digital memory computing architecture provided by the present invention, as shown below. Figure 1 As shown, the present invention provides a push-train integrated SRAM digital in-memory computing architecture, including a push-train integrated SRAM digital in-memory computing core module 101, a WL driver & forward-input driver module 102, a BL driver module 103, a forward-output module 104, a reverse-input switching switch module 105, a reverse-input driver module 106, a reverse-output module 107, and a control module 108.

[0022] The integrated training and push-simulation SRAM digital memory core module 101 consists of 128×128 transposed SRAM digital memory computation modules 1011. Its inputs come from the WL driver & forward-input driver module 102 and the reverse-input driver module 106, and its outputs go to the BL driver module 103, the forward-output module 104, and the reverse-output module 107. When the integrated training and push-simulation SRAM digital memory core module 101 operates in memory read / write mode, the WL driver and BL driver are enabled, allowing reading and writing of the 6T SRAM memory in the transposed SRAM digital memory array. When the integrated training and push-simulation SRAM digital memory core module 101 operates in memory computation mode, the WL driver & forward-input driver, reverse-input driver, forward-output, and reverse-output are enabled. Input feature values ​​enter through the forward-input driver, and after the forward addition tree completes the multiplication and accumulation calculation with the weights, they are output through the forward-output module 104. The calculation formula is... Meanwhile, the input error enters through the inverse-input driving module 106, and after the inverse addition tree completes the multiplication and accumulation calculation with the weights, it is output through the inverse-output module 107. The calculation formula is as follows: It supports simultaneous forward and backward computation; The transposed SRAM digital memory computation module 1011 includes a transposed SRAM digital memory computation array, a forward addition tree, and a backward addition tree. The transposed SRAM digital memory computation array is used to perform matrix multiplication operations, the forward addition tree is used to perform addition operations on the calculation results of forward propagation, and the backward addition tree is used to perform addition operations on the calculation results of backward propagation. Both the forward addition tree and the backward addition tree are implemented using digital addition circuits. Figure 2 A schematic diagram of a transposed SRAM digital storage array circuit provided by the present invention is shown below. Figure 2 As shown, this invention provides a transposed SRAM digital memory array circuit, including 6T SRAM and two NOR gates, totaling 14 transistors. The SRAM stores weight data, which can be read and written via WL and BL. During in-memory computation, the inverted signal of the forward input is... The inverted signal QB of the SRAM data is input into the NOR gate, and the output result is... Forward The result of Q, for example, when When =1 and Q=1, at this time =0, QB=0, =1; invert the input signal. The inverted signal QB of the SRAM data is input into the NOR gate, and the output result is... Forward The result of Q, for example, when When =1 and Q=1, at this time =0, QB=0, =1, enabling simultaneous forward and backward propagation. The WL drive & forward-input drive module 102 is used to activate the target SRAM row according to the input data, control the read and write operations of the push-train integrated SRAM digital storage and computing core module 101 in memory read and write mode, and transmit the input feature value to the push-train integrated SRAM digital storage and computing core module 101 in memory computing mode. The drive circuit is implemented by cascaded inverters. The BL drive module 103 is used to control the charging and discharging of the bit lines and read and write SRAM in memory read and write mode, and to turn off in memory computing mode. Its switch is controlled by the control module 108, and the drive circuit is implemented by cascaded inverters. The forward-output module 104 is used to output the forward propagation multiplication-accumulation calculation result in in-memory calculation mode. The system performs shifting and splicing processes, and is turned off during memory read / write mode. Its switch is controlled by the control module 108. The reverse-input exchange switch module 105 is used to exchange input errors, realize the reverse input exchange operation of the corresponding transposed weight matrix, and transmit the result to the reverse-input driver module 106. During the neural network training process, when calculating gradient information, it is necessary to perform matrix multiplication and addition calculations on the transpose of the input and weight matrix. At this time, the reverse-input exchange switch module 105 can be used to exchange input data to replace the transpose operation of weight parameters, so that the exchanged input data corresponds one-to-one with the transposed weight data. This module allows the weight parameters to be directly written into SRAM, and the forward input and the exchanged reverse input can be used for forward and backward propagation, improving data utilization. Figure 3 A schematic diagram of an inverting-input switching circuit provided by the present invention is shown below. Figure 3 As shown, this invention provides a reverse-input switching circuit for implementing matrix transpose. During backpropagation, calculating gradient information requires matrix multiplication and addition of the input and weight matrices under transpose. This can be achieved by changing the input order to ensure a one-to-one correspondence with the transposed weight data. The switching circuit for the two input signals is as follows: Figure 3 As shown, it consists of 24 transistors in total, consisting of 6 NAND gates: switching occurs when C=1. = , = No swap occurs when C=0. = , = Whether the input signals are exchanged is determined by the control module 108.

[0023] The inverting-input driving module 106 is used to transmit the inverting input error of the inverting-input switching module 105 to the push-train integrated SRAM digital storage and computing core module 101. The driving circuit is implemented by cascading inverters. The reverse-output module 107 is used to output the multiplication-accumulation calculation result of the reverse propagation. The data is then shifted and spliced, and finally the weights are updated and calculated. ; The control module 108 is used to control the forward propagation and backward propagation computing modes, including controlling the switching of the integrated SRAM digital in-memory computing architecture for memory read / write mode, inference in-memory computing mode, and integrated SRAM digital in-memory computing mode, as well as the switching of the corresponding circuit modules. The switching of modes is manually controlled.

[0024] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0025] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A push-train integrated SRAM digital in-memory computing architecture, comprising: The application relates to a push-training integrated SRAM digital memory and calculation core module. The push-training integrated SRAM digital memory and calculation core module is composed of a plurality of transpose SRAM digital memory and calculation modules, receives forward input signals from a WL driving and forward-input driving module and receives reverse input signals from a reverse-input driving module, and outputs forward output signals to a forward-output module and reverse output signals to a reverse-output module while outputting bit line signals to a BL driving module. The output of the WL driving and forward-input driving module is connected to the input of the push-training integrated SRAM digital memory and calculation core module, and the module provides word line driving signals and forward input signals to the memory and calculation core module. The input of the BL driving module is connected to the output of the push-training integrated SRAM digital memory and calculation core module, and the module receives bit line signals from the memory and calculation core module and drives the bit lines. The input of the forward-output module is connected to the output of the push-training integrated SRAM digital memory and calculation core module, and the module receives forward output signals from the memory and calculation core module and outputs forward multiply-accumulate calculation results. The input of the reverse-input switching switch module receives reverse input signals, and the module outputs switched reverse input signals to a reverse-input driving module. The input of the reverse-input driving module is connected to the output of the reverse-input switching switch module, and the output of the module is connected to the input of the push-training integrated SRAM digital memory and calculation core module, and the module provides reverse input signals to the memory and calculation core module. The input of the reverse-output module is connected to the output of the push-training integrated SRAM digital memory and calculation core module, and the module receives reverse output signals from the memory and calculation core module and outputs reverse multiply-accumulate calculation results. The output of the control module is connected to the control ends of the push-training integrated SRAM digital memory and calculation core module, the WL driving and forward-input driving module, the BL driving module, the forward-output module, the reverse-input switching switch module, the reverse-input driving module and the reverse-output module, and the module provides control signals to select operation modes. The push-training integrated SRAM digital memory and calculation core module is composed of 128*128 transpose SRAM digital memory and calculation modules, each of which comprises a transpose SRAM digital memory and calculation array, a forward addition tree and a reverse addition tree.

2. The push-train integrated SRAM digital in-memory computing architecture of claim 1, wherein, The input of the transpose SRAM digital memory and calculation array receives forward input signals from the WL driving and forward-input driving module and reverse input signals from the reverse-input driving module, and the output provides forward output signals to the forward addition tree and reverse output signals to the reverse addition tree. The input of the forward addition tree is connected to the forward output signals of the transpose SRAM digital memory and calculation array, and the output is connected to the forward-output module. ​ The input of the reverse addition tree is connected to the reverse output signal of the transpose SRAM digital storage and calculation array, and the output is connected to the reverse-output module.

3. The push-train integrated SRAM digital compute-in-memory architecture of claim 2, wherein, The transpose SRAM digital storage and calculation array comprises a 6T SRAM storage unit and two NOR gate logic circuits; The 6T SRAM storage unit has a word line WL, a bit line BL, a data output Q and an inverse data output QB; The first input of the first NOR gate receives a forward input inverse signal INB_F, the second input is connected to the inverse data output QB, and the output provides a forward output signal OUT_F; The first input of the second NOR gate receives a reverse input inverse signal INB_B, the second input is connected to the inverse data output QB, and the output provides a reverse output signal OUT_B.

4. The push-train integrated SRAM digital compute-in-memory architecture of claim 2, wherein, The forward addition tree and the reverse addition tree are both realized by digital addition circuits; The forward addition tree performs addition operation on the forward output signals of the transpose SRAM digital computation and storage array, and outputs a forward multiply-accumulate calculation result wherein is a weight matrix of the nth layer, is a forward multiply-accumulate calculation result of the nth layer, is a forward multiply-accumulate calculation result of the nth layer. The reverse addition tree performs addition operation on the reverse output signals of the transpose SRAM digital compute array, and outputs a reverse multiply-accumulate calculation result wherein is a matrix transpose symbol, is a reverse multiply-accumulate calculation result of an (n+1)th layer, is a reverse multiply-accumulate calculation result of an nth layer.

5. The push-train integrated SRAM digital compute-in-memory architecture of claim 1, wherein, The driving circuit of the WL driving & forward-input driving module is realized by cascading inverters; The input of the WL driving & forward-input driving module receives forward input data and control signals, and the output provides a word line driving signal and a forward input driving signal to the push-training integrated SRAM digital storage and calculation core module.

6. The push-train integrated SRAM digital compute-in-memory architecture of claim 1, wherein, The driving circuit of the BL driving module is realized by cascading inverters; The input of the BL driving module is connected to the bit line output of the push-training integrated SRAM digital storage and calculation core module, and the output provides a bit line driving signal to perform bit line charging and discharging operation.

7. The push-train integrated SRAM digital compute-in-memory architecture of claim 1, wherein, The switching circuit of the reverse-input exchange switch module comprises six NAND gate logic elements; The first input of the reverse-input exchange switch module receives a first reverse input signal IN0, the second input receives a second reverse input signal IN1, and the control input receives a switching control signal C; When the exchange control signal C is a logic 1, the first output outputs the second inverted input signal ; and the second output outputs the first inverted input signal. When the exchange control signal C is a logic 0, the first output outputs the first inverted input signal . When the exchange control signal C is a logic 1, the second output outputs the second inverted input signal .

8. The push-train integrated SRAM digital in-memory computing architecture of claim 1, wherein, The driving circuit of the reverse-input driving module is realized by cascading inverters; The input of the reverse-input driving module is connected to the output of the reverse-input exchange switch module, and the output provides a reverse input driving signal to the push-training integrated SRAM digital storage and calculation core module.

9. The push-train integrated SRAM digital compute-in-memory architecture of claim 4, wherein, The input of the reverse-output module is connected to the reverse output of the push-training integrated SRAM digital computing core module, and the output provides a reverse multiply-accumulate calculation result , and the output signal is shifted and spliced, and weight update calculation is performed , wherein is the updated weight, is the original weight, is the learning rate, is the gradient of the weight.

10. The push-train integrated SRAM digital in-memory computing architecture of claim 1, wherein, The output control signal of the control module switches the operation mode of the architecture, including a memory read-write mode, an inference in-memory calculation mode and a push-training integrated in-memory calculation mode; In the memory read-write mode, the control module activates the WL driving & forward-input driving module and the BL driving module, and closes the forward-output module, the reverse-input driving module and the reverse-output module; In the inference in-memory calculation mode, the control module activates the WL driving & forward-input driving module and the forward-output module, and closes the BL driving module, the reverse-input driving module and the reverse-output module; In the push-training integrated in-memory calculation mode, the control module activates the WL driving & forward-input driving module, the forward-output module, the reverse-input exchange switch module, the reverse-input driving module and the reverse-output module, and closes the BL driving module.

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