Control circuit, control method and resonant converter compatible with llc and dcx

Abstract

The application discloses a control circuit, a control method and a resonant converter compatible with LLC and DCX, the control circuit comprises: a reference voltage generation circuit, which is used for generating a corresponding pulse width modulation reference voltage according to a selected control mode; a modulation signal generation circuit, which is used for comparing a slope voltage with the pulse width modulation reference voltage to output a pulse width modulation signal, and comparing the slope voltage with a correlation voltage of the pulse width modulation reference voltage to output a pulse frequency modulation signal; the correlation voltage comprises at least one voltage used for generating the pulse width modulation reference voltage; and a logic control circuit, which is used for generating an upper tube driving signal and a lower tube driving signal according to the pulse width modulation signal and the pulse frequency modulation signal. The application can configure the resonant converter to work in the DCX mode or the LLC mode according to different scenes, and reduces the design complexity and cost of the resonant converter system.

Description

Technical Field

[0001] This invention relates to the field of current source control technology, and more specifically, to a control circuit, control method, and resonant converter compatible with LLC and DCX. Background Technology

[0002] The resonant converter can achieve zero-voltage turn-on (ZVS) of the two primary-side main MOS switches and zero-current turn-off (ZCS) of the secondary-side rectifier diodes, reducing the switching losses of the current source and improving the efficiency and power density of the power converter. Therefore, it can simultaneously meet the requirements of aerospace design for high-power output and high-efficiency transmission of the current source system.

[0003] Existing resonant converters have two operating modes: LLC mode and DCX mode. LLC mode typically uses Pulse Frequency Modulation (PFM) to achieve power regulation by increasing the switching frequency as the load lightens. However, due to the operating speed limitations of the circuit and system components, the switching frequency must be controlled within an upper limit to avoid the risk of the LLC control loop going out of control. Therefore, once the switching frequency reaches the upper limit, LLC mode usually uses Pulse Width Modulation (PWM) to further reduce the output power. Thus, in LLC mode, PFM or PWM control needs to be selected based on different load conditions. In DCX mode, to prevent output overshoot or burnout due to excessive output power at startup, a soft-start process is typically used, i.e., a gradual increase in output power from low to high. This soft-start process is achieved using Pulse Width Modulation (PWM).

[0004] Figure 1a This is a typical PWM control circuit, in which: comparator CMP1 outputs a PWM signal, its positive input is connected to the ramp voltage Ramp, its negative input is connected to the error signal EAO, and its output is connected to the R terminal of an RS flip-flop. A fixed-period narrow pulse signal min_ton_time is connected to the S terminal of the RS flip-flop. The RS flip-flop controls the upper transistor drive signal prout1 and the lower transistor drive signal prout2, where prout1 and prout2 are used to drive the upper power transistor M1 and the lower power transistor M2, respectively. Prout2 controls the current source to charge the capacitor, so that Ramp starts to rise. Figure 1b It shows Figure 1a Waveforms of each signal. Figure 1a and 1bIt can be seen that traditional PWM control requires a fixed-period narrow pulse signal min_ton_time for periodic setting, which cannot meet the requirements of LLC resonant converters to select between PFM and PWM control under different load conditions. Therefore, traditional PWM control cannot be used in LLC resonant converters. Furthermore, traditional PWM control cannot simultaneously control both LLC and DCX resonant converters, limiting application scenarios and increasing system cost and complexity. Summary of the Invention

[0005] In view of this, the main objective of this invention is to propose a control circuit, control method, and resonant converter compatible with LLC and DCX, in order to at least partially solve the technical problems in the above-mentioned circuit.

[0006] To address the aforementioned technical problems, the first aspect of this invention proposes a control circuit compatible with LLC and DCX, comprising:

[0007] A reference voltage generation circuit is used to generate a corresponding pulse width modulation reference voltage according to the selected control mode; the control modes include LLC mode and DCX mode.

[0008] A modulation signal generation circuit is configured to compare a ramp voltage with the pulse width modulation reference voltage to output a pulse width modulation signal; and to compare the ramp voltage with an associated voltage of the pulse width modulation reference voltage to output a pulse frequency modulation signal; the associated voltage includes at least one voltage used to generate the pulse width modulation reference voltage.

[0009] A logic control circuit is used to generate an upper transistor drive signal and a lower transistor drive signal based on the pulse width modulation signal and the pulse frequency modulation signal.

[0010] According to a preferred embodiment of the present invention, the pulse width modulation reference voltage generated by the reference voltage generation circuit in LLC mode is the difference between the frequency control voltage and the error voltage, and the pulse width modulation reference voltage generated in DCX mode is the difference between the second fixed voltage and the soft-start voltage, wherein: the second fixed voltage is equal to the frequency control voltage plus a preset offset voltage.

[0011] Correspondingly, the pulse frequency modulation comparator compares the ramp voltage with the larger of the frequency control voltage and the error voltage in LLC mode and outputs a pulse frequency modulation signal; in DCX mode, it compares the ramp voltage with the frequency control voltage and outputs a pulse frequency modulation signal.

[0012] According to a preferred embodiment of the present invention, the reference voltage generation circuit includes: a first voltage terminal and a second voltage terminal. The first voltage terminal is connected to a first operational amplifier to feed back the voltage signal of the first voltage terminal to a first reference point. The second voltage terminal is connected to a second operational amplifier to feed back the voltage signal of the second voltage terminal to a second reference point. The first reference point is connected to the output terminal through a first resistor and a current mirror, and the second reference point is connected to the output terminal through a second resistor. Specifically, the first voltage terminal is connected to the error voltage output terminal in LLC mode and to the soft-start voltage output terminal in DCX mode. The second voltage terminal is connected to the frequency control voltage output terminal in LLC mode and to the frequency control voltage output terminal via a preset offset voltage in DCX mode.

[0013] According to a preferred embodiment of the present invention, the modulation signal generation circuit includes: a ramp signal generator, a pulse width modulation comparator, and a pulse frequency modulation comparator.

[0014] The ramp signal generator is used to generate periodic ramp voltage signals.

[0015] The output of the ramp signal generator is connected to the negative inputs of the pulse width modulation comparator and the pulse frequency modulation comparator, respectively. The output of the reference voltage generation circuit is connected to the positive input of the pulse width modulation comparator. The first positive input of the pulse frequency modulation comparator is connected to the frequency control voltage output. The second positive input of the pulse frequency modulation comparator is connected to the error voltage output in LLC mode and to the power supply in DCX mode.

[0016] According to a preferred embodiment of the present invention, the ramp signal generator includes: a current source, one end of which is connected to a power supply, and the other end of which is connected to a bias voltage and then grounded via a charging and discharging circuit. The charging and discharging circuit includes: a charging and discharging capacitor, and a discharge control signal output terminal connected in parallel with the charging and discharging capacitor.

[0017] According to a preferred embodiment of the present invention, the logic control circuit is configured to generate an upper MOSFET drive signal based on the pulse width modulation signal and the pulse frequency modulation signal and record the on-time of the upper MOSFET drive signal, generate a lower MOSFET drive signal based on the pulse width modulation signal and the pulse frequency modulation signal, and control the on-time of the lower MOSFET drive signal to be the same as the on-time of the lower MOSFET drive signal, wherein: the on-time refers to the duration during which the upper or lower MOSFET drive signal is at a high level.

[0018] To address the aforementioned technical problems, a second aspect of the present invention provides a resonant converter, including the control circuit compatible with LLC and DCX as described in any one of the preceding claims.

[0019] To address the aforementioned technical problems, a fourth aspect of the present invention provides a control method compatible with LLC and DCX, comprising:

[0020] A corresponding pulse width modulation reference voltage is generated based on the selected control mode; the control modes include LLC mode and DCX mode.

[0021] The ramp voltage is compared with the pulse width modulation reference voltage to output a pulse width modulation signal; the ramp voltage is compared with the associated voltage of the pulse width modulation reference voltage to output a pulse frequency modulation signal; the associated voltage includes at least one voltage used to generate the pulse width modulation reference voltage.

[0022] The upper transistor drive signal and the lower transistor drive signal are generated based on the pulse width modulation signal and the pulse frequency modulation signal.

[0023] According to a preferred embodiment of the present invention, the pulse width modulation reference voltage generated in LLC mode is the difference between the frequency control voltage and the error voltage, and the pulse width modulation reference voltage generated in DCX mode is the difference between the second fixed voltage and the soft-start voltage, wherein: the second fixed voltage is equal to the frequency control voltage plus a preset offset voltage.

[0024] Correspondingly, in LLC mode, the ramp voltage is compared with the larger of the frequency control voltage and the error voltage, and a pulse frequency modulation signal is output; in DCX mode, the ramp voltage is compared with the frequency control voltage, and a pulse frequency modulation signal is output.

[0025] In summary, the reference voltage generation circuit of this invention can generate a corresponding pulse width modulation (PWM) reference voltage according to the selected LLC or DCX mode; compare the ramp voltage with the PWM reference voltage to output a PWM signal; compare the ramp voltage with a associated voltage of the PWM reference voltage to output a pulse frequency modulation (PWM) signal; the associated voltage includes at least one voltage used to generate the PWM reference voltage; finally, a synchronous logic control circuit generates upper and lower transistor drive signals according to the PWM signal and the PWM signal to achieve switching control of the upper and lower transistors. In this invention, since both the output PWM signal and the PWM signal are controlled by the PWM reference voltage, and the PWM reference voltage is related to the selected LLC or DCX mode, control signals can be generated under either LLC or DCX mode depending on the selected mode, making it compatible with the control of both LLC and DCX resonant converters. Meanwhile, in LLC mode, since the ramp voltage is compared both with the pulse width modulation (PWM) reference voltage to output a PWM signal and with the associated voltage of the PWM reference voltage to output a pulse frequency modulation (PWM) signal, the switching between PWM signal control and pulse frequency modulation signal control can be achieved as the ramp voltage value changes. This satisfies the requirement of the LLC resonant converter to select between PFM control and PWM control under different load conditions. Compared with the prior art, this invention has at least the following beneficial effects:

[0026] 1. Compatible with LLC and DCX modes: The upper and lower power transistors of LLC and DCX resonators can be controlled through a single circuit, which greatly expands the application scenarios of the chip and reduces the complexity and cost of system design.

[0027] 2. Smooth control: By automatically changing the PWM reference voltage, the system enables the selection from PFM control to PWM control in LLC mode, as well as the soft-start process of PWM control in DCX mode, resulting in excellent control performance.

[0028] 3. Eliminate bias magnetization: By accurately recording and copying the turn-on time of the upper and lower transistors through the synchronous logic module, the transformer bias magnetization problem caused by asymmetrical drive is fundamentally avoided, thereby improving system reliability and lifespan. Attached Figure Description

[0029] To make the technical problems solved by this invention, the technical means adopted, and the technical effects achieved clearer, specific embodiments of this invention will be described in detail below with reference to the accompanying drawings. However, it should be noted that the drawings described below are merely drawings of exemplary embodiments of this invention. Those skilled in the art can obtain drawings of other embodiments based on these drawings without any creative effort.

[0030] Figure 1aThis is a typical PWM control circuit diagram in the existing technology.

[0031] Figure 1b yes Figure 1a Waveforms of each signal.

[0032] Figure 2 This is a control circuit diagram compatible with LLC and DCX provided by an embodiment of the present invention.

[0033] Figure 3a This is a circuit diagram of the ramp signal generator provided in an embodiment of the present invention.

[0034] Figure 3b This is an embodiment of the invention during the soft-start phase in DCX mode. Figure 3a The provided waveform diagram shows the operation of the ramp signal generator.

[0035] Figure 4a yes Figure 2 The provided control circuit, compatible with LLC and DCX, displays the operating waveforms in LLC mode.

[0036] Figure 4b yes Figure 2 The provided control circuit, compatible with LLC and DCX, displays the operating waveforms in DCX mode.

[0037] Figure 5 This is a flowchart illustrating a control method compatible with LLC and DCX provided in an embodiment of the present invention. Detailed Implementation

[0038] Subject to the inventive concept, the structures, performance, effects or other features described in a particular embodiment may be combined in any suitable manner with one or more other embodiments.

[0039] In the description of specific embodiments, detailed descriptions of structures, performance, effects, or other features are provided to enable those skilled in the art to fully understand the embodiments. However, it is not excluded that those skilled in the art can implement the present invention under certain circumstances with technical solutions that do not contain the above-described structures, performance, effects, or other features. The figures in the accompanying drawings are merely illustrative examples and do not imply that the solutions of the present invention must include all the contents, operations, and steps shown in the figures, nor do they imply that they must be performed in the order shown in the figures.

[0040] Before describing the technical solution of this invention, the technical terms involved in this invention will be explained first:

[0041] LLC: In an LLC resonant converter, LLC is short for a resonant circuit consisting of two inductors and one capacitor. These three components are the resonant inductor (Lr), the magnetizing inductor (Lm), and the resonant capacitor (Cr).

[0042] DCX: The DCX resonant converter is a resonant circuit consisting of two inductors and one capacitor. Its control method is open-loop control, with a fixed switching frequency achieving a fixed gain for both the input and output voltages; the output voltage varies with the input voltage.

[0043] PWM: Pulse Width Modulation, the output voltage changes with the duty cycle.

[0044] PFM: Pulse Frequency Modulation, the output voltage changes with the output frequency.

[0045] Magnetic bias: Transformer magnetic bias refers to the phenomenon where the magnetic flux in the transformer core deviates from the symmetrical sine waveform, resulting in a unidirectional magnetic flux component.

[0046] refer to Figure 2 , Figure 2 This is a circuit diagram of a control circuit compatible with LLC and DCX provided in an embodiment of the present invention, such as... Figure 2 As shown, the control circuit includes:

[0047] A reference voltage generation circuit is used to generate a corresponding pulse width modulation reference voltage according to the selected control mode; the control modes include LLC mode and DCX mode.

[0048] A modulation signal generation circuit is configured to compare a ramp voltage with the pulse width modulation reference voltage to output a pulse width modulation signal; and to compare the ramp voltage with an associated voltage of the pulse width modulation reference voltage to output a pulse frequency modulation signal; the associated voltage includes at least one voltage used to generate the pulse width modulation reference voltage.

[0049] A synchronous logic control circuit is used to generate an upper transistor drive signal and a lower transistor drive signal based on the pulse width modulation signal and the pulse frequency modulation signal.

[0050] In this embodiment, the pulse width modulation reference voltage generated in LLC mode is different from that generated in DCX mode. Therefore, the pulse width modulation signal and pulse frequency modulation signal output in LLC mode and DCX mode are different, which can generate the upper MOSFET drive signal and the lower MOSFET drive signal in the two modes.

[0051] In one possible implementation, the pulse width modulation reference voltage generated by the reference voltage generation circuit in LLC mode is the difference between the frequency control voltage and the error voltage, and the pulse width modulation reference voltage generated in DCX mode is the difference between the second fixed voltage and the soft-start voltage, wherein: the second fixed voltage is equal to the frequency control voltage plus a preset offset voltage; correspondingly, the pulse frequency modulation comparator compares the ramp voltage with the larger of the frequency control voltage and the error voltage in LLC mode and outputs a pulse frequency modulation signal; in DCX mode, it compares the ramp voltage with the frequency control voltage and outputs a pulse frequency modulation signal.

[0052] refer to Figure 2 The reference voltage generation circuit may include: a first voltage terminal Q1 and a second voltage terminal Q2. The first voltage terminal Q1 is connected to a first operational amplifier OP1 to feed back the voltage signal of the first voltage terminal Q1 to a first reference point A. The second voltage terminal Q2 is connected to a second operational amplifier OP2 to feed back the voltage signal of the second voltage terminal Q2 to a second reference point B. The first reference point A is connected to the output terminal Vramp_pwm through a first resistor R1 and a current mirror. The second reference point B is connected to the output terminal Vramp_pwm through a second resistor R2. In LLC mode, the first voltage terminal Q1 is connected to the error voltage output terminal EAO, and in DCX mode, it is connected to the soft-start voltage output terminal SS. In LLC mode, the second voltage terminal Q2 is connected to the frequency control voltage output terminal Freq_high_clamp, and in DCX mode, it is connected to the frequency control voltage output terminal Freq_high_clamp through a preset offset voltage S1. For example, switch T1 can be set between the first voltage terminal Q1 and the error voltage output terminal EAO; switch T2 can be set between the first voltage terminal Q1 and the soft-start voltage output terminal SS; switch T3 can be set between the second voltage terminal Q2 and the frequency control voltage output terminal Freq_high_clamp; and switch T4 can be set between the second voltage terminal Q2 and the preset offset voltage S1. The opening and closing of these switches are controlled according to the selected mode. For example, in LLC mode, switches T1 and T3 are closed, and switches T2 and T4 are open; in DCX mode, switches T1 and T3 are open, and switches T2 and T4 are closed. The current mirror is preferably a 1:1 PMOS current mirror and an NMOS current mirror, and the preset offset voltage S1 is 0.2V.

[0053] The modulation signal generation circuit includes: a ramp signal generator, a pulse width modulation comparator, and a pulse frequency modulation comparator; wherein:

[0054] like Figure 2The output terminal Ramp of the ramp signal generator is connected to the negative input terminals of the pulse width modulation (PWM) comparator CMP2 and the pulse frequency modulation (PFM) comparator CMP1, respectively. The output terminal Vramp_pwm of the reference voltage generation circuit is connected to the positive input terminal of the PWM comparator CMP2. The first positive input terminal of the PFM comparator CMP1 is connected to the frequency control voltage output terminal Freq_high_clamp. The second positive input terminal of the PFM comparator CMP1 is connected to the error voltage output terminal EAO in LLC mode and to the power supply Vdd in DCX mode. For example, a switch T5 can be set between the second positive input terminal of the PFM comparator CMP1 and the error voltage output terminal EAO, and a switch T6 can be set between the second positive input terminal of the PFM comparator CMP1 and the power supply Vdd. The opening and closing of these switches are controlled according to the selected mode. For example, in LLC mode, switch T5 is controlled to be closed and switch T6 to be open; in DCX mode, switch T5 is controlled to be open and switch T6 to be closed.

[0055] The ramp signal generator is used to generate periodic ramp voltage signals.

[0056] In one possible implementation, such as Figure 3a As shown, the ramp signal generator includes: a current source Rs, one end of which is connected to a power supply Vdd, and the other end is connected to a bias voltage (Vdd) via a charging and discharging circuit. Figure 3a The lowest ramp voltage (Ramp_low_damp) is grounded, and a ramp signal is output at the output terminal SS between the current source and the discharge circuit. The charge / discharge circuit includes a charge / discharge capacitor C1 and a discharge control signal output terminal EN connected in parallel with the charge / discharge capacitor C1.

[0057] In this embodiment, the logic control circuit generates an upper-side drive signal `prout1` to control the upper power transistor switch M1 and a lower-side drive signal `prout2` to control the lower power transistor switch M2, based on the pulse width modulation signal and the pulse frequency modulation signal. For example, when the upper-side drive signal `prout1` is high, the upper power transistor M1 is turned on; when `prout1` is low, the upper power transistor M1 is turned off. Similarly, when the lower-side drive signal `prout2` is high, the lower power transistor M2 is turned on; when `prout2` is low, the lower power transistor M2 is turned off. Figure 2As shown, the logic control circuit L is used to generate an upper-side drive signal `prout1` based on the pulse width modulation signal and the pulse frequency modulation signal, and record the on-time T of the upper-side drive signal `prout1`. It also generates a lower-side drive signal `prout2` based on the pulse width modulation signal and the pulse frequency modulation signal, and controls the on-time of the lower-side drive signal `prout2` to be equal to the on-time T of the upper-side drive signal `prout1`. The on-time refers to the duration during which the upper or lower-side drive signal is at a high level (i.e., the duration for which the upper / lower power transistor is on), thereby ensuring that the on-times of the upper power transistor M1 and the lower power transistor M2 are equal. Optionally, the logic control circuit L can record the on-time T using a digital timer. Furthermore, the logic control circuit L can also immediately terminate the upper-side drive signal at the end of the pulse frequency modulation signal indication period, and simultaneously or subsequently turn on the lower-side drive signal. Optionally, the function of the logic control circuit L can be implemented using digital sequential logic circuits.

[0058] It is understood that in the control circuit compatible with LLC and DCX provided in the embodiments of the present invention, the specific values ​​of each resistor and bias voltage can be configured according to actual conditions. The voltage difference polarity of the input voltage signals at each input terminal of the comparator can be reversed compared to the above embodiments, and the output polarity of the comparator is also reversed compared to the above embodiments. Equivalent substitutions made based on this are all within the protection scope of the present invention.

[0059] The following is combined Figure 2 , Figure 3a , 3b and Figure 4a , 4b The present invention will be described in detail below.

[0060] refer to Figure 2 In the modulation signal generation circuit:

[0061] When LLC mode is selected, the paths of switches T1 and T3 are closed, and the paths of switches T2 and T4 are open. The voltage at the first reference point A is equal to the voltage EAO under the feedback loop of the first operational amplifier OP1. The current flowing through the first resistor R1 is I. R1 =V EAO / R1. After being mirrored by a 1:1 PMOS current mirror and an NMOS current mirror, the voltage difference V across R2 is obtained. R2 It is V EAO The second voltage at the second reference point B, under the influence of the feedback loop of operational amplifier OP2, is equal to the Freq_high_clamp voltage. Therefore: Vramp_pwm = V B -V R2 =V Freq_high_clamp -V EAO .

[0062] When DCX mode is selected, the paths of switches T2 and T4 are closed, while the paths of switches T1 and T3 are open. The voltage at the first reference point A, under the action of the feedback loop of the first operational amplifier OP1, is equal to the voltage V at the soft-start voltage output terminal SS. SS The voltage at the second reference point B, under the action of the feedback loop of the second operational amplifier OP2, is equal to V. Freq_high_clamp +0.2V, then: V ramp_pwm =V B -V R2 =V Freq_high_clamp +0.2VV SS .

[0063] In the modulation signal generation circuit, CMP1 is a PFM comparator used to determine the frequency of the resonant converter's output drive signal. CMP2 is a PWM comparator used to determine the duty cycle of the resonant converter's output drive signal. The ramp signal generator is used to generate a periodic ramp voltage signal; such as... Figure 2 The ramp signal generator relies on the power supply Vdd to periodically charge capacitor C1. The discharge control signal output from the discharge control terminal Ramp_rst of capacitor C1 is prout2. Therefore, the output voltage of the ramp signal generator is at its lowest voltage of V. Ramp_low_clamp ramp voltage V ramp .

[0064] The logic control circuit L1 is used to generate the upper transistor drive signal prout1 based on the pfm signal output by comparator CMP1 and the PWM signal output by comparator CPM2, and to record the on-time T of the upper transistor drive signal prout1. It also generates the lower transistor drive signal prout2 based on the pfm signal output by comparator CMP1 and the PWM signal output by comparator CPM2, and controls the on-time of the lower transistor drive signal prout2 to be equal to the on-time T of the upper transistor drive signal prout1, thereby achieving equal on-time of the upper power transistor M1 and the lower power transistor M2.

[0065] Figure 4a for Figure 2 Waveform diagram of the circuit operating in LLC mode. (Reference) Figure 2 and Figure 4a In LLC mode, the pulse width modulated reference voltage V generated by the reference voltage generation circuit... ramp_pwm Frequency control voltage V Freq_high_clamp With error voltage V EAO The difference is V ramp_pwm The associated voltage can be expressed as V. Freq_high_clamp Or V EAO Or V Freq_high_clamp and V EAO ; Figure 2 Chinese V ramp_pwmThe associated voltage is V Freq_high_clamp and V EAO Then the output of comparator CMP1 is V. Freq_high_clamp and V EAO The maximum value of V Ramp The comparison value (pulse frequency modulation signal pfm), the comparator CMP2 outputs V ramp_pwm and V ramp The comparison value (i.e., the pulse width modulation signal pwm) determines whether the output of prout1 is high or low.

[0066] During operation, when the output signal (prout2) of the discharge control terminal Ramp_rst is low, the Ramp signal starts to rise from its initial value, and the Ramp signal rises to V. Freq_high_clamp and V EAO When the value reaches its maximum, the CMP1 comparator output pfm changes from low to high. pfm is connected to the input of the logic control circuit L1, indicating the end of the power transistor M1's on-state. prout1 changes from high to low, and prout2 changes from low to high, thus turning on. Therefore, the output signal of Ramp_rst (prout2) is high, and Ramp changes low. The logic control circuit L1 records the aforementioned Ramp rise time T (i.e., the on-state time T of the power transistor M1). prout2 changes from low to high and begins timing. When the time equals T, if prout2 is high, it changes low; if it is low, it remains unchanged, and prout1 is allowed to go high. Subsequently, the Ramp_rst output signal changes from high to low, Ramp starts rising again, and the next switching cycle begins. Repeating this behavior determines the switching frequency of the resonant converter output. Since V... EAO Since the output voltage of the error amplifier is a variable voltage, the switching frequency of the resonant converter varies with V. EAO The minimum output voltage at the positive input terminal of the CMP1 comparator is V, which decreases and increases. Freq_high_clamp This determines the maximum value of the switching frequency of the resonant converter.

[0067] Because in LLC mode, V ramp_pwm = V Freq_high_clamp -V EAO When V EAO It's very high, and a V will appear. ramp_pwm The minimum voltage V less than Ramp Ramp_low_clamp At this time, the pwm output of the CMP2 comparator is constantly high, indicating that prout1 is allowed to output a high level. The corresponding operating mode is the 50% duty cycle PFM mode. During the time the ramp increases, prout1 remains high. V ramp_pwm With V EAO The value increases as the rate decreases, rising to a level greater than the minimum value V of the Ramp. Ramp_low_clamp Afterwards, V ramp_pwm >Vramp During the specified time, the CMP2 comparator output pwm is high, allowing prout1 to output a high level. ramp_pwm <V ramp During the specified time, the CMP2 comparator output pwm is low, disallowing prout1 to output a high level. That is, when the Ramp voltage rises and V... ramp_pwm <V ramp During the time period, prout1 is low, and when the Ramp voltage rises and V... ramp_pwm >V ramp During this time period, prout1 is high. At this time, it operates in PWM control mode. The switching frequency is fixed by V. Freq_high_clamp Decision. When V ramp_pwm Increase, i.e., V EAO Decrease, V ramp_pwm With V ramp The higher the intersection point, the later the enable time for probe1 to turn on, and the shorter the start duration of probe1. This allows adjustment of the duty cycle of the output drive signal probe1 within a single switching cycle. The enable time for probe2 is precisely replicated from the enable duration T of probe1 by the logic control circuit L1. When V... EAO Reduce to make V ramp_pwm When the Ramp voltage exceeds its maximum value, the CMP2 comparator output PWM remains constantly low, disallowing Prout1 to output a high level; that is, both Prout1 and Prout2 outputs are low. In this state, the circuit operates in skip-cycle mode. By adjusting the duty cycle of the power switch drive in this way, the output power of the resonant converter can be adjusted.

[0068] In DCX mode, after the resonant converter starts up, the output voltage needs to rise slowly from low to high (i.e., the soft-start phase), and the output power needs to increase slowly from low to high to avoid overshooting of the output voltage and damaging the load devices. For example, refer to... Figure 3a and 3b During the soft-start phase, the output power can be adjusted via... Figure 3a Medium current Source Rs When capacitor C1 is charged, the output voltage V is generated at the output terminal SS. SS It rises slowly and increases slowly. Figure 3b This illustrates the soft-start phase, with voltage V. SS As the discharge control signal output terminal EN changes.

[0069] Figure 4b for Figure 2 Waveform diagram of the circuit during the soft-start phase in DCX mode. (Reference) Figure 2 and Figure 4b In DCX mode, the pulse-width modulated reference voltage V generated by the reference voltage generation circuit... ramp_pwmFrequency control voltage V Freq_high_clamp Add a preset offset voltage of 0.2V and a soft-start voltage V SS The difference is V ramp_pwm The associated voltage can be V Freq_high_clamp Or a preset offset voltage of 0.2V, or V SS Or a combination of the above three voltages, such as: V Freq_high_clamp and a preset offset voltage of 0.2V, V Freq_high_clamp and a preset offset voltage of 0.2V and V SS And so on, which will not be listed here. Figure 2 Chinese V ramp_pwm The associated voltage is V Freq_high_clamp Then the output of comparator CMP1 is V. Freq_high_clamp With V ramp The comparison value (pulse frequency modulation signal pfm), the comparator CMP2 outputs V ramp_pwm and V ramp The comparison value (i.e., the pulse width modulation signal pwm).

[0070] During the soft start phase, refer to Figure 3a and 3b When containing Figure 2 When the chip in the circuit is turned off, the output voltage SS is V. SS V is 0 when the chip is turned on. SS It begins to rise slowly. Ramp starts to rise when the Ramp_rst output control signal (prout2) is low. prout1 is determined by the output pwm of the CMP2 comparator. When V ramp Rise to V Freq_high_clamp At this time, the CMP1 comparator output pfm changes from low to high. pfm is connected to the input of logic control circuit L1, indicating the end of the upper transistor's on / off state. When prout1 changes from high to low and prout2 changes from low to high, the Ramp_rst output control signal is high, and V... ramp The value decreases. Logic control circuit L1 records the aforementioned V. ramp The rise time is T1, starting when propose2 goes from low to high. When the time equals T1, if propose2 is high, it goes low; if propose2 is low, it remains unchanged, and propose1 is allowed to go high. Simultaneously, the Ramp_rst output control signal changes from high to low, V... ramp The switching cycle begins again. The operation of the DCX resonant converter, which determines the switching frequency, is similar to that in LLC mode. The difference is that in DCX mode, comparator CMP1 is not connected to V. EAO V EAO V does not participate in control Freq_high_clamp Because the voltage is fixed, the switching frequency of the resonant converter is fixed in DCX mode.

[0071] Because in DCX mode, V ramp_pwm =V Freq_high_clamp +0.2VV SS When the chip is off, V SS V is 0 ramp_pwm =V Freq_high_clamp +0.2V>V Freq_high_clamp , where: V Freq_high_clamp This represents the maximum value of the ramp voltage. Compared to LLC mode, V... Freq_high_clamp The purpose of increasing the maximum voltage by 0.2V is to ensure that, under different operating conditions and process angles, when V SS When =0, ensure V ramp_pwm > V Freq_high_clamp V ramp_pwm The voltage exceeds the maximum value V of the ramp voltage. Freq_high_clamp Afterwards, the CMP2 comparator output PWM is low, disallowing prout1 to output a high level; that is, both prout1 and prout2 outputs are low. With V... SS V continues to rise ramp_pwm It continues to decline and begins to align with V. ramp There is an intersection. V ramp_pwm >V ramp When the CMP2 comparator outputs pwm high, the prout1 output is high. ramp_pwm <V ramp At that time, the CMP2 comparator output pwm is low, disallowing the probe1 output to be high. That is, during the time the Ramp voltage rises, V... ramp_pwm <V ramp When prout1 is low, V ramp_pwm >V ramp When prout1 is high. As V... SS Continue to rise, V ramp_pwm Continue to decline, V ramp_pwm With V ramp The lower the intersection point, the earlier prout1 can be turned on, and the longer prout1 can be turned on, thus allowing adjustment of the duty cycle of the output drive prout1 within a single switching cycle. As V... SS Continue to rise, V ramp_pwm =V Freq_high_clamp +0.2VV SS Less than V Ramp_low_clampAt this time, the output PWM of the CMP2 comparator is constantly high, allowing probe1 to output a high level. Therefore, during the time the ramp increases, probe1 remains high. At this point, the PWM operation mode has exited, the chip's soft-start ends, and it operates in a normal fixed-frequency state with a 50% duty cycle. The turn-on duration of probe2 is precisely replicated by the logic control circuit L1. By adjusting the duty cycle of the DCX resonant converter drive signal in this way, a soft-start operating mode is achieved where the output power of the resonant converter increases slowly after the DCX resonant converter is enabled, i.e., the output voltage increases slowly.

[0072] Based on the above-described control circuit compatible with LLC and DCX, this embodiment of the invention also provides a resonant converter, including the control circuit compatible with LLC and DCX described in any one of the above-described embodiments.

[0073] Based on the aforementioned control circuit compatible with LLC and DCX, embodiments of the present invention also provide a control method compatible with LLC and DCX, such as... Figure 5 As shown, the method includes:

[0074] S1. Generate the corresponding pulse width modulation reference voltage according to the selected control mode; the control modes include LLC mode and DCX mode.

[0075] S2. Compare the ramp voltage with the pulse width modulation reference voltage and output a pulse width modulation signal; compare the ramp voltage with the associated voltage of the pulse width modulation reference voltage and output a pulse frequency modulation signal; the associated voltage includes at least one voltage used to generate the pulse width modulation reference voltage.

[0076] S3. Generate the upper transistor drive signal and the lower transistor drive signal based on the pulse width modulation signal and the pulse frequency modulation signal.

[0077] In one possible implementation, in step S1, the pulse width modulation reference voltage generated in LLC mode is the difference between the frequency control voltage and the error voltage, and the pulse width modulation reference voltage generated in DCX mode is the difference between the second fixed voltage and the soft-start voltage, wherein: the second fixed voltage is equal to the frequency control voltage plus a preset offset voltage.

[0078] Correspondingly, in step S2, in LLC mode, the ramp voltage is compared with the larger of the frequency control voltage and the error voltage, and a pulse frequency modulation signal is output; in DCX mode, the ramp voltage is compared with the frequency control voltage, and a pulse frequency modulation signal is output.

[0079] In summary, this invention allows the resonant converter to operate in DCX or LLC mode according to different scenarios, playing a key role in reducing the cost and complexity of resonant converter system design.

[0080] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the present invention is not inherently related to any specific computer, virtual device, or electronic device, and various general-purpose devices can also implement the present invention. The above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A control circuit compatible with LLC and DCX, characterized in that, include: The reference voltage generation circuit is used to generate a corresponding pulse width modulation reference voltage according to the selected control mode. The control modes include: LLC mode and DCX mode; the pulse width modulation reference voltage generated in LLC mode is the difference between the frequency control voltage and the error voltage, and the pulse width modulation reference voltage generated in DCX mode is the difference between the second fixed voltage and the soft-start voltage, wherein: the second fixed voltage is equal to the frequency control voltage plus a preset offset voltage. The modulation signal generation circuit is used to compare the ramp voltage with the pulse width modulation reference voltage and output a pulse width modulation signal; in LLC mode, it compares the ramp voltage with the larger of the frequency control voltage and the error voltage and outputs a pulse frequency modulation signal; in DCX mode, it compares the ramp voltage with the frequency control voltage and outputs a pulse frequency modulation signal. A logic control circuit is used to generate an upper transistor drive signal and a lower transistor drive signal based on the pulse width modulation signal and the pulse frequency modulation signal.

2. The control circuit compatible with LLC and DCX according to claim 1, characterized in that, The reference voltage generation circuit includes: a first voltage terminal and a second voltage terminal. The first voltage terminal is connected to a first operational amplifier to feed back the voltage signal of the first voltage terminal to a first reference point. The second voltage terminal is connected to a second operational amplifier to feed back the voltage signal of the second voltage terminal to a second reference point. The first reference point is connected to the output terminal through a first resistor and a current mirror. The second reference point is connected to the output terminal through a second resistor. Specifically, the first voltage terminal is connected to the error voltage output terminal in LLC mode and to the soft-start voltage output terminal in DCX mode. The second voltage terminal is connected to the frequency control voltage output terminal in LLC mode and to the frequency control voltage output terminal through a preset offset voltage in DCX mode.

3. The control circuit compatible with LLC and DCX according to claim 1, characterized in that, The modulation signal generation circuit includes: a ramp signal generator, a pulse width modulation comparator, and a pulse frequency modulation comparator; The ramp signal generator is used to generate periodic ramp voltage signals; The output of the ramp signal generator is connected to the negative inputs of the pulse width modulation comparator and the pulse frequency modulation comparator, respectively. The output of the reference voltage generation circuit is connected to the positive input of the pulse width modulation comparator. The first positive input of the pulse frequency modulation comparator is connected to the frequency control voltage output. The second positive input of the pulse frequency modulation comparator is connected to the error voltage output in LLC mode and to the power supply in DCX mode.

4. The control circuit compatible with LLC and DCX according to claim 3, characterized in that, The ramp signal generator includes a current source, one end of which is connected to a power supply, and the other end is connected to a bias voltage and then grounded via a charging and discharging circuit. The charging and discharging circuit includes a charging and discharging capacitor and a discharge control signal output terminal connected in parallel with the charging and discharging capacitor.

5. The control circuit compatible with LLC and DCX according to any one of claims 1 to 4, characterized in that, The logic control circuit is used to generate an upper MOSFET drive signal based on the pulse width modulation signal and the pulse frequency modulation signal and record the on-time of the upper MOSFET drive signal, generate a lower MOSFET drive signal based on the pulse width modulation signal and the pulse frequency modulation signal, and control the on-time of the lower MOSFET drive signal to be the same as the on-time of the lower MOSFET drive signal, wherein: the on-time refers to the duration during which the upper or lower MOSFET drive signal is at a high level.

6. A resonant converter, characterized in that, The control circuit includes any one of claims 1 to 4 that is compatible with LLC and DCX.

7. A control method compatible with LLC and DCX, characterized in that, include: Generate the corresponding pulse width modulation reference voltage according to the selected control mode; The control modes include: LLC mode and DCX mode; the pulse width modulation reference voltage generated in LLC mode is the difference between the frequency control voltage and the error voltage, and the pulse width modulation reference voltage generated in DCX mode is the difference between the second fixed voltage and the soft-start voltage, wherein: the second fixed voltage is equal to the frequency control voltage plus a preset offset voltage. The ramp voltage is compared with the pulse width modulation reference voltage, and a pulse width modulation signal is output; in LLC mode, the ramp voltage is compared with the larger of the frequency control voltage and the error voltage, and a pulse frequency modulation signal is output; in DCX mode, the ramp voltage is compared with the frequency control voltage, and a pulse frequency modulation signal is output. The upper transistor drive signal and the lower transistor drive signal are generated based on the pulse width modulation signal and the pulse frequency modulation signal.

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