Pulse width modulation method and system for minimizing switching loss

Abstract

The invention relates to the field of pulse width modulation of power electronic converters, in particular to a pulse width modulation method and system for minimizing switching loss, which are suitable for minimizing switching loss under any modulation ratio and power factor of a three-level neutral-point clamped inverter topology. The three-level space vector diagram is divided into 6 large sectors and corresponding 24 areas according to a nearest three-vector synthesis principle. All possible five-segment switch sequences in different clamping phases of each region are obtained according to a nearest three-vector synthesis principle, the obtained five-segment switch sequences are selected according to a certain rule and checked according to a corresponding rule, and zero-sequence component calculation is performed on the five-segment switch sequences in different clamping phases. And finally, selecting a zero-sequence component under the corresponding clamping phase according to the current maximum phase or secondary maximum phase. And meanwhile, modeling is carried out on the switching loss of the switching loss minimization DPWM modulation and the switching loss of the traditional DPWM1 modulation, and the effectiveness of the pulse width modulation method is verified through comparison.

Description

Technical Field

[0001] This invention relates to the field of pulse width modulation, specifically to a pulse width modulation method and system that minimizes switching losses. Background Technology

[0002] In medium-voltage, high-power applications, traditional two-level topologies place high demands on the voltage stress of switching devices and result in significant losses, making it difficult to meet power quality requirements. Therefore, multi-level topologies, such as three-level midpoint clamp inverter topologies, are widely used. Switching losses are a major component of inverter system losses, and minimizing these losses is crucial for improving inverter efficiency. Modulation strategies, as a vital part of inverter control, also significantly impact switching losses. Traditional three-level DPWM (Discontinuous Pulse Width Modulation) reduces the number of switching actions per switching cycle by one-third compared to three-level SVPWM (Space Vector Pulse Width Modulation) by clamping a specific phase, thus reducing switching losses. However, with traditional DPWM modulation, the clamping phase is fixed, preventing free selection of the desired clamping phase. This causes switching losses to vary with modulation depth and power factor, making it impossible to guarantee minimum switching losses across the entire modulation depth and power factor range. Summary of the Invention

[0003] To overcome the shortcomings of the prior art, the present invention provides a pulse width modulation method and system for minimizing switching losses, which is used in medium-voltage high-power applications to further improve the efficiency of three-level midpoint clamp inverter topologies.

[0004] According to one aspect of the present invention, a pulse width modulation method for minimizing switching losses is provided, comprising: S1. Based on the principle of nearest three-vector synthesis, the three-level space vector diagram is divided into 6 large sectors, each sector corresponding to 4 regions. Based on the principle of nearest three-vector synthesis, all possible five-segment switching sequences under different clamping phases in each region are obtained. S2, Select and check the obtained five-segment switch sequence according to the preset rules; S3, calculate the zero-sequence component of the five-segment switching sequence under different clamping phases; S4. Based on the phase with the largest or second largest current, select the zero-sequence component under the corresponding clamping phase to obtain the three-phase modulation wave with minimized switching losses. S5, Model the switching losses of the power devices of the three-phase modulation wave and the existing DPWM1 modulation wave, and compare them to verify the effectiveness of the pulse width modulation method.

[0005] As a more preferred embodiment of the present invention, S1 specifically includes: According to the three phases A, B, and C of the midpoint clamped three-level inverter topology, each phase voltage has three levels: P, O, and N. Through permutation and combination, a total of 27 basic composite voltage vectors are obtained, which are divided into 6 large vectors, 6 medium vectors, 12 small vectors, and 3 zero vectors, corresponding to 6 basic space vectors, 6 basic space vectors, 6 basic space vectors, and 1 basic space vector, respectively. Based on the six basic spatial vectors corresponding to the six major vectors, the three-level spatial vector diagram is divided into six major sectors, namely I, II, III, IV, V, and VI, every 60°. Based on different nearest three-vector synthesis methods, each large sector is divided into regions: the region where the nearest three-vector synthesis method is one zero vector and two small vectors is region 1; the region where the nearest three-vector synthesis method is two small vectors and one medium vector is region 2; the region where the nearest three-vector synthesis method is one small vector, one medium vector and one large vector is region 3 and region 4. On the three-level space vector diagram, they are region 3 and region 4 in counterclockwise order.

[0006] As a more preferred embodiment of the present invention, S1 specifically includes: (1) I1 region: The three closest vectors involved in vector synthesis are OOO, NNN, PPP of zero vector, ONN, POO of small vector, OON, PPO of small vector; When the clamping phase is phase A, the five-segment switching sequence that can be formed by the above three nearest vectors includes: OOO, OON, ONN, OON, OOO; ONN, OON, OOO, OON, ONN; PPP, PPO, POO, PPO, PPP; POO, PPO, PPP, PPO, POO; When the clamping phase is phase B, the five-segment switching sequence that can be formed by the above three nearest vectors includes: OON, OOO, POO, OOO, OON; POO, OOO, OON, OOO, POO; When the clamping phase is phase C, the five-segment switching sequence that can be formed by the above three nearest vectors includes: OOO, POO, PPO, POO, OOO; PPO, POO, OOO, POO, PPO; NNN, ONN, OON, ONN, NNN; OON, ONN, NNN, ONN, OON; (2) I2 region: The three closest vectors involved in vector synthesis are the small vector ONN, POO, the small vector OON, PPO, and the medium vector PON. When the clamping phase is phase A, the five-segment switching sequence that can be formed by the above three nearest vectors includes: PPO, POO, PON, POO, PPO; PON, POO, PPO, POO, PON; When the clamping phase is phase B, the five-segment switching sequence that can be formed by the above three nearest vectors includes: POO, PON, OON, PON, POO; OON, PON, POO, PON, OON; When the clamping phase is phase C, the five-segment switching sequence that can be formed by the above three nearest vectors includes: ONN, OON, PON, OON, ONN; PON, OON, ONN, OON, PON; (3) I3 region: The three closest vectors involved in vector synthesis are the small vector ONN, POO, the medium vector PON, and the large vector PNN. When the clamping phase is phase A, the five-segment switching sequence that can be formed by the above three nearest vectors includes: POO, PON, PNN, PON, POO; PNN, PON, POO, PON, PNN; When the clamping phase is phase B, there is no switch sequence that can clamp phase B among the five-segment switch sequences that can be formed by the three nearest vectors mentioned above. When the clamping phase is phase C, the five-segment switching sequence that can be formed by the above three nearest vectors includes: ONN, PNN, PON, PNN, ONN; PON, PNN, ONN, PNN, PON; (4) I4 region: The three closest vectors involved in vector synthesis are OON and PPO of the small vector, PON of the medium vector, and PPN of the large vector; When the clamping phase is phase A, the five-segment switching sequence that can be formed by the above three nearest vectors includes: PPO, PPN, PON, PPN, PPO; PON, PPN, PPO, PPN, PON; When the clamping phase is phase B, there is no switch sequence that can clamp phase B among the five-segment switch sequences that can be formed by the three nearest vectors mentioned above. When the clamping phase is phase C, the five-segment switching sequence that can be formed by the above three nearest vectors includes: OON, PON, PPN, PON, OON; PPN, PON, OON, PON, PPN; The same principle applies to the selection of five-segment switching sequences under different clamping phases in other large sector regions, for all the most recent three-vector synthesis methods.

[0007] As a more preferred embodiment of the present invention, S2 specifically includes: For all possible five-segment switching sequences under different clamping phases in each region, a preset rule is used to select the switching sequence. In addition to satisfying the nearest three-vector synthesis principle, the selection of the switching sequence must also meet the following rule: (1) The selection of the switching sequence within the six major sectors remains symmetrical; (2) Ensure that there is no switching between P and N levels when switching between different regions and different clamping phases; Finally, a five-segment switching sequence under different clamping phases in each region was determined.

[0008] As a more preferred embodiment of the present invention, the inspection in S2 specifically includes: The five-segment switching sequences under different clamping phases in each region are checked according to the above rule (2).

[0009] Within sector I, for the first switching sequence of 10 switching sequences under different clamping phases in 4 regions, phase A only includes O and P levels, phase B only includes O level, and phase C only includes O and N levels. There will be no switching between P and N levels in any of the three phases. The same applies when switching between different regions and different clamping phases in sectors II to VI. When switching between Area 1 of major sectors: When switching between regions I1 and II1, for the first switching sequence of the six switching sequences under different clamping phases in the two regions, phase A only includes O and P levels, phase B only includes O level, and phase C only includes O and N levels. There will be no switching between P and N levels in any of the three phases. The same applies when switching other large sector regions 1. When switching between Zone 3 and Zone 4 of major sectors: When switching between regions I4 and II3, for the first switching sequence of the four switching sequences under different clamping phases in the two regions, phase A only includes O and P levels, phase B only includes O and P levels, and phase C only includes N level. There will be no switching between P and N levels in any of the three phases. The same applies when switching between other large sector regions 3 and 4.

[0010] As a more preferred embodiment of the present invention, S3 specifically includes: For the five-segment switching sequence under different clamping phases in each region selected in S2, a carrier comparison-based method is adopted. The modulated wave is compared with the double triangular carrier. When the modulated wave is greater than the upper triangular carrier, the corresponding output level is P; when the modulated wave is less than the lower triangular carrier, the corresponding output level is N; when the modulated wave is between the upper and lower triangular carriers, the corresponding output level is O. When the modulated wave does not have a zero-sequence component superimposed, SPWM modulation is implemented. When different zero-sequence components are superimposed, different modulation methods are implemented. The zero-sequence components in different regions and clamping phases under the obtained switching sequence are determined by calculation.

[0011] As a more preferred embodiment of the present invention, S4 specifically includes: For the zero-sequence components under different clamping phases in each region obtained in step S3, the clamping phase is selected according to the different phases with the maximum current. Within regions 1 and 2, compare the magnitudes of the three-phase currents and select the phase with the largest three-phase current as the clamping phase. Within regions 3 and 4, the magnitudes of the three-phase currents are compared first. When the phase with the largest current can be clamped, the phase with the largest current among the three phases is selected as the clamping phase; when the phase with the largest current cannot be clamped, the phase with the second largest current among the three phases is selected as the clamping phase.

[0012] The present invention also provides a pulse width modulation system with minimized switching losses, comprising: The region division module divides the three-level space vector diagram into 6 large sectors according to the nearest three-vector synthesis principle. Each large sector corresponds to 4 regions. Based on the nearest three-vector synthesis principle, all possible five-segment switching sequences under different clamping phases in each region are obtained. Select the module, select and check the obtained five-segment switch sequence according to the preset rules; The zero-sequence component calculation module performs zero-sequence component calculation on the five-segment switching sequence under different clamping phases. The modulation output module selects the zero-sequence component under the corresponding clamping phase according to the phase with the largest or second largest current, and obtains a three-phase modulation wave with minimized switching losses. The comparison and verification module models the switching losses of the power devices of the three-phase modulation wave and the existing DPWM1 modulation wave, and compares them to verify the effectiveness of the pulse width modulation method.

[0013] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the pulse width modulation method for minimizing switching losses.

[0014] The present invention also provides a non-transitory computer read storage medium storing computer instructions that cause the computer to perform the steps of the pulse width modulation method for minimizing switching losses.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) In this invention, when a five-segment switch sequence is used, one phase switch will always not operate, which is called the clamping state. Compared with the seven-segment switch sequence, the number of switching operations in one switching cycle can be reduced by 1 / 3.

[0016] (2) Different regions and different clamping phases within each large sector are switched according to the first rule and the second rule to ensure that there is no switching between P and N levels.

[0017] (3) The zero-sequence component is calculated for the selected five-segment switching sequence, and the zero-sequence component is selected according to the phase with the largest current or the phase with the second largest current to obtain the three-phase modulation wave with minimized switching loss. It can be concluded that, compared with the traditional DPWM modulation, the pulse width modulation of the present invention reduces the switching loss under any power factor and modulation ratio.

[0018] (4) The switching losses of the traditional DPWM modulation method are modeled and analyzed using a three-level ANPC inverter topology as an example. The switching losses of the DPWM modulation method of the present invention, which selects the phase with the largest or second largest current as the clamping phase, are also modeled and analyzed using a three-level ANPC inverter topology as an example. Finally, a comparison chart of SLFs is obtained. The comparison chart shows that the switching losses are reduced when using the scheme of the present invention. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of an active midpoint clamping three-level inverter topology for a pulse width modulation method that minimizes switching losses, provided in an embodiment of the present invention;

[0021] Figure 2 A three-level space vector diagram illustrating a pulse width modulation method for minimizing switching losses provided in an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of the clamping phase of each region in a DPWM1 modulation space vector diagram for a pulse width modulation method that minimizes switching losses, provided in an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of the non-clamping region in a pulse width modulation method for minimizing switching losses provided in an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram comparing DPWM modulation and DPWM1 modulation SLF in a pulse width modulation method for minimizing switching losses provided in an embodiment of the present invention. Detailed Implementation

[0025] The terms “comprising” and “having”, and any variations thereof, in the specification, claims, and accompanying drawings of this invention are intended to cover a non-exclusive inclusion, such as a process, method, system, product, or apparatus that includes a series of steps or units, not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined to form new technical solutions. Such combinations are not bound by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0027] This invention provides a pulse width modulation method for minimizing switching losses, applicable to DPWM modulation strategies that minimize switching losses under arbitrary modulation ratios and power factors in three-level midpoint clamped inverter topologies. The specific implementation steps are as follows.

[0028] (1) Based on the three phases A, B, and C and the three levels P, O, and N of the midpoint clamped three-level inverter topology (NPC topology or ANPC topology), the three-level space vector diagram is obtained. Based on the principle of Nearest Three Vectors (NTV), the three-level space vector diagram is divided into 6 large sectors: I, II, III, IV, V, and VI. Each large sector is divided into 1, 2, 3, and 4 small regions.

[0029] (2) For each small region divided in step (1), the nearest three-vector synthesis principle is used to obtain all possible five-segment switching sequences under different clamping phases;

[0030] (3) Select all possible five-segment switching sequences under different clamping phases in each small region obtained in step (2) according to certain rules;

[0031] (4) The five-segment switch sequences selected under different clamping phases in each small area in step (3) are checked according to the corresponding rules;

[0032] (5) Calculate the zero-sequence component of the five-segment switching sequence obtained under different clamping phases in each small region in step (3);

[0033] (6) Select the zero-sequence component under different clamping phases in each small region obtained in step (5) according to the different phases with the largest or second largest current.

[0034] (7) For the traditional DPWM modulation method, taking the three-level ANPC inverter topology as an example, we perform modeling and analysis of switching losses;

[0035] (8) For the DPWM modulation method in step (6) where the phase with the largest or second largest current is selected as the clamping phase, take the three-level ANPC inverter topology as an example, perform modeling and analysis of switching losses, and compare it with the traditional DPWM modulation method.

[0036] Step (1) specifically includes: such as Figure 1 As shown, based on the active neutral-point clamped three-level inverter topology, each phase voltage of the three phases A, B, and C has three levels: P, O, and N. Through different permutations and combinations of the three phases, a total of 27 basic composite voltage vectors are obtained, including: 6 large vectors (PNN, PPN, NPN, NPP, NNP, PNP, etc.) corresponding to 6 basic space vectors; 6 medium vectors (PON, OPN, NPO, NOP, ONP, PNO, etc.) corresponding to 6 basic space vectors; 12 small vectors (ONN, POO, OON, PPO, NON, OPO, NOO, OPP, OOP, NNO, ONO, POP, etc.) corresponding to 6 basic space vectors; and 3 zero vectors (OOO, NNN, PPP, etc.) corresponding to 1 basic space vector.

[0037] like Figure 2 As shown, based on the six basic spatial vectors corresponding to the six large vectors, the three-level space vector diagram is divided into six large sectors (Ⅰ, Ⅱ, Ⅲ, Ⅳ, Ⅴ, Ⅵ) every 60°. Each large sector is further subdivided into smaller regions based on different nearest three-vector synthesis methods. The region where the nearest three-vector synthesis method is one zero vector and two small vectors is small region 1; the region where the nearest three-vector synthesis method is two small vectors and one medium vector is small region 2; and the regions where the nearest three-vector synthesis method is one small vector, one medium vector, and one large vector are small regions 3 and 4. On the three-level space vector diagram, these are small regions 3 and 4 in counter-clockwise order.

[0038] Step (2) specifically includes: taking sector I as an example, explaining the five-segment switching sequences under different clamping phases in different small regions under all the most recent three-vector synthesis methods. Among them, when using the five-segment switching sequence, there is always one phase switch that does not operate, which is called the clamping state. Compared with the seven-segment switching sequence, the number of switching operations in one switching cycle can be reduced by 1 / 3.

[0039] (1) I1 region. The three most recent vectors involved in vector synthesis are the zero vector (OOO, NNN, PPP), the small vector (ONN, POO), and the small vector (OON, PPO).

[0040] When the clamping phase is phase A, the five-segment switching sequence that can be formed by the above three nearest vectors includes: OOO, OON, ONN, OON, OOO; ONN, OON, OOO, OON, ONN; PPP, PPO, POO, PPO, PPP; POO, PPO, PPP, PPO, POO.

[0041] When the clamping phase is phase B, the five-segment switching sequence that can be formed by the above three nearest vectors includes: OON, OOO, POO, OOO, OON; POO, OOO, OON, OOO, POO.

[0042] When the clamping phase is phase C, the five-segment switching sequence that can be formed by the above three nearest vectors includes: OOO, POO, PPO, POO, OOO; PPO, POO, OOO, POO, PPO; NNN, ONN, OON, ONN, NNN; OON, ONN, NNN, ONN, OON.

[0043] (2) I2 region. The three closest vectors involved in vector synthesis are the small vector (ONN, POO), the small vector (OON, PPO), and the medium vector (PON).

[0044] When the clamping phase is phase A, the five-segment switching sequence that can be formed by the above three nearest vectors includes: PPO, POO, PON, POO, PPO; PON, POO, PPO, POO, PON.

[0045] When the clamping phase is phase B, the five-segment switching sequence that can be formed by the above three nearest vectors includes: POO, PON, OON, PON, POO; OON, PON, POO, PON, OON.

[0046] When the clamping phase is phase C, the five-segment switching sequence that can be formed by the above three nearest vectors includes: ONN, OON, PON, OON, ONN; PON, OON, ONN, OON, PON.

[0047] (3) I3 region. The three most recent vectors involved in vector synthesis are the small vector (ONN, POO), the medium vector (PON), and the large vector (PNN).

[0048] When the clamping phase is phase A, the five-segment switching sequence that can be formed by the above three nearest vectors includes: POO, PON, PNN, PON, POO; PNN, PON, POO, PON, PNN.

[0049] When the clamping phase is phase B, there is no switch sequence that can clamp phase B among the five-segment switch sequences that can be formed by the three nearest vectors mentioned above.

[0050] When the clamping phase is phase C, the five-segment switching sequence that can be formed by the above three nearest vectors includes: ONN, PNN, PON, PNN, ONN; PON, PNN, ONN, PNN, PON.

[0051] (4) I4 region. The three most recent vectors involved in vector synthesis are the small vector (OON, PPO), the medium vector (PON), and the large vector (PPN).

[0052] When the clamping phase is phase A, the five-segment switching sequence that can be formed by the above three nearest vectors includes: PPO, PPN, PON, PPN, PPO; PON, PPN, PPO, PPN, PON.

[0053] When the clamping phase is phase B, there is no switch sequence that can clamp phase B among the five-segment switch sequences that can be formed by the three nearest vectors mentioned above.

[0054] When the clamping phase is phase C, the five-segment switching sequence that can be formed by the above three nearest vectors includes: OON, PON, PPN, PON, OON; PPN, PON, OON, PON, PPN.

[0055] The analysis of the five-segment switching sequences under different clamping phases in the small regions of the II-VI large sectors is similar.

[0056] Step (3) specifically includes: selecting all possible five-segment switching sequences under different clamping phases in each small region according to certain rules. Under the premise that the principle of nearest three-vector synthesis has been satisfied, the selection of the switching sequence also needs to satisfy the following rules.

[0057] (1) The selection of the switching sequence within the six major sectors must be symmetrical in order to avoid affecting the midpoint potential balance.

[0058] (2) When switching between different regions and different clamping phases, it must be ensured that there is no switching between P and N levels.

[0059] The final five-segment switching sequence under different clamping phases in each region was determined as shown in Table 1.

[0060] Table 1. Five-stage switching sequences under different clamping phases in various regions.

[0061]

[0062]

[0063]

[0064]

[0065]

[0066]

[0067] Step (4) specifically includes: checking the five-segment switching sequences under different clamping phases in each region obtained in step (3) according to the corresponding principle. The corresponding rule mentioned in step (3) includes:

[0068] (1) The selection of the switching sequence within the six major sectors must be symmetrical in order to avoid affecting the midpoint potential balance.

[0069] (2) When switching between different regions and different clamping phases, it must be ensured that there is no switching between P and N levels.

[0070] The switch sequence has already met the first rule when it is selected, namely the rules (1) and (2) above. Next, the obtained switch sequence is checked according to the second rule.

[0071] (1) Explain the phase switching of different regions and different clamp positions within each large sector.

[0072] Within sector I, for the first switching sequence of 10 switching sequences under different clamping phases in four smaller regions, phase A includes O and P levels, phase B includes O level, and phase C includes O and N levels. Therefore, when switching between different regions and different clamping phases within sector I, there will be no switching between P and N levels.

[0073] In sector II, for the first switching sequence of 10 switching sequences under different clamping phases in the four smaller regions, phase A includes 0 level, phase B includes 0 and P levels, and phase C includes 0 and N levels. Therefore, when switching between different regions and different clamping phases within sector II, there will be no switching between P and N levels.

[0074] In sector III, for the first switching sequence of 10 switching sequences under different clamping phases in the four smaller regions, phase A includes O and N levels, phase B includes O and P levels, and phase C includes O level. Therefore, when switching between different regions and different clamping phases within sector III, there will be no switching between P and N levels.

[0075] In sector IV, for the first switching sequence of 10 switching sequences under different clamping phases in the four smaller regions, phase A includes O and N levels, phase B includes O level, and phase C includes O and P levels. Therefore, when switching between different regions and different clamping phases within sector IV, there will be no switching between P and N levels.

[0076] In sector V, for the first switching sequence of 10 switching sequences under different clamping phases in the four smaller regions, phase A includes 0 level, phase B includes 0 and N levels, and phase C includes 0 and P levels. Therefore, when switching between different regions and different clamping phases within sector V, there will be no switching between P and N levels.

[0077] In sector VI, for the first switching sequence of 10 switching sequences under different clamping phases in the four smaller regions, phase A includes O and P levels, phase B includes O and N levels, and phase C includes O level. Therefore, there will be no switching between P and N levels when switching between different regions and different clamping phases within sector VI.

[0078] (2) Explanation of the switching of small area 1 in major sectors.

[0079] When switching between regions I1 and II1, for the first switching sequence of the six switching sequences under different clamping phases in the two small regions, phase A includes O and P levels, phase B includes O level, and phase C includes O and N levels. Therefore, when switching between regions I1 and II1, there will be no switching between P and N levels.

[0080] When switching between regions II1 and III1, for the first switching sequence of the six switching sequences under different clamping phases in the two small regions, phase A includes the 0 level, phase B includes the 0 and P levels, and phase C includes the 0 and N levels. Therefore, when switching between regions II1 and III1, there will be no switching between the P and N levels.

[0081] When switching between regions III1 and IV1, for the first switching sequence of the six switching sequences under different clamping phases in the two small regions, phase A includes O and N levels, phase B includes O and P levels, and phase C includes O level. Therefore, when switching between regions III1 and IV1, there will be no switching between P and N levels.

[0082] When switching between regions IV1 and V1, for the first switching sequence of the six switching sequences under different clamping phases in the two small regions, phase A includes O and N levels, phase B includes O level, and phase C includes O and P levels. Therefore, when switching between regions IV1 and V1, there will be no switching between P and N levels.

[0083] When switching between regions V1 and VI1, for the first switching sequence of the six switching sequences under different clamping phases in the two small regions, phase A includes 0 level, phase B includes 0 and N levels, and phase C includes 0 and P levels. Therefore, when switching between regions V1 and VI1, there will be no switching between P and N levels.

[0084] When switching between regions VI1 and I1, for the first switching sequence of the six switching sequences under different clamping phases in the two small regions, phase A includes O and P levels, phase B includes O and N levels, and phase C includes O level. Therefore, when switching between regions VI1 and I1, there will be no switching between P and N levels.

[0085] (3) Explanation of the switching between sub-regions 3 and 4 of major sectors.

[0086] When switching between regions I4 and II3, for the first switching sequence of the four switching sequences under different clamping phases in the two small regions, phase A includes O and P levels, phase B includes O and P levels, and phase C includes N level. Therefore, when switching between regions I4 and II3, there will be no switching between P and N levels.

[0087] When switching between regions II4 and III3, for the first switching sequence of the four switching sequences under different clamping phases in the two small regions, phase A includes O and N levels, phase B includes P level, and phase C includes O and N levels. Therefore, when switching between regions II4 and III3, there will be no switching between P and N levels.

[0088] When switching between regions III4 and IV3, for the first switching sequence of the four switching sequences under different clamping phases in the two small regions, phase A includes N level, phase B includes O and P levels, and phase C includes O and P levels. Therefore, when switching between regions III4 and IV3, there will be no switching between P and N levels.

[0089] When switching between regions IV4 and V3, for the first switching sequence of the four switching sequences under different clamping phases in the two small regions, phase A includes 0 and N levels, phase B includes 0 and N levels, and phase C includes P level. Therefore, when switching between regions IV4 and V3, there will be no switching between P and N levels.

[0090] When switching between regions V4 and VI3, for the first switching sequence of the four switching sequences under different clamping phases in the two small regions, phase A includes 0 and P levels, phase B includes N level, and phase C includes 0 and P levels. Therefore, when switching between regions V4 and VI3, there will be no switching between P and N levels.

[0091] When switching between regions VI4 and I3, for the first switching sequence of the four switching sequences under different clamping phases in the two small regions, phase A includes P level, phase B includes O and N levels, and phase C includes O and N levels. Therefore, when switching between regions VI4 and I3, there will be no switching between P and N levels.

[0092] In summary, the switch sequence selected in step (3) will not switch between P and N levels when switching between different regions and different clamping phases, thus meeting the requirements of the second rule.

[0093] Step (5) specifically includes: For the five-segment switching sequence under different clamping phases in each selected small region, a carrier comparison-based method can be used to implement it. The modulating wave is compared with the double triangular carrier. When the modulating wave is greater than the upper triangular carrier, the corresponding output level is P; when the modulating wave is less than the lower triangular carrier, the corresponding output level is N; when the modulating wave is between the upper and lower triangular carriers, the corresponding output level is O. When the modulating wave does not have a zero-sequence component superimposed, SPWM modulation is implemented. When different zero-sequence components are superimposed, different modulation methods are implemented.

[0094] Taking the switching sequence of phase A clamping in region I1 as an example, its zero-sequence component is calculated.

[0095] The three vectors involved in vector synthesis are, in order, the zero vector (OOO), the small vector (OON), and the small vector (ONN), and are set sequentially according to the order of the switch sequence. , , Then at this time , , The expression in the α-β coordinate system is shown in equation (1), where This is the DC side voltage.

[0096] (1)

[0097] Let the three-phase voltages be respectively , , The reference voltage vector formed after the three-phase voltages are combined is ,but The expression in the α-β coordinate system is shown in equation (2).

[0098] (2)

[0099] Let vector , , The duration of action are respectively , , The switching cycle is Then, according to the principle of buoyancy balance, we can obtain equation (3).

[0100] (3)

[0101] Substituting equations (1) and (2) into equation (3) yields equation (4).

[0102] (4)

[0103] This yields the result. , , Vectors in variable form , , The duration of action.

[0104] set up This is the original modulated wave when using SPWM modulation. In order to be in The modulated wave after superimposing the zero-sequence component, For the superimposed zero-order components, This represents the amplitude of the triangular carrier wave.

[0105] The original modulated wave can be calculated and obtained as shown in equation (5).

[0106] (5)

[0107] Based on the corresponding five-segment switching sequence, the modulation wave after superimposing the zero-sequence component is calculated, and the result is shown in Equation (6).

[0108] (6)

[0109] Substituting the vector action time equation (4) into equation (6), we obtain equation (7).

[0110] (7)

[0111] By comparing equations (5) and (7), the zero-order component can be obtained. .

[0112] Similarly, the zero-sequence components under the clamping phase in other regions can be determined by calculation. The zero-sequence components under different clamping phases in each region are shown in Table 2.

[0113] Table 2 Zero-sequence components under different clamping phases in each region

[0114]

[0115]

[0116]

[0117] Step (6) specifically includes: selecting the clamping phase based on the different phases with the maximum current for the zero-sequence components under different clamping phases in each small region obtained in step (5).

[0118] Within small regions 1 and 2, since all three phases can be clamped, it is only necessary to compare the magnitudes of the three-phase currents and select the phase with the largest current as the clamping phase.

[0119] Within small regions 3 and 4, since a certain phase cannot be clamped, the magnitudes of the three-phase currents are compared first. When the phase with the largest current can be clamped, the phase with the largest current among the three phases is selected as the clamping phase; when the phase with the largest current cannot be clamped, the phase with the second largest current among the three phases is selected as the clamping phase.

[0120] Step (7) specifically includes: From the switching loss curve of a traditional power switching device, it is known that at a constant temperature, the switching loss of each pulse is approximately proportional to the current flowing through the device. Therefore, the switching loss of each pulse at any given time can be expressed as shown in equation (8), where... This represents the ratio of the switching loss of each pulse power switching device to the current flowing through it. Indicates peak current. This represents one power frequency cycle.

[0121] (8)

[0122] For SVPWM modulation, all three phases switch within one switching cycle. The ratio of the switching frequency to the power frequency is given by equation (9), and the switching loss is calculated as shown in equation (9).

[0123] (9)

[0124] because For a large value, the above formula can be approximated as shown in formula (10).

[0125] (10)

[0126] To compare the switching losses of various modulation strategies, the concept of average switching loss factor (SLF) is introduced. It is defined as the ratio of the average switching loss of a certain modulation strategy to be compared to that of the traditional SVPWM modulation strategy within one power frequency cycle. Its calculation expression can be shown in Equation (11).

[0127] (11)

[0128] Among them, P sw To account for switching losses, taking DPWM1 as an example, we model and analyze the switching losses of the traditional DPWM modulation strategy, assuming the DC voltage utilization rate is... The power factor angle is ,like Figure 3 As shown, A, B, and C represent the clamping phases of each interval, and yellow, green, and red represent the power factor angles, respectively. The interval where the peak currents of phases A, B, and C are the largest.

[0129] (1) When At times, such as Figure 3 As shown, the reference voltage vector passes through small regions 1 or 1, 2. Taking the A-phase current as an example, the clamping phase of DPWM1 modulation is analyzed. It can be seen that the clamping interval is the large sector II and V. The switching loss is calculated as shown in equation (12).

[0130] (12)

[0131] because For a large value, the above formula can be approximated as shown in formula (13).

[0132] (13)

[0133] (2) When At times, such as Figure 3 As shown, the reference voltage vector passes through small regions 2, 3, and 4. Taking the A-phase current as an example, the clamping phase of DPWM1 modulation is analyzed. It can be seen that the clamping interval is region VI6, I5, II3, II4, III6, IV5, V3, and V4. The switching loss is calculated as shown in equation (14).

[0134] (14)

[0135] in The angle between region 2 and the boundary of the large sector when switching between region 3 or region 4 is given by equation (15).

[0136] (15)

[0137] because For a large value, equation (14) can be used for approximate calculation, as shown in equation (16).

[0138] (16)

[0139] Step (8) specifically includes: for the DPWM modulation strategy that minimizes switching losses under any modulation ratio and power factor applicable to the midpoint clamped three-level inverter topology, taking the three-level ANPC inverter topology as an example, performing modeling and analysis of switching losses, such as... Figure 4 As shown, A, B, and C represent the corresponding phases in this interval that cannot be clamped, and yellow, green, and red represent the power factor angles, respectively. The interval where the current values ​​of phases A, B, and C are the largest.

[0140] when At times, such as Figure 4 As shown, the reference voltage vector passes through small region 1 or small regions 1 and 2, and all three phases have a switching sequence that can achieve clamping. The switching loss is calculated as shown in equation (17).

[0141] (17)

[0142] when At times, such as Figure 4 As shown, the reference voltage vector passes through regions 2, 3, and 4. When the reference voltage vector passes through region 2, all three phases have a switching sequence that can achieve clamping. When the reference voltage vector passes through regions 3 and 4, only two phases have a switching sequence that can achieve clamping. The analysis is based on the current of phase A.

[0143] (1) Within the maximum current range of phase A, phase A can be clamped, and its switching loss is calculated as shown in equation (18).

[0144] (18)

[0145] (2) There exists a region where the phase with the maximum current cannot be clamped, and , Related.

[0146] when The switching loss is calculated as shown in equation (19).

[0147] (19)

[0148] when The switching loss is calculated as shown in equation (20).

[0149] (20)

[0150] (3) There exists a region where the phase with the maximum current cannot be clamped, and , Related.

[0151] when and The switching loss is calculated as shown in equation (21).

[0152] (twenty one)

[0153] when and The switching loss is calculated as shown in equation (22).

[0154] (twenty two)

[0155] when and The switching loss is calculated as shown in equation (23).

[0156] (twenty three)

[0157] when and The switching loss is calculated as shown in equation (24).

[0158] (twenty four)

[0159] A comparison diagram of the SLF of DPWM1 modulation and the modulation method of the present invention embodiment is drawn from steps (7) and (8), as follows. Figure 5 As shown. Compared with traditional DPWM1 modulation, the DPWM modulation that minimizes switching losses under arbitrary modulation ratios and power factors reduces switching losses under arbitrary power factors and modulation ratios.

[0160] Based on the same inventive concept as any of the foregoing embodiments, this embodiment of the invention also provides a pulse width modulation system for minimizing switching losses. This pulse width modulation system is used to implement a pulse width modulation method for minimizing switching losses in any of the foregoing embodiments, specifically including:

[0161] The region division module obtains a three-level space vector diagram based on the three phases A, B, and C and the three levels P, O, and N of the midpoint clamped three-level inverter topology. According to the principle of nearest three-vector synthesis, the three-level space vector diagram is divided into six major sectors: I, II, III, IV, V, and VI. Each major sector is further divided into four regions: 1, 2, 3, and 4.

[0162] The synthesis module uses the nearest three-vector synthesis principle for each region to obtain a five-segment switching sequence under different clamping phases;

[0163] Select the module and select the five-segment switch sequence according to the first rule;

[0164] The inspection module checks the selected five-segment switch sequence according to the second rule;

[0165] The zero-sequence component calculation module calculates the zero-sequence component of the selected five-segment switch sequence.

[0166] The modulation output module selects the zero-sequence component based on whether the current is the largest or the second largest phase to obtain a three-phase modulation wave with minimized switching losses.

[0167] Based on the same inventive concept as any of the foregoing embodiments, this embodiment of the invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the aforementioned pulse width modulation method for minimizing switching losses.

[0168] Based on the same inventive concept as any of the foregoing embodiments, this embodiment of the invention also provides a non-transitory computer read storage medium that stores computer instructions that cause the computer to execute the steps of the aforementioned pulse width modulation method for minimizing switching losses.

[0169] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0170] (1) In this invention, when a five-segment switch sequence is used, one phase switch will always not operate, which is called the clamping state. Compared with the seven-segment switch sequence, the number of switching operations in one switching cycle can be reduced by 1 / 3.

[0171] (2) Different regions and different clamping phases within each large sector are switched according to the first rule and the second rule to ensure that there is no switching between P and N levels.

[0172] (3) The zero-sequence component is calculated for the selected five-segment switching sequence, and the zero-sequence component is selected according to the phase with the largest current or the phase with the second largest current to obtain the three-phase modulation wave with minimized switching loss. It can be concluded that, compared with the traditional DPWM1 modulation, the pulse width modulation of the present invention reduces the switching loss under any power factor and modulation ratio.

[0173] (4) The switching losses of the traditional DPWM modulation method are modeled and analyzed using a three-level ANPC inverter topology as an example. The switching losses of the DPWM modulation method of the present invention, which selects the phase with the largest or second largest current as the clamping phase, are also modeled and analyzed using a three-level ANPC inverter topology as an example. Finally, a comparison chart of SLFs is obtained. The comparison chart shows that the switching losses are reduced when using the scheme of the present invention.

[0174] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the technical solutions of the embodiments of the present invention.

Claims

1. A method of minimizing switching losses in pulse width modulation, characterized by, The method comprises the following steps: S1, according to the principle of the nearest three vector synthesis, the three-level space vector diagram is divided into six large sectors, each large sector corresponds to four regions, and according to the principle of the nearest three vector synthesis, all possible five-segment switching sequences under different clamping phases of each region are obtained; S2, the obtained five-segment switching sequences are selected and checked according to a preset rule; S3, the zero sequence components of the five-segment switching sequences under different clamping phases are calculated; S4, according to the maximum phase or the second maximum phase of the current, the zero sequence components under the corresponding clamping phase are selected, and a three-phase modulation wave with minimized switching loss is obtained; S5, the switching losses of the power devices of the three-phase modulation wave and the existing DPWM1 modulation wave are modeled, and the effectiveness of the pulse width modulation method is verified by comparison.

2. A method of minimizing switching losses in pulse width modulation as claimed in claim 1 wherein, The S1 specifically comprises: According to the A, B and C three-phase of the midpoint clamped three-level inverter topology, there are P, O and N three levels of phase voltage in each phase, and 27 basic synthesis voltage vectors are obtained through permutation and combination, which are divided into six large vectors, six medium vectors, twelve small vectors and one zero vector, which correspond to six basic space vectors, six basic space vectors, six basic space vectors and one basic space vector respectively; According to the six basic space vectors corresponding to the six large vectors, the three-level space vector diagram is divided into six large sectors at intervals of 60°, namely I, II, III, IV, V and VI; According to different nearest three vector synthesis modes, the regions of each large sector are divided: the region of the nearest three vector synthesis mode of one zero vector and two small vectors is region 1; the region of the nearest three vector synthesis mode of two small vectors and one medium vector is region 2; the region of the nearest three vector synthesis mode of one small vector, one medium vector and one large vector is region 3 and region 4, which are region 3 and region 4 in anticlockwise order on the three-level space vector diagram.

3. The method as claimed in claim 1, wherein the switching loss is minimized by using a pulse width modulation method. The S1 specifically comprises: (1) I1 region: the nearest three vectors participating in vector synthesis are OOO, NNN and PPP of the zero vector, ONN and POO of the small vector, and OON and PPO of the small vector; When the clamping phase is the A phase, the five-segment switching sequences that can be composed by the above nearest three vectors include: OOO, OON, ONN, OON, OOO; ONN, OON, OOO, OON, ONN; PPP, PPO, POO, PPO, PPP; POO, PPO, PPP, PPO, POO; When the clamping phase is the B phase, the five-segment switching sequences that can be composed by the above nearest three vectors include: OON, OOO, POO, OOO, OON; POO, OOO, OON, OOO, POO; When the clamping phase is the C phase, the five-segment switching sequences that can be composed by the above nearest three vectors include: OOO, POO, PPO, POO, OOO; PPO, POO, OOO, POO, PPO; NNN, ONN, OON, ONN, NNN; OON, ONN, NNN, ONN, OON; (2) I2 region: the nearest three vectors participating in vector synthesis are ONN and POO of the small vector, OON and PPO of the small vector, and PON of the medium vector. When the clamping phase is A phase, the five-segment switching sequence composed of the above-mentioned nearest three vectors comprises: PPO, POO, PON, POO, PPO; PON, POO, PPO, POO, PON; When the clamping phase is B phase, the five-segment switching sequence composed of the above-mentioned nearest three vectors comprises: POO, PON, OON, PON, POO; OON, PON, POO, PON, OON; When the clamping phase is C phase, the five-segment switching sequence composed of the above-mentioned nearest three vectors comprises: ONN, OON, PON, OON, ONN; PON, OON, ONN, OON, PON; (3) I3 region: the nearest three vectors participating in vector synthesis are ONN of the small vector, POO of the middle vector and PNN of the large vector respectively; When the clamping phase is A phase, the five-segment switching sequence composed of the above-mentioned nearest three vectors comprises: POO, PON, PNN, PON, POO; PNN, PON, POO, PON, PNN; When the clamping phase is B phase, the five-segment switching sequence composed of the above-mentioned nearest three vectors has no switching sequence that can clamp B phase; When the clamping phase is C phase, the five-segment switching sequence composed of the above-mentioned nearest three vectors comprises: ONN, PNN, PON, PNN, ONN; PON, PNN, ONN, PNN, PON; (4) I4 region: the nearest three vectors participating in vector synthesis are OON of the small vector, PPO of the middle vector and PPN of the large vector respectively; When the clamping phase is A phase, the five-segment switching sequence composed of the above-mentioned nearest three vectors comprises: PPO, PPN, PON, PPN, PPO; PON, PPN, PPO, PPN, PON; When the clamping phase is B phase, the five-segment switching sequence composed of the above-mentioned nearest three vectors has no switching sequence that can clamp B phase; When the clamping phase is C phase, the five-segment switching sequence composed of the above-mentioned nearest three vectors comprises: OON, PON, PPN, PON, OON; PPN, PON, OON, PON, PPN; The selection of the five-segment switching sequence under all nearest three vector synthesis modes under different clamping phases in other large sector regions is the same.

4. The method of claim 1, wherein the minimum switching loss pulse width modulation method is characterized by, The S2 specifically comprises: The five-segment switching sequences under different clamping phases in each region are selected according to the preset rule, and under the condition that the nearest three vector synthesis principle has been met, the selection of the switching sequence also needs to meet the following rules: (1) the selection of the switching sequence in the six large sectors remains symmetrical; (2) when switching in different regions and different clamping phases, it is ensured that there is no switching between P and N levels; Finally, a five-segment switching sequence under different clamping phases in each region is determined.

5. The method of claim 4, wherein the minimum switching loss pulse width modulation method is characterized by, The checking in the S2 specifically comprises: The five-segment switching sequences under different clamping phases in each region are checked according to the above-mentioned rule (2); In the I sector, for the first switch sequence of 10 switch sequences in different clamping phases in 4 regions, A phase only includes O, P level, B phase only includes O level, C phase only includes O, N level, and the switching between P and N levels will not occur in three phases; in II to VI sectors, different regions and different clamping phase switching, the same reason; In the region 1 switching of each sector: In the I1 and II1 region switching, for the first switch sequence of 6 switch sequences in different clamping phases in 2 regions, A phase only includes O, P level, B phase only includes O level, C phase only includes O, N level, and the switching between P and N levels will not occur in three phases; in the region 1 switching of other sectors, the same reason; In the region 3, region 4 switching of each sector: In the I4 and II3 region switching, for the first switch sequence of 4 switch sequences in different clamping phases in 2 regions, A phase only includes O, P level, B phase only includes O, P level, C phase only includes N level, and the switching between P and N levels will not occur in three phases; in the region 3, region 4 switching of other sectors, the same reason.

6. The method of pulse width modulation with minimum switching loss as claimed in claim 1 wherein, The S3 specifically includes: For the five-segment switch sequence in each region in different clamping phases selected in S2, a carrier comparison-based mode is adopted, the modulating wave is compared with the double-triangle carrier, when the modulating wave is greater than the upper triangle carrier, the corresponding P level is output; when the modulating wave is less than the lower triangle carrier, the corresponding N level is output; when the modulating wave is between the upper and lower triangle carriers, the corresponding O level is output; When the modulating wave does not superimpose zero sequence component, the SPWM modulation is realized, when different zero sequence components are superimposed, different modulation modes are realized, and the zero sequence components in different regions and clamping phases under the obtained switch sequence are determined by calculation.

7. The method of claim 1, wherein the minimum switching loss pulse width modulation method further comprises: The S4 specifically includes: For the zero sequence components in different clamping phases in each region obtained in step S3, the clamping phase is selected according to the difference of the maximum phase of the current; In regions 1 and 2, the maximum phase of the three-phase current is selected as the clamping phase by comparing the sizes of the three-phase currents; In regions 3 and 4, the maximum phase of the three-phase current is selected as the clamping phase by comparing the sizes of the three-phase currents when the maximum phase of the current can be clamped; when the maximum phase of the current cannot be clamped, the second largest phase of the three-phase current is selected as the clamping phase.

8. A pulse width modulation system with minimized switching losses, characterized by It includes: The region division module divides the three-level space vector diagram into 6 sectors according to the principle of the nearest three vector synthesis, each sector corresponds to 4 regions, and all possible five-segment switch sequences in different clamping phases in each region are obtained according to the principle of the nearest three vector synthesis; The selection module selects and checks the obtained five-segment switch sequence according to the preset rule; The zero sequence component calculation module calculates the zero sequence component of the five-segment switch sequence in different clamping phases; The modulation output module selects the zero sequence component under the corresponding clamping phase according to the maximum phase or the second largest phase of the current to obtain the three-phase modulating wave with the minimum switch loss; The comparison and verification module models the switch loss of the power device of the three-phase modulating wave and the existing DPWM1 modulating wave, and compares and verifies the effectiveness of the pulse width modulation method. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-8 when the computer program is executed by the processor. The processor, when executing the computer program, implements the steps of the switch loss minimization pulse width modulation method of any one of claims 1 to 7.

10. A non-transitory computer readable storage medium, comprising: The non-transitory computer readable storage medium stores computer instructions that cause the computer to perform the steps of the switch loss minimization pulse width modulation method of any one of claims 1 to 7.

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