A circuit for reducing turn-on surge current of a PMOS transistor

Abstract

The application relates to an improvement of a MOS tube protection circuit design, in particular to a circuit for reducing the starting impact current of a PMOS tube, after the circuit of the application is added, the impact current flowing through the PMOS tube can be reduced by more than 50%, and the impact current of the PMOS tube is greatly reduced. The circuit comprises a PMOS tube Q1, a base B of a triode Q2, a ground of an emitter E, a connection of a collector C and a resistor R2, a connection of the resistor R2 with a gate G of the PMOS tube Q1 and one end of a resistor R1, a connection of the other end of the resistor R2 with a source S of the PMOS tube Q1, a connection of the source S of the PMOS tube Q1 with an input voltage, a drain D of the PMOS tube for outputting a voltage, and a connection of the output voltage with a filter capacitor C1; and further comprises a PNP triode Q3, an NPN triode Q4, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a capacitor C2 and a diode D1.

Description

Technical Field

[0001] This invention relates to an improvement in the design of MOS transistor protection circuits, specifically a circuit for reducing the turn-on inrush current of a PMOS transistor. Background Technology

[0002] Current PMOS transistor structures include... Figure 1 As shown, this is also the type of turn-on circuit used in actual applications. The input voltage controls the output through the PMOS transistor Q1, and an electrolytic capacitor C1 is connected to each output.

[0003] In PMOS transistor Q1, the input voltage is connected to the source (S) terminal of Q1, and the drain (D) terminal of Q1 is the output. Resistors R1 and R2, along with transistor Q2, form the turn-on circuit for PMOS transistor Q1.

[0004] When the base of NPN transistor Q2 is at a high level, the collector of the transistor pulls down the gate level of PMOS transistor Q1 through R2, and PMOS transistor Q1 is turned on.

[0005] The input voltage outputs through PMOS transistor Q1. Due to the presence of electrolytic capacitor C1, after the PMOS transistor is turned on, the input voltage charges the electrolytic capacitor C1 through PMOS transistor Q1. Due to the characteristics of the electrolytic capacitor, the current is very large at the moment the voltage is turned on to charge the electrolytic capacitor. The higher the output voltage, the larger the charging current of the electrolytic capacitor C1, and thus the larger the current flowing through PMOS transistor Q1.

[0006] Taking an input voltage of 12V as an example, if the capacitance of electrolytic capacitor C1 is 2000uF, the instantaneous current of the electrolytic capacitor during charging can reach more than 100A.

[0007] This large current flows through the PMOS transistor Q1. Q1 must withstand this instantaneous large current. If a PMOS transistor with a smaller current rating is selected, it will exceed the PMOS transistor's capacity and cause the PMOS transistor to be damaged.

[0008] In summary, how to prevent the instantaneous current in the circuit from exceeding the specification current of the PMOS transistor and thus protect the PMOS transistor is a technical problem that needs to be solved. Summary of the Invention

[0009] In view of the above-mentioned problems existing in the prior art, the present invention provides a circuit for reducing the turn-on inrush current of PMOS transistors.

[0010] The technical solution adopted by this application to solve its technical problem is: a circuit for reducing the turn-on inrush current of a PMOS transistor, including a PMOS transistor Q1, a transistor Q2 whose base B is connected to an external control voltage, an emitter E grounded, a collector C connected to a resistor R2 and then connected to the gate G of the PMOS transistor Q1 and one end of the resistor R1 respectively, the other end of the resistor R2 connected to the source S of the PMOS transistor Q1, the source S of the PMOS transistor Q1 is also connected to the input voltage, the drain D of the PMOS transistor outputs the voltage, and the output voltage is connected to a filter capacitor C1; It also includes PNP transistor Q3, NPN transistor Q4, resistors R3, R4, R5, and R6, capacitor C2, and diode D1. The input voltage is connected to the base B of the PNP transistor Q3 after passing through resistor R3, and also to the emitter E of the PNP transistor Q3. The collector C of the PNP transistor Q3 is connected between resistors R1 and R2. The base B of the PNP transistor Q3 is also connected to one end of the resistor R4. The other end of the resistor R4 is also connected to the collector C of the NPN transistor Q4 through the capacitor C2. The output voltage is connected to the base B of the NPN transistor Q4 through the resistor R5. The base B and emitter E of the NPN transistor Q4 are connected by the resistor R6. The emitter E is grounded. The emitter E is also connected to the collector C through the diode D1.

[0011] The beneficial effects of this invention are: by adding the circuit of this invention, the current flowing through the PMOS transistor can be reduced to below 50A, and the inrush current can be reduced by more than 50%, which greatly reduces the inrush current to the PMOS transistor. Attached Figure Description

[0012] Figure 1 A schematic diagram of an existing PMOS transistor turn-on circuit; Figure 2 This is a schematic diagram of the PMOS transistor turn-on circuit of the present invention; Figure 3 This is a schematic diagram of the output voltage waveform characteristics of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be described below with reference to the accompanying drawings: The present invention provides a circuit for reducing the turn-on inrush current of a PMOS transistor, comprising a PMOS transistor Q1, a transistor Q2 whose base B is connected to an external control voltage, an emitter E grounded, a collector C connected to a resistor R2 and then connected to the gate G of the PMOS transistor Q1 and one end of the resistor R1, the other end of the resistor R2 connected to the source S of the PMOS transistor Q1, the source S of the PMOS transistor Q1 also connected to the input voltage, and the drain D of the PMOS transistor outputs a voltage, which is connected to a filter capacitor C1. It also includes PNP transistor Q3, NPN transistor Q4, resistors R3, R4, R5, and R6, capacitor C2, and diode D1. The input voltage is connected to the base B of the PNP transistor Q3 after passing through resistor R3, and also to the emitter E of the PNP transistor Q3. The collector C of the PNP transistor Q3 is connected between resistors R1 and R2. The base B of the PNP transistor Q3 is also connected to one end of resistor R4. The other end of resistor R4 is connected to the collector C of the NPN transistor Q4 through capacitor C2. The output voltage is connected to the base B of the NPN transistor Q4 through resistor R5. Resistor R6 is connected between the base B and emitter E of the NPN transistor Q4. The emitter E is grounded and is also connected to the collector C through diode D1. The capacitance of the filter capacitor C1 is assumed to be 2000uF.

[0014] Add the following components to the circuit: PNP transistor Q3, resistors R3 and R4, capacitor C2, NPN transistor Q4, diode D1, resistors R5 and R6; PMOS transistor Q1, with the input voltage connected to the source (S) terminal and the drain (D) terminal of Q1 as the output. Resistors R1 and R2, along with transistor Q2, form the turn-on circuit for PMOS transistor Q1.

[0015] When the base of NPN transistor Q2 is at a high level, the collector of transistor Q2 pulls down the gate level of PMOS transistor Q1 through R2, and PMOS transistor Q1 is turned on.

[0016] After PMOS transistor Q1 is turned on, the input voltage outputs through PMOS transistor Q1. Due to the presence of filter capacitor C1, after PMOS transistor Q1 is turned on, the input voltage charges filter capacitor C1 through PMOS transistor Q1. Due to the characteristics of the filter capacitor, the current increases at the instant the voltage turns on to charge the filter capacitor, and the current flowing through PMOS transistor Q increases.

[0017] Resistor R5 is connected to the output voltage. When the output voltage reaches the turn-on voltage of NPN transistor Q4 (the value of R5 and R6 can be adjusted to set the output voltage at which Q4 turns on; for example, if the input voltage is 12V, the turn-on voltage is set to 5V), Q4 turns on. Then, the input voltage charges capacitor C2 through R3 and R4, and the voltage across R4 decreases. As a result, the voltage between the base and emitter of PNP transistor Q3 decreases. Once the turn-on voltage of Q3 is reached, Q3 turns on.

[0018] (The charging time of capacitor C2 determines the turn-on time of PNP transistor Q3. The larger the capacitance of C2, the longer the charging time, the longer the conduction time of Q3, and the longer the turn-off time of PMOS transistor Q1. The smaller the capacitance of C2, the shorter the turn-off time of Q1.) After Q3 turns on, the gate-source voltage of PMOS transistor Q1 increases, and Q1 turns off. After Q1 turns off, the charging current of filter capacitor C1 through PMOS transistor Q1 is cut off. The current charging electrolytic capacitor through PMOS transistor Q1 is also cut off.

[0019] Because the output voltage is cut off when it rises to a very low level, the current charging the electrolytic capacitor is small due to the low output voltage, and the current flowing through the PMOS transistor Q1 is naturally very small as well.

[0020] The turn-off time of Q1 can be adjusted by changing the capacitance of capacitor C2, and can be adjusted according to the magnitude of the current flowing through Q1. If the current flowing through Q1 is large, the capacitance of capacitor C2 can be increased to make the turn-off time of Q1 longer, thereby reducing the current flowing through Q1. It is generally set to 0.1us to 0.3s.

[0021] When capacitor C2 is fully charged, the voltage difference between the base and emitter of PNP transistor Q3 decreases, and Q3 turns off. The gate-source voltage of PMOS transistor Q1 decreases, and Q1 turns on again. After Q1 turns on again, it outputs voltage again. Since electrolytic capacitor C1 has already been charged once, the charging current will be greatly reduced.

[0022] Diode D1 is used to discharge capacitor C2, and the output voltage waveform characteristics are as follows: Figure 2 By adding the circuit of the present invention, the current exceeding the specification of PMOS transistor Q1 can be prevented, thereby achieving the purpose of protecting PMOS transistor Q1.

[0023] Taking an input voltage of 12V as an example, assuming that the capacitance of electrolytic capacitor C1 is 2000uF, the instantaneous current of the electrolytic capacitor during charging can reach more than 100A.

[0024] With the addition of the circuit of this invention, the current flowing through the PMOS is reduced to below 50A, which greatly reduces the impact current on the PMOS transistor.

[0025] The above embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

Claims

1. A circuit for reducing the turn-on inrush current of a PMOS transistor, comprising a PMOS transistor Q1, a transistor Q2 whose base B is externally connected to a control voltage, its emitter E is grounded, its collector C is connected to a resistor R2 and then to the gate G of the PMOS transistor Q1 and one end of the resistor R1, the other end of the resistor R2 is connected to the source S of the PMOS transistor Q1, the source S of the PMOS transistor Q1 is also connected to an input voltage, the drain D of the PMOS transistor outputs a voltage, and the output voltage is connected to a filter capacitor C1; characterized in that, It also includes PNP transistor Q3, NPN transistor Q4, resistors R3, R4, R5, and R6, capacitor C2, and diode D1; The input voltage is connected to the base B of the PNP transistor Q3 after passing through resistor R3, and also to the emitter E of the PNP transistor Q3. The collector C of the PNP transistor Q3 is connected between resistors R1 and R2. The base B of the PNP transistor Q3 is also connected to one end of the resistor R4. The other end of the resistor R4 is also connected to the collector C of the NPN transistor Q4 through the capacitor C2. The output voltage is connected to the base B of the NPN transistor Q4 through the resistor R5. The base B and emitter E of the NPN transistor Q4 are connected by the resistor R6. The emitter E is grounded. The emitter E is also connected to the collector C through the diode D1. During operation, when the base of NPN transistor Q2 is high, the collector of transistor Q2 pulls down the gate level of PMOS transistor Q1 through R2, and PMOS transistor Q1 is turned on. After PMOS transistor Q1 is turned on, the input voltage outputs through PMOS transistor Q1. Due to the presence of filter capacitor C1, after PMOS transistor is turned on, the input voltage charges filter capacitor C1 through PMOS transistor Q1. Resistor R5 is connected to the output voltage. When the output voltage reaches the turn-on voltage of NPN transistor Q4, Q4 turns on. The input voltage then charges capacitor C2 through R3 and R4. The voltage across R4 decreases, which reduces the base-beta voltage of PNP transistor Q3. Once Q3 reaches its turn-on voltage, Q3 turns on. After Q3 turns on, the gate-source voltage of PMOS transistor Q1 increases, and Q1 turns off. After Q1 turns off, the charging current of PMOS transistor Q1 to filter capacitor C1 is cut off. The charging time of capacitor C2 determines the turn-on time of PNP transistor Q3. The larger the capacitance of C2, the longer the charging time, the longer the conduction time of Q3, and the longer the turn-off time of PMOS transistor Q1. The smaller the capacitance of C2, the shorter the turn-off time of Q1. When capacitor C2 is fully charged, the voltage difference between the base and emitter of PNP transistor Q3 decreases, and Q3 turns off. The gate-source voltage of PMOS transistor Q1 decreases, and Q1 turns on again. Diode D1 is used to discharge capacitor C2.

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