Silicon carbide MOSFET device and preparation method thereof

Abstract

The invention discloses a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof, and belongs to the technical field of semiconductors, the device comprises drain metal, an N + type silicon carbide substrate, a first N-type silicon carbide epitaxial layer, a second intrinsic silicon carbide epitaxial layer, an interlayer insulating medium and source metal from bottom to top; a P-type body region and an N + type source region are arranged in the second intrinsic silicon carbide epitaxial layer, and a P + type source region is arranged beside the N + type source region; a longitudinal groove penetrates through the second intrinsic type silicon carbide epitaxial layer into the first N-type silicon carbide epitaxial layer, and the bottom and at least part of the side wall of the longitudinal groove are coated by the P-type column region; upper polycrystalline silicon and lower polycrystalline silicon which are separated and separated by an interlayer dielectric are arranged in the longitudinal groove, the upper surface of the upper polycrystalline silicon is covered by the interlayer insulating dielectric, and the side surface of the upper polycrystalline silicon is coated by a gate oxide layer; the two sides and the bottom of the lower polycrystalline silicon are wrapped by the shield gate oxide layer, so that the lower polycrystalline silicon is isolated from the P-type column region. The shield gate oxide layer can be protected, the reliability of the device is improved, and the on-resistance of the device is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a silicon carbide MOSFET device and its fabrication method. Background Technology

[0002] Silicon carbide, as a wide-bandgap semiconductor material, possesses advantages such as high critical breakdown electric field strength, high saturated electron mobility, and high thermal conductivity, giving it a significant material advantage in the field of power electronic devices. Compared to planar vertical double-diffused metal-oxide-semiconductor (VDMOS) devices, trench-type silicon carbide MOSFETs have a vertically located conductive channel, eliminating the parasitic junction field-effect transistor (JFET) resistance of planar VDMOS, reducing cell size, and increasing cell density. This results in a significant increase in current density and a substantial reduction in the device's on-resistance.

[0003] Currently, asymmetric trench MOSFETs and dual-trench MOSFETs are commonly used. In asymmetric trench MOSFETs, one side of the gate trench is used for conduction, and the other side is used to create a P+ shielding region. However, when an asymmetric trench MOSFET is turned on, the P+ shielding region and the N-type epitaxial layer form a depletion region, which greatly reduces the electron current flow path and increases the on-resistance of the MOSFET. Dual-trench MOSFETs introduce gate trenches and source trenches; however, a large electric field strength still exists in the center of the gate trench, providing insufficient protection for the gate oxide layer, especially at the corners where the gate oxide layer is easily broken down by the electric field. Current techniques for protecting the trench gate oxide layer involve introducing a P-type protection zone, which reintroduces a JFET region into the device structure. However, this increases the on-resistance of the device. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a silicon carbide MOSFET device and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, embodiments of the present invention provide a silicon carbide MOSFET device, comprising: The structure includes a drain metal, an N+ type silicon carbide substrate, a first N- type silicon carbide epitaxial layer, a second intrinsic type silicon carbide epitaxial layer, an interlayer insulating medium, and a source metal. Within the middle region of the second intrinsic type silicon carbide epitaxial layer, a P-type body region and an N+ type source region are disposed from bottom to top, and a P+ type source region is disposed on each side of the N+ type source region. A longitudinal trench is provided at one end of the first N-type silicon carbide epitaxial layer away from the N+ type silicon carbide substrate, penetrating the second intrinsic silicon carbide epitaxial layer and extending into the first N-type silicon carbide epitaxial layer. The longitudinal trench is located in the middle of the two P+ type source regions, and the bottom and at least part of the sidewalls of the longitudinal trench are covered by P-type pillar regions. The longitudinal trench contains upper and lower polysilicon layers separated by an interlayer dielectric. The upper surface of the upper polysilicon is covered by the interlayer insulating dielectric, and its sides are covered by a gate oxide layer. The sides and bottom surface of the lower polysilicon are covered by a shielding gate oxide layer, thereby isolating it from the bottom P-type pillar region.

[0005] In a second aspect, embodiments of the present invention provide a method for fabricating a silicon carbide MOSFET device, used to fabricate the silicon carbide MOSFET device described in the first aspect, the method comprising: S1, select an N+ type substrate of silicon carbide as a high-concentration N-type drain, and then grow the first N-type silicon carbide epitaxial layer. S2, using a pre-designed photomask, determine the location range of the periodically arranged combined structure regions within the first N-type silicon carbide epitaxial layer, and form an N-type conductive region at the top position of the first preset region within the first N-type silicon carbide epitaxial layer by ion implantation for the first preset region in different combined structure regions; wherein, the region within the same combined structure region other than the first preset region is the second preset region; the positional distribution of the first preset region and the second preset region in different combined structure regions is different, but the proportion of the first preset region within the same combined structure region is greater than the proportion of the second preset region. S3, a second intrinsic silicon carbide epitaxial layer is prepared on the entire surface of the first N-type silicon carbide epitaxial layer; and two P-type body regions are formed in the second intrinsic silicon carbide epitaxial layer in the first and second preset regions by ion implantation. In the first preset region, the two P-type body regions are symmetrically distributed on the upper surface of the N-type conductive region and are in partial contact with the N-type conductive region. S4, In the top region of the P-type body region, an N+ type source region is formed by ion implantation, and a P+ type source region is formed next to each N+ type source region by ion implantation. S5, a longitudinal trench is etched downward from the top of the second intrinsic silicon carbide epitaxial layer, such that the longitudinal trench is located in the middle of the two P+ type source regions and extends into the first N- type silicon carbide epitaxial layer. S6, Ion implantation is performed at the bottom and sidewalls of the longitudinal trench to form P-type column regions. In the first preset region, the P-type column regions of the longitudinal trench sidewalls are located below and in contact with the N-type conductive regions, so that the P-type column regions partially cover the longitudinal trench sidewalls. In the second preset region, the longitudinal trench sidewalls are completely covered by the P-type column regions. S7, a shielding gate oxide layer is formed in the longitudinal trench, and polysilicon is filled in the shielding gate oxide layer; and part of the shielding gate oxide layer and polysilicon in the longitudinal trench are removed, and an interlayer dielectric is formed on the inner surface of the longitudinal trench, so that the polysilicon under the interlayer dielectric is used as the lower polysilicon. S8, a gate oxide layer is formed on the interlayer dielectric in the longitudinal trench, and polysilicon is filled in the region inside the gate oxide layer to form upper polysilicon; S9, an interlayer insulating dielectric is formed on the surface of the second intrinsic silicon carbide epitaxial layer, and metal contact holes are etched at the positions corresponding to the P+ type source region by photolithography and etching processes, source metal is formed by metal deposition, and drain metal is formed by metal deposition on the back side of the N+ type silicon carbide substrate.

[0006] The beneficial effects of this invention are: The silicon carbide MOSFET device provided in this embodiment of the invention forms P-type pillar regions at the bottom and sidewalls of the shielding gate within a longitudinal trench to completely cover the shielding gate oxide layer. When the device withstands reverse voltage, this structure shields most of the electric field, thereby reducing the electric field strength of the oxide layer at the bottom of the trench. The oxide layer thickness at the bottom of the trench is much greater than that of a conventional gate oxide layer, resulting in higher resistance to electric fields and further ensuring the reliability of the device.

[0007] Furthermore, the device structure of this embodiment forms an N-type conductive region in advance through buried layer implantation. The doping concentration of this region is much higher than that of the first N-type silicon carbide epitaxial layer. Moreover, the distance between the P-type pillar region and the P-type body region in this structure can be increased by the thickness of the N-type conductive region, which can greatly reduce the on-resistance when current flows. It also avoids the problem of high on-resistance in the JFET region after introducing a trench protection structure.

[0008] The device structure of the present invention introduces a P-type pillar region as a protective structure for the shielding gate oxide layer without increasing the JFET resistance. When the device is in reverse breakdown voltage state, the trench gate is connected to zero potential or negative potential. At this time, the P-type pillar region and the first N-type silicon carbide epitaxial layer form lateral depletion. The presence of the P-type pillar region can protect the shielding gate oxide layer, improve the reliability of the device, and increase the doping concentration of the first N-type silicon carbide epitaxial layer, thereby further reducing the on-resistance of the device. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the periodically changing N-type conductive region and P-type columnar region, and their corresponding cross-sectional structures, according to an embodiment of the present invention. Figure 2 This is a schematic flowchart of a method for fabricating a silicon carbide MOSFET device according to an embodiment of the present invention; Figure 3 This is a schematic cross-sectional view of the structure after the formation of the first N-type silicon carbide epitaxial layer in an embodiment of the present invention; Figure 4 This is a schematic cross-sectional view of the structure after the N-type conductive region is formed according to an embodiment of the present invention; Figure 5 This is a schematic cross-sectional view of the structure after forming the second intrinsic silicon carbide epitaxial layer according to an embodiment of the present invention; Figure 6 This is a schematic cross-sectional view of the P-shaped body region after formation according to an embodiment of the present invention; Figure 7 This is a schematic cross-sectional view of the N+ type source region and the P+ type source region after formation according to an embodiment of the present invention; Figure 8 This is a schematic cross-sectional view of the structure after the longitudinal groove is formed according to an embodiment of the present invention; Figure 9 This is a schematic cross-sectional view of the P-shaped column region after formation according to an embodiment of the present invention; Figure 10 This is a schematic cross-sectional view of the trench sidewall oxide layer and polysilicon after forming according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the cross-sectional structure after etching away part of the oxide layer and polysilicon inside the longitudinal trench in an embodiment of the present invention; Figure 12 This is a schematic cross-sectional view of the structure after the interlayer medium is formed according to an embodiment of the present invention; Figure 13 This is a schematic cross-sectional view of the structure after the gate oxide layer and the upper polysilicon layer have been grown according to an embodiment of the present invention. Figure 14 This is a cross-sectional schematic diagram of a device structure after forming an interlayer insulating dielectric, a source metal, and a drain metal according to an embodiment of the present invention. Figure 15 This is a cross-sectional schematic diagram of another device structure formed after the interlayer insulating dielectric, source metal and drain metal are formed according to an embodiment of the present invention.

[0010] Figure label: 01-N+ type silicon carbide substrate; 02-First N- type silicon carbide epitaxial layer; 03-N-type conductive region; 04-Second intrinsic type silicon carbide epitaxial layer; 05-P-type body region; 06-N+ type source region; 07-P+ type source region; 08-Vertical trench; 09-P-type pillar region; 10-Shielding gate oxide layer; 11-Lower polysilicon; 12-Upper half of vertical trench; 13-Interlayer dielectric; 14-Gate oxide layer; 15-Upper polysilicon; 16-Interlayer insulating dielectric; 17-Source metal; 18-Drain metal. Detailed Implementation

[0011] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0012] To address the issues of increased on-resistance in MOSFET devices and insufficient electric field protection for the gate oxide layer, particularly the vulnerability of the gate oxide layer at corners to electric field breakdown, this invention provides a silicon carbide MOSFET device and its fabrication method.

[0013] In a first aspect, embodiments of the present invention provide a silicon carbide MOSFET device, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of the periodically changing N-type conductive region 03 and P-type pillar region 09, and their corresponding cross-sectional structures, according to an embodiment of the present invention; wherein, Figure 1 Figure (a) in the figure is a planar view of the overall structure of the device from above, but for simplification, only some layers are shown. Figure 1 Figures (b) and (c) are schematic cross-sectional views of two silicon carbide MOSFET devices provided in embodiments of the present invention. The present invention will describe the structure of these two silicon carbide MOSFET devices as a whole, which includes, from bottom to top: The structure includes a drain metal 18, an N+ type silicon carbide substrate 01, a first N- type silicon carbide epitaxial layer 02, a second intrinsic type silicon carbide epitaxial layer 04, an interlayer insulating medium 16, and a source metal 17. Inside the middle region of the second intrinsic type silicon carbide epitaxial layer 04, a P-type body region 05 and an N+ type source region 06 are disposed from bottom to top, and a P+ type source region 07 is disposed on each side of the N+ type source region 06. A longitudinal trench 08 is provided at one end of the first N-type silicon carbide epitaxial layer 02 away from the N+ type silicon carbide substrate 01, penetrating the second intrinsic silicon carbide epitaxial layer 04 and extending into the first N-type silicon carbide epitaxial layer 02. The longitudinal trench 08 is located in the middle of the two P+ type source regions 07, and the bottom and at least part of the sidewalls of the longitudinal trench 08 are covered by P-type pillar regions 09. An upper polysilicon 15 and a lower polysilicon 11, separated and isolated by an interlayer dielectric 13, are provided in the longitudinal trench 08. The upper surface of the upper polysilicon 15 is covered by the interlayer insulating dielectric 16, and the sides are covered by a gate oxide layer 14. The two sides and the bottom surface of the lower polysilicon 11 are wrapped by a shielding gate oxide layer 10, thereby isolating it from the bottom P-type pillar region 09.

[0014] Please refer to the following for details. Figure 1 Please refer to Figures (b) and (c) for clarification. The difference between the two structures lies in whether the sidewalls of the longitudinal groove 08 are entirely covered by the P-type column region 09. Figure 1 Figure (b) shows that the sidewalls of the longitudinal trench 08 are completely covered by the P-type column region 09, while Figure 1 Figure (c) shows that the sidewalls of the longitudinal trench 08 are only partially covered by the P-type pillar region 09, while the sidewalls not covered by the P-type pillar region 09 are covered by the N-type conductive region 03. Therefore, in general, the longitudinal trench 08 of the present invention is at least partially covered by the P-type pillar region 09.

[0015] In this embodiment of the invention, at least a portion of the sidewalls of the longitudinal trench 08 are covered by P-type pillar regions 09. This is achieved by pre-periodically ion-implanting partitions on the surface of the first N-type silicon carbide epitaxial layer 02 to form N-type conductive regions 03, thereby constructing two silicon carbide MOSFET device structures according to the layout design. This results in the N-type conductive regions 03 exhibiting a discontinuous structure on the device planar structure.

[0016] This section can be found at [link / reference]. Figure 1 Figure (a) in the middle and combined with Figure 1 Use diagrams (b) and (c) in the text to understand. Figure 1 Figure (a) shows the overall planar structure of the device composed of different silicon carbide MOSFET device structures from a top-down view. For simplification and intuitive understanding, it only shows the first N-type silicon carbide epitaxial layer 02, N-type conductive region 03, longitudinal trench 08 and P-type pillar region 09.

[0017] Figure 1 Figures (b) and (c) illustrate two silicon carbide MOSFET device structures, with the cross-sectional direction parallel to the short side of the long dashed frame. Specifically, the two silicon carbide MOSFET device structures include a first silicon carbide MOSFET device structure and a second silicon carbide MOSFET device structure; wherein, In the first silicon carbide MOSFET device structure, all sidewalls of the longitudinal trench 08 are covered by the P-type pillar region 09, and the P-type pillar region 09 of the sidewall of the longitudinal trench 08 is connected to the P-type body region 05; the first silicon carbide MOSFET device structure corresponds to Figure 1 Figure (b) in the middle, and corresponding to Figure 1 Area A is marked in Figure (a); In the second silicon carbide MOSFET device structure, a portion of the sidewall of the longitudinal trench 08 is covered by the P-type pillar region 09, and the N-type conductive region 03 is located above the surface of the P-type pillar region 09 on the sidewall. The N-type conductive region 03 is connected to the P-type body region 05. The second silicon carbide MOSFET device structure corresponds to... Figure 1 Figure (c) in the middle, and corresponding to Figure 1 Area B is marked in Figure (a).

[0018] In the planar structure of the device, the first silicon carbide MOSFET device structure and the second silicon carbide MOSFET device structure form different combined structure regions, and the different combined structure regions are arranged in an intermittent and periodic manner. The P-type pillar regions 09 of the different combined structure regions are interconnected and eventually connected to the P-type body region 05.

[0019] Figure 1 Figure (a) shows three combined structure regions enclosed by long dashed boxes, serving as an example of different combined structure regions arranged in a periodic and intermittent manner. It can be seen that the positions of regions A and B within the first two long dashed boxes are not the same, representing two different styles of combined structure regions. Starting from the third long dashed box, the two types of combined structure regions repeat periodically (not shown in subsequent figures). The different combined structure regions are spaced apart and are all located on the same underlying structure (the underlying structure from bottom to top consists of drain metal 18, N+ type silicon carbide substrate 01, and first N- type silicon carbide epitaxial layer 02).

[0020] Specifically, the different combined structural regions include a first combined structural region and a second combined structural region; please refer to the respective sections. Figure 1 The first two long, dashed boxes in Figure (a). From the perspective of the device's planar structure, In the first combined structure region, the first silicon carbide MOSFET device structure is located at both ends, and the second silicon carbide MOSFET device structure is located in the middle, and they are connected to each other; from Figure 1 As shown in Figure (a), the dark gray areas at the top and bottom of the first combined structure region represent region A, i.e., the structure of the first silicon carbide MOSFET device (see cross-sectional structure). Figure 1 (Figure b) shows the structure of the second silicon carbide MOSFET device (see cross-sectional structure). The light gray area in the middle represents region B, which is region B. Figure 1 (Figure c)

[0021] In the second combined structure region, the second silicon carbide MOSFET device structure is located at both ends, and the first silicon carbide MOSFET device structure is located in the middle, and they are connected to each other; from Figure 1 As shown in Figure (a), the dark gray area in the middle of the second combined structure region represents region A, which is the structure of the first silicon carbide MOSFET device (see cross-sectional structure). Figure 1 (Figure b) shows the structure of the second silicon carbide MOSFET device, while the light gray areas at the top and bottom represent region B (see cross-sectional structure). Figure 1 (Figure c)

[0022] As can be seen from the comparison, in both the first and second combined structure regions, the area proportion of the second silicon carbide MOSFET device structure is greater than that of the first silicon carbide MOSFET device structure. Specifically, the existence of the device structure in region A ensures that the P-type pillar region 09 and the source electrode in the device structures of regions A and B maintain the same potential. During the reverse breakdown voltage process of the device, the P-type pillar region 09, the P-type body region 05, and the first N-type silicon carbide epitaxial layer 02 are depleted together, thus protecting the bottom shield gate and the channel gate oxide layer. The device structure in region A does not play a conductive role; only the device structure in region B plays a conductive role. To ensure that the on-resistance of the chip is minimized, this invention reduces the area of ​​region A as much as possible.

[0023] The planar dimensions of each combined structural area can be the same, the spacing between two adjacent combined structural areas can be the same, and the planar dimensions of all areas A can also be the same.

[0024] Furthermore, it is understandable that for each composite structural region, its distribution along the long side of the corresponding dashed frame is also periodic. For example, for... Figure 1 In Figure (a), the first long dashed box on the left represents the first combined structural area. Above region A is region B, and above region B is region A again… Two adjacent first combined structural areas share region A. Of course, for… Figure 1 In Figure (a), the first long dashed box on the left shows a first composite structure region with a similar periodic distribution below region A. The second composite structure region is similar. For simplicity, in... Figure 1 The multiple combined structural regions with periodicity in the vertical direction are not illustrated in Figure (a).

[0025] The following describes each part of the silicon carbide MOSFET device structure according to an embodiment of the present invention.

[0026] In this embodiment of the invention, the N+ type silicon carbide substrate 01 serves as a high-concentration N-type drain, with a doping concentration of [missing information]. The thickness can be set as needed. The N+ type silicon carbide substrate 01 can be made of materials such as 4H SiC, 6H SiC or 3C SiC, with 4H SiC being the most commonly used.

[0027] In this embodiment of the invention, the first N-type silicon carbide epitaxial layer 02 is obtained by epitaxial growth on an N+ type silicon carbide substrate 01 and requires cleaning treatment. Its thickness can be 8~15um.

[0028] In this embodiment of the invention, the periodic appearance of the N-type conductive region 03 is achieved by selectively implanting nitrogen ions into the first N-type silicon carbide epitaxial layer 02. This is a pre-formation process of the N-type conductive region. Specifically, for the location where the N-type conductive region 03 exists, nitrogen ions are implanted into the first N-type silicon carbide epitaxial layer 02 to form the N-type conductive region 03 in the top region at its center. The N-type conductive region 03 does not reach the bottom surface of the first N-type silicon carbide epitaxial layer 02. The N-type conductive region 03 exhibits a discontinuous structure on the device's planar structure. This ensures that the P-type pillar region 09 and the P-type body region 05 are connected together, ultimately maintaining the same potential for the P-type pillar region 09, the P-type body region 05, and the drain metal 18. This ensures that, after maintaining the same potential, during the reverse breakdown voltage process of the device, the P-type pillar region 09, the P-type body region 05, and the first N-type silicon carbide epitaxial layer 02 jointly deplete and protect the P-type pillar region 09 and the gate oxide layer 14. In this embodiment, the doping concentration of the N-type conductive region 03 is greater than the doping concentration of the first N-type silicon carbide epitaxial layer 02 because a higher concentration of the N-type conductive region 03 can reduce the on-resistance of the device. For example, in one optional embodiment, the doping concentration of the N-type conductive region 03 is... The purpose is to prevent inversion by the subsequent P-type pillar region 09 and to reduce the on-resistance of the device. The doping concentration of the first N-type silicon carbide epitaxial layer 02 is [missing information]. Furthermore, in one optional embodiment, the width of the N-type conductive region 03 can be 1.5~3.5µm, and the thickness of the N-type conductive region 03 can be 0.7~1.5µm. In this embodiment, the depth (i.e., vertical spacing) of the N-type conductive region 03 is increased, resulting in a lower on-resistance of the device. However, if it is too deep, i.e., the vertical spacing between the P-type body region 05 and the P-type pillar region 09 is too large, the protective effect on the gate oxide layer 14 will be weakened. Therefore, the depth of the N-type conductive region 03 needs to be balanced between the protective effect of the gate oxide layer 14 and the on-resistance of the device. The bottom of the N-type conductive region 03 is 0.3~0.5µm deeper than the bottom of the interlayer dielectric 13. In this embodiment, the depth of the N-type conductive region 03 can be adjusted by the injection energy of the N-type conductive region 03, and is not necessarily a fixed depth.

[0029] In this embodiment of the invention, the thickness of the second intrinsic silicon carbide epitaxial layer 04 is 0.5~1.5 μm. The purpose of fabricating the second intrinsic silicon carbide epitaxial layer 04 in this embodiment is to reduce the on-resistance of the channel. Specifically, this invention does not require ion compensation in the second intrinsic silicon carbide epitaxial layer 04, which can reduce the ion doping concentration in the P-type body region 05. The channel between the P-type body region 05 and the gate oxide layer 14 experiences a decrease in ion collision rate, thereby increasing the ion mobility of the channel region and reducing the channel resistance.

[0030] In the same device structure of this invention embodiment, there are two P-type body regions 05, which are formed by aluminum ion deposition on the second intrinsic silicon carbide epitaxial layer 04. In the device structure with an N-type conductive region 03, these two P-type body regions 05 are symmetrically distributed on the N-type conductive region 03 and partially overlap with it, with each overlapping region having a length of 0.3~0.8 μm. The lower surface height of the second intrinsic silicon carbide epitaxial layer 04 is equal to or lower than the lower surface height of the P-type body region 05. The depth range of the second intrinsic silicon carbide epitaxial layer 04 and the P-type body region 05 can be 0.8~1.2 μm. The doping concentration of the P-type body region 05 can be... .

[0031] In this embodiment of the invention, the N+ source region 06 is formed by implanting nitrogen ions into the P-type body region 05. The upper surface of the N+ source region 06 is flush with the upper surface of the second intrinsic silicon carbide epitaxial layer 04, and the lower surface contacts the P-type body region 05.

[0032] In this embodiment of the invention, the P+ type source region 07 is formed by implanting aluminum ions into the middle region of each N+ type source region 06. The upper surface of the P+ type source region 07 is flush with the upper surface of the N+ type source region 06 and the upper surface of the second intrinsic silicon carbide epitaxial layer 04, and the lower surface of the P+ type source region 07 contacts the P-type body region 05.

[0033] In this embodiment of the invention, the longitudinal trench 08 is etched from the upper surface of the second intrinsic silicon carbide epitaxial layer 04 between the two P-type body regions 05, along the inner edges of the two P-type body regions 05, towards the N+ type silicon carbide substrate 01. The longitudinal trench 08 penetrates the second intrinsic silicon carbide epitaxial layer 04 and extends into the first N-type silicon carbide epitaxial layer 02. However, since the thickness of the first N-type silicon carbide epitaxial layer 02 is much greater than the depth of the longitudinal trench 08, the longitudinal trench 08 will not reach the bottom of the first N-type silicon carbide epitaxial layer 02. For device structures with N-type conductive regions 03, the longitudinal trench 08 will completely penetrate the N-type conductive regions 03, but N-type conductive regions 03 will exist on the sidewalls of the longitudinal trench 08. In one optional embodiment, the depth of the longitudinal trench 08 is 2~5µm, and the width is 1~3µm.

[0034] In this embodiment of the invention, the P-type pillar region 09 is formed by implanting aluminum ions into the bottom and sidewalls of the longitudinal trench 08. The lower edge of the P-type pillar region 09 at the bottom of the longitudinal trench 08 does not reach the lower surface of the first N-type silicon carbide epitaxial layer 02. The P-type pillar region 09 is connected to the source metal 17 through a layout. The P-type pillar region 09 and the source maintain the same potential. During the reverse breakdown voltage process of the device, the P-type pillar region 09, the P-type body region 05, and the first N-type silicon carbide epitaxial layer 02 are depleted together to protect the bottom shield gate and the channel gate oxide layer. The periodic implantation of the N-type conductive region 03 results in a periodic arrangement of the two types of P-type pillar regions 09. The doping concentration of the P-type pillar region 09 is... This doping concentration and the doping concentration of the P-type body region 05 It is quite the same. Furthermore, when only part of the sidewall of the longitudinal trench 08 is covered by the P-type pillar region 09, the upper surface of the P-type pillar region 09 of the sidewall is lower than the lower surface of the interlayer medium 13, that is, the depth of the N-type conductive region 03 is deeper than that of the interlayer medium 13.

[0035] In this embodiment of the invention, the shielding gate oxide layer 10 covers the sides and bottom of the lower polysilicon 11, and the upper surface of the lower polysilicon 11 is covered by the interlayer dielectric 13. This isolated and discrete lower polysilicon 11 reduces the gate charge of the device. The width of the lower polysilicon 11 can be 0.4~2.4 μm. Furthermore, in this embodiment of the invention, the shielding gate oxide layer 10 covers the bottom of the lower polysilicon 11, ensuring that the lower polysilicon 11 does not contact the P-type pillar region 09.

[0036] In this embodiment of the invention, a gate oxide layer 14 and an upper polysilicon layer 15 are formed in the upper half 12 of the remaining longitudinal trench 08, which is isolated by the interlayer dielectric 13. The bottom of the upper half 12 of the longitudinal trench does not exceed the depth of the N-type conductive region 03, thereby reducing the gate charge of the device. The gate oxide layer 14 covers the side of the upper polysilicon layer 15, the upper surface of the upper polysilicon layer 15 is covered by the interlayer insulating dielectric 16, and the lower surface of the upper polysilicon layer 15 contacts the interlayer dielectric 13. The upper polysilicon layer 15, thus isolated and separated, is used as the gate. Furthermore, the lower surface of the gate oxide layer 14 is deeper than the lower surface of the P-type body region 05. Specifically, the lower surface of the gate oxide layer 14 is 0.3~0.8 μm deeper than the lower surface of the P-type body region 05 to ensure normal channel conduction and reduce on-resistance. In addition, in this embodiment of the invention, the thickness of the shielding gate oxide layer 10 is greater than the thickness of the gate oxide layer 14. With a higher thickness of the bottom shielding gate oxide layer, the resistance to electric fields is higher. In one optional embodiment, the thickness of the shielding gate oxide layer 10 is 0.5~1µm, and the thickness of the gate oxide layer 14 is 80~120nm.

[0037] In this embodiment of the invention, the interlayer insulating medium 16 covers the entire upper surface of the second intrinsic silicon carbide epitaxial layer 04, that is, it also covers the N+ source region 06, the P+ source region 07, the gate oxide layer 14, and the upper polysilicon layer 15. The thickness of the interlayer insulating medium 16 can be set as needed.

[0038] In this embodiment of the invention, the source metal 17 covers the upper surface of the interlayer insulating medium 16 and contacts the P+ type source region 07 through a metal contact hole corresponding to the P+ type source region 07. The metal contact hole is located directly above the P+ type source region 07 and its width is greater than the width of the P+ type source region 07. The source metal 17 can be made of aluminum, and the thickness of the source metal 17 covering the upper surface of the interlayer insulating medium 16 can be 4 μm.

[0039] In this embodiment of the invention, the drain metal 18 is formed on the surface of the N+ type silicon carbide substrate 01 away from the first N- type silicon carbide epitaxial layer 02. It can be a titanium-nickel-silver alloy, wherein the thickness of titanium can be 30 nm, the thickness of nickel can be 60 nm, and the thickness of silver can be 300 nm.

[0040] For the single silicon carbide MOSFET device provided in this embodiment of the invention, P-type pillar regions 09 are formed at the bottom and sidewalls of the shielding gate within the longitudinal trench 08 to completely cover the shielding gate oxide layer 10. When the device is subjected to reverse breakdown voltage, this structure shields most of the electric field, thereby reducing the electric field strength of the oxide layer at the bottom of the trench. The oxide layer thickness at the bottom of the trench is much greater than that of a conventional gate oxide layer, resulting in higher resistance to electric fields and further ensuring the reliability of the device.

[0041] Furthermore, in this embodiment of the invention, the N-type conductive region 03 is pre-formed via buried layer implantation. The doping concentration of this region is much higher than that of the first N-type silicon carbide epitaxial layer 02. Moreover, the distance between the P-type pillar region 09 and the P-type body region 05 in this structure can be significantly increased by the thickness of the N-type conductive region 03, greatly reducing the on-resistance during current flow. This also avoids the problem of high on-resistance in the JFET region after introducing a trench protection structure.

[0042] The device structure of the present invention introduces a P-type pillar region 09 as a protective structure for the shielding gate oxide layer 10 without increasing the JFET resistance. When the device is in reverse breakdown voltage state, the trench gate is connected to zero potential or negative potential. At this time, the P-type pillar region 09 and the first N-type silicon carbide epitaxial layer 02 form lateral depletion. The presence of the P-type pillar region 09 can protect the shielding gate oxide layer, improve the reliability of the device, and increase the doping concentration of the first N-type silicon carbide epitaxial layer 02, thereby further reducing the on-resistance of the device.

[0043] As mentioned earlier, the presence of the device structure in region A ensures that the P-type pillar region 09 and the source in the device structures of regions A and B maintain the same potential (the P-type pillar region 09 in the structure of region A contacts the P-type body region 05, and the P-type body region 05 contacts the source metal 17 through the P+ type source region 07; the contact between the P-type pillar region 09 in the structure of region A and the P-type pillar region 09 in the structure of region B is equivalent to the contact between the P-type pillar region 09 in the structure of region B and the source metal 17). During the reverse breakdown voltage process of the device, the P-type pillar region 09, the P-type body region 05, and the first N-type silicon carbide epitaxial layer 02 are depleted together to protect the bottom shield gate and the channel gate oxide layer. The device structure in region A does not conduct electricity; only the device structure in region B conducts electricity. To minimize the on-resistance of the chip, this invention minimizes the area of ​​region A. The periodic appearance of region A is to ensure a more stable contact effect.

[0044] Furthermore, during the design process of this invention, some design schemes were compared and optimized. For example, compared to the scheme of ion implantation of the upper part of the P-type pillar region on the sidewall after the formation of the longitudinal trench to form the N-type conductive region, the process of forming the N-type conductive region 03 in this embodiment of the invention is to form the N-type conductive region 03 in advance in the first N-type silicon carbide epitaxial layer 02 by buried layer implantation, and then grow the second intrinsic silicon carbide epitaxial layer 04. With this process, the depth of the N-type conductive region 03 in this invention can be made deeper, and its depth can be below the interlayer dielectric 13. With the N-type conductive region 03 being deeper, the resistance between the P-type body region 05 and the P-type pillar region 09 will be reduced, thereby further reducing the on-resistance of the device.

[0045] Furthermore, compared to designs that involve etching contact points at the bottom of the shielding gate oxide layer, connecting the lower polysilicon to the P-type pillar region, and finally linking it to the source metal, the P-type pillar region 09 in this embodiment is segmented. The P-type pillar region 09 contacts the P-type body region 05 and ultimately maintains the same potential as the source metal 17. Moreover, designing the lower polysilicon 11 and the P-type pillar region 09 to be non-contact in this invention reduces the capacitance between the drain and source of the device.

[0046] Secondly, embodiments of the present invention provide a method for fabricating a silicon carbide MOSFET device, used to fabricate the silicon carbide MOSFET device described in the first aspect, such as... Figure 2 As shown, the method may include the following steps: S1, select an N+ type substrate 01 of silicon carbide material as a high-concentration N-type drain, and then grow the first N-type silicon carbide epitaxial layer 02. Among them, the N+ type silicon carbide substrate 01 serves as a high-concentration N-type drain, with a doping concentration of [missing information]. The thickness can be set as needed. The N+ type silicon carbide substrate 01 can be made of materials such as 4H SiC, 6H SiC or 3C SiC, with 4H SiC being the most commonly used.

[0047] Then, a first N-type silicon carbide epitaxial layer 02 is epitaxially grown on the upper surface of the N+ type silicon carbide substrate 01. The epitaxial wafer is then cleaned to obtain the following... Figure 3 The device structure shown is as follows. The thickness of the first N-type silicon carbide epitaxial layer 02 can be relatively large to accommodate the depth of the longitudinal trench 08. For example, the thickness of the first N-type silicon carbide epitaxial layer 02 can be 8~15 μm.

[0048] S2, using a pre-designed photomask, determine the location range of the periodically arranged combined structure regions within the first N-type silicon carbide epitaxial layer 02, and form an N-type conductive region 03 at the top position of the first preset region within the first N-type silicon carbide epitaxial layer 02 by ion implantation for the first preset region in different combined structure regions; wherein, the region within the same combined structure region other than the first preset region is the second preset region; the positional distribution of the first preset region and the second preset region in different combined structure regions is different, but the proportion of the first preset region within the same combined structure region is greater than the proportion of the second preset region. In this embodiment of the invention, because two silicon carbide MOSFET device structures need to be fabricated and periodically distributed, a special photomask is pre-designed. The pattern distribution of this photomask can be found in [reference needed]. Figure 1 As illustrated in Figure (a), the first preset region in each of the different combined structure regions corresponds to the range of region B. Nitrogen ions are implanted at the top position of the first N-type silicon carbide epitaxial layer 02 corresponding to these regions to form an N-type conductive region 03. The region in each combined structure region other than the first preset region is designated as the second preset region. This region corresponds to the range of region A, and nitrogen ions do not need to be implanted into the first N-type silicon carbide epitaxial layer 02 to form the N-type conductive region 03.

[0049] Specifically, a mask layer is first deposited on top of the first N-type silicon carbide epitaxial layer 02. An ion implantation window is then etched using photolithography and etching processes. Nitrogen ions are selectively implanted to form the N-type conductive region 03. The mask layer is then removed. For the device structure with the N-type conductive region 03, please refer to [link to relevant documentation]. Figure 4 It is understood that, for ease of understanding, the preparation methods of S1 to S9 provided in the embodiments of the present invention are all exemplified by a device structure having an N-type conductive region O3.

[0050] See Figure 4It can be seen that the N-type conductive region 03 does not reach the bottom surface of the first N-type silicon carbide epitaxial layer 02. In one optional embodiment, the width of the N-type conductive region 03 can be 1.5~3.5um, and the thickness of the N-type conductive region 03 can be 0.7~1.5um.

[0051] Furthermore, the doping concentration of the N-type conductive region 03 is greater than the doping concentration of the first N-type silicon carbide epitaxial layer 02. For example, in one optional embodiment, the doping concentration of the N-type conductive region 03 is... The doping concentration of the first N-type silicon carbide epitaxial layer O2 is .

[0052] S3, a second intrinsic silicon carbide epitaxial layer 04 is prepared on the entire surface of the first N-type silicon carbide epitaxial layer 02; and within the second intrinsic silicon carbide epitaxial layer 04 in the first and second preset regions, two P-type body regions 05 are formed by ion implantation. Specifically, for the first preset region, the two P-type body regions 05 are symmetrically distributed on the upper surface of the N-type conductive region 03 and are in partial contact with the N-type conductive region 03. In both silicon carbide MOSFET device structures provided in the embodiments of the present invention, a second intrinsic silicon carbide epitaxial layer 04 is prepared on the entire surface of the first N-type silicon carbide epitaxial layer 02. It can be understood that, for device structures with an N-type conductive region 03, the second intrinsic silicon carbide epitaxial layer 04 covers the upper surface of the N-type conductive region 03.

[0053] Specifically, a mask layer is deposited on top of the entire first N-type silicon carbide epitaxial layer 02, and a second intrinsic silicon carbide epitaxial layer 04 is formed by chemical vapor deposition. The resulting structure can be found in [reference needed]. Figure 5 .

[0054] In this embodiment of the invention, the thickness of the second intrinsic silicon carbide epitaxial layer 04 can be 0.5~1.5 μm, and its resistivity is the same as that of the first N-type silicon carbide epitaxial layer 02. The doping concentration of the second intrinsic silicon carbide epitaxial layer 04 can be... In this embodiment of the invention, the second intrinsic silicon carbide epitaxial layer O4 is prepared to reduce the on-resistance of the channel.

[0055] For the two silicon carbide MOSFET device structures provided in the embodiments of the present invention, S3 also requires depositing a mask layer on top of the second intrinsic silicon carbide epitaxial layer 04, etching out the ion implantation window through photolithography and etching processes, selectively implanting aluminum ions to form two P-type body regions 05, and then removing the mask layer. The resulting structure is shown in [reference needed]. Figure 6Understood. In a device structure with an N-type conductive region 03, the two P-type body regions 05 are symmetrically distributed on the N-type conductive region 03, and both partially overlap with the N-type conductive region 03. The length of each overlapping region can be 0.3~0.8um.

[0056] The lower surface height of the second intrinsic silicon carbide epitaxial layer 04 is equal to or lower than the lower surface height of the P-type body region 05. The depth range of the second intrinsic silicon carbide epitaxial layer 04 and the P-type body region 05 can be 0.8~1.2 μm.

[0057] The doping concentration of the P-type body region 05 can be Its doping concentration is greater than that of the second intrinsic silicon carbide epitaxial layer O4.

[0058] S4, In the top region within the P-type body region 05, an N+ type source region 06 is formed by ion implantation, and a P+ type source region 07 is formed next to each N+ type source region 06 by ion implantation. For the two silicon carbide MOSFET device structures provided in the embodiments of the present invention, in S4, a mask layer is deposited on top of the second intrinsic silicon carbide epitaxial layer 04 of the device. An ion implantation window is etched using photolithography and etching processes, and nitrogen ions are selectively implanted to form an N+ source region 06 in the top layer region of each P-type body region 05. Then, the mask is removed. The upper surface of the N+ source region 06 is flush with the upper surface of the second intrinsic silicon carbide epitaxial layer 04, and the lower surface contacts the P-type body region 05. Thus, for each device, N+ source regions 06 can be formed on both sides.

[0059] Then, a mask layer is deposited again on top of the second intrinsic silicon carbide epitaxial layer 04. An ion implantation window is etched using photolithography and etching processes, and aluminum ions are selectively implanted to form a P+ type source region 07 in the middle of the N+ type source region 06. The upper surface of the P+ type source region 07 is flush with the upper surface of the N+ type source region 06 and the upper surface of the second intrinsic silicon carbide epitaxial layer 04, and the lower surface of the P+ type source region 07 contacts the P-type body region 05. The resulting structure can be found in [reference needed]. Figure 7 It can be seen that the P+ source region 07 is located between the two reserved N+ source regions 06.

[0060] S5, a longitudinal trench 08 is etched downward from the top of the second intrinsic silicon carbide epitaxial layer 04, such that the longitudinal trench 08 is located in the middle of the two P+ type source regions 07 and extends into the first N- type silicon carbide epitaxial layer 02. For the two silicon carbide MOSFET device structures provided in the embodiments of the present invention, S5 involves depositing a mask layer on top of the second intrinsic silicon carbide epitaxial layer 04, etching trench windows through photolithography and etching processes, and utilizing the different selectivity of plasma etching to etch vertical trenches 08 downwards, resulting in the following structure: Figure 8 The device structure shown; Specifically, the longitudinal trench 08 is etched from the upper surface of the second intrinsic silicon carbide epitaxial layer 04 between the two P-type body regions 05, along the inner edges of the two P-type body regions 05, towards the N+ type silicon carbide substrate 01. The longitudinal trench 08 penetrates the second intrinsic silicon carbide epitaxial layer 04 and extends into the first N-type silicon carbide epitaxial layer 02. However, because the thickness of the first N-type silicon carbide epitaxial layer 02 is much greater than the depth of the longitudinal trench 08, the longitudinal trench 08 does not reach the bottom of the first N-type silicon carbide epitaxial layer 02. See also Figure 8 It is understood that for device structures with N-type conductive regions 03, the longitudinal trench 08 will completely penetrate the N-type conductive regions 03, but N-type conductive regions 03 will exist on the sidewalls of the longitudinal trench 08. In one optional embodiment, the depth of the longitudinal trench 08 is 2~5µm and the width is 1~3µm.

[0061] S6, Ion implantation is performed on the bottom and sidewalls of the longitudinal trench 08 to form P-type pillar regions 09. Specifically, for the first preset region, the P-type pillar regions 09 on the sidewalls of the longitudinal trench 08 are located below and in contact with the N-type conductive region 03, thereby partially covering the sidewalls of the longitudinal trench 08 by the P-type pillar regions 09. For the second preset region, the sidewalls of the longitudinal trench 08 are completely covered by the P-type pillar regions 09. In this embodiment of the invention, aluminum ions are implanted into the bottom and sidewalls of a longitudinal trench 08 using ion implantation to obtain P-type pillar regions 09. The P-type pillar regions 09 at the bottom and sidewalls are formed sequentially, thus the ion implantation is performed in two stages: a first 0° angle implantation and a second 3°~5° angle four-quadrant implantation. After covering the top of the second intrinsic silicon carbide epitaxial layer 04 and the trench sidewalls with a carbon film, all implanted areas are annealed to remove the carbon film, finally obtaining the desired result. Figure 9 The device structure shown.

[0062] The lower edge of the P-type pillar region 09 at the bottom of the longitudinal trench 08 does not reach the lower surface of the first N-type silicon carbide epitaxial layer 02. The P-type pillar region 09 is connected to the source metal 17 through a layout; the periodic implantation of the N-type conductive region 03 results in a periodic arrangement of the two types of P-type pillar regions 09.

[0063] The doping concentration of the P-type pillar region 09 is This doping concentration and the doping concentration of the P-type body region 05 It is quite.

[0064] like Figure 9 As shown, for a device structure containing an N-type conductive region 03, only a portion of the sidewalls of the longitudinal trench 08 are covered by a P-type pillar region 09, and the upper surface of the P-type pillar region 09 is in contact with the N-type conductive region 03. It can be understood that, for a device structure not containing an N-type conductive region 03, the P-type pillar region 09 covers the entire sidewalls of the longitudinal trench 08, and the upper surface of the P-type pillar region 09 is in contact with the P-type body region 05.

[0065] S7, a shielding gate oxide layer 10 is formed in the longitudinal trench 08, and polysilicon is filled in the shielding gate oxide layer 10; and part of the shielding gate oxide layer 10 and polysilicon in the longitudinal trench 08 are removed, and an interlayer dielectric 13 is formed on the inner surface of the longitudinal trench 08, thereby using the polysilicon under the interlayer dielectric 13 as the lower polysilicon 11. In this embodiment of the invention, a sacrificial oxide layer is first grown in the longitudinal trench 08, then the sacrificial oxide layer is removed, and then a shielding gate oxide layer 10 is grown by thermo-oxidative growth and low-pressure chemical vapor deposition. Afterwards, polysilicon is filled inside the longitudinal trench 08, and then chemically mechanically polished until flush with the surface of the longitudinal trench, resulting in the desired product. Figure 10 The device structure shown.

[0066] Reference Figure 10 As can be seen, the shielding gate oxide layer 10 covers the sides and bottom of the polycrystalline silicon, and the width of the filled polycrystalline silicon can be 0.4~2.4um. Since the shielding gate oxide layer 10 covers the bottom of the polycrystalline silicon, the bottom of the polycrystalline silicon does not contact the P-type pillar region 09.

[0067] Then, a portion of the shielding gate oxide layer 10 and polysilicon in the longitudinal trench 08 is removed by dry etching, leaving the surface of the shielding gate oxide layer 10 and polysilicon higher than the upper surface of the sidewall P-type pillar region 09. At this point, the remaining empty trench portion of the longitudinal trench 08 serves as the upper half 12 of the longitudinal trench. Therefore, it is required that the bottom of the upper half 12 of the longitudinal trench cannot exceed the depth of the N-type conductive region 03; resulting in... Figure 11 The device structure shown.

[0068] Subsequently, an interlayer dielectric 13 is formed on the upper surface of the shielding gate oxide layer 10 and the polycrystalline silicon surface retained within the longitudinal trench 08 using high-density plasma vapor deposition technology, resulting in the following... Figure 12 The device structure shown; the polysilicon beneath the interlayer dielectric 13 is used as the lower polysilicon 11.

[0069] In this embodiment of the invention, the bottom of the interlayer dielectric 13 is higher than the bottom of the N-type conductive region 03. For example, the bottom of the N-type conductive region 03 is 0.3~0.5um deeper than the bottom of the interlayer dielectric 13.

[0070] S8, a gate oxide layer 14 is formed on the interlayer dielectric 13 in the longitudinal trench 08, and polysilicon is filled in the inner region of the gate oxide layer 14 to form an upper polysilicon 15. Specifically, a sacrificial oxide layer is first grown on the interlayer dielectric 13 within the longitudinal trench 08. Then, the sacrificial oxide layer is removed, followed by the growth of a gate oxide layer 14 via thermo-oxidative growth and annealing. N-type polysilicon is deposited to form the upper polysilicon layer 15. Next, excess silicon dioxide and polysilicon previously formed on the surface of the N-type conductive region 03 are removed to form the gate structure in the longitudinal trench, resulting in the desired structure. Figure 13 The device structure shown; like Figure 13 As shown, the polysilicon within the longitudinal trench 08 is separated into upper polysilicon 15 and lower polysilicon 11 by the interlayer dielectric 13. The lower surface of the gate oxide layer 14 is deeper than the lower surface of the P-type body region 05; specifically, the lower surface of the gate oxide layer 14 is 0.3~0.8 μm deeper than the lower surface of the P-type body region 05.

[0071] In addition, in this embodiment of the invention, the thickness of the shielding gate oxide layer 10 is greater than the thickness of the gate oxide layer 14, resulting in higher resistance to electric fields. In one optional embodiment, the thickness of the shielding gate oxide layer 10 is 0.5~1µm, and the thickness of the gate oxide layer 14 is 80~120nm.

[0072] S9, an interlayer insulating medium 16 is formed on the surface of the second intrinsic silicon carbide epitaxial layer 04, and a metal contact hole is etched at the position corresponding to the P+ type source region 07 by photolithography and etching process, a source metal 17 is formed by depositing metal, and a drain metal 18 is formed by depositing metal on the back side of the N+ type silicon carbide substrate 01.

[0073] First, an interlayer insulating dielectric 16 is deposited on the surface of the second intrinsic silicon carbide epitaxial layer 04. Therefore, the interlayer insulating dielectric 16 covers the entire upper surface of the second intrinsic silicon carbide epitaxial layer 04, that is, it also covers the N+ source region 06, the P+ source region 07, the gate oxide layer 14, and the upper polysilicon layer 15. Then, metal contact holes are etched using photolithography and etching processes. The metal contact holes are located directly above the P+ source region 07, and the width of the metal contact holes is greater than the width of the P+ source region 07 below them.

[0074] Subsequently, source metal 17 is formed by depositing metal, and drain metal 18 is formed by depositing metal on the back side of the N+ type silicon carbide substrate 01, resulting in the following: Figure 14 or Figure 15 The device structure shown; wherein, Figure 14 This represents a device structure containing an N-type conductive region 03. Figure 15This indicates a device structure that does not contain the N-type conductive region O3.

[0075] The source metal 17 can be made of aluminum with a thickness of 4 μm. The drain metal 18 can be made of a titanium-nickel-silver alloy, where the titanium has a thickness of 30 nm, the nickel has a thickness of 60 nm, and the silver has a thickness of 300 nm.

[0076] The silicon carbide MOSFET device obtained by the fabrication method provided in this invention exhibits lateral depletion between the P-type pillar region 09 and the first N-type silicon carbide epitaxial layer 02 during reverse breakdown, which can improve the breakdown voltage of the device. The presence of the P-type pillar region can protect the shielding gate oxide layer and improve the reliability of the device.

[0077] It should be noted that, in the description of this invention, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0078] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0079] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0080] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A silicon carbide MOSFET device, characterized by, From bottom to top, it includes: Drain metal (18), N+ type silicon carbide substrate (01), first N- type silicon carbide epitaxial layer (02), second intrinsic type silicon carbide epitaxial layer (04), interlayer insulating medium (16) and source metal (17); inside the middle region of the second intrinsic type silicon carbide epitaxial layer (04), P type body region (05) and N+ type source region (06) are arranged from bottom to top, and N+ type source region (06) is provided with one P+ type source region (07) on each side; A longitudinal trench (08) is arranged at one end of the first N- type silicon carbide epitaxial layer (02) away from the N+ type silicon carbide substrate (01), which penetrates through the second intrinsic type silicon carbide epitaxial layer (04) and extends to the first N- type silicon carbide epitaxial layer (02), the longitudinal trench (08) is located at the middle position of the two P+ type source regions (07), and the bottom and at least part of the sidewall of the longitudinal trench (08) are covered by the P- type column region (09); The upper polysilicon (15) and the lower polysilicon (11) are separated by the interlayer medium (13) in the longitudinal trench (08), the upper surface of the upper polysilicon (15) is covered by the interlayer insulating medium (16), and the side surface is covered by the gate oxide layer (14); the two sides and the bottom surface of the lower polysilicon (11) are wrapped by the shielding gate oxide layer (10), so as to be isolated from the P- type column region (09) at the bottom.

2. The silicon carbide MOSFET device of claim 1, wherein, At least part of the sidewall of the longitudinal trench (08) is covered by the P- type column region (09), which is realized by constructing two kinds of silicon carbide MOSFET device structures according to the layout design, by pre-ion implantation of the N type conductive region (03) on the surface of the first N- type silicon carbide epitaxial layer (02) to form a partition, so that the N type conductive region (03) presents a discontinuous structure on the device plane structure.

3. The silicon carbide MOSFET device of Claim 2, wherein, The two kinds of silicon carbide MOSFET device structures include a first silicon carbide MOSFET device structure and a second silicon carbide MOSFET device structure; wherein, In the first silicon carbide MOSFET device structure, all sidewalls of the longitudinal trench (08) are covered by the P- type column region (09), and the P- type column region (09) of the sidewall of the longitudinal trench (08) is connected with the P type body region (05); In the second silicon carbide MOSFET device structure, part of the sidewall of the longitudinal trench (08) is covered by the P- type column region (09), the N type conductive region (03) is located on the surface of the P- type column region (09) of the sidewall, and the N type conductive region (03) is connected with the P type body region (05).

4. The silicon carbide MOSFET device of claim 3, wherein, On the device plane structure, the first silicon carbide MOSFET device structure and the second silicon carbide MOSFET device structure form different combination structure regions, and the different combination structure regions are arranged periodically and spacedly, and the P- type column regions (09) of the different combination structure regions are connected with each other and finally connected with the P type body region (05).

5. The silicon carbide MOSFET device of Claim 4, wherein, The different combination structure regions include a first combination structure region and a second combination structure region; wherein, in the perspective of the device plane structure, In the first combined structure region, the first silicon carbide MOSFET device structure is located at both ends, and the second silicon carbide MOSFET device structure is located in the middle and connected to each other. In the second combined structure region, the second silicon carbide MOSFET device structure is located at both ends, and the first silicon carbide MOSFET device structure is located in the middle and connected to each other. In the first combined structure region and the second combined structure region, the area proportion of the second silicon carbide MOSFET device structure is greater than that of the first silicon carbide MOSFET device structure.

6. The silicon carbide MOSFET device of claim 1 or 3, wherein, When the longitudinal groove (08) is only partially surrounded by the P-type column region (09) on the sidewall, the upper surface of the P-type column region (09) on the sidewall is lower than the lower surface of the interlayer medium (13).

7. The silicon carbide MOSFET device of Claim 1, wherein, The lower surface of the second intrinsic silicon carbide epitaxial layer (04) is equal to or lower than the lower surface of the P-type body region (05).

8. The silicon carbide MOSFET device of Claim 1, wherein, The lower surface of the gate oxide layer (14) is 0.3-0.8 um deeper than the lower surface of the P-type body region (05).

9. The silicon carbide MOSFET device of Claim 1, wherein, The P-type column region (09) is connected to the source metal (17) through layout.

10. A method of fabricating a silicon carbide MOSFET device, comprising: The method for preparing the silicon carbide MOSFET device of any one of claims 1-9 comprises: S1, selecting an N+ type substrate (01) of silicon carbide material as a high-concentration N type drain, and then epitaxially growing a first N type silicon carbide epitaxial layer (02); S2, determining the position range of the combined structure region periodically arranged in the first N type silicon carbide epitaxial layer (02) by using a pre-designed photoetching plate, and forming an N type conductive region (03) in the top position of the first N type silicon carbide epitaxial layer (02) by ion implantation in the first preset area in different combined structure regions; wherein, the area in the same combined structure region except the first preset area is the second preset area; the position distribution of the first preset area and the second preset area in different combined structure regions is different, but the proportion of the first preset area in the same combined structure region is greater than that of the second preset area; S3, preparing a second intrinsic silicon carbide epitaxial layer (04) on the surface of the entire first N type silicon carbide epitaxial layer (02); and forming two P type body regions (05) in the second intrinsic silicon carbide epitaxial layer (04) in the first preset area and the second preset area by ion implantation, wherein, for the first preset area, the two P type body regions (05) are symmetrically distributed on the upper surface of the N type conductive region (03) and partially contact the N type conductive region (03); S4, forming an N+ type source region (06) in the top region of the P type body region (05) by ion implantation, and forming a P+ type source region (07) beside each N+ type source region (06) by ion implantation; S5, etching a longitudinal groove (08) from the top of the second intrinsic silicon carbide epitaxial layer (04) downward, so that the longitudinal groove (08) is located at the middle position of the two P+ type source regions (07) and extends into the first N type silicon carbide epitaxial layer (02). S6, ion implantation is performed at the bottom and sidewall of the longitudinal trench (08) to form P-type column region (09), wherein, for the first preset area, the P-type column region (09) of the sidewall of the longitudinal trench (08) is located below and in contact with the N-type conductive region (03), so that the P-type column region (09) partially covers the sidewall of the longitudinal trench (08); for the second preset area, the sidewall of the longitudinal trench (08) is entirely covered by the P-type column region (09); S7, a shielding gate oxide layer (10) is formed in the longitudinal trench (08), and polysilicon is filled in the shielding gate oxide layer (10); and part of the shielding gate oxide layer (10) and the polysilicon in the longitudinal trench (08) are removed, and an interlayer dielectric (13) is formed on the inner surface of the longitudinal trench (08), so that the polysilicon below the interlayer dielectric (13) is used as lower polysilicon (11); S8, a gate oxide layer (14) is formed on the interlayer dielectric (13) in the longitudinal trench (08), and upper polysilicon (15) is formed by filling polysilicon in the inner region of the gate oxide layer (14); S9, an interlayer insulating medium (16) is formed on the surface of the second intrinsic silicon carbide epitaxial layer (04), a metal contact hole is etched at a position corresponding to the P+ type source region (07) by a photoetching and etching process, a source metal (17) is formed by depositing metal, and a drain metal (18) is formed by depositing metal on the back surface of the N+ type silicon carbide substrate (01).

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