Semiconductor structure

Abstract

The invention discloses a semiconductor structure, which includes a substrate having a plurality of fins; a first well and a second well disposed in the substrate, the plurality of fins partially overlapping the first well and partially overlapping the second well; an epitaxial source region disposed on the plurality of fins within the first well; an epitaxial drain region disposed on the plurality of fins in the second well; the grid electrode is arranged on the fins between the epitaxial source electrode region and the epitaxial drain electrode region; a trench isolation region disposed in the second well between the gate and the epitaxial drain region; and a slot contact disposed on the trench isolation region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an improved high-voltage metal-oxide-semiconductor transistor structure. Background Technology

[0002] Miniaturization and performance improvement are the cornerstones of semiconductor technology advancement. This relentless pursuit has driven improvements in semiconductor components in terms of speed, efficiency, integration density, and cost per unit area. With the maturation of semiconductor technology, high-power components have been applied to a wide range of electronic products across various fields.

[0003] Laterally diffused metal-oxide-semiconductor (LDMOS) transistors and extended-drain metal-oxide-semiconductor (EDMOS) transistors are widely used as drive components in high-voltage or high-power power management integrated circuits (PMICs). On-resistance (Ron) is a critical parameter of these components, directly affecting power consumption. Lower on-resistance translates to lower power consumption. Therefore, one of the main development goals for LDMOS and EDMOS is to improve the on-resistance to breakdown voltage ratio (Ron / BVD). Summary of the Invention

[0004] The main objective of this invention is to provide an improved high-voltage metal-oxide-semiconductor transistor structure to overcome the shortcomings or disadvantages of existing technologies.

[0005] This invention provides a semiconductor structure comprising: a substrate having a plurality of fins extending along a first direction; a first well having a first conductivity type disposed in the substrate; a second well having a second conductivity type disposed in the substrate, wherein the plurality of fins partially overlap with the first well and partially overlap with the second well; an epitaxial source region having the second conductivity type disposed on the plurality of fins within the first well; and an epitaxial drain region having the second conductivity type disposed within the substrate. On the plurality of fins within the second well, wherein the epitaxial drain region is spaced apart from the epitaxial source region; a gate is disposed on the plurality of fins between the epitaxial source region and the epitaxial drain region, wherein the gate extends along a second direction; a trench isolation region is disposed within the second well between the gate and the epitaxial drain region, wherein the trench isolation region extends along the second direction and cuts off the plurality of fins between the gate and the epitaxial drain region; and a slot contact is disposed on the trench isolation region and extends along the second direction.

[0006] According to an embodiment of the present invention, when viewed from above, the gate does not overlap with the trench isolation region.

[0007] According to an embodiment of the present invention, the gate is electrically connected to the slot contact.

[0008] According to an embodiment of the present invention, the gate is not connected to the slot contact, wherein the gate is electrically coupled to a gate voltage and the slot contact is electrically coupled to a contact voltage.

[0009] According to an embodiment of the present invention, the slot contact has a grid structure.

[0010] According to an embodiment of the present invention, the slot contact comprises at least two parallel sub-contacts.

[0011] According to an embodiment of the present invention, the top surface of the trench isolation region is lower than the top surface of the epitaxial source region and the top surface of the epitaxial drain region.

[0012] According to an embodiment of the present invention, the second well is adjacent to and borders the first well.

[0013] According to an embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type.

[0014] According to an embodiment of the present invention, the gate is a metal gate.

[0015] Another aspect of the present invention provides a semiconductor structure comprising: a substrate having a plurality of fins thereon, wherein the plurality of fins extend along a first direction; a first well having a first conductivity type disposed in the substrate; a second well having a second conductivity type disposed in the substrate, wherein the plurality of fins partially overlap with the first well and partially overlap with the second well; an epitaxial source region having the second conductivity type disposed on the plurality of fins within the first well; an epitaxial drain region having the second conductivity type disposed on the plurality of fins within the second well, wherein the epitaxial drain region is spaced apart from the epitaxial source region; a gate disposed on the plurality of fins between the epitaxial source region and the epitaxial drain region, wherein the gate extends along a second direction; a plurality of trench isolation regions disposed within the second well between the plurality of fins, wherein the plurality of trench isolation regions extend along the first direction; and a plurality of trench contacts respectively disposed on the plurality of trench isolation regions and extending along the first direction.

[0016] According to an embodiment of the present invention, the plurality of trench isolation regions are disposed in an extended region between the gate and the epitaxial drain region, wherein, when viewed from above, the gate does not overlap with the plurality of trench isolation regions.

[0017] According to an embodiment of the present invention, the gate is electrically connected to the plurality of slot contacts.

[0018] According to an embodiment of the present invention, the gate is not connected to the plurality of slot contacts, wherein the gate is electrically coupled to a gate voltage and the plurality of slot contacts are electrically coupled to a contact voltage.

[0019] According to an embodiment of the present invention, the plurality of slot contacts extend into the plurality of trench isolation areas respectively.

[0020] According to an embodiment of the present invention, the plurality of slot contacts are parallel to the plurality of fins.

[0021] According to an embodiment of the present invention, in the extended region, the top surfaces of the plurality of trench isolation regions are coplanar with the top surfaces of the epitaxial source region, the epitaxial drain region, and the plurality of fins.

[0022] According to an embodiment of the present invention, the second well is adjacent to and borders the first well.

[0023] According to an embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type.

[0024] According to an embodiment of the present invention, the gate is a metal gate. Attached Figure Description

[0025] Figure 1 This is a partial top view of a semiconductor structure illustrated according to an embodiment of the present invention.

[0026] Figure 2 For along Figure 1 A schematic cross-sectional view shown by the tangent line I-I'.

[0027] Figure 3 This is a three-dimensional side view of a semiconductor structure.

[0028] Figure 4 This is a schematic diagram illustrating a slot contact that comprises at least two parallel sub-contacts.

[0029] Figure 5 This is a perspective side view of a semiconductor structure illustrated according to another embodiment of the present invention.

[0030] Figure 6 For along Figure 5 A schematic cross-sectional view shown by the tangent line II-II'.

[0031] Figure 7 For along Figure 5 A schematic cross-sectional view shown by the tangent line III-III'.

[0032] Symbol Explanation

[0033] 1.2 Semiconductor Structure

[0034] 100 base

[0035] 101 First Trap

[0036] 102 Second Trap

[0037] D1 First Direction

[0038] D2 Second Direction

[0039] DE epitaxial drain region

[0040] DL1 first dielectric layer

[0041] DL2 second dielectric layer

[0042] F fins

[0043] GD gate dielectric layer

[0044] GE gate

[0045] MI Metal Inline Structure

[0046] ML wires

[0047] MV conductive via

[0048] SC slot contact

[0049] SC-1 and SC-2 sub-contacts

[0050] SCS, SCD slot contact

[0051] SE epitaxial source polar region

[0052] SP spacer wall

[0053] ST shallow trench insulation structure

[0054] TR trench isolation zone Detailed Implementation

[0055] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and are depicted in a manner that describes specific examples in which the embodiments may be practiced. The embodiments described below are given sufficient detail to enable those skilled in the art to implement them.

[0056] Of course, other embodiments may be implemented, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the detailed description below should not be considered limiting; rather, the embodiments included therein will be defined by the appended claims.

[0057] Please see Figures 1 to 3 ,in, Figure 1 This is a partial top view of a semiconductor structure illustrated according to an embodiment of the present invention. Figure 2 For along Figure 1 A schematic cross-sectional view shown by the tangent line I-I'. Figure 3 An example of a three-dimensional side view of a semiconductor structure is shown, wherein, for ease of explanation, Figure 3The interlayer dielectric layer is omitted. The high-voltage semiconductor structure illustrated in the figures of this specification may be a laterally diffused metal-oxide-semiconductor (LDMOS) transistor compatible with finFET fabrication processes of 14 nanometers or smaller.

[0058] like Figures 1 to 3 As shown, the semiconductor structure 1 includes a substrate 100, such as a silicon substrate, on which a plurality of fins F are disposed. According to an embodiment of the present invention, a shallow trench insulating structure ST may be provided between the plurality of fins F, and the plurality of fins F protrude from the upper surface of the shallow trench insulating structure ST. According to an embodiment of the present invention, the fins F are, for example, silicon fins, but are not limited thereto. According to an embodiment of the present invention, the plurality of fins F and the shallow trench insulating structure ST may extend along a first direction D1.

[0059] According to an embodiment of the present invention, a first well 101 is provided in a substrate 100, wherein the first well 101 has a first conductivity type. According to an embodiment of the present invention, a second well 102 is further provided in the substrate 100, wherein the second well 102 has a second conductivity type. According to an embodiment of the present invention, the first conductivity type is, for example, P-type, and the second conductivity type is, for example, N-type. According to an embodiment of the present invention, the second well 102 is adjacent to and borders the first well 101. According to an embodiment of the present invention, a plurality of fins F partially overlap with the first well 101 and partially overlap with the second well 102.

[0060] According to an embodiment of the present invention, an epitaxial source region SE is disposed on a plurality of fins F within the first well 101, wherein the epitaxial source region SE has a second conductivity type, for example, N-type. According to an embodiment of the present invention, an epitaxial drain region DE is disposed on a plurality of fins F within the second well 102, wherein the epitaxial drain region DE has a second conductivity type, for example, N-type. According to an embodiment of the present invention, the epitaxial drain region DE is spaced apart from the epitaxial source region SE. According to an embodiment of the present invention, for example, the epitaxial source region SE and the epitaxial drain region DE may comprise SiP or SiGe, but are not limited thereto.

[0061] According to an embodiment of the present invention, a gate GE is disposed on a plurality of fins F between the epitaxial source region SE and the epitaxial drain region DE. According to an embodiment of the present invention, the gate GE can be a metal gate, for example, a replaced metal gate. According to an embodiment of the present invention, the gate GE extends along a second direction D2. According to an embodiment of the present invention, for example, a first direction D1 is perpendicular to the second direction D2. According to an embodiment of the present invention, the gate GE may include a spacer SP, for example, a silicon nitride spacer. According to an embodiment of the present invention, the gate GE further includes a gate dielectric layer GD, for example, silicon dioxide, but is not limited thereto.

[0062] According to an embodiment of the present invention, a trench isolation region TR is provided within a second well 102 between the gate GE and the epitaxial drain region DE. According to an embodiment of the present invention, the trench isolation region TR extends along a second direction D2 and cuts off a plurality of fins F between the gate GE and the epitaxial drain region DE. According to an embodiment of the present invention, as... Figure 1 As shown, when viewed from above, the gate GE does not overlap with the trench isolation region TR. According to an embodiment of the present invention, as... Figure 2 As shown, the top surface of the trench isolation region TR is lower than the top surface of the epitaxial source region SE and the top surface of the epitaxial drain region DE.

[0063] According to an embodiment of the present invention, the trench isolation region TR can be formed together with the shallow trench insulation structure ST using a shallow trench insulation fabrication process, wherein the trench isolation region TR and the shallow trench insulation structure ST can contain an insulating material such as silicon dioxide. According to an embodiment of the present invention, the bottom depth of the trench isolation region TR will not exceed the contact depth of the second well 102.

[0064] According to an embodiment of the present invention, a slot contact SC is provided on the trench isolation region TR. According to an embodiment of the present invention, the slot contact SC may, for example, comprise tungsten, titanium, titanium nitride, or combinations thereof, but is not limited thereto. According to an embodiment of the present invention, the slot contact SC extends along a second direction D2. According to an embodiment of the present invention, the slot contact SC may have a grid structure to avoid the dishing effect caused by grinding, but is not limited thereto.

[0065] According to another embodiment of the present invention, such as Figure 4 As shown, the slot contact SC may comprise at least two parallel sub-contacts SC-1 and SC-2, wherein sub-contacts SC-1 and SC-2 do not directly contact each other and also have a lattice structure, but are not limited thereto. In other embodiments, for example, sub-contacts SC-1 and SC-2 may be filled solid structures.

[0066] According to an embodiment of the present invention, a slot contact SCS is provided on the epitaxial source region SE, and a slot contact SCD is provided on the epitaxial drain region DE, wherein the slot contact SCS and the slot contact SCD can extend along the second direction D2. According to an embodiment of the present invention, as Figure 2 As shown, slot contact SC, slot contact SCS, and slot contact SCD can be formed in the first dielectric layer DL1. According to an embodiment of the present invention, as... Figure 2 As shown, a second dielectric layer DL2, such as a low dielectric constant material layer or an ultra-low dielectric constant material layer, can be formed on the first dielectric layer DL1.

[0067] According to an embodiment of the present invention, the gate GE can be electrically connected to the slot contact SC via a metal interconnect structure MI formed in the second dielectric layer DL2. According to an embodiment of the present invention, the metal interconnect structure MI can include a conductive via MV and a wire ML. According to another embodiment of the present invention, the gate GE may not be electrically connected to the slot contact SC, wherein the gate GE can be electrically coupled to the gate voltage VG, while the slot contact SC is electrically coupled to the contact voltage VC, thus allowing control of the gate voltage VG and the contact voltage VC respectively.

[0068] The advantage of this invention is that it can change the electric field below the trench isolation region TR by controlling the voltage of the slot contact SC, thereby reducing the on-resistance (RON) and improving the operating performance of high-voltage components.

[0069] Please see Figures 5 to 7 ,in, Figure 5 This is a perspective side view of a semiconductor structure illustrated according to another embodiment of the present invention. Figure 6 For along Figure 5 A schematic diagram of the cross-section shown by the mid-tangent II-II'. Figure 7 For along Figure 5 The cross-sectional diagram shown by the tangent line III-III' shows that the same regions, materials, and layers are still represented by the same symbols.

[0070] like Figures 5 to 7 As shown, the semiconductor structure 2 also includes a substrate 100, such as a silicon substrate, on which a plurality of fins F are disposed. According to an embodiment of the present invention, a shallow trench insulating structure ST may be provided between the plurality of fins F, and the plurality of fins F protrude from the upper surface of the shallow trench insulating structure ST. According to an embodiment of the present invention, the fins F are, for example, silicon fins, but are not limited thereto. According to an embodiment of the present invention, the plurality of fins F and the shallow trench insulating structure ST may extend along a first direction D1.

[0071] According to an embodiment of the present invention, a first well 101 is also provided in the substrate 100, wherein the first well 101 has a first conductivity type. According to an embodiment of the present invention, a second well 102 is further provided in the substrate 100, wherein the second well 102 has a second conductivity type. According to an embodiment of the present invention, the first conductivity type is, for example, P-type, and the second conductivity type is, for example, N-type. According to an embodiment of the present invention, the second well 102 is adjacent to the first well 101. According to an embodiment of the present invention, a plurality of fins F partially overlap with the first well 101 and partially overlap with the second well 102.

[0072] According to an embodiment of the present invention, an epitaxial source region SE is disposed on a plurality of fins F within the first well 101, wherein the epitaxial source region SE has a second conductivity type, for example, N-type. According to an embodiment of the present invention, an epitaxial drain region DE is disposed on a plurality of fins F within the second well 102, wherein the epitaxial drain region DE has a second conductivity type, for example, N-type. According to an embodiment of the present invention, the epitaxial drain region DE is spaced apart from the epitaxial source region SE. According to an embodiment of the present invention, for example, the epitaxial source region SE and the epitaxial drain region DE may comprise SiP or SiGe, but are not limited thereto.

[0073] According to an embodiment of the present invention, a gate GE is disposed on a plurality of fins F between the epitaxial source region SE and the epitaxial drain region DE. According to an embodiment of the present invention, the gate GE can be a metal gate, for example, a replaced metal gate. According to an embodiment of the present invention, the gate GE extends along a second direction D2, spanning the plurality of fins F. According to an embodiment of the present invention, for example, a first direction D1 is perpendicular to the second direction D2. According to an embodiment of the present invention, the gate GE may include a spacer wall SP, for example, a silicon nitride spacer wall. According to an embodiment of the present invention, the gate GE further includes a gate dielectric layer GD, for example, silicon dioxide, but is not limited thereto.

[0074] According to an embodiment of the present invention, a plurality of trench isolation regions TR are provided within a second well 102 between the gate GE and the epitaxial drain region DE. According to an embodiment of the present invention, the trench isolation regions TR extend along a second direction D2. Figure 5 It can be seen that the trench isolation region TR does not cut through the multiple fins F between the gate GE and the epitaxial drain region DE. According to an embodiment of the present invention, as... Figure 5 As shown, when viewed from above, the gate GE does not overlap with the trench isolation region TR. According to an embodiment of the present invention, multiple trench isolation regions TR are disposed in an extension region ER between the gate GE and the epitaxial drain region DE. According to an embodiment of the present invention, in the extension region ER, the top surfaces of the multiple trench isolation regions TR are coplanar with the top surfaces of the epitaxial source region DE, the epitaxial drain region SE, and the multiple fins F.

[0075] According to an embodiment of the present invention, the trench isolation region TR can be formed together with the shallow trench insulation structure ST using a shallow trench insulation fabrication process, wherein the trench isolation region TR and the shallow trench insulation structure ST can contain an insulating material such as silicon dioxide. According to an embodiment of the present invention, the bottom depth of the trench isolation region TR will not exceed the contact depth of the second well 102.

[0076] According to an embodiment of the present invention, a plurality of slot contacts SC extending along a first direction D1 are respectively provided on a plurality of trench isolation regions TR. According to an embodiment of the present invention, for example, the plurality of slot contacts SC may comprise tungsten, titanium, titanium nitride, or combinations thereof, but are not limited thereto. According to an embodiment of the present invention, from... Figure 6 As can be seen, the multiple slot contacts SC extend into the multiple trench isolation areas to a predetermined depth. According to an embodiment of the present invention, the multiple slot contacts SC are parallel to the multiple fins F and do not directly contact the multiple fins F.

[0077] According to an embodiment of the present invention, the gate GE can be via, as follows Figure 1 The illustrated metal interconnect structure MI is electrically connected to multiple slot contacts SC. According to another embodiment of the invention, the gate GE may not be electrically connected to the slot contacts SC, wherein the gate GE can be electrically coupled to the gate voltage VG, while the slot contacts SC are electrically coupled to the contact voltage VC, thus allowing separate control of the gate voltage VG and the contact voltage VC.

[0078] When the channel of the semiconductor structure 2, such as the laterally diffused metal-oxide-semiconductor (LDMOS) transistor, is turned on, the multiple slot contacts SC extending into the multiple trench isolation regions TR help attract more charge carriers to the sidewalls (drift regions) of the multiple fins F for the purpose of reducing the on-resistance (RON) and improving the operating performance of the high-voltage component.

[0079] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure, comprising: a substrate having a plurality of fins thereon, wherein a plurality of fins disposed in the substrate; a first well of a first conductivity type disposed in the substrate; a second well of a second conductivity type disposed in the substrate, wherein the plurality of fins partially overlap the first well and partially overlap the second well; an epitaxial source region of the second conductivity type disposed on the plurality of fins within the first well; an epitaxial drain region of the second conductivity type disposed on the plurality of fins within the second well, wherein the epitaxial drain region is spaced apart from the epitaxial source region; a gate disposed on the plurality of fins between the epitaxial source region and the epitaxial drain region, wherein the gate extends in a second direction; a trench isolation region disposed in the second well between the gate and the epitaxial drain region, wherein the trench isolation region extends along the second direction and cuts off the plurality of fins between the gate and the epitaxial drain region; and a slot contact disposed on the trench isolation region and extending in the second direction.

2. The semiconductor structure of claim 1, wherein, When viewed from top to bottom, the gate does not overlap the trench isolation region.

3. The semiconductor structure of claim 1, wherein, The gate is electrically connected to the slot contact.

4. The semiconductor structure of claim 1, wherein, The gate is not connected to the slot contact, wherein the gate is electrically coupled to a gate voltage and the slot contact is electrically coupled to a contact voltage.

5. The semiconductor structure of claim 1, wherein, The slot contact has a grid structure.

6. The semiconductor structure of claim 1, wherein, The slot contact comprises at least two parallel sub-contacts.

7. The semiconductor structure of claim 1, wherein, A top surface of the trench isolation region is lower than a top surface of the epitaxial source region and a top surface of the epitaxial drain region.

8. The semiconductor structure of claim 1, wherein, The second well is adjacent to the first well.

9. The semiconductor structure of claim 1, wherein, The first conductivity type is P-type and the second conductivity type is N-type.

10. The semiconductor structure of claim 1, wherein, The gate is a metal gate.

11. A semiconductor structure, comprising: a substrate having a plurality of fins thereon, wherein a plurality of fins disposed in the substrate; a first well of a first conductivity type disposed in the substrate; a second well of a second conductivity type disposed in the substrate, wherein the plurality of fins partially overlap the first well and partially overlap the second well; an epitaxial source region of the second conductivity type disposed on the plurality of fins within the first well; an epitaxial drain region of the second conductivity type disposed on the plurality of fins within the second well, wherein the epitaxial drain region is spaced apart from the epitaxial source region; a gate disposed on the plurality of fins between the epitaxial source region and the epitaxial drain region, wherein the gate extends in a second direction; a plurality of trench isolation regions disposed in the second well between the plurality of fins, wherein the plurality of trench isolation regions extend in the first direction; and a plurality of slot contacts respectively disposed on the plurality of trench isolation regions and extending in the first direction.

12. The semiconductor structure of claim 11, wherein, The plurality of trench isolation regions are disposed in an extended region between the gate and the epitaxial drain region, and wherein, when viewed from top to bottom, the gate does not overlap the plurality of trench isolation regions.

13. The semiconductor structure of claim 11, wherein, The gate is electrically connected to the plurality of slot contacts.

14. The semiconductor structure of claim 11, wherein, The gate is not connected to the plurality of slot contacts, wherein the gate is electrically coupled to a gate voltage and the plurality of slot contacts is electrically coupled to a contact voltage.

15. The semiconductor structure of claim 11, wherein, The plurality of slot contacts respectively extend into the plurality of trench isolation regions.

16. The semiconductor structure of claim 11, wherein, The plurality of slot contacts are parallel to the plurality of fins.

17. The semiconductor structure of claim 12, wherein, In the extended region, top surfaces of the plurality of trench isolation regions are coplanar with a top surface of the epitaxial source region, a top surface of the epitaxial drain region, and top surfaces of the plurality of fins.

18. The semiconductor structure of claim 11, wherein, The second well is adjacent to the first well.

19. The semiconductor structure of claim 11, wherein, The first conductivity type is P-type and the second conductivity type is N-type.

20. The semiconductor structure of claim 11, wherein, The gate is a metal gate.

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