Semiconductor device and manufacturing method thereof

Abstract

The semiconductor device includes: an active gate structure disposed over a substrate; first source / drain features disposed at two opposite sides of the active gate structure; a dielectric gate structure disposed over the substrate, the dielectric gate structure and the active gate structure being stacked on each other along a vertical direction perpendicular to the substrate; and a second source / drain feature disposed at two opposite sides of the dielectric gate structure, where the first source / drain feature and the second source / drain feature have different conductivity types. The embodiment of the invention also relates to a method for manufacturing the semiconductor device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to semiconductor devices and methods of manufacturing the same. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras and other electronic devices. The semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor material layers over a substrate, and patterning each of the material layers using photolithography techniques to form electrical circuit components and elements on the material layers.

[0003] As the semiconductor industry moves toward nanotechnology, there has recently been a push toward three-dimensional designs to pursue higher device densities, improved performance, and reduced costs. These devices can include, for example, metal oxide semiconductor field effect transistors (MOSFETs), field effect transistors (FETs), fin field effect transistors (FinFETs), gate-all-around (GAA) devices (nanowire / nanosheet), GAA devices configured as complementary field effect transistor (CFET) devices, and multi-bridge channel field effect transistors (MBCFET) devices (nanosheet). While such devices have generally been sufficient to improve various device performance, they have not been entirely satisfactory in all respects. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor device including: an active gate structure disposed over a substrate; first source / drain parts disposed at two opposite sides of the active gate structure; a dielectric gate structure disposed over the substrate, the dielectric gate structure and the active gate structure stacked with each other along a first direction; and second source / drain parts disposed at two opposite sides of the dielectric gate structure, wherein the first source / drain parts and the second source / drain parts have different conductivity types.

[0005] Another embodiment of the present disclosure provides a semiconductor device including:

[0006] an active device disposed over a front side of a substrate, and the active device including: a metal gate structure extending along a first direction, and first source / drain parts separated from the metal gate structure along a second direction perpendicular to the first direction; and

[0007] A passive device is disposed above the front side of the substrate, the passive device and the active device are stacked on top of each other along a third direction perpendicular to the first direction and the second direction, the passive device comprising: an isolation structure extending along the first direction; and a second source / drain component separated by the isolation structure along the second direction, wherein the first source / drain component and the second source / drain component have different conductivity types.

[0008] Another embodiment of this disclosure provides a method of manufacturing a semiconductor device, comprising: forming a semiconductor device on the front side of a substrate, the semiconductor device including a first active gate structure and a second active gate structure stacked on top of each other and separated by a first isolation structure; removing one of the first active gate structure or the second active gate structure to form a trench; and forming a second isolation structure in the trench. Attached Figure Description

[0009] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0010] Figure 1 and Figure 4 Each of the above shows a partial or complete three-dimensional perspective view of a semiconductor device having a vertically stacked structure according to some embodiments.

[0011] Figure 2 and Figure 5 Each shows a separate path along some embodiments. Figure 1 and Figure 4 A partial or complete cross-sectional view of the semiconductor device shown, taken from line AA'.

[0012] Figure 3 and Figure 6 Each shows a separate path along some embodiments. Figure 1 and Figure 4 A partial or complete cross-sectional view of line BB' of the semiconductor device shown.

[0013] Figure 7 A partial or complete circuit diagram of a semiconductor device having a vertically stacked structure according to some embodiments is shown.

[0014] Figure 8 The diagram illustrates the relationship between [various embodiments] and [other embodiments]. Figure 7 A front view of an example layout design corresponding to part or all of the semiconductor device shown.

[0015] Figure 9A backside view of an example layout design corresponding to part or all of the semiconductor device shown is shown in accordance with some embodiments. Figure 7 A backside view of an example layout design corresponding to part or all of the semiconductor device shown is shown in accordance with some embodiments.

[0016] Figure 10 A flow diagram of a method of manufacturing a semiconductor device in accordance with some embodiments is shown.

[0017] Figure 11 A block diagram of a system of generating an IC layout design in accordance with some embodiments is shown.

[0018] Figure 12 A block diagram of an IC manufacturing system and its related IC manufacturing flow in accordance with some embodiments is shown.

[0019] Figure 13 A flow diagram of part or all of a method of manufacturing a semiconductor device with a vertical stack structure in accordance with some embodiments is shown.

[0020] Figure 14 A flow diagram of a method for implementing part of the method shown in the flow diagram of Figure 13 A three-dimensional perspective view of part of a semiconductor device with a vertical stack structure at an intermediate stage of the method shown in the flow diagram of

[0021] Figure 15 A three-dimensional perspective view of part of a semiconductor device with a vertical stack structure at an intermediate stage of the method shown in the flow diagram of Figure 19 A cross-sectional view of part or all of the semiconductor device taken along line CC’ shown in Figure 14 A cross-sectional view of part or all of the semiconductor device taken along line CC’ shown in

[0022] Figure 16 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 17 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 18 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 20 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 22 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 24 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 26 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 27 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 28 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 14 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 15 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in

[0023] Figure 21 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 23 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 25 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 14 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in Figure 15 A cross-sectional view of part or all of the semiconductor device taken along line DD’ shown in

[0024] Figure 29A flow diagram illustrating a method of fabricating part or all of a semiconductor device having a vertically stacked structure is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0025] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the disclosure. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the descriptions below, forming a first component over or on a second component can include embodiments in which the first component and the second component are in direct contact, and can also include embodiments in which additional components can be formed between the first component and the second component such that the first component and the second component can not be in direct contact. Furthermore, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0026] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0027] The structures and methods described below relate to structures, designs, and methods of fabrication for CFETIC devices. In some embodiments, a stack of semiconductor devices includes a top or upper semiconductor device physically stacked above a bottom or lower semiconductor device along a vertical direction. For simplicity, the stack of semiconductor devices is sometimes referred to as a device stack. Depending on the device design, the included device stack (e.g., CFET structure) includes stacked semiconductor devices of the same conductivity type and / or a device stack in which the stacked semiconductor devices have different conductivity types. For example, n-type metal-oxide-semiconductor (NMOS) transistors can be vertically stacked above p-type metal-oxide-semiconductor (PMOS) transistors. In some embodiments, by configuring the semiconductor devices in a device stack, the required chip area is reduced by up to 50%.

[0028] While CFET structures generally have enhanced target performance of IC devices with respect to area saving benefits as described above, they are not fully satisfactory in all respects. In some cases, it can be desirable to independently adjust one of the two stacked devices to effect a skewing of performance of the complementary device (e.g., a pair of NMOS and PMOS devices). For example, it can be desirable to disable an NMOS device without substantially affecting a PMOS device to effect a matching of current levels between the two stacked devices without substantially altering the channel width of the devices or inadvertently increasing device capacitance.

[0029] Figure 1 A schematic perspective view of an embodiment of a portion or all of a semiconductor device 100A (hereinafter referred to as device 100A) is shown in accordance with some embodiments of the present disclosure. The device 100A includes a multilayer structure 110 (e.g., a multilayer structure 910 described below) having a lower (or first) device 110L (e.g., a lower device 910L described below) and an upper (or second) device 110U (e.g., an upper device 910U described below) stacked above the lower device 110L. A fin 128 (e.g., a fin 928 described below; alternatively referred to as an active region 128) of each of the lower device 110L and the upper device 110U extends longitudinally along a first direction (e.g., an X-direction). While only one fin 128 is depicted herein, the device 100A can include any suitable number of fins 128 disposed above a substrate, where adjacent fins 128 (not depicted herein) are spaced apart along a second direction (e.g., a Y-direction) perpendicular to the first direction in a top view of the device 100A.

[0030] The lower device 110L is disposed above a front side (FS) of a substrate (e.g., a substrate 920 described below; not shown here). In a cross-sectional view of the device 100A (e.g., as shown in FIG. 1A), the lower device 110L is disposed between the front side of the substrate and the upper device 110U along a third direction (e.g., a Z-direction) perpendicular to each of the first direction and the second direction. Figure 2 and Figure 3 As shown in each of FIGS. 1A-1C, the upper device 110U is physically stacked above the lower device 110L on the front side of the substrate along a third direction (e.g., a Z-direction) perpendicular to each of the first direction and the second direction. In this regard, the lower device 110L is disposed between the front side of the substrate and the upper device 110U along the third direction. In other words, along the third direction, the lower device 110L is disposed closer to the front side of the substrate than the upper device 110U. In some embodiments, the first direction, the second direction, the third direction are mutually transverse to each other. In some embodiments, the first direction, the second direction, the third direction are mutually perpendicular to each other as described herein.

[0031] The present disclosure provides CFET structures (e.g., device 100A, device 100B, 200, or 900 described below) in which one of the lower device or an upper device stacked above along a third direction is an active device, and the other of the lower device and the upper device is a passive device. Specifically, only one of the lower device and the upper device includes an active (e.g., metallic, conductive, etc.) gate structure, and the other of the lower device and the lower device includes a passive gate structure, such as a dielectric gate structure, which can be optionally referred to as an isolation structure, an isolation gate, etc. In this regard, such CFET structures can be described as including an active device (e.g., the lower device or the upper device) and a passive device (e.g., the upper device or the lower device) stacked with each other along the third direction.

[0032] In some embodiments, with reference to Figure 1 , device 100A is configured to have a lower device 110L that is a passive device having a dielectric gate structure 183L in place of an active gate structure, and an upper device 110U that is an active device having an active gate structure 182U (e.g., upper metal gate structure 982U described below) stacked above the lower device 110L. In the present disclosure, the dielectric gate structure 183L (e.g., third isolation structure 1102 described below) is optionally referred to as an isolation structure 183L or a passive gate structure 183L. In the present embodiment, the active gate structure 182U is hereinafter referred to as a metal gate structure 182U to distinguish from the dielectric gate structure 183L. In the present disclosure, the metal gate structure 182U (e.g., upper metal gate structure 982U described below) is optionally referred to as an active gate structure 182U or an active metal gate structure 182U. Figure 1 、 Figure 2 and Figure 3 Details of the lower device 110L and the upper device 110U are described in the views of Figure 2 shows a schematic cross-sectional view of the device 100A taken along the line AA’ of Figure 1 , and Figure 3 shows a schematic longitudinal cross-sectional view of the device 100A taken along the line BB’ of Figure 1 .

[0033] In some embodiments, the upper device 110U includes a multi-channel structure of nanosheets 126’U surrounded by the metal gate structure 182U. The multi-channel structure can include a nanosheet structure (e.g., nanosheet transistor), a nanowire structure (e.g., nanowire transistor), a nanorod structure (e.g., nanorod transistor), etc. In the example configuration shown herein, the upper device 110U includes a nanosheet structure. With reference to Figure 1 to Figure 3The upper device 110U includes a metal gate structure 182U wrapping a multi-channel structure and a pair of source / drain components 162U (e.g., upper source / drain components 962U described below) disposed on opposite sides of the metal gate structure 182 along the first direction. The metal gate structure 182U extends or elongates along the second direction. The number of nanosheets 126’U in the multi-channel structure is at least one.

[0034] The nanosheets 126’U are configured to extend along the first direction between the source / drain components 162U, thereby connecting the source / drain components 162U. The nanosheets 126’U can be optionally referred to as a semiconductor layer 126’U (e.g., a second semiconductor layer 926’U described below). In the example configuration of Figure 2 In the example configuration of the upper device 110U includes two nanosheets 126’U. Other numbers of nanosheets per device are within the scope of various embodiments. The nanosheets 126’U include a suitable semiconductor material, such as Si, SiGe, etc., configured as a channel for the upper device 110U. In the present embodiment, the nanosheets 126’U include Si. In some embodiments, the nanosheets 126’U are formed as part of a multi-layer structure (e.g., a multi-layer structure 922’ described below) over a substrate.

[0035] The metal gate structure 182U includes a gate dielectric layer 178 (e.g., a gate dielectric layer 978 described below) and a gate electrode 180U (e.g., a gate electrode 980 described below) disposed over the gate dielectric layer 178, where the gate dielectric layer 178 extends around or wraps each of the nanosheets 126’U and electrically isolates the gate electrode 180U from the nanosheets 126’U. The metal gate structure 182U extends around the gate dielectric layer 178 and the nanosheets 126’U in a configuration referred to as a gate-all-around (GAA) configuration. In some embodiments, the metal gate structure 182U is said to be interleaved with the nanosheets 126’U to form the GAA configuration. Other gate configurations are within the scope of various embodiments.

[0036] In some embodiments, reference is made to Figure 2 and Figure 3The gate dielectric layer 178 includes silicon oxide (SiO2), a high-k dielectric material, or the like, or a combination thereof. The high-k dielectric material can include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate electrode 180U is formed over and around the gate dielectric layer 178 and the nanosheet 126’U. The gate electrode 180U surrounds each nanosheet 126’U. In some embodiments, the gate electrode 180U includes polysilicon, Al, Cu, Ti, Ta, W, Co, Mo, nickel silicide, cobalt silicide, TaN, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, a metal alloy, or the like, or a combination thereof. In some embodiments, the gate electrode material includes one or more work function metals.

[0037] The lower device 110L includes a dielectric gate structure 183L and a source / drain component 162L (e.g., a lower source / drain component 962 described below) disposed on opposite sides of the dielectric gate structure 183L. The dielectric gate structure 183L and the source / drain component 162L are vertically aligned with the metal gate structure 182U and the source / drain component 162U, respectively. In other words, the dielectric gate structure 183L and the source / drain component 162L respectively overlap the metal gate structure 182U and the source / drain component 162U along the third direction.

[0038] In this embodiment, a dielectric gate structure 183L is provided in place of a metal gate structure that is interleaved with a stack of nanosheets configured as channel regions between the source / drain components 162L. The dielectric gate structure 183L can include any suitable dielectric material. For example, the dielectric gate structure 183L can include an oxide-containing or nitride-containing dielectric material. Example dielectric materials include SiO2, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbinitride (SiOCN), silicon carbonitride (SiCN), or the like, or a combination thereof. In some embodiments, the dielectric gate structure 183L includes one layer of dielectric material. In some embodiments, the dielectric gate structure 183L includes multiple layers of dielectric material. As will be described in detail below, the dielectric gate structure 183L can be formed concurrently with isolation structures configured as active regions (or fins) of the device 100A.

[0039] In some embodiments, with reference to Figure 1 and Figure 2 The source / drain components 162U, 162L include an epitaxial structure, and thus can sometimes be referred to as source / drain epitaxial structures 162U, 162L. In this embodiment, the source / drain components 162U, 162L are formed on opposite sides of their respective gate structures along the first direction.

[0040] In some embodiments, the upper device 110U and the lower device 110L include source / drain components of different conductivity types. In one such example, the upper device 110U includes source / drain components 162U configured as n-type conductivity (e.g., including silicon (Si) or silicon-carbon (Si-C) doped with n-type dopants), and the lower device 110L includes source / drain components 162L configured as p-type conductivity (e.g., including silicon-germanium (SiGe) doped with p-type dopants). Thus, the upper device 110U, as an active device of the device 100A, is configured as an NMOS device. In another such example, the source / drain components 162U are configured as p-type conductivity, and the source / drain components 162L are configured as n-type conductivity, such that the upper device 110U is a PMOS device. In some embodiments, the source / drain components 162U, 162L are configured as dopants of the same conductivity type, such as both n-type or both p-type. Example n-type dopants include phosphorus (P), arsenic (As), antimony (Sb), etc., or combinations thereof, and example p-type dopants include boron (B), aluminum (Al), indium (In), and gallium (Ga), etc., or combinations thereof.

[0041] In some embodiments, the device 100A further includes an isolation structure 172 disposed between each source / drain component 162U and the corresponding source / drain component 162L along the third direction, such that the isolation structure 172 electrically isolates the source / drain components of the upper device 110U from the source / drain components of the lower device 110L. In this regard, the isolation structure 172 is optionally referred to as a source / drain isolation structure 172. In some embodiments, with reference to Figure 2 Each sidewall of the dielectric gate structure 183L extends beyond the bottom surface of the source / drain component 162U along the third direction, such that the sidewall of the source / drain component 162U also partially overlaps or interfaces with the sidewall of the corresponding isolation structure 172.

[0042] In some embodiments, although not shown separately, the isolation structure 172 includes multiple layers, such as a liner (e.g., the liner 963 described below) and a dielectric layer (e.g., the dielectric layer 968 described below) disposed above the liner. The liner (also referred to as a contact etch stop layer (CESL)) can include SiN and can form a U-shaped conformal layer above the source / drain component 162L. The dielectric layer can include a suitable dielectric material or insulating material, such as SiO2, a SiO2-based dielectric material, etc. In some examples, the dielectric layer can have similar composition as the dielectric gate structure 183L. In the present embodiment, the source / drain component 162U is formed above and in direct contact with the upper surface of the isolation structure 172 (i.e., the liner and the dielectric layer).

[0043] Referring to Figure 1 to Figure 3 The multi-layer structure 110 also includes an intermediate layer 156 (e.g., intermediate layer 990 described below) disposed between the dielectric gate structure 183L and the metal gate structure 182U along the third direction. In other words, the dielectric gate structure 183L and the metal gate structure 182U are separated by the intermediate layer 156 along the third direction. In some embodiments, the intermediate layer 156 includes a dielectric layer (e.g., inner isolation structure 956 described below) and is configured as a vertical gate isolation structure that electrically isolates the dielectric gate structure 183L from the metal gate structure 182U, providing independent control of the dielectric gate structure 183L and the metal gate structure 182U, in a configuration referred to as an isolated gate configuration. In this regard, the intermediate layer 156 is optionally referred to as an isolation structure 156. In some embodiments, referring to Figure 2 and Figure 3 The intermediate layer 156 is aligned with the nanosheet 126’U along the third direction,

[0044] That is, in a cross-sectional view of the device 100A, a sidewall of the intermediate layer 56 is aligned with a sidewall of the nanosheet 126’U.

[0045] In some embodiments, although not shown separately, the intermediate layer 156 can also include at least two intermediate second semiconductor layers (e.g., second conductor layer 926’M described below), each disposed between the dielectric layer and each of the metal gate structure 182U and the dielectric gate structure 183L along the third direction. Thus, the dielectric layer is disposed between the two intermediate semiconductor layers along the third direction. The intermediate second semiconductor layers can be configured as pseudo semiconductor layers (i.e., pseudo channels) and can have substantially the same composition as the nanosheet 126’U and can be formed during the same operation as the nanosheet 126’U.

[0046] As can be seen in the CFET structures as provided herein, such as the device 100A, stacking one device on top of another device saves about 50% of the required chip area compared to other methods of not stacking semiconductor devices. In some embodiments, an IC device including multiple device stacks can be fabricated by a CFET process with little to no changes to the fabrication process.

[0047] In some embodiments, although Figure 1 to Figure 3As not shown, device 100A also includes isolation structures (e.g., isolation structures 932 described below) disposed in trenches (not shown) above the substrate and between adjacent fins 128. The isolation structures adjacent to fins 128 can include Si02, SiN, low-k dielectric materials (tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), FSG, phosphosilicate glass (PSG), boron-doped silicon glass (BSG), etc.), or combinations thereof. In some embodiments, the isolation structures surround bottom portions of fins 128 and are in direct contact with the upper surface of the substrate.

[0048] Still referring to Figure 2 , device 100A also includes internal spacers 154M disposed at end portions of metal gate structures 182U and between each source / drain component 162U and metal gate structure 182U. Similarly, device 100A includes internal spacers 154D disposed at end portions of dielectric gate structures 183L and between each source / drain component 162L and dielectric gate structure 183L. In the depicted embodiment, internal spacers 154M, 154D are aligned along the third direction and are spaced apart from one another. In some embodiments, internal spacers 154M, 154D are disposed between each source / drain component 162U, 162L and the substrate. Figure 2 In the depicted cross-sectional view, each internal spacer 154D is surrounded by dielectric gate structure 183L. In some embodiments, each internal spacer 154D is embedded within and completely enclosed by dielectric gate structure 183L.

[0049] Internal spacers 154M, 154D can be configured to have substantially the same composition and structure, and can be collectively referred to as internal spacers 154 (e.g., internal spacers 954 described below). Internal spacers 154 can include any suitable dielectric material such as Si02, SiN, SiC, SiOC, SiON, SiCN, SiOCN, etc., or combinations thereof. In some embodiments, internal spacers 154 include multiple layers.

[0050] Referring to Figure 1 and Figure 3 , device 100A also includes gate isolation structures 186 extending longitudinally along the first direction (i.e., parallel to fins 128). Gate isolation structures 186 are configured to cut or truncate metal gate structures 182U and dielectric gate structures 183L, and can be optionally referred to as gate cut components 186. In the present embodiment, two gate isolation structures 186 are depicted sandwiching fins 128 therebetween. In some embodiments, referring to Figure 1 , gate isolation structures 186 are in direct contact with sidewalls of each source / drain component 162U, 162L. In some embodiments, referring to Figure 3The gate electrode 180U is disposed along the second direction between each nanosheet 126'U and an adjacent one of the gate isolation structures 186, such that the gate electrode 180U wraps around each nanosheet 126'U. The gate isolation structures 186 directly contact sidewalls of the metal gate structure 182U and the dielectric gate structure 183L. In addition, portions of the gate electrode 180U are disposed along the second direction between each nanosheet 126'U and an adjacent one of the gate isolation structures 186, such that the gate electrode 180U wraps around each nanosheet 126'U.

[0051] Figure 4 , Figure 5 and Figure 6 shows a schematic diagram of embodiments of some or all of a semiconductor device 100B (hereinafter referred to as device 100B) according to some embodiments of the present disclosure. Figure 4 shows a schematic perspective view of the device 100B; Figure 5 shows a schematic cross-sectional view of the device 100B along the line AA’ of Figure 4 ; and Figure 6 shows a schematic cross-sectional view of the device 100B along the line BB’ of Figure 4 .

[0052] In the present embodiments, since the device 100B is substantially similar or identical in structure to the device 100A in some respects, the same reference numerals are used to depict components common to both devices, and a description of them is omitted below for the sake of simplicity. However, the device 100B also differs from the device 100A in some other respects.

[0053] For example, still referring to Figure 4 to Figure 6 , the upper device 110U of the device 100B is configured as a passive device having a dielectric gate structure 183U in place of an active gate structure, while the lower device 110L of the device 100B is configured as an active device having an active (or metal) gate structure 182L (e.g., a lower metal gate structure 982L described below) extending along a third direction from the dielectric gate structure 183U (e.g., a third isolation structure 1102 described below). In this regard, the lower device 110L includes a multi-channel structure of nanosheets 126’L surrounded by the metal gate structure 182L. The structure and composition of each nanosheet 126’L is substantially similar or identical to that of the nanosheet 126’U, and the number of nanosheets 126’L in the multi-channel structure of the lower device 1109L is at least one, such as two in the depicted embodiments. The structure and composition of the metal gate structure 182L is substantially similar or identical to that of the metal gate structure 182U, and the structure and composition of the dielectric gate structure 183U is substantially similar or identical to that of the dielectric gate structure 183L as described above. The metal gate structure 182L and the dielectric gate structure 183U are separated by the intervening layer 156, which is described in detail above with respect to the device 100A. In addition, referring to Figure 5The dielectric gate structure 183U is disposed between the source / drain components 162U and is separated from the source / drain components 162U by the internal spacer 154D, and the metal gate structure 182L is disposed between the source / drain components 162L and is separated from the source / drain components 162L by the internal spacer 154M. The source / drain components 162U, 162L and the internal spacers 154D, 154M are also described in detail above with respect to the device 100A.

[0054] In this disclosure, the devices 100A and 100B can be collectively referred to as a device 100 having a CFET structure configured as having two devices stacked along a vertical direction from one another. One of the two devices is configured as an active device having an active gate structure (or a metal gate structure; e.g., the metal gate structure 182U / 182L), and the other of the two devices is configured as a passive device having a passive gate structure (or a dielectric gate structure; e.g., the dielectric gate structure 183L / 183U). In some embodiments, such as in the case of the device 100A, the active device can be an upper device (e.g., the upper device 110U), and the passive device can be a lower device (e.g., the lower device 110L). In some embodiments, such as in the case of the device 100B, the active device can be a lower device (e.g., the lower device 110L), and the passive device can be an upper device (e.g., the upper device 110U). The active device and the passive device can be configured to have different conductivity types. The device 100 generally includes an intermediate layer (e.g., the intermediate layer 156) that electrically isolates the active gate structure from the passive gate structure along a third (vertical) direction.

[0055] Because the passive device and the active device can be configured with source / drain components (e.g., the source / drain components 162U, 162L) of different conductivity types, embodiments of this disclosure provide a means for adjusting device performance to compensate for or otherwise adjust for differences in measured current levels in NMOS devices and PMOS devices. For example, by configuring a NMOS device to be passive (i.e., replacing an active gate structure with a passive gate structure in the NMOS device) and configuring a complementary PMOS device stacked above or below the NMOS device in a CFET inverter to remain active, the speed of the NMOS device can be reduced to match the speed of the PMOS device.

[0056] Advantageously, embodiments provided herein allow for performance "skewing" of NMOS devices and complementary PMOS devices in a CFET structure without changing the size of the NMOS / PMOS channels. For example, if a passive device is configured as an NMOS device (i.e., includes source / drain components of n-type conductivity), the CFET structure is considered to include a skewed PMOS device. Conversely, if a passive device is configured as a PMOS device (i.e., includes source / drain components of p-type conductivity), the CFET structure is considered to include a skewed NMOS device. Moreover, by replacing one metal gate structure in the CFET structure (e.g., the metal gate structure of either the NMOS device or the PMOS device) with a dielectric gate structure, the number of conductors (e.g., metal gate structures and any contact or interconnect components electrically coupled to the metal gate structures) can be reduced, resulting in reduced capacitance and improved overall performance of the device.

[0057] In some embodiments, such as the embodiments described with reference to Figure 7 , Figure 8 and Figure 9 , these advantages associated with the device 100 can be implemented in a device (e.g., device 200) that has multiple CFET structures. Figure 7 A circuit diagram illustrating portions or all of the device 200 is shown, which includes components similar to those of the device 100B. Figure 8 An example layout diagram of a front side FS of the device 200 is shown in Figure 9 An example layout diagram of a back side BS of the device 200 is shown in. In the depicted embodiment, the device 200 can be configured to include a cell of logic devices (e.g., a buffer cell, a NAND logic gate, a NOR logic gate, etc.). Embodiments of the present disclosure can also be applied to a cell that includes a memory (e.g., static random access memory (SRAM)) device.

[0058] Referring collectively to Figure 7 and Figure 8 , the device 200 includes a first upper device 210U, a second upper device 220U, a third upper device 230U, and a fourth upper device 240U provided or formed on the front side FS. Referring collectively to Figure 7 and Figure 9 , the device 200 includes a first lower device 210L, a second lower device 220L, a third lower device 230L, and a fourth lower device 240L provided or formed on the back side BS and corresponding to the upper devices 210U, 220U, 230U, and 240U, respectively. Specifically, the upper devices 210U, 220U, 230U and the lower devices 210L, 220L, 230L, 240L are configured as active devices, and the fourth upper device 240U is configured as a passive device similar to the upper device 110U of the device 100B.

[0059] During device operation, with reference to Figure 7 to Figure 9 An input signal I can be provided to a first CFET structure (e.g., a CFET inverter) including first upper devices 210U and first lower devices 210L through a gate contact (e.g., gate contact 74A described below) on the front side FS, with an output signal ZN of the first inverter then provided through an inter-device source / drain contact (e.g., inter-device source / drain contact described below) within the first inverter and then through a backside source / drain contact (e.g., backside source / drain contact 82A described below) to a backside metal line (e.g., backside metal line 90C described below). From the backside BS, via the backside metal line and backside gate contacts (e.g., backside gate contacts 84A, 84B, and 84C described below, respectively) to respective lower devices 220L, 230L, 240L, the output signal ZN can be provided as an input signal to each of the three remaining CFET structures in device 200. This arrangement differs from existing devices with CFET structures, in which the input signal I is provided to each CFET structure from the front side FS (i.e., to upper devices 220U, 230U, and 240U, with upper device 240U configured as an active device) rather than from the backside BS.

[0060] Since upper device 240U is a passive device, the total output Z of device 200 is then provided from upper devices 220U, 230U to a front side metal line (e.g., front side metal line 80C described below) through respective front side source / drain contacts (e.g., front side via contacts 78A, 78B described below). In the depicted embodiment, VSS (e.g., ground) is coupled to upper devices 220U, 230U on the front side FS, while VDD (e.g., a supply voltage) is coupled to lower devices 220L, 230L, 240L on the backside BS.

[0061] Details of device 200 are described with reference to the layout diagrams of Figure 8 and Figure 9 Certain components of device 200 (such as a substrate, isolation structures between adjacent active regions, interlayer dielectric (ILD) layers, etc.) are omitted in the layout diagrams of Figure 8 and Figure 9 and the corresponding descriptions below thereof for simplicity.

[0062] Reference is made to Figure 8When viewed from the front side FS, the device 200 includes at least one upper active region 22A (optionally referred to as an upper fin 22A) extending along a first direction, and additional upper active regions (collectively referred to as upper active regions 22) spaced apart along a second direction. The device 200 also includes a plurality of metal gate structures 32A, 32B, 32C (collectively referred to as metal gate structures 32), each extending along the second direction and spaced apart along the first direction. Each metal gate structure 32A, 32B, 32C is joined with a respective channel region of the upper active region 22A to form upper devices 210U, 220U, 230U as active devices, respectively, each of which includes a plurality of nanosheets (optionally referred to as semiconductor layers) stacked along a third direction and wrapped by the respective metal gate structure. The device 200 also includes a dielectric gate structure 42 spaced apart from the metal gate structure 32C along the second direction and extending vertically along the third direction from the metal gate structure 30D (of a lower device 240L). The dielectric gate structure 42 is joined with the upper active region 22A to form an upper device 240U as a passive device. In the depicted embodiment, the upper devices 210U, 220U, 230U, 240U are configured to have the same conductivity type, such as n-type, although the present disclosure does not limit the upper devices to any particular conductivity type.

[0063] Reference is made to Figure 9 When viewed from the back side BS, the device 200 includes at least one lower active region 20A (optionally referred to as a lower fin 20A) extending along a first direction, and additional lower active regions (collectively referred to as lower active regions 20) spaced apart along a second direction. The device 200 includes a plurality of metal gate structures 30A, 30B, 30C, and 30D (collectively referred to as metal gate structures 30), each extending along the second direction and spaced apart along the first direction. Each metal gate structure 30 is joined with a respective channel region of the lower active region 20A to form lower devices 210L, 220L, 230L, 240L as active devices, respectively, each of which includes a plurality of semiconductor nanosheets stacked along a vertical direction and wrapped by the respective metal gate structure. In the depicted embodiment, the lower devices 210L, 220L, 230L, 240L are configured to have the same conductivity type, such as p-type, which is different from the conductivity type of the upper devices 210U, 220U, 230U, 240U, although the present disclosure does not limit each of the upper and lower devices to any particular conductivity type.

[0064] Accordingly, in the depicted embodiment, the upper active region 22A can correspond to an upper one of the fins 128, the lower active region 20A can correspond to a lower one of the fins 128, the nanosheet in each channel region can correspond to the nanosheet 126’U, 126’L, the dielectric gate structure 42 can correspond to the dielectric gate structure 183U, and the metal gate structure 30D can correspond to the metal gate structure 182L, as described above with respect to the device 100B.

[0065] Referring to Figure 8 , the device 200 includes a plurality of source / drain features 26 (e.g., 26A) adjacent to each metal gate structure 32 (i.e., adjacent to the stack of nanosheets in the upper active region 22). For example, the source / drain feature 26A is formed adjacent to the stack of nanosheets in the upper active region 22A. Similarly, referring to Figure 9 , the device 200 includes a plurality of source / drain features 24 (e.g., 24A) adjacent to each metal gate structure 30 (i.e., adjacent to the stack of nanosheets in the lower active region 20). For example, the source / drain feature 24A is formed adjacent to the stack of nanosheets in the lower active region 20A. For embodiments in which the upper devices 210U, 220U, 230U, 240U are configured as NMOS devices and the lower devices 210L, 220L, 230L, 240L are configured as PMOS devices, the source / drain features 26 can comprise Si or silicon-carbon (Si-C) doped with n-type dopants described herein, and the source / drain features 24 can comprise SiGe doped with p-type dopants described herein.

[0066] Referring again to Figure 8 , the device 200 includes a plurality of front-side source / drain contacts 70A, 70B, 70C, 70D, 70E (collectively, front-side source / drain contacts 70), each extending along the second direction and disposed between two adjacent metal gate structures 32 along the first direction. Each front-side source / drain contact 70 can be continuous along the second direction across a plurality of upper active regions 22 or across a single upper active region 20. Each front-side source / drain contact 70 is electrically coupled to a source / drain feature 26.

[0067] In some embodiments, the device 200 also includes inter-device source / drain contacts 72A, 72B, and 72C (collectively, inter-device source / drain contacts 72), each electrically coupling one of the front-side source / drain contacts 70 to a respective back-side source / drain contact 82 (e.g., one of the back-side source / drain contacts 82A, 82B, 82C, 82D, 82E). The device 200 also includes at least one gate contact 74A that extends vertically along the third direction and electrically couples one of the metal gate structures 32 to a front-side interconnect structure (e.g., one of the front-side metal lines 80).

[0068] Further, still referring to Figure 8 , the device 200 can include a plurality of front-side interconnect structures electrically coupled to the contact structures described herein. For example, the device 200 includes a plurality of front-side via contacts 78A, 78B (collectively, front-side via contacts 78). Each of the front-side via contacts 78 extends vertically along the third direction and electrically couples a contact structure (e.g., a front-side source / drain contact 70) to one of the front-side metal lines 80A, 80B, 80C, 80D (collectively, front-side metal lines 80). In the depicted embodiment, the front-side metal line 80B provides an input signal I; the front-side metal line 80C receives a total output signal Z; and the front-side metal line 80D is configured as VSS. The front-side metal lines 80 are optionally referred to as M0 metal lines because they are disposed in the metallization layer M0 closest to the front side of the substrate of the device 200. The device 200 can also include front-side power via contacts 79A and 79B (collectively, front-side power via contacts 79), each electrically coupling one of the front-side source / drain contacts 70 to VSS.

[0069] When viewed from the back side BS, referring to Figure 9 , the device 200 also includes a plurality of back-side source / drain contacts 82A, 82B, 82C, 82D, 82E (collectively, front-side source / drain contacts 82) electrically coupled to one of the source / drain components 24. The device 200 includes a plurality of back-side gate contacts 84A, 84B, 84C (collectively, back-side gate contacts 84). The device 200 also includes at least one back-side via contact 88A that electrically couples one of the back-side source / drain contacts 82 to one of the back-side metal lines (e.g., the back-side metal line 90C). The device 200 can also include back-side power via contacts 81A and 81B (collectively, back-side power via contacts 81), each electrically coupling one of the back-side source / drain contacts 82 to VDD.

[0070] Further, the device 200 includes a plurality of backside metal lines 90A, 90B, 90C (collectively, backside metal lines 90). The backside via contacts 88A electrically couple one of the backside source / drain contacts 82 to a respective one of the backside metal lines 90, and each of the backside gate contacts 84 electrically couple one of the metal gate structures 30 to one of the backside metal lines 90 (e.g., the backside metal line 90C). In some embodiments, the backside metal line 90A is configured as VDD.

[0071] In various embodiments, each of the frontside / backside source / drain contacts 70 / 82, the inter-device source / drain contacts 72, the frontside / backside gate contacts 74 / 84, the frontside / backside via contacts 78 / 88A, and the frontside / backside metal lines 80 / 90 include an electrically conductive material, such as tungsten (W), copper (Cu), cobalt (Co), ruthenium (Ru), aluminum (Al), titanium (Ti), tantalum (Ta), platinum (Pt), etc., or combinations (or alloys) thereof. In some embodiments, a barrier layer having TiN, TaN, etc., a silicide layer having a metal silicide material such as NiSi, other suitable materials, or combinations thereof can be included in one or more of the above-described contact structures, interconnect structures, and metal lines.

[0072] Further, although omitted herein for simplicity, each of the above-described contact structures, interconnect structures, and metal lines can be formed in or embedded into a dielectric layer including one or more of an ILD layer, a contact etch stop layer (CESL), etc., or combinations thereof, configured to electrically isolate the above-described structures from surrounding electrically conductive components.

[0073] As described herein, still referring to Figure 8 and Figure 9 Each of the active region isolation structures 40 (e.g., the active region isolation structures 40A, 40B) extends along the second direction and truncates the active regions 20 and 22 into separate portions, defining a vertical cell boundary 1 IB of the device 200. Each vertical cell boundary 1 IB is perpendicular to the horizontal cell boundary 11 A. In some embodiments, each active region isolation structure 40 is configured to prevent or otherwise reduce shorting between adjacent devices.

[0074] Figure 10 is a flowchart of a method 400 of forming or fabricating part or all of a semiconductor device, such as any one of the semiconductor devices 100A-100C, in accordance with some embodiments. It should be understood that additional operations can be performed before, during, and / or after the method 400 shown. Figure 10 The method 400 shown can be performed before, during, and / or after additional operations.

[0075] In operation 410 of method 400, a layout design for the semiconductor device is generated. Operation 410 is performed by a processing device configured to execute instructions for generating the layout design (e.g., Figure 11 The processor 502 executes the process. In one method, a layout design is generated by placing one or more standard cells through a user interface. In another method, the layout design is automatically generated by a processor executing a synthesis tool that converts a logic design (e.g., Verilog) into a corresponding layout design. In some embodiments, the layout design is presented in a Graphical Database System (GDSII) file format. In some embodiments, the layout design includes... Figure 8 and Figure 9 Any example layout depicted herein is similar to the layout described herein, each layout depicting an embodiment of the semiconductor device 100C described herein.

[0076] In operation 420 of method 400, a semiconductor device is manufactured based on a layout design. In some embodiments, operation 420 of method 400 includes manufacturing at least one mask based on a layout design, and manufacturing a semiconductor device based on at least one mask. Example manufacturing operations of operation 420 may include patterning, implantation, deposition, etching, planarization, or combinations thereof to form a plurality of front-end process device components (e.g., active regions 20 / 22, source / drain components 24 / 26, metal gate structures 30 / 32, active region isolation structures 40, etc.), device-level (or mid-end process) contacts (e.g., front / back-side source / drain contacts 70 / 82, inter-device source / drain contacts 72, etc.), interconnect structures (or back-end process structures; e.g., front / back-side via contacts 78 / 88A, etc.), and metal lines (or back-end process structures); e.g., front / back-side metal lines 80 / 90, etc.).

[0077] In some embodiments, method 400 is implemented as a standalone software application executed by a processor. In some embodiments, method 400 is implemented as a software application that is part of an additional software application. In some embodiments, method 400 is implemented as a plug-in to a software application. In some embodiments, method 400 is implemented as a software application that is part of an EDA tool. In some embodiments, method 400 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout design for an integrated circuit device. In some embodiments, the layout design is stored on a non-transitory computer-readable medium. In some embodiments, the layout design is generated based on a netlist, which is created based on a schematic design.

[0078] Figure 11is a schematic diagram of a system 500 for designing and manufacturing IC layout designs according to some embodiments. The system 500 generates or places one or more IC layout designs as described herein. In some embodiments, the system 500 manufactures one or more semiconductor devices based on one or more IC layout designs as described herein. The system 500 includes a (e.g., hardware) processor 502 and a non-transitory computer-readable storage medium 504 encoded with (e.g., storing) computer program code 506 (e.g., a set of executable instructions), for example. The computer-readable storage medium 504 is configured to interface with a manufacturing machine for producing semiconductor devices. The processor 502 is electrically coupled to the computer-readable storage medium 504 through a bus 508. The processor 502 is also electrically coupled to an I / O interface 510 through the bus 508. A network interface 512 is also electrically connected to the processor 502 through the bus 508. The network interface 512 is connected to a network 514 so that the processor 502 and the computer-readable storage medium 504 can connect to external elements via the network 514. The processor 502 is configured to execute the computer program code 506 encoded in the computer-readable storage medium 504 to cause the system 500 to be operable to perform some or all of the operations described in the method 400.

[0079] In some embodiments, the processor 502 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit. In some embodiments, the computer-readable storage medium 504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 504 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid disk, and / or an optical disk. In some embodiments that use optical disks, the computer-readable storage medium 504 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0080] In some embodiments, the computer-readable storage medium 504 stores the computer program code 506 configured to cause the system 500 to perform the method 400. In some embodiments, the computer-readable storage medium 504 also stores information required for performing the method 400 and information generated during the performance of the method 400, such as the layout designs 516, the user interface 518, the manufacturing cells 520, and / or a set of executable instructions performing the operations of the method 400.

[0081] In some embodiments, the computer-readable storage medium 504 stores instructions (e.g., computer program code 506) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 506) enable the processor 502 to generate manufacturing instructions readable by the manufacturing machine to effectively implement the method 400 during a manufacturing process.

[0082] The system 500 includes an I / O interface 510. The I / O interface 510 is coupled to external circuits. In some embodiments, the I / O interface 510 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, and / or cursor direction keys to convey information and commands to the processor 502.

[0083] The system 500 also includes a network interface 512 coupled to the processor 502. The network interface 512 allows the system 500 to communicate with a network 514 to which one or more other computer systems are connected. The network interface 512 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-13154. In some embodiments, the method 400 is implemented in two or more systems 500, and information such as layout designs, user interfaces, and manufacturing cells are exchanged between the different systems 500 over the network 514.

[0084] The system 500 is configured to receive information related to a layout design through the I / O interface 510 or the network interface 512. The information is transmitted through the bus 508 to the processor 502 to determine a layout design for producing an IC. The layout design is then stored in the computer-readable storage medium 504 as a layout design 516. The system 500 is configured to receive information related to a user interface through the I / O interface 510 or the network interface 512. The information is stored in the computer-readable storage medium 504 as a user interface 518. The system 500 is configured to receive information related to a manufacturing cell through the I / O interface 510 or the network interface 512. The information is stored in the computer-readable storage medium 504 as a manufacturing cell 520. In some embodiments, the manufacturing cell 520 includes manufacturing information utilized by the system 500.

[0085] In some embodiments, the method 400 is implemented by a manufacturing device to manufacture an integrated circuit using a set of masks based on one or more layout designs generated by the system 500. In some embodiments, the system 500 includes a manufacturing device (e.g., a manufacturing tool 522) to manufacture an integrated circuit using a set of masks based on one or more layout designs of the present disclosure. In some embodiments, Figure 11 The system 500 generates smaller IC layout designs than other methods. In some embodiments, Figure 11The system 500 of the present disclosure generates a layout design of a semiconductor device that occupies less area than other methods.

[0086] Figure 12 is a block diagram of an integrated circuit (IC) / semiconductor device manufacturing system 600 and its associated IC manufacturing flow in accordance with at least one embodiment of the present disclosure.

[0087] In Figure 12 , the IC manufacturing system 600 includes entities, such as a design house 620, a mask house 630, and an IC manufacturer / fabricator (“fab”) 640, that interact with each other in the design, development, and manufacturing cycle and / or services related to manufacturing an IC device (semiconductor device) 660 (e.g., corresponding to any of the devices 100A, 100B, and 200). The entities in the IC manufacturing system 600 are connected through a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is various different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 620, the mask house 630, and the IC manufacturer 640 are owned by a single company. In some embodiments, two or more of the design house 620, the mask house 630, and the IC manufacturer 640 coexist in a common facility and use common resources.

[0088] The design house (or design team) 620 generates an IC design layout 622. The IC design layout 622 includes various geometric patterns designed for the IC device 660. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up various components of the IC device 660 to be manufactured. The various layers combine to form various IC components. For example, portions of the IC design layout 622 include various IC components, such as active regions, gate structures, source / drain regions, interconnect structures, and openings for bond pads to be formed in a semiconductor substrate (such as a silicon wafer), as well as various material layers disposed on the semiconductor substrate. The design house 620 implements appropriate design procedures to form the IC design layout 622. The design procedures include one or more of logic design, physical design, or layout and routing. The IC design layout 622 is presented in the form of one or more data files with geometric pattern information. For example, the IC design layout 622 can be represented in a GDSII file format or a DFII file format.

[0089] The mask room 630 includes mask data preparation 632 and mask manufacturing 634. The mask room 630 uses the IC design layout 622 to manufacture one or more masks for use in fabricating the various layers of the IC device 660 according to the IC design layout 621. The mask room 630 performs mask data preparation 632 in which the IC design layout 622 is converted into a representative data file ("RDF"). The mask data preparation 632 provides the RDF to the mask manufacturing 634. The mask manufacturing 634 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The design layout is manipulated by the mask data preparation 632 to conform to the particular characteristics of the mask writer and / or the requirements of the IC fabricator 640. In Figure 12 In some embodiments, the mask data preparation 632 and the mask manufacturing 634 are shown as separate elements. In some embodiments, the mask data preparation 632 and the mask manufacturing 634 can be collectively referred to as mask data preparation.

[0090] In some embodiments, the mask data preparation 632 includes optical proximity correction (OPC) that uses lithography enhancement techniques to compensate for image errors, such as those that can be caused by diffraction, interference, other process effects, etc. The OPC adjusts the IC design layout 622. In some embodiments, the mask data preparation 632 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat the OPC as an inverse imaging problem.

[0091] In some embodiments, the mask data preparation 632 includes a mask rule checker (MRC) that checks the IC design layout against a set of mask creation rules that contain certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability of the semiconductor fabrication process, etc. In some embodiments, the MRC modifies the IC design layout to compensate for limitations during the mask manufacturing 634, which can undo some of the modifications performed by the OPC to satisfy the mask creation rules.

[0092] In some embodiments, mask data preparation 632 includes lithography process checking (LPC), which simulates the processing to be performed by IC manufacturer 640 to manufacture IC device 660. LPC simulates the processing based on IC design layout 622 to create a simulated manufactured device, such as IC device 660. The processing parameters in the LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as, for example, aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and / or combinations thereof. In some embodiments, after the LPC creates a simulated manufactured device, if the shapes of the simulated device are not close enough to meet design rules, then OPC and / or MRC can be repeated to further refine IC design layout 622.

[0093] It should be appreciated that the above description of mask data preparation 632 has been simplified for the sake of clarity. In some embodiments, mask data preparation 632 includes additional features, such as logic operations (LOPs) that modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to IC design layout 622 during mask data preparation 632 can be performed in various different orders.

[0094] After mask data preparation 632 and during mask manufacturing 634, a mask or set of masks is manufactured based on the modified IC design layout. In some embodiments, based on the modified IC design layout, a pattern is formed on a mask (photomask or reticle) using an electron beam (e-beam) or multiple e-beam mechanism. The mask can be formed using various techniques. In some embodiments, the mask is formed using binary technology. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation (such as an ultraviolet (UV) beam) used to expose a layer of image-sensitive material (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, the mask is formed using phase shift technology. In a phase shift mask (PSM), various components in the pattern formed on the mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by mask manufacturing 634 is used for various processes. For example, such a mask is used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in a semiconductor wafer, and / or for other suitable processes.

[0095] IC manufacturer 640 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturer 640 is a semiconductor foundry. For example, there can be a first manufacturing facility for front-end manufacturing (e.g., active regions 20 / 22, source / drain components 24 / 26, metal gate structures 30 / 32, active region isolation structures 40, etc.) of multiple IC products, while a second manufacturing facility can provide middle-end manufacturing (e.g., front-side / back-side source / drain contacts 70 / 82, inter-device source / drain contacts 72, front-side / back-side gate contacts 74 / 84, etc.) of interconnects for the IC products, and a third manufacturing facility can provide back-end manufacturing (e.g., front-side / back-side via contacts 78 / 88A, front-side / back-side metal lines 80 / 90, etc.) of interconnects and packaging for the IC products, and a fourth manufacturing facility can provide other services for foundry entities.

[0096] IC manufacturer 640 manufactures IC devices 660 using one or more masks manufactured by mask room 630. Thus, IC manufacturer 640 indirectly uses IC design layout 622 to manufacture IC devices 660. In some embodiments, semiconductor wafer 642 is manufactured by IC manufacturer 640 using a mask (or multiple masks) to form IC devices 660. Semiconductor wafer 642 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer also includes one or more of various doped regions, dielectric components, multilevel interconnects, etc. (formed at subsequent manufacturing steps).

[0097] IC manufacturing system 600 is shown as having design room 620, mask room 630, and IC manufacturer 640 as separate components or entities. However, it should be understood that one or more of design room 620, mask room 630, and IC manufacturer 640 are part of the same component or entity.

[0098] Figure 13 A flowchart of a method 700 for forming part or all of a semiconductor device (referred to as a device for simplicity hereinafter) in accordance with one or more embodiments of the present disclosure is shown. In some embodiments, method 700 can be implemented as part or all of manufacturing device 100B and device 200, as described above with reference to FIGS. 1A-1B and 2, respectively. It should be noted that method 700 is merely an example and is not intended to limit the present disclosure. Thus, it should be understood that additional operations can be provided before, during, and after method 700, and some other operations described herein can be omitted. Figure 4 to Figure 6 and Figure 7 to Figure 9 It should be noted that method 700 is merely an example and is not intended to limit the present disclosure. Thus, it should be understood that additional operations can be provided before, during, and after method 700, and some other operations described herein can be omitted.

[0099] Referring to Figure 13At operation 702, an assembly of the intermediate structure of the aforementioned device 100B or device 200 is formed on the front side FS of the substrate. The intermediate structure includes a lower (or first) metal gate structure (structurally similar to the aforementioned lower metal gate structure 182L or any metal gate structure 30, or the lower metal gate structure 982L described below) and an upper (or second) metal gate structure (structurally similar to the aforementioned upper metal gate structure 182U or any metal gate structure 32, or the upper metal gate structure 982U described below) stacked vertically above the first metal gate structure along a third direction. The metal gate structures are separated by a first isolation structure (e.g., the aforementioned intermediate layer 156, intermediate layer 990 described below). The first metal gate structure and the second metal gate structure are coupled with corresponding active regions (e.g., the lower one of the fins 128, the upper one of the fins 128, the lower active region 20 or the upper active region 22) to form a lower device (e.g., any one of the lower devices 210L, 220L, 230L, 240L, or the lower device 910L described below) and an upper device (e.g., any one of the upper devices 210U, 220U, 230U, or the upper device 910U described below).

[0100] In this embodiment, according to one or more embodiments of the present disclosure, reference is made to a semiconductor device 900 (hereinafter referred to as device 900), and it has the following characteristics: Figure 19 The example structure shown in the three-dimensional diagram illustrates the operation of method 700. In this respect, consistent with the descriptions of devices 100A, 100B, and 200, device 900 includes a plurality of upper devices (e.g., upper or second devices 910U) stacked vertically above a plurality of lower devices (e.g., lower or first device 910L) along a third direction. In this respect, the lower device 910L is closer to the back side BS than the upper device 910U.

[0101] Figure 14 A flowchart of a method 800 for forming an intermediate structure of device 900 is shown. In some embodiments, method 800 may be implemented at operation 702 described above. It should be noted that method 800 is merely an example and is not intended to limit this disclosure. Therefore, it should be understood that additional operations may be provided before, during, and after method 800, and only a few other operations may be briefly described herein. In some embodiments, the operation of method 800 may be combined with, for example... Figure 15 to Figure 19 (This will be discussed in detail below) The perspective and cross-sectional views of device 900 at each manufacturing stage are associated.

[0102] refer to Figure 14 and Figure 15At operation 802, a multilayer structure 922’ of alternating first semiconductor layers 924’A, 924’B (or first nanosheets) and second semiconductor layers 926’U, 926’L (or second nanosheets) is formed over a substrate 920.

[0103] In some embodiments, the substrate 920 includes an elemental semiconductor material such as Si. In some implementations, the substrate 920 includes a semiconductor-on-insulator (SOI) structure. For example, the substrate 920 can include a buried oxygen (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding. The substrate 920 can include other suitable semiconductor materials.

[0104] In some embodiments, the multilayer structure 922’ includes an upper portion having alternating first semiconductor material (e.g., first semiconductor layers 924’A) and second semiconductor material (e.g., second semiconductor layers 926’U); a lower portion having alternating first semiconductor material and second semiconductor material (e.g., second semiconductor layers 926’L); and an intermediate layer of a third semiconductor material (e.g., intermediate first semiconductor layers 924’B) that is different in composition from the first and second semiconductor materials. The intermediate layer of the third semiconductor material is interleaved between two layers of the second semiconductor material (e.g., intermediate second semiconductor layers 926’M) configured as a pseudo layer.

[0105] In Figure 15 The multilayer structure 922’ is shown in a state after formation of fins, as described herein. The multilayer structure 922’ includes first semiconductor layers 924’A, 924’B and second semiconductor layers 926’U (i.e., nanosheets 926’U), 926’L (i.e., nanosheets 926L’) arranged alternately. The first semiconductor layers 924’A, 924’B and the second semiconductor layers 926’U, 926’L include semiconductor materials having different etch selectivity and / or oxidation rates. For example, in some embodiments, the first semiconductor layers 924’A, 924’B include SiGe and the second semiconductor layers 926’U, 926’L include Si. In some embodiments, the first semiconductor layers 924’A, 924’B and the second semiconductor layers 926’U, 926’L are formed by a deposition process such as epitaxy. For example, epitaxial growth of the layers of the multilayer structure 922’ is performed by a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0106] At operation 804, a plurality of fins 928 (also referred to as active regions 928) are defined in the multi-layer structure by one or more etching processes. An isolation structure 932 can be formed over the substrate and between the fins. Each fin 928 includes a substrate portion 920’ of the substrate 920 and a portion 934 of the multi-layer structure 922’. The portion 934 of the multi-layer structure 922’ is sometimes referred to as a stack of semiconductor layers 934. In some embodiments, the fins 928 are fabricated using a suitable process, such as a double patterning or multiple patterning process. For example, in one or more embodiments, a sacrificial layer is formed over the substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers are then used to pattern the fins 928 by etching the multi-layer structure 922’ and the substrate 920. Example etching processes include, but are not limited to, dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In Figure 15 In the example shown in FIG. 8, two fins 928 are shown; the number of fins is not limited to two.

[0107] In some embodiments, at operation 804, an isolation structure 932 comprising an insulating material is formed in trenches (not shown) over the substrate 920 and between the fins 928. For example, the insulating material is deposited over the substrate 920 and the fins 928. Example insulating materials of the isolation structure 932 include, but are not limited to, Si02, fluorine-doped silicate glass (FSG), SiN, SiON, SiOCN, SiCN, low-k dielectric materials, and / or the like or a combination thereof. Deposition of the insulating material includes suitable methods, such as low pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD). Then, a planarization operation (such as a CMP process and / or an etch-back process) is performed so that the top of the fins 928 is exposed from the insulating material. Portions of the insulating material between adjacent fins 928 are removed. The remaining portions of the insulating material constitute the isolation structure 932. The portion removal of the insulating material includes dry etching, wet etching, and / or the like.

[0108] Subsequently, still referring to Figure 14 to Figure 16At operation 806, a sacrificial gate structure 942 including a sacrificial gate dielectric layer 936, a sacrificial gate electrode layer 938, and a mask structure 940 is formed over the fins 928. In some embodiments, the sacrificial gate dielectric layer 936 includes one or more layers of dielectric material, such as Si02, SiN, a high-k dielectric material, or the like, or combinations thereof. In some embodiments, the sacrificial gate dielectric layer 936 is deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, an FCVD process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, or other suitable process. In at least one embodiment, the sacrificial gate electrode layer 938 includes polysilicon. In some embodiments, the mask structure 940 includes a multi-layer structure. In some embodiments, the sacrificial gate electrode layer 938 and the mask structure 940 are formed by one or more processes to obtain the device 900, such as layer deposition, e.g., CVD (including LPCVD and PECVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques.

[0109] The sacrificial gate structure 942 is formed by one or more patterning and / or etching processes performed on the deposited sacrificial gate dielectric layer 936, the sacrificial gate electrode layer 938, and the mask structure 940. Example patterning processes include a photolithography process. Example etching processes include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations thereof. Each sacrificial gate structure 942 includes portions of each of the sacrificial gate dielectric layer 936, the sacrificial gate electrode layer 938, and the mask structure 940. The sacrificial gate structure 942 extends or elongates along the second direction. In Figure 16 In the example shown in FIG. 8, three sacrificial gate structures 942 are shown; however, the number of sacrificial gate structures 942 is not limited to two.

[0110] Referring to Figure 14 and Figure 16 At operation 808, a respective spacer 944 is then formed over the sidewalls of the sacrificial gate structure 942. The spacer 944 is formed on the sidewalls of the sacrificial gate structure 942. For example, the spacer 944 is formed by first depositing a conformal layer, and subsequently etching back the conformal layer to form the spacer 944. The spacer 944 includes a dielectric material, such as Si02, SiN, SiC, SiOC, SiON, SiCN, SiOCN, or the like, or combinations thereof. In some embodiments, the spacer 944 includes multiple layers of dielectric material.

[0111] Still referring to Figure 14 and 16At operation 810, trenches 946 (also referred to as source / drain recesses) are formed in each fin 928. For example, exposed portions of the stack 934 of semiconductor layers of the fin 928 not covered by the sacrificial gate structures 942 and the spacers 944 are selectively removed by one or more suitable etching processes (such as dry etching, wet etching, or a combination thereof) to form the trenches 946, which are optionally referred to as source / drain recesses.

[0112] Subsequently, at operation 812, exposed portions of the first semiconductor material in the trenches 946 (e.g., the exposed edge portions of each first semiconductor layer 924’A) and the entire third semiconductor material (e.g., the middle first semiconductor layer 924’B) are then recessed or etched to form a middle opening (not shown). The second semiconductor material (e.g., the second semiconductor layers 926’U, 926’L) remains substantially intact during the recessing at operation 812.

[0113] In particular, at operation 812, the middle first semiconductor layer 924’B is removed by the selective wet etching process. The exposed edge portions of the first semiconductor layers 924’A and the middle second semiconductor layers 926’M are also removed by the selective wet etching process. Figure 16 In particular, the lowermost one of the second semiconductor layers 926’U and the uppermost one of the second semiconductor layers 926’L are designated as middle second semiconductor layers 926’M, with the middle first semiconductor layer 924’B sandwiched between them. The middle second semiconductor layers 926’M and the middle first semiconductor layer 924’B are not configured to form channel regions of the upper device 910U and the lower device 910L. The edge portions of the first semiconductor layers 924’A, 924’B and the second semiconductor layers 926’U, 926’L, 926’M are exposed in the trenches 946. The trenches 946 also expose portions of the substrate portion 920’, resulting in a device 900 as shown in FIG. 9B. Figure 16

[0114] Subsequently, the exposed edge portions of the first semiconductor layers 924’A are replaced. In some embodiments, this replacement is achieved by a selective wet etching process. The selective wet etching process also completely (or substantially completely) removes the middle first semiconductor layer 924’B of the stack 934 of semiconductor layers. For example, in embodiments in which the first semiconductor layers 924’A, 924’B comprise SiGe and the second semiconductor layers 926’U, 926’L, 926’M comprise Si, the selective wet etching is configured to etch the first semiconductor layers 924’B at a highest etch rate, the first semiconductor layers 924’A at a second highest etch rate, and the second semiconductor layers 926’U, 926’L, 926’M at a slowest etch rate. As a result, the exposed edge portions of each of the first semiconductor layers 924’A and all (or substantially all) of each of the first semiconductor layers 924’B are removed, while the second semiconductor layers 926’U, 926’L, 926’M are substantially unchanged.

[0115] ​Subsequently, at operation 814, a dielectric material is deposited in the intermediate openings to form inner spacers 954 and inner isolation structures 956. Examples of the dielectric material forming the inner spacers 954 and the inner isolation structures 956 include SiO2, SiN, SiCN, SiOC, SiOCN, etc.; high-k dielectric materials such as HfO2, ZrO x , ZrAlO x , HfAlO x , HfSiO x , AlO x , etc.; other suitable dielectric materials; or combinations thereof. In some embodiments, the inner spacers 954 and the inner isolation structures 956 include different dielectric materials. In some embodiments, the composition of the inner isolation structures 956 is selected to exhibit etch selectivity with respect to adjacent components, such as the intermediate second semiconductor layer 926’M. In an example process, a conformal layer of the dielectric material is deposited by using a conformal deposition process, such as ALD, followed by an anisotropic etch to remove portions of the conformal layer other than the inner spacers 954 and the inner isolation structures 956, forming the inner spacers 954 and the inner isolation structures 956.

[0116] Referring to Figure 14 and Figure 17 , at operation 816, lower source / drain components 962L and upper source / drain components 962U are formed over the inner spacers 954 and the inner isolation structures 956 in the trenches 946. In some embodiments, a liner 963 and a dielectric layer 968 are formed over the upper surface of the lower source / drain components 962L prior to forming the upper source / drain components 962U. In some embodiments, the lower source / drain components 962L and the upper source / drain components 962U are formed by using an epitaxial process. Figure 17 In an example configuration in

[0117] The lower source / drain feature 962L is formed over and in contact with the exposed portions of the substrate portion 920' and the exposed edge portions of the second semiconductor layer 926'L. Example epitaxial growth processes for growing the source / drain features 962L, 962U include CVD, ALD, MBE, etc. In some embodiments, the lower source / drain feature 962L is grown to a height above the uppermost second semiconductor layer 926'L, and then a top portion of the lower source / drain feature 962L is partially removed, e.g., by dry etching or wet etching, so that an upper surface of the remaining lower source / drain feature 962L is at the level of the uppermost first semiconductor layer 924'A immediately below the middle second semiconductor layer 926'M, as shown in FIG. 9B. Figure 17

[0118] The liner 963 is formed at least over the upper surface of the lower source / drain feature 962L and the exposed side surfaces of the middle second semiconductor layer 926'M, the inner isolation structure 956. In some embodiments, the liner 963 includes SiN. In an example process, the liner 963 includes a conformal layer formed by a conformal process, such as an ALD process. The dielectric layer 968 is formed over the liner 963 and over the lower source / drain feature 962L. In some embodiments, the dielectric layer 968 includes the same material and / or is formed by the same method as the isolation structure 932. The liner 963 and the dielectric layer 968 are removed outside the trench 946 and partially removed inside the trench 946, e.g., by dry etching or wet etching. As a result, as shown in FIG. 9C, the upper surfaces of the liner 963 and the dielectric layer 968 are at the level of the lowermost first semiconductor layer 924'A immediately above the uppermost middle second semiconductor layer 926'M. The liner 963 and the dielectric layer 968 together provide an isolation structure between the lower source / drain feature 962L and the upper source / drain feature 962U formed subsequently thereover. Figure 17

[0119] The upper source / drain feature 962U is formed over and in direct contact with the upper surfaces of the liner 963 and the dielectric layer 968 and the exposed edge portions of the second semiconductor layer 926'U. In some embodiments, the upper source / drain feature 962U is grown to a height above the sacrificial gate dielectric layer 936, and then a top portion of the upper source / drain feature 962U is partially removed, e.g., by dry etching or wet etching, so that an upper surface of the remaining upper source / drain feature 962U is at the level of the sacrificial gate dielectric layer 936, as shown in FIG. 9D. Figure 17 ​​The height of the upper source / drain component 962U is controllable, as shown. This is an example, and the height of the upper source / drain component 962U is controllable depending on the particular application and / or manufacturing process for the device 900.

[0120] Still referring to Figure 14 and Figure 17 The CESL 970 is then formed over the upper source / drain component 962U prior to forming the ILD layer 972 at operation 818. In some embodiments, the CESL 970 is formed over the upper source / drain component 962U prior to forming the ILD layer 972. A chemical mechanical polishing (CMP) process is subsequently performed to planarize the CESL 970 and / or the ILD layer 972. The planarization process also removes portions of the ILD layer 972 and the CESL 970. For example, the exposed sacrificial gate electrode layer 938 and the sacrificial gate dielectric layer 936 are removed by one or more suitable processes, such as dry etching, wet etching, or a combination thereof.

[0121] The CESL 970 is formed over the upper source / drain component 962U prior to forming the ILD layer 972. Example materials for the CESL 970 include SiN, SiCN, SiON, Si02, SiOC, SiOCN, and the like, or a combination thereof. The CESL 970 can be formed by CVD, PECVD, ALD, or any suitable deposition technique. Example materials for the ILD layer 972 include Si02, the low-k dielectric materials described above, and the like, or a combination thereof. The ILD layer 972 can be deposited by a PECVD process or other suitable deposition technique to achieve a device 900 as shown. Figure 17

[0122] Subsequently, with reference to Figure 14 and Figure 18 The sacrificial gate structure 942 and the remaining portion of the first semiconductor layer 924’A are replaced with upper and lower metal gate structures 982U, 982L including a gate dielectric layer 978 and respective gate electrodes at operation 820. The first semiconductor layer 924’A can be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. Removing the first semiconductor layer 924’A exposes the inner spacers 954 and the second semiconductor layers 926’U, 926’L, and creates a space between and around the exposed portions of the second semiconductor layers 926’U, 926’L that are not covered by the inner spacers 954. The exposed portions of the second semiconductor layers 926’U, 926’L provide information about Figure 19 The depicted nanosheets 926’U and 926’L. The intermediate second semiconductor layer 926’M and the inner isolation structure 956 are covered by the liner 963 and the dielectric layer 968, and are substantially unaffected by the removal of the first semiconductor layer 924’A.

[0123] ​Subsequently, upper metal gate structures 982U and lower metal gate structures 982L are formed. In the depicted embodiment, each of the upper metal gate structures 982U formed in the upper portion of the device 900 (i.e., above the inner isolation structure 956) includes a gate electrode 980U, and each of the lower metal gate structures 982L formed in the lower portion of the device 900 (i.e., below the inner isolation structure 956) includes a gate electrode 980L. In some embodiments, the inner isolation structure 956 and the two intervening second semiconductor layers 926’M are collectively referred to as an intervening layer 990, and are configured to at least partially isolate the upper metal gate structures 982U from their respective lower metal gate structures 982L along the third direction. In this regard, the intervening layer 990 is optionally referred to as a (first) isolation structure 990.

[0124] A gate dielectric layer 978 is formed over and around each nanosheet 926’U, 926’L. In some embodiments, the gate dielectric layer 978 includes the same material as the sacrificial gate dielectric layer 936. In some embodiments, the gate dielectric layer 978 includes a dielectric material described above with reference to the gate dielectric layer 178, such as a high-k dielectric material. In some embodiments, the gate dielectric layer 978 is formed by a conformal deposition process, such as an ALD process.

[0125] A gate electrode 980U is formed over and around the gate dielectric layer 978 and the nanosheet 926’U, 926’L. The gate electrode 980U surrounds each nanosheet 926’U, i.e., is disposed above the inner isolation structure 956, and is configured to form each upper metal gate structure 982U. The gate electrode 980L surrounds each nanosheet 926’L, i.e., is disposed below the inner isolation structure 956, and is configured to form each lower metal gate structure 982L. In some embodiments, each of the gate electrodes 980U and 980L includes a material described above with reference to the gate electrode 180U. In some embodiments, the gate electrode material includes one or more work function metals. Example processes for depositing the gate electrode material include, but are not limited to, PVD, CVD, ALD, electroplating, or other suitable methods.

[0126] Figure 19 A schematic perspective view of an embodiment of a portion or all of the device 900 is shown in accordance with some embodiments of the present disclosure. The device 900 can be fabricated using the method 800 described above with reference to FIG. 8. For example, in implementations where the device 900 is a vertical NAND device, the device 900 can be fabricated using the method 800 described above with reference to FIG. 8. Figure 14 A schematic perspective view of an embodiment of a portion or all of the device 900 is shown in accordance with some embodiments of the present disclosure. The device 900 can be fabricated using the method 800 described above with reference to FIG. 8. For example, in implementations where the device 900 is a vertical NAND device, the device 900 can be fabricated using the method 800 described above with reference to FIG. 8. Figure 18After the illustrated operation 820, the device 900 can correspond to a portion of the device 900. In the depicted embodiment, the lower metal gate structure 982L is closer to the substrate 920 (e.g., the backside BS) than the upper metal gate structure 982U. In some embodiments, the metal gate structures 982L, 982U are separated by a first isolation structure 990, also referred to as the middle layer 990. In some embodiments, as described with reference to the devices 100A, 100B, and 200, the upper device 910U and the lower device 910L are configured to have different conductivity types, with the lower device 910L disposed closer to the backside BS than the upper device 910U. For example, the upper device 910U can be configured as an NMOS device, and the lower device 910L can be configured as a PMOS device, or vice versa. In some embodiments, the upper device 910U and the lower device 910L are configured to have the same conductivity type.

[0127] Continuing with the operation 704 of the method 700, with reference to Figure 13 and Figure 21 , a second isolation structure 1100 (e.g., the isolation structure 186 of the device 100B) is formed between the two fins 928 and extends vertically along the sidewalls of the lower (or first) metal gate structure 982L and the upper (or second) metal gate structure 982U formed in the device 900. In some embodiments, as illustrated in Figure 21 and further demonstrated by Figure 1 to Figure 6 , the second isolation structure 1100 is configured to truncate or cut each pair of metal gate structures 982U / 982L into two portions separated along the first direction. Thus, similar to the description of the isolation structure 186, the second isolation structure 1100 is optionally referred to as a gate isolation structure 1100 or a gate cut component 1100. In some embodiments, the second isolation structure 1100 directly contacts the sidewalls of the lower metal gate structure 982L and the upper metal gate structure 982U. In some examples, the operation 704 can be omitted, and the method 700 proceeds directly from the operation 702 to the operation 706. In some examples, the operation 704 can be implemented at a later stage of the method 700.

[0128] With reference to Figure 13 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 and Figure 25At operations 706, 708, and 710, the upper metal gate structure 982U of the upper device 910U is removed from the device 900, and a third isolation structure 1102 (optionally referred to as a dielectric gate structure 1102 similar to the dielectric gate structure 183U of the device 100B) is formed at a location above the first isolation structure 990. In other words, the upper metal gate structure 982U is replaced with the third isolation structure 1102, which is disposed between the pair of upper source / drain components 962U along the first direction. Forming the third isolation structure 1102 in place of the upper metal gate structure 982U makes the upper device 910U a passive device, while the active device is the lower device 910L. In the depicted embodiment, the third isolation structure 1102 extends along the third direction to stop on the upper surface of the intermediate layer 990.

[0129] Referring to Figure 13 , Figure 20 and Figure 21 , at operation 706, the upper metal gate structure 982U is removed from the device 900 to form the trench 1000. In some embodiments, a mask structure 998 comprising a dielectric material such as SiN is first formed over the device 900 to protect portions of the device 900 that are not intended to be etched. Subsequently, a patterned mask PR is formed over the device 900, where the patterned mask PR exposes portions of the mask structure 998 above the second metal gate structure 982U that are to be removed. The patterned mask PR can comprise a photoresist material that can be patterned using photolithography techniques. Subsequently, the mask structure 998 is patterned using the patterned mask PR as an etch mask to expose the second metal gate structure 982U, and then the second metal gate structure 982U is removed using a suitable etching process such as dry etching, wet etching, RIE, or other suitable process to form the trench 1000. The patterned mask PR can then be removed using any suitable method such as plasma ashing or photoresist stripping.

[0130] In some embodiments, by removing the upper metal gate structure 982U, the nanosheet 926’U, the upper one of the intermediate second semiconductor layers 926’M, and in some cases the upper portion of the inner isolation structure 956, the trench 1000 exposes the inner isolation structure 956 to ensure complete removal of the upper metal gate structure 982U. In some embodiments, referring to Figure 21 , forming the trench 1000 also removes portions of the second isolation structure 1100 along the third direction.

[0131] Referring to Figure 13 , Figure 22 and Figure 23At operation 708, a dielectric material is deposited in the trench 1000. The dielectric material can include any suitable material, such as SiO2, SiN, SiON, SiOCN, SiCN, etc., or combinations thereof, as described above with respect to the dielectric gate structures 183L, 183U. The dielectric material can be deposited in the trench 1000 using any suitable deposition process, such as CVD, ALD, PVD, etc., or combinations thereof.

[0132] Referring Figure 13 , Figure 24 and Figure 25 The dielectric material is then planarized at operation 710 to form a third isolation structure 1102. The dielectric material can be planarized using a CMP process, resulting in the third isolation structure 1102 being substantially coplanar with the mask structure 992 disposed above the remaining upper metal gate structures 982U.

[0133] Referring Figure 13 and Figure 26 At operation 712, front-side contact structures are formed above and electrically coupled to a front side of the device 900 including the upper device 910U. The front-side contact structures can include a front-side source / drain contact (e.g., the front-side source / drain contact 70) that is electrically coupled from the front side FS of the substrate 920 to at least some of the upper source / drain components 962U (e.g., the source / drain components 26). The contact structures can also include a front-side gate contact (e.g., the front-side gate contact 74 of the device 200, etc.) that is electrically coupled from the front side FS of the substrate 920 to those of the upper metal gate structures 982U (e.g., the front-side metal gate structures 32) that are not shown in FIG. 11. Figure 26 In this embodiment, since one of the upper metal gate structures 982U is replaced by the third isolation structure 1102, the device 900 does not include a front-side gate contact that is electrically coupled to the third isolation structure 1102, which helps to further reduce capacitance in the device 900.

[0134] In some embodiments, forming the front-side source / drain contacts includes patterning the ILD layer 972 to form trenches that expose the upper source / drain components 962U. A silicide layer 994 is formed above the source / drain components 962U exposed in the trenches, and then the front-side source / drain contacts are formed in each of the trenches and above the silicide layer 994. Example conductive materials for the front-side source / drain contacts include Cu, Co, Ru, Al, Ti, Ta, TiN, TaN, Pt, etc., or combinations (or alloys) thereof. For example, the conductive material for the front-side source / drain contacts can be deposited by any suitable process, such as PVD, ECP, or CVD, and planarized by a CMP process.

[0135] Still referringFigure 13 And Figure 26 At operation 712, front-side interconnect structures (e.g., front-side via contacts 1010) and metallization layers are subsequently formed over and electrically coupled to the front-side contact structures of device 900. In some examples, forming front-side via contacts 1010 (e.g., front-side via contacts 78) can include patterning a stack of mask structure 992, ILD layer 1006, and CESL 1004 to form via openings, and then filling the via openings with a conductive material as described above with respect to the various conductive components of device 200. The conductive material can then be planarized using a CMP process, resulting in front-side via contacts 1010.

[0136] Thereafter, for example, a multilayer interconnect (MLI) structure 1014 is formed over and electrically coupled to the front-side source / drain contacts and any front-side gate contacts. MLI structure 1014 includes a plurality of front-side metal lines 1018A (e.g., front-side metal lines 80 in a front-side metallization layer M0), 1018B (e.g., front-side metal lines 92 in a front-side metallization layer Ml), and 1018C formed over front-side via contacts 1010, and front-side via contacts 1017. In some embodiments, metal lines 1018A are formed in metallization layer M0, metal lines 1018B immediately above metal lines 1018A are formed in metal layer Ml, and so on. MLI structure 1014 also includes various ILD layers 1016 in which the metal lines and via contacts are embedded. Although not shown herein, as part of MLI 1014, additional dielectric layers, front-side via contacts, and front-side metal lines can be formed over front-side metal lines 1018C.

[0137] Referring to Figure 13 And Figure 27 At operation 714, the flipped substrate 920 is polished along line EE’ to remove excess portions of substrate 920 and expose the backside of lower device 910L, including the backside of lower metal gate structure 982L and lower source / drain components 962L, using a CMP process, for example, in preparation for fabricating backside components of device 900.

[0138] Referring to Figure 13 And Figure 28At operation 716, backside contact structures, interconnect structures, and metallization layers similar to those on the front side FS of the device 900 are formed over the backside BS of the lower device 910L, and are electrically coupled to the backside BS of the lower device 910L. The backside contact structures, interconnect structures, and metallization layers can be formed in processes similar to those of the corresponding front side components, and thus are only briefly described below.

[0139] In some embodiments, dielectric layers 1028 and 1030 are formed on the backside of the lower device 910L. The dielectric layers 1028 and 1030 are patterned to form trenches in which silicide layers 1034 and backside source / drain contacts 1040 (e.g., backside source / drain contacts 82) over the silicide layers 1034 are formed. In this regard, the backside source / drain contacts 1040 are electrically coupled to the backside of the lower source / drain components 962L (e.g., source / gate features 24). Subsequently, dielectric layers 1048 and 1050 similar to the dielectric layers 1028 and 1030, respectively, are formed over the backside source / drain contacts 1040. The dielectric layers 1048 and 1050 are patterned to form trenches in which backside via contacts 1060 (e.g., backside via contacts 88A) and backside gate contacts 1062 (e.g., backside gate contacts 84 of the device 200) are formed, and are electrically coupled to their respective backside source / drain contacts 1040 and lower metal gate structures 982L, respectively. Although not shown herein, at least one backside metal line (e.g., backside metal line 90) can be formed as part of a backside metallization layer BM0 that is electrically coupled to at least the backside gate contacts 1062 to facilitate transmission of signals (e.g., output signals ZN) from the backside BS to the front side FS as described in detail above with respect to the device 200. Moreover, additional dielectric layers, backside via contacts, and backside metal lines can be formed over the backside metal line. Figure 7 and Figure 9 The backside source / drain contacts 1040 are electrically coupled to the backside of the lower source / drain components 962L (e.g., source / gate features 24). Subsequently, dielectric layers 1048 and 1050 similar to the dielectric layers 1028 and 1030, respectively, are formed over the backside source / drain contacts 1040. The dielectric layers 1048 and 1050 are patterned to form trenches in which backside via contacts 1060 (e.g., backside via contacts 88A) and backside gate contacts 1062 (e.g., backside gate contacts 84 of the device 200) are formed, and are electrically coupled to their respective backside source / drain contacts 1040 and lower metal gate structures 982L, respectively. Although not shown herein, at least one backside metal line (e.g., backside metal line 90) can be formed as part of a backside metallization layer BM0 that is electrically coupled to at least the backside gate contacts 1062 to facilitate transmission of signals (e.g., output signals ZN) from the backside BS to the front side FS as described in detail above with respect to the device 200. Moreover, additional dielectric layers, backside via contacts, and backside metal lines can be formed over the backside metal line.

[0140] Figure 29 A flowchart illustrating a method 1200 for forming part or all of a device in accordance with one or more embodiments of the present disclosure is shown. In some embodiments, the method 1200 can be implemented to manufacture the device 100A described above with reference to FIGS. 1A-1C. It should be noted that the method 1200 is an example and is not intended to limit the present disclosure. Therefore, it is to be understood that additional operations can be provided before, during, and after the method 1200, and some of the operations described herein can be modified or eliminated, and Figure 1 to Figure 3 some other operations can be added, without departing from the scope of the present disclosure. Moreover, the operations of the method 1200 can be similar to those of the method 700 described above, and thus are only briefly described below for the sake of brevity.

[0141] For simplicity, the method 1200 is described below with reference to the device 900 shown in FIGS. 9A and 9B. Figure 18 and Figure 19 At operation 1202, similar to operation 702, components of an intermediate structure of the device 900 are formed on the front side FS of the substrate. The intermediate structure includes a lower (or first) metal gate structure 982L and an upper (or second) metal gate structure 982U vertically stacked above the lower metal gate structure 982L along the third direction, the metal gate structures 982L, 982U separated by a first isolation structure 990.

[0142] Subsequently, at operation 1204, similar to operation 704, a second isolation structure 1100 is formed adjacent to one of the fins 928 and extends vertically along sidewalls of the metal gate structures 982L, 982U formed in the device 900.

[0143] At operation 1206, similar to operation 712, front side contact structures, front side interconnect structures, and metallization layers are formed over and electrically coupled to the front side of the device 900, including the upper device 910U. Thereafter, at operation 1208, similar to operation 714, the substrate 920 is flipped to expose the back side BS of the substrate 920 in preparation for fabricating back side components of the device 900.

[0144] At operation 1210, the lower metal gate structure 982L is then removed from the back side BS of the device 900 by a series of photolithography and etching processes similar to those described above with reference to operation 706 to form a trench, except that the processes of operation 1210 are implemented from the back side BS of the substrate 920. Similar to operations 708 and 710, dielectric material is deposited to fill the trench at operations 1212 and 1214, respectively, followed by planarization to form a third isolation structure (optionally referred to as a dielectric gate structure similar to the dielectric gate structure 183U of the device 100B) in place of the lower metal gate structure 982U. As a result, forming the third isolation structure in place of the lower metal gate structure 982L renders the lower device 910L a passive device, while the upper device 910U is an active device.

[0145] Subsequently, at operation 1216, similar to operation 716, back side contact structures, interconnect structures, and metallization layers are formed over and electrically coupled to the back side BS of the lower device 910L similar to those on the front side FS of the device 900.

[0146] Although structures and methods will be discussed in terms of CFET-structured devices, one of ordinary skill in the art will appreciate that the structures and methods are not limited to this and that certain aspects of the embodiments discussed are suitable for inclusion in manufacturing processes for other classes and configurations of IC devices. The structures and methods disclosed herein are equally applicable to various manufacturing processes for implementing vertically-stacked structures, including monolithic CFET manufacturing processes and sequential CFET manufacturing processes.

[0147] It should be understood that not all advantages are necessarily discussed, not all embodiments or examples necessarily include all the advantages, and other embodiments or examples can provide different advantages.

[0148] In some aspects, the disclosure provides a semiconductor device, comprising: an active gate structure disposed above a substrate; first source / drain components disposed on two opposite sides of the active gate structure; a dielectric gate structure disposed above the substrate, the dielectric gate structure and the active gate structure stacked with each other along a vertical direction perpendicular to the substrate; and second source / drain components disposed on two opposite sides of the dielectric gate structure, wherein the first source / drain components and the second source / drain components have different conductive types.

[0149] The disclosure provides a semiconductor device, comprising: an active gate structure disposed above a substrate; first source / drain components disposed at two opposite sides of the active gate structure; a dielectric gate structure disposed above the substrate, the dielectric gate structure and the active gate structure stacked with each other along a first direction; and second source / drain components disposed at two opposite sides of the dielectric gate structure, wherein the first source / drain components and the second source / drain components have different conductive types.

[0150] In some embodiments, the first source / drain components have n-type conductivity, and the second source / drain components have p-type conductivity.

[0151] In some embodiments, the first source / drain components have p-type conductivity, and the second source / drain components have n-type conductivity.

[0152] In some embodiments, the semiconductor device further comprises a semiconductor layer extending between the first source / drain components or between the second source / drain components along a second direction perpendicular to the first direction, wherein the semiconductor layer is wrapped by the active gate structure.

[0153] In some embodiments, the semiconductor device further comprises an isolation structure disposed between the active gate structure and the dielectric gate structure.

[0154] In some embodiments, the isolation structure comprises a dielectric layer interposed between at least two semiconductor layers.

[0155] In some embodiments, the semiconductor device further comprises an internal spacer embedded in the dielectric gate structure.

[0156] In some aspects, the disclosure provides a semiconductor device, comprising: an active device disposed above a front side of a substrate, and comprising: gate structures extending along a first lateral direction, and first source / drain components separated by the gate structures along a second lateral direction perpendicular to the first lateral direction; and a passive device disposed above the front side of the substrate, the passive device and the active device stacked with each other along a vertical direction perpendicular to the first lateral direction, the passive device comprising: an isolation structure extending along the first lateral direction; and second source / drain components separated by the isolation structure along the second lateral direction, wherein the first source / drain components and the second source / drain components have different conductivity types.

[0157] In some aspects, the disclosure provides a semiconductor device, comprising an active device and a passive device, the active device disposed above a front side of a substrate, and the active device comprising: metal gate structures extending along a first direction, and first source / drain components separated by the metal gate structures along a second direction perpendicular to the first direction; the passive device disposed above the front side of the substrate, the passive device and the active device stacked with each other along a third direction perpendicular to the first direction and the second direction, the passive device comprising: an isolation structure extending along the first direction; and second source / drain components separated by the isolation structure along the second direction, wherein the first source / drain components and the second source / drain components have different conductivity types.

[0158] In some embodiments, wherein: the isolation structure is a first isolation structure, and the semiconductor device further comprises a second isolation structure disposed between one of the first source / drain components and one of the second source / drain components.

[0159] In some embodiments, the semiconductor device further comprises a gate isolation structure extending along the second direction, wherein sidewalls of the gate isolation structure extend along sidewalls of the metal gate structures and sidewalls of the isolation structure in the third direction.

[0160] In some embodiments, the sidewalls of the gate isolation structure directly contact the sidewalls of the metal gate structures and the sidewalls of the isolation structure.

[0161] In some embodiments, the isolation structure is a first isolation structure, and the semiconductor device further includes a second isolation structure disposed between one of the first source / drain components and one of the second source / drain components.

[0162] In some embodiments, the semiconductor device further includes an intermediate layer disposed between the metal gate structure and the isolation structure.

[0163] In some embodiments, the semiconductor device further includes a first internal spacer disposed between one of the first source / drain components and the metal gate structure, and a second internal spacer disposed between one of the second source / drain components and the isolation structure, wherein the first internal spacer and the second internal spacer are aligned along the third direction.

[0164] In some embodiments, the semiconductor device further includes a third internal spacer disposed between one of the second source / drain components and the isolation structure, the third internal spacer disposed between the first internal spacer and the second internal spacer along the third direction.

[0165] In some embodiments, wherein: the substrate includes a backside opposite the frontside, the active device is disposed closer to the backside of the substrate than the passive device, and the semiconductor device further includes a metallization layer disposed on the backside of the substrate and electrically coupled to the active device.

[0166] In some aspects, the disclosure provides a method, comprising: forming a semiconductor device on a frontside of a substrate, the semiconductor device including a first active gate structure and a second active gate structure stacked on each other and separated by a first isolation structure; removing one of the first active gate structure or the second active gate structure to form a trench; and forming a second isolation structure in the trench such that the first active gate structure.

[0167] In some embodiments, the method further includes, prior to removing one of the first active gate structure or the second active gate structure, forming a third isolation structure extending along sidewalls of the first active gate structure and the second active gate structure.

[0168] In some embodiments, forming the second isolation structure includes depositing a dielectric layer in the trench and planarizing the dielectric layer.

[0169] In some embodiments, wherein: the substrate includes a backside opposite the frontside, the first active gate structure is disposed closer to the backside of the substrate than the second active gate structure, and the method further includes forming a metallization layer over the backside of the substrate, the metallization layer electrically coupled to the first active gate structure.

[0170] The foregoing summary of features of several embodiments has been presented for the purposes of illustration so that those skilled in the art can better understand the aspects of the disclosure. It will be appreciated that those skilled in the art will be able to devise other processes and structures that, although perhaps not explicitly described or shown herein, embody the principles of the disclosure and achieve the same results, that are within the spirit and scope of the disclosure. As such, their teaching will be within the purview of the disclosure, and they are intended to be covered by the following claims, as well as in the numerous alternatives and equivalents thereof.

Claims

1. A semiconductor device, comprising: an active gate structure disposed above a substrate; first source / drain components disposed at two opposite sides of the active gate structure; a dielectric gate structure disposed above the substrate, the dielectric gate structure and the active gate structure being stacked with each other along a first direction; and second source / drain components disposed at two opposite sides of the dielectric gate structure, wherein the first source / drain components and the second source / drain components have different conductivity types. The first source / drain components have n-type conductivity, and the second source / drain components have p-type conductivity.

2. The semiconductor device of claim 1, wherein, The first source / drain components have p-type conductivity, and the second source / drain components have n-type conductivity.

3. The semiconductor device of claim 1, wherein, The semiconductor layer is wrapped by the active gate structure.

4. The semiconductor device according to claim 1, further comprising a semiconductor layer extending between the first source / drain parts or between the second source / drain parts along a second direction perpendicular to the first direction, wherein, 5. The semiconductor device of claim 4, further comprising an isolation structure disposed between the active gate structure and the dielectric gate structure. The isolation structure includes a dielectric layer interposed between at least two semiconductor layers.

6. The semiconductor device of claim 5, wherein, 7. The semiconductor device of claim 1, further comprising an internal spacer embedded in the dielectric gate structure.

8. A semiconductor device, comprising: an active device disposed above a front side of a substrate, and including: a metal gate structure extending along a first direction, and first source / drain components separated by the metal gate structure along a second direction perpendicular to the first direction; and a passive device disposed above the front side of the substrate, the passive device and the active device being stacked with each other along a third direction perpendicular to the first direction and the second direction, the passive device including: an isolation structure extending along the first direction; and second source / drain components separated by the isolation structure along the second direction, wherein the first source / drain components and the second source / drain components have different conductivity types.

9. The semiconductor device of claim 8, wherein: the isolation structure is a first isolation structure, and the semiconductor device further includes a second isolation structure disposed between one of the first source / drain components and one of the second source / drain components.

10. A method of manufacturing a semiconductor device, comprising: forming a semiconductor device on a front side of a substrate, the semiconductor device including first and second active gate structures stacked with each other and separated by a first isolation structure; removing one of the first or second active gate structures to form a trench; and forming a second isolation structure in the trench. ​ ​

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