A method for predicting a seal ring delamination defect

Abstract

A method for predicting a seal ring peeling defect, the method comprising: providing a wafer which has completed a front-end process and formed with a seal ring; performing at least one annealing process on the wafer, and performing a defect detection on the seal ring after each of the annealing processes; and evaluating a risk of the wafer having a seal ring peeling defect in a subsequent backside illumination process based on a detection result of the defect detection. The present application can predict a risk of the seal ring having a peeling defect in the backside illumination process in the front-end process, thereby saving cost and improving yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for predicting sealing ring peeling defects. Background Technology

[0002] Back-illuminated CMOS (or Back-Side Illuminated CMOS) image sensors are often abbreviated as BSI CMOS. Compared to traditional front-illuminated structures, the BSI structure swaps the positions of the photodiode and the metal circuit layer. Its layered structure from top to bottom consists of: microlens, color filter, photodiode, and circuit layer. This structure effectively improves the quantum efficiency of CMOS image sensors, giving them superior performance under low-light conditions.

[0003] A sealing ring is a closed ring structure formed by stacking multiple metal layers and metal vias around the edge of a chip cell. Its core function is to resist mechanical stress from damaging the core functional areas inside the chip during wafer dicing, effectively preventing external moisture and impurities from intruding into the chip from the sides after dicing, thus ensuring the chip's long-term reliability. By grounding the sealing ring, external noise interference can be shielded. Simultaneously, it can conduct static electricity generated during dicing to the nearest ground wire and share the instantaneous large current with the sealing rings of adjacent chips, thereby minimizing the electrical impact on the chip itself.

[0004] In the BSI manufacturing process, the wafer undergoes multiple high-temperature processes, such as wafer bonding and the deposition of high-stress thin films like silicon nitride. These high-temperature processes cause continuous changes and redistribution of stress within the wafer. Because the sealing ring structure itself is composed of multiple layers of thin films made of various materials, its inherent internal stress is relatively high, making it more sensitive to stress fluctuations caused by the process. If the sealing ring's structural design is mismatched with the process stress, its stress fluctuations during high-temperature processes will be significantly greater than in other areas of the chip, easily leading to peeling defects at the interfaces between layers.

[0005] Currently, this peeling defect problem is typically only detected after the entire BSI process is completed. This means that once the defect is discovered, the entire BSI process (including wafer bonding and thinning processes) is scrapped, resulting in significant material and time cost losses. Existing technology lacks a method to effectively assess and predict the reliability of the sealing ring in subsequent BSI processes, especially in the front-end process stages. Summary of the Invention

[0006] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] To address the existing problems, one embodiment of the present invention provides a method for predicting sealing ring peeling defects, used in a back-illuminated CMOS image sensor, the method comprising:

[0008] Provide wafers with completed front-end processes and formed sealing rings;

[0009] The wafer is subjected to at least one annealing process, and a defect detection is performed on the sealing ring after each annealing process;

[0010] The risk of the wafer experiencing a sealing ring peeling defect in subsequent back-illuminated processes is assessed based on the detection results of the defect detection.

[0011] In one embodiment, the annealing process is planned multiple times, and the method further includes:

[0012] Based on the defect detection results after each annealing process, it is determined whether to perform the next annealing process. If the detection results meet the preset requirements, the next annealing process is performed; otherwise, the next annealing process is not performed, and the risk of the wafer experiencing sealing ring peeling defects in subsequent back-illuminated processes is determined to be high.

[0013] When the number of annealing processes reaches the planned number, and the defect detection result performed after the last annealing process meets the preset requirements, the risk of the wafer experiencing a sealing ring peeling defect in the subsequent back-illuminated process is determined to be low.

[0014] In one embodiment, the annealing process is planned to be performed four times or more.

[0015] In one embodiment, prior to performing the annealing process on the wafer, the method further includes:

[0016] Initial defect detection is performed on the sealing ring of the wafer to obtain initial detection results;

[0017] The assessment of the risk of seal ring peeling defects in subsequent back-illuminated processes based on the defect detection results includes:

[0018] The defect detection results after the annealing process are compared with the initial defect detection results to obtain a comparison result;

[0019] The risk of the wafer experiencing sealing ring peeling defects in subsequent back-illuminated processes is assessed based on the comparison results.

[0020] In one embodiment, the comparison result includes whether the sealing ring has new defects and / or the number of newly added defects compared to the initial defect detection result.

[0021] In one embodiment, the annealing process includes alloy annealing.

[0022] In one embodiment, the temperature range of the alloy annealing treatment is 350°C to 450°C, and the time range of the alloy annealing treatment is 120 minutes to 240 minutes.

[0023] In one embodiment, the atmosphere used for the annealing process includes nitrogen, hydrogen, or a mixture of nitrogen and hydrogen.

[0024] In one embodiment, the front-end process includes forming a circuit structure and a metal interconnect layer on the front side of the wafer, the metal interconnect layer also serving to form the sealing ring;

[0025] The back-illuminated process includes bonding the front side of the wafer to a carrier wafer, thinning the back side of the wafer under the support of the carrier wafer, and forming an optical structure on the back side of the wafer after thinning.

[0026] The method for predicting peeling defects of sealing rings according to embodiments of the present invention simulates the high-temperature environment of the sealing ring in the subsequent back-illuminated process by annealing. It can predict the risk of peeling defects of the sealing ring in the back-illuminated process in the front-end process, effectively shortening the defect verification cycle and saving the carrier wafer. Attached Figure Description

[0027] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0028] In the attached image:

[0029] Figure 1 A schematic diagram of a sealing ring peeling defect occurring in a BSI device is shown;

[0030] Figure 2 A schematic flowchart of a method for predicting sealing ring peeling defects according to a specific embodiment of the present invention is shown.

[0031] Figure 3A A schematic diagram of the sealing ring formed after the upstream process is shown;

[0032] Figure 3BA schematic diagram of the sealing ring after the back-illuminated process is shown. Detailed Implementation

[0033] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0034] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0036] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0038] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0039] The manufacturing process of CMOS image sensors includes front-end processes and subsequent back-illuminated processes. The front-end processes involve forming transistors and metal interconnect layers on the front side of the wafer; these interconnect layers also form the sealing ring. The back-illuminated process involves bonding the front side of the wafer to a carrier wafer, thinning the back side of the wafer under the support of the carrier wafer, and forming optical structures on the thinned back side of the wafer. In the back-illuminated process, the wafer undergoes multiple high-temperature treatments. After these high temperatures, the stress on the wafer changes continuously, especially when bonding to the carrier wafer or depositing high-stress films such as silicon nitride (SiN). Due to the numerous layers in the sealing ring, the stress is high, and the stress fluctuations are relatively large. If the design is not reasonable, the stress fluctuations in the sealing ring will be greater than in other areas of the wafer, leading to delamination defects in the sealing ring. Figure 1 As shown.

[0040] To address the aforementioned problems, embodiments of the present invention propose a method for predicting sealing ring peeling defects, applicable to back-illuminated CMOS image sensors. The following refers to... Figure 2 , Figure 3A and Figure 3B The method for predicting sealing ring peeling defects according to embodiments of the present invention will be described in detail, wherein, Figure 2 A flowchart illustrating the steps of a method for predicting sealing ring peeling defects according to an embodiment of the present invention is shown. Figure 3A A schematic diagram of the sealing ring formed after the upstream process is shown; Figure 3B A schematic diagram of the sealing ring after the back-illuminated process is shown.

[0041] First, step S201 is executed, providing a wafer that has completed the front-end process and has formed a sealing ring, such as... Figure 3A As shown.

[0042] In this embodiment of the invention, a wafer with completed front-end processes refers to a wafer on which all front-side circuit structures of a CMOS image sensor have been fabricated. Its front-end processes mainly include the formation of circuit structures and metal interconnect layers. The circuit structures include active and passive devices such as transistors, diodes, capacitors, and resistors formed on the front side of the wafer.

[0043] For example, in the front-end process, an active region is first defined on the semiconductor substrate 301 using shallow trench isolation technology. Then, a photodiode serving as a photosensitive unit is formed within the active region using processes such as ion implantation, and the fabrication of a MOSFET transistor for signal readout is completed, including the formation of the gate structure and source / drain regions. Next, a metal interconnect layer is formed above the circuit structure to complete the electrical connection: first, an interlayer dielectric layer is deposited and planarized using chemical mechanical polishing; then, contact holes are formed using photolithography and etching processes, typically filled with tungsten plugs to connect the circuit structure. Subsequently, a multilayer metal interconnect structure, including vias and metal wires, is sequentially constructed through repeated damascene processes. The metal material used is typically copper or aluminum, and the layers are isolated by an interlayer dielectric layer.

[0044] While serving as a chip protection structure, the sealing ring 302 is also formed simultaneously in the aforementioned front-end process. Figure 3A The sealing ring 302 comprises four metal layers and contact holes between each metal layer, but this is only an example. During the construction of each metal layer and contact hole, the same photolithography and etching steps are used to simultaneously form a sealing ring pattern made of the same material inside the scribe line at the chip edge. This process is repeated cyclically to ultimately form a sealing ring 302 that starts from the semiconductor substrate 301, runs through the entire interlayer dielectric layer, and is composed of multiple metal layers and vertically interconnected contact holes. This sealing ring 302 is completed simultaneously with the chip body, surrounding the core functional area of ​​the chip, but it is electrically isolated from the internal circuitry. It is typically grounded through the semiconductor substrate to provide mechanical support, prevent crack propagation, block external moisture intrusion, and provide electrostatic discharge protection.

[0045] Next, step S202 is performed to anneal the wafer at least once, and to perform defect detection on the sealing ring after each annealing process; and step S203 is performed to assess the risk of sealing ring peeling defects in the wafer during subsequent back-illuminated processes based on the detection results of the defect detection.

[0046] Since the sealing ring peeling defect is mainly induced in the back-illuminated process, but its root cause is the unreasonable design of the front-end process, the embodiments of the present invention simulate the high-temperature environment of the wafer in the subsequent back-illuminated process by annealing after the front-end process and before the back-illuminated process, actively exposing the potential defects of the sealing ring structure, thereby predicting the risk of sealing ring peeling defects in the subsequent back-illuminated process, which can effectively shorten the defect verification cycle and save the carrier wafer.

[0047] For example, before any heat treatment, an initial defect inspection is performed on the wafer's sealing ring region using an optical defect inspection machine or scanning electron microscope. The purpose of this inspection is to obtain the initial state of the sealing ring, record all existing defects and their locations and quantities, forming an initial inspection result as a benchmark for subsequent evaluation. During the subsequent evaluation, the inspection results of defects after annealing can be compared with the initial defect inspection results to obtain a comparison result; based on the comparison result, the risk of sealing ring peeling defects in subsequent back-illuminated processes is assessed. The comparison result includes whether new defects have appeared in the sealing ring and / or the number of newly added defects compared to the initial defect inspection results.

[0048] Before entering the prediction process, the sealing ring of a wafer may have inherent initial defects of varying degrees. If only the inspection results after heat treatment are used as the criterion, it will be difficult to distinguish the source of these defects. This invention uses a comparison of the defect conditions before and after heat treatment to assess the risk of sealing ring peeling, rather than relying solely on the absolute results after heat treatment. This effectively eliminates the interference of the wafer's initial state, considering only defects newly introduced or exacerbated by applied thermal stress, thus ensuring the accuracy of risk prediction.

[0049] Next, at least one annealing process is performed, and defect detection is conducted on the sealing ring after each annealing process. The annealing process can be alloy annealing, with each alloy annealing process ranging from 350°C to 450°C and from 120 minutes to 240 minutes. Alloy annealing is chosen to predict the risk of sealing ring peeling because its process conditions are more compatible with back-illuminated processes. Alloy annealing is typically performed in a medium-temperature range, where the long-duration thermal budget pattern is similar to the thermal environment experienced by wafer bonding or stress film deposition in back-illuminated processes. This simulates the continuous thermal stress induced by multiple high-temperature processes in back-illuminated processes, effectively inducing a similar stress state at the multilayer interfaces of the sealing ring. Furthermore, alloy annealing can be performed in an inert or reducing atmosphere, which prevents material oxidation at high temperatures, ensuring that any observed defects are purely due to interface peeling induced by thermomechanical stress, rather than other side reactions. For example, the atmosphere used for the annealing process includes nitrogen, hydrogen, or a mixture of nitrogen and hydrogen.

[0050] For example, the annealing process is planned to be performed multiple times. After each annealing process, the decision to proceed with the next annealing process is based on the defect detection results. If the detection results meet preset requirements, the next annealing process is performed; otherwise, it is not. The risk of the wafer experiencing a seal ring peeling defect in the subsequent back-illuminated process is then assessed as high risk. When the planned number of annealing processes is reached, and the defect detection results performed after the last annealing process meet preset requirements, the risk of the wafer experiencing a seal ring peeling defect in the subsequent back-illuminated process is assessed as low risk. To better simulate the high-temperature environment the wafer experiences in the back-illuminated process, the planned number of annealing processes is greater than or equal to four.

[0051] Taking a planned number of times as an example, the steps for annealing and defect detection are as follows:

[0052] First, the wafer is fed into the annealing furnace tube for the first annealing treatment, which is an alloy annealing treatment. The process conditions are as follows: the alloy annealing temperature is 400°C, the treatment time is 180 minutes, and the atmosphere used is a mixture of nitrogen and hydrogen.

[0053] After the first annealing process is completed, the wafer is removed and cooled to room temperature. Defect detection is then performed on the sealing ring of the wafer to obtain the detection results of the first annealing process. Based on the detection results of the first defect detection, it is determined whether to perform the next annealing process.

[0054] Specifically, the test results after the first annealing treatment can be compared with the initial test results to determine whether new defects have appeared in the sealing ring and / or whether the number of new defects exceeds a preset threshold. If the comparison results show that new defects have appeared in the sealing ring or the number of new defects exceeds the preset threshold, the test results are determined to not meet the preset requirements. In this case, the next annealing treatment will not be performed, and the risk of sealing ring peeling defects in the subsequent back-illuminated process of this wafer will be directly assessed as high risk. If the comparison results show that no new defects have appeared or the number of new defects is within the preset threshold, the test results are determined to meet the preset requirements, and the next annealing treatment will be performed.

[0055] For wafers that pass the first test, annealing and defect detection are repeated. After each defect detection, a high-risk predicted structure is output or the next annealing process is performed based on the result of the defect detection.

[0056] If a wafer undergoes four consecutive annealing processes and defect inspections, and the inspection results for each defect inspection meet the preset requirements, then the final assessment indicates that the risk of the wafer experiencing a seal ring peeling defect in the subsequent back-illuminated process is low. This demonstrates that the seal ring structure of the wafer is reasonable and it can safely proceed to the subsequent back-illuminated process.

[0057] For example, such as Figure 3B As shown, the back-illuminated process includes bonding the front side of the wafer to a carrier wafer 303, thinning the back side of the wafer under the support of the carrier wafer 303, and forming an optical structure on the thinned back side of the wafer. The optical structure includes microlenses, color filters, etc. After completing the front-end processes, photodiodes, transistors, and metal interconnect layers have been fabricated on the front side of the wafer. At this point, if light were to enter from the front, it would be blocked by the metal layer, resulting in low efficiency. In the back-illuminated process, the front side of the wafer is first fixed to a temporary or permanent carrier wafer by adhesive bonding or direct bonding. The role of the carrier wafer is to provide mechanical support for the thinned wafer in subsequent steps, preventing it from breaking. Next, the wafer is mechanically ground and chemically polished from the back side, thinning it to a thickness of tens of micrometers. This allows light to directly enter the photodiode from the back side, avoiding the obstruction of the metal interconnects. Then, the optical structure is fabricated on the thinned back side. First, a color filter array is fabricated on the back of the wafer using processes such as coating, photolithography, and etching, with each filter corresponding to one pixel. Next, a microlens array is formed on top of the color filters using a similar process. The function of the microlenses is to focus more incident light onto the corresponding photodiode, thereby significantly improving the sensor's light sensitivity. This invention eliminates the need to detect sealing ring peeling after numerous processes such as bonding, thinning, and optical structure fabrication; instead, it verifies the risk of sealing ring peeling beforehand, saving numerous steps and conserving the carrier wafer.

[0058] Thus, the process steps for implementing the method for predicting sealing ring peeling defects according to the first aspect embodiment of the present invention are completed. It is understood that the method for predicting sealing ring peeling defects in this embodiment includes not only the above-described steps, but may also include other necessary steps before, during or after the above-described steps, all of which are included within the scope of the manufacturing method of this embodiment.

[0059] The method for predicting peeling defects of sealing rings according to embodiments of the present invention simulates the high-temperature environment of the sealing ring in the subsequent back-illuminated process by annealing. It can predict the risk of peeling defects of the sealing ring in the back-illuminated process in the front-end process, effectively shortening the defect verification cycle and saving the carrier wafer.

[0060] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for predicting sealing ring peeling defects, used in a back-illuminated CMOS image sensor, characterized in that, The method includes: Provide wafers with completed front-end processes and formed sealing rings; The wafer is subjected to at least one annealing process, and a defect detection is performed on the sealing ring after each annealing process; The risk of the wafer experiencing a seal ring peeling defect in subsequent back-illuminated processes is assessed based on the detection results of the defect detection. Before performing the annealing process on the wafer, the method further includes: Initial defect detection is performed on the sealing ring of the wafer to obtain initial detection results; The assessment of the risk of seal ring peeling defects in subsequent back-illuminated processes based on the defect detection results includes: The defect detection results after the annealing process are compared with the initial defect detection results to obtain a comparison result; The risk of the wafer experiencing sealing ring peeling defects in subsequent back-illuminated processes is assessed based on the comparison results.

2. The method according to claim 1, characterized in that, The annealing process is planned to be performed multiple times, and the method further includes: Based on the defect detection results after each annealing process, it is determined whether to perform the next annealing process. If the detection results meet the preset requirements, the next annealing process is performed; otherwise, the next annealing process is not performed, and the risk of the wafer experiencing sealing ring peeling defects in subsequent back-illuminated processes is determined to be high. When the number of annealing processes reaches the planned number, and the defect detection result performed after the last annealing process meets the preset requirements, the risk of the wafer experiencing a sealing ring peeling defect in the subsequent back-illuminated process is determined to be low.

3. The method according to claim 2, characterized in that, The planned number of annealing processes is greater than or equal to four.

4. The method according to claim 1, characterized in that, The comparison results include whether new defects and / or the number of newly added defects appear in the sealing ring compared with the initial defect detection results.

5. The method according to claim 1, characterized in that, The annealing process includes alloy annealing.

6. The method according to claim 5, characterized in that, The temperature range for the alloy annealing treatment is 350°C to 450°C, and the time range for the alloy annealing treatment is 120 minutes to 240 minutes.

7. The method according to claim 1, characterized in that, The atmosphere used in the annealing process includes nitrogen, hydrogen, or a mixture of nitrogen and hydrogen.

8. The method according to claim 1, characterized in that, The front-end process includes forming a circuit structure and a metal interconnect layer on the front side of the wafer, the metal interconnect layer also serving to form the sealing ring; The back-illuminated process includes bonding the front side of the wafer to a carrier wafer, thinning the back side of the wafer under the support of the carrier wafer, and forming an optical structure on the back side of the wafer after thinning.

Images