Semiconductor structure

Abstract

A semiconductor structure comprises a substrate, an active device and a passive device, wherein the active device and the passive device are arranged above the substrate. The active device is arranged in the first area of the substrate, and the passive device is arranged in the second area of the substrate. The semiconductor structure further comprises a shielding structure and a protection layer. The shielding structure comprises a barrier layer and a top cover layer, the barrier layer is positioned above the passive device and the active device, and the top cover layer is positioned above the barrier layer. The protective layer is located below the barrier layer and covers the top surface of the passive device. A sidewall of the barrier layer, a bottom surface of the cap layer, and the substrate define an air cavity. According to the invention, the parasitic capacitance generally generated between the source electrode / drain electrode and the gate electrode of the active device can be obviously reduced, and the electronic characteristics of the active device can be improved.

Description

[0001] This application is a divisional application of the original application with application number 202111441109.5, filed on November 30, 2021, and titled “Semiconductor Structure”. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor structure, and in particular, to a semiconductor structure including an electronic device. BACKGROUND

[0003] Electronic devices generally include active devices and passive devices, which are formed on a substrate as a whole. The active devices are different from the passive devices in many aspects, such as their functions, energy properties, power gain capabilities, etc. The active devices can include diodes and transistors. The passive devices can include resistors, capacitors, and inductors.

[0004] For the active devices and the passive devices on the substrate, sufficient moisture resistance must be provided to protect these devices.

[0005] Although the existing moisture resistant structures on the active devices and the passive devices of the semiconductor structure are generally suitable for their intended purposes, they are not entirely satisfactory in all respects, and there is still room for improvement. SUMMARY

[0006] The present disclosure provides a semiconductor structure including a substrate, an active device disposed above the substrate, and a passive device. The active device is disposed in a first region of the substrate, and the passive device is disposed in a second region of the substrate. The semiconductor structure further includes a shielding structure and a protective layer. The shielding structure includes a barrier layer and a cap layer, the barrier layer is disposed above the passive device and the active device, and the cap layer is disposed above the barrier layer. The protective layer is disposed below the barrier layer and covers a top surface of the passive device. A sidewall of the barrier layer, a bottom surface of the cap layer, and the substrate define an air cavity.

[0007] The present disclosure can significantly reduce the parasitic capacitance between the source electrode / drain electrode (of the source / drain structure) and the gate electrode of the active device, which is usually generated, and can improve the electronic properties of the active device. BRIEF DESCRIPTION OF DRAWINGS

[0008] The embodiments of the present disclosure can be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which it should be emphasized that the various concepts disclosed herein are not limited to the specific embodiments described. Rather, specific details are included to provide a thorough understanding of the application. However, it will be apparent to those skilled in the art that embodiments of the present disclosure can be practiced without some or all of the specific details. In other instances, well known process steps have been described only in general terms so as to not obscure the present disclosure in unnecessary detail.

[0009] Figure 1 A cross-sectional schematic view of a semiconductor structure according to some embodiments of the present disclosure is shown schematically.

[0010] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E A cross-sectional schematic view of an intermediate stage of forming a semiconductor structure according to some embodiments of the present disclosure is shown.

[0011] Figure 3 A cross-sectional schematic view of a semiconductor structure according to some embodiments of the present disclosure is shown schematically.

[0012] Figure 4 A cross-sectional schematic view of an active device according to a comparative example is shown schematically.

[0013] Figure 5 A cross-sectional schematic view of an active device according to one of the exemplary embodiments is shown schematically.

[0014] Figure 6A A plot of the threshold voltage (normalized) versus time for a sample of the active device of the comparative example under biased high-temperature / humidity stress testing.

[0015] Figure 6B A plot of the leakage current (i.e., Igs; gate-to-source current) versus time for a sample of the active device of the comparative example under biased high-temperature / humidity stress testing.

[0016] Figure 7A A plot of the threshold voltage (normalized) versus time for a sample of the active device of the exemplary embodiment under biased high-temperature / humidity stress testing.

[0017] Figure 7B A plot of the leakage current (i.e., Igs; gate-to-source current) versus time for a sample of the active device of the exemplary embodiment under biased high-temperature / humidity stress testing.

[0018] Figure 8 A cross-sectional schematic view of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0019] Figure 9 is Figure 8 a magnified view of the encircled portion.

[0020] Reference numerals:

[0021] A1: first region

[0022] A2: second region

[0023] D A , D A : active device

[0024] GE, 20: gate electrode

[0025] SE: source electrode

[0026] DE: drain electrode

[0027] 100: substrate

[0028] 110: compound semiconductor epitaxial layer

[0029] 201, 202: air gap

[0030] 21: source structure

[0031] 211: first covering portion

[0032] 231: first conductive portion

[0033] 22: drain structure

[0034] 212: second covering portion

[0035] 232: second conductive portion

[0036] 25: dielectric layer

[0037] 251: first dielectric portion

[0038] 252: protective nitride layer

[0039] 253: polybenzoxazole layer

[0040] 255: second dielectric portion

[0041] 25a: first sub-layer

[0042] 25b: second sub-layer

[0043] 25c: third sub-layer

[0044] D P : passive device

[0045] 235: first conductive part

[0046] 27: second conductive layer

[0047] 271: first part of the second conductive layer

[0048] 275: second conductive part (second part of the second conductive layer)

[0049] 275H: hole

[0050] 280: conductive bridge

[0051] 31: protective layer

[0052] 311-0, 411-0: opening

[0053] 311: first part of the protective layer

[0054] 3111, 3112: parts of the first part of the protective layer

[0055] 312: second part of the protective layer

[0056] 313: protective liner

[0057] 40: shielding structure

[0058] 40C: air cavity

[0059] 41: barrier layer

[0060] 411: first barrier part

[0061] 412: second barrier part

[0062] 413: third barrier part

[0063] 42: top cap layer

[0064] 110a, 231a, 232a, 235a, 271a, 280a, 411a: top surface

[0065] 211s, 212s, 231s, 232s, 235s, 271s, 275s, 411s: sidewall

[0066] 42b: bottom surface

[0067] 90: selected portion

[0068] D1: first direction

[0069] D2: second direction

[0070] D3: third direction

[0071] T1, T2, T3, T n , T n , T h : thickness DETAILED DESCRIPTION

[0072] The following detailed description is presented in terms of a number of different embodiments or examples, featuring various aspects of the application. These components and configurations are described with specificity to assist in understanding various embodiments of the application. It is to be understood, however, that the various embodiments of the present application can be implemented in a variety of ways, and that the terminology used is for the purpose of describing the particular embodiments only and is not intended to be limiting. For example, as used herein, the statement that two components are "coupled" means that the components are joined or operate to yield a desired effect. The word "coupled" is intended to mean both "directly coupled" (i.e., joined without intervening components) and "indirectly coupled" (i.e., joined with intervening components) unless otherwise specifically stated. Further, the word "comprise" is used throughout in order to avoid limitations on the claims. It is intended that the word "comprise" encompasses the words "consist of and "consisting of."

[0073] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0074] Likewise, the spatially relative terms can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0075] The terms "about", "approximately", "substantially" are generally intended to refer to within 20% of a given value or range, preferably within 10%, more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It is to be understood that the amounts herein are approximate amounts, i.e., the terms "about", "approximately", "substantially" are implied even when not specifically mentioned.

[0076] Although some embodiments discuss steps performed in a particular order, the steps can be performed in another logical order. Additional steps can be provided before, during, and / or after various stages of the methods described in this disclosure. Some stages described can also be eliminated, or replaced by other stages, in various embodiments. Additional components can be added to the semiconductor structure described in this disclosure. Some components described below can also be replaced or eliminated in various embodiments.

[0077] Embodiments of the disclosure provide a semiconductor structure including a passive device and an active device formed on a substrate. A protective layer formed on the substrate can cover the passive device, and the protective layer has an opening exposing at least a portion of the active device. Thus, the protective layer can provide moisture resistance properties for the passive device without degrading performance of the active device. In addition, a shielding structure can be formed over the protective layer to further prevent the active device and the passive device from degrading due to moisture.

[0078] Figure 1 A cross-sectional view of a semiconductor structure according to some embodiments of the disclosure is schematically shown. Embodiments of the disclosure provide a semiconductor structure including an electronic device over a substrate 100 and a protective layer 31 over the electronic device. The substrate 100 can have a first region Al and a second region A2. In some embodiments, the electronic device includes one or more active devices D A in the first region Al and one or more passive devices D P in the second region A2. In some embodiments, the protective layer 31 includes a portion (i.e., a second portion 312 described later) covering the passive devices D P and at least one opening 311-O exposing the active devices D A .

[0079] According to some embodiments, the active devices D A include a gate electrode GE, a source electrode SE and a drain electrode DE on opposite sides of the gate electrode GE, and other components and / or layers selected as needed in the active devices D A . A dielectric layer 25 (including, for example, a first dielectric portion 251 and a second dielectric portion 255) can be further formed over the substrate 100, details of which are described later. For the purpose of simplicity and clarity, some components and / or layers are not shown in the drawings. It should be noted that other types of active devices can also be applicable, and the configuration of the electrodes and other components can be varied according to the type of active devices to be formed in the application. Figure 1

[0080] In some embodiments, the protective layer 31 has an opening 311-O exposing at least a portion of the active devices D A ​The opening 311-O, and a portion of the protective layer 31 (i.e., portion 3112 of the first portion 311 described later) is located outside the exposed area. Therefore, the impact of the active device D can be reduced. A Between adjacent electrodes (e.g., between the source electrode SE and the gate electrode GE, or between the gate electrode GE and the drain electrode D) E Unwanted parasitic capacitances generated by the dielectric material between (between). When the semiconductor structure of the embodiment is applied to radio frequency integrated circuits (especially to radio frequency integrated circuits operating at high frequencies), the active device D can be improved. A The electrical properties. Furthermore, another part of the protective layer 31 (i.e., the second part 312 described later) covers the passive device D. P To protect the passive device D P This protects against moisture intrusion, thereby improving the reliability of the semiconductor structure in this disclosed embodiment. In some embodiments, it includes an active device D. A and passive device D P The semiconductor structure is used as at least part of a power amplifier, which operates at a frequency in the range of 27 GHz to 40 GHz. In some embodiments, the power amplifier operates at a frequency in the range of 30 GHz to 300 GHz (e.g., between 60 GHz and 90 GHz, between 75 GHz and 110 GHz, or between 110 GHz and 170 GHz). In some embodiments, the power amplifier operates at a frequency in the range of 1 GHz to 2 GHz.

[0081] According to some embodiments, the semiconductor structure also includes a shielding structure 40 located above the substrate 100 to protect the electronic device from harmful contaminants such as moisture, air humidity, particulate matter, or ionic impurities. In some embodiments, the active device D A The shielding structure 40 is surrounded by multiple portions (e.g., a first blocking portion 411 as a barrier wall and a top cover layer 42). In some embodiments, the shielding structure 40 has an air cavity 40C located above the opening 311-O of the protective layer 31. In some embodiments, the air cavity 40C communicates with the lower opening 311-O. For example, the opening 311-O of the protective layer 31 communicating with the air cavity 40C can expose the active device D. A The gate electrode GE and / or drain electrode DE.

[0082] In some embodiments, the semiconductor structure is applied to a radio frequency integrated circuit. Active device D AThis can include field-effect transistors (FETs), such as gallium nitride high electron mobility transistors (GaN HEMTs) and pseudomorphic high electron mobility transistors (pHEMTs). Active device D A It may also include a two-junction junction transistor (BJT), such as a heterojunction two-junction transistor (HBT). In some embodiments, the passive device D P This includes resistors, inductors, capacitors, or other suitable passive devices. In some embodiments, an example is a pseudo-high electron mobility transistor in the first region A1 and a capacitor in the second region A2 (e.g., Figures 2A-2E As shown and described below, the active device D is used to illustrate the semiconductor structure. A and passive device D P It should be noted that this disclosure is not limited to those exemplary capacitors and pseudo-high electron mobility transistors.

[0083] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E This is a schematic cross-sectional view illustrating an intermediate stage in the formation of a semiconductor structure according to some embodiments of the present invention.

[0084] Reference Figure 2A The semiconductor structure includes a substrate 100 having a first region A1 and a second region A2. In some embodiments, the substrate 100 is a semiconductor substrate. Further, the substrate 100 may include a III-V group semiconductor, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), or combinations thereof. In some embodiments, the substrate 100 includes undoped gallium arsenide. Furthermore, multiple electronic devices may be formed on the substrate 100. For example, one or more active devices D are formed in the first region A1. A And one or more passive devices D are formed in the second region A2. P .

[0085] In some embodiments, the substrate 100 is a device wafer, and various film layers and / or device elements are formed on the substrate 100. For the purposes of simplicity and clarity, some film layers and / or device elements may not be shown in the figures. Figures 2A-2EIn some embodiments, only a compound semiconductor epitaxial layer (or simply compound semiconductor layer) 110 is shown on the substrate 100 for clear and simple illustration. The substrate 100 for forming the pseudomorphic high electron mobility transistor can have a plurality of III-V semiconductor layers formed thereon, each having a suitable conductivity type and doping concentration. In some embodiments, the active device D A The compound semiconductor epitaxial layer 110 and an electrode formed thereon.

[0086] In some embodiments, the compound semiconductor epitaxial layer 110 formed on the substrate 100 can serve as a substrate for the electrode of the pseudomorphic high electron mobility transistor formed thereon. The compound semiconductor epitaxial layer 110 can be a multi-layer structure and can include a III-V semiconductor, such as gallium nitride, aluminum gallium nitride, aluminum nitride, gallium arsenide, aluminum gallium arsenide, indium phosphide, aluminum indium arsenide, gallium indium arsenide, gallium antimonide, or a combination thereof. In some embodiments, the compound semiconductor epitaxial layer 110 includes one or more highly doped p-type gallium arsenide layers doped with carbon, magnesium, zinc, calcium, beryllium, strontium, barium, or radium. The doping concentration of the compound semiconductor epitaxial layer 110 can be in a range between 1e18 cm-3and 1e20 cm-3. The compound semiconductor epitaxial layer 110 can be formed by molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), chemical vapor deposition, hydride vapor phase epitaxy (HVPE), other suitable methods, or a combination thereof.

[0087] In some embodiments, the compound semiconductor epitaxial layer 110 of the pseudomorphic high electron mobility transistor includes a plurality of layers epitaxially grown on the substrate 100, such as a buffer layer, a channel layer, a carrier supply layer, and a Schottky barrier layer. The buffer layer is formed on the substrate 100, and the channel layer is formed on the buffer layer. The carrier supply layer is formed on the channel layer, and the Schottky barrier layer is formed on the carrier supply layer. The subsequently formed gate electrode is disposed on the Schottky barrier layer. In some embodiments, the substrate 100 includes gallium arsenide, and the buffer layer includes at least one of gallium arsenide and aluminum gallium arsenide. In some embodiments, the channel layer includes at least one of gallium arsenide and gallium indium arsenide, and the carrier supply layer includes at least one of aluminum gallium arsenide, aluminum gallium arsenide phosphide (AlGaAsP), and indium aluminum gallium arsenide (InAlGaAs). The Schottky barrier layer is a single layer structure or a multi-layer structure. In some embodiments, the Schottky barrier layer includes aluminum gallium arsenide, aluminum gallium arsenide phosphide, indium aluminum gallium arsenide, indium gallium phosphide (InGaP), indium gallium phosphide arsenide (InGaPAs), aluminum indium gallium phosphide (AlInGaP), or a combination thereof. For the purpose of simplicity and clear illustration, only a single layer structure of the compound semiconductor epitaxial layer 110 is shown in the related drawings of these exemplary embodiments.

[0088] In some embodiments, as an active device D A of a pseudomorphic high electron mobility transistor, in the first region A1 is at least a portion of the compound semiconductor epitaxial layer 110, a gate electrode 20 located above the compound semiconductor epitaxial layer 110, a source structure 21 and a drain structure 22 located on opposite sides of the gate electrode 20. As Figure 2A indicated, the number of gate electrodes 20, drain structures 22 and source structures 21 is only an example and is not intended to limit the scope of the present disclosure. Adjacent gate electrodes 20, source structures 21 and drain structures 22 are spaced apart from each other in a first direction D1 (e.g., the X direction). Furthermore, the gate electrodes 20, source structures 21 and drain structures 22 can extend in a second direction D2 (e.g., the Y direction). The second direction D2 can be different from the first direction D1. For example, the second direction D2 is perpendicular to the first direction D1.

[0089] As Figure 2A indicated, according to some embodiments, each source structure 21 includes a first covering portion 211 and a first conductive portion 231 located above the first covering portion 211, and the drain structure 22 includes a second covering portion 212 and a second conductive portion 232 located above the second covering portion 212. The first covering portion 211 and the second covering portion 212 can be formed by a deposition manufacturing process (e.g., molecular beam epitaxy, metal organic chemical vapor deposition, chemical vapor deposition, hydride vapor phase epitaxy, other suitable methods, or a combination of the foregoing), followed by a patterning manufacturing process. In some embodiments, the first covering portion 211 and the second covering portion 212 include a group III-V semiconductor, such as gallium nitride, aluminum gallium nitride, aluminum nitride, gallium arsenide, aluminum gallium arsenide, indium phosphide, aluminum indium arsenide, indium gallium arsenide, or a combination of the foregoing. In some embodiments, the first covering portion 211 and the second covering portion 212 include a high-doped n-type indium gallium arsenide, and form an ohmic contact with the subsequently formed conductive portion used as a source / drain electrode.

[0090] The first conductive portion 231 of the source structure 21 and the second conductive portion 232 of the drain structure 22 can be formed by patterning the same conductive layer, such as a first conductive layer or a first metal layer. The conductive layer may include titanium, aluminum, gold, palladium, platinum, copper, tungsten, other suitable metals, the aforementioned alloys, or combinations thereof. Therefore, the first conductive portion 231 and the second conductive portion 232 may also be referred to as the source metal layer and the drain metal layer, respectively. In some embodiments, the first conductive portion 231 and the second conductive portion 232 are formed by a deposition process and a subsequent patterning process. The aforementioned deposition process may include electroplating, physical vapor deposition (e.g., sputtering, evaporation), chemical vapor deposition, atomic layer deposition, other suitable processes, or combinations thereof. The aforementioned patterning process may include photolithography, etching, other applicable processes, or combinations thereof.

[0091] like Figure 2A As shown, according to some embodiments, each gate electrode 20 between the source structure 21 and the drain structure 22 is formed above the compound semiconductor epitaxial layer 110. In some embodiments, the gate electrode 20 is presented as (but not limited to) a comb-shaped electrode in a top view (not shown). The gate electrode 20 may include titanium, aluminum, gold, palladium, platinum, copper, tungsten, other suitable metals, the aforementioned alloys, or combinations thereof. The manufacturing process for forming the gate electrode 20 may be the same as or similar to the manufacturing process for forming the first conductive portion 231 and the second conductive portion 232. For the sake of brevity, its manufacturing process will not be repeated here.

[0092] In this exemplary embodiment, as a passive device D above the substrate 100 P One capacitor is located in the second region A2. In some embodiments, such as Figure 2A As shown, this passive device D P (For example, a capacitor) includes a first conductive portion 235 above a substrate 100, a second conductive portion 275 above the first conductive portion 235, and a dielectric layer (e.g., a second dielectric portion 255 of the dielectric layer described later) between the first conductive portion 235 and the second conductive portion 275. The second conductive portion 275 may be formed directly on the second dielectric portion 255 of the dielectric layer 25. In some embodiments, the passive device D P It has a hole 275H, and this hole 275H is located between the second conductive portion 275 and the second dielectric portion 255 of the dielectric layer 25. It should be noted that the passive device D of the embodiment... P It is not limited to this exemplary capacitor.

[0093] According to some embodiments, the semiconductor structure further includes a dielectric layer 25 compliantly formed on the active device D.A Above. In some embodiments, the dielectric layer 25 covers the exposed portion of the top surface 110a of the compound semiconductor epitaxial layer 110, thereby preventing oxidation of the compound semiconductor epitaxial layer 110. In some embodiments, the dielectric layer 25 also functions as a barrier layer to protect the active device D. A and passive device D P Protected from moisture intrusion. In some embodiments, the dielectric layer 25 includes a first dielectric portion 251 formed in a first region A1 and a second dielectric portion 255 formed in a second region A2.

[0094] Dielectric layer 25 may include silicon nitride (Si3N4), silicon oxide (SiO2), and silicon oxynitride (SiO2). x N y The dielectric layer 25 may be formed by low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition, evaporation, or other suitable methods. In some embodiments, the thickness of the dielectric layer 25 is approximately 50 angstroms. The dielectric layer 25 can be adjusted to improve the performance of the semiconductor structure. The dielectric layer thickness is between approximately 100 angstroms and approximately 3000 angstroms, and even more particularly between approximately 300 angstroms and approximately 1500 angstroms.

[0095] like Figure 2A As shown, according to some embodiments, the first dielectric portion 251 of the dielectric layer 25 is formed directly and compliantly on the gate electrode 20, the source structure 21, and the drain structure 22. For example, the first dielectric portion 251 covers the outer surface of the gate electrode 20, the top surface and sidewalls of the drain structure 22, and the sidewalls and a portion of the top surface of the source structure 21. Specifically, in this embodiment, the first dielectric portion 251 covers the top surface 232a, the sidewalls 232s of the second conductive portion 232 of the drain structure 22, and the sidewalls 212s of the second cover portion 212. Furthermore, the first dielectric portion 251 covers a portion of the top surface 231a, the sidewalls 231s of the first conductive portion 231 of the source structure 21, and the sidewalls 211s of the first cover portion 211.

[0096] like Figure 2A As shown, according to some embodiments, the second dielectric portion 255 of the dielectric layer 25 covers the passive device D in the second region A2. Pthe exposed surface of the first conductive portion 235 and the top surface 110a of the compound semiconductor epitaxial layer 110. Specifically, in this embodiment, the second dielectric portion 255 covers the top surface 235a and the sidewall 235s of the first conductive portion 235. The second dielectric portion 255 also extends to the top surface 110a of the compound semiconductor epitaxial layer 110 adjacent to the first conductive portion 235.

[0097] In some embodiments, the semiconductor structure includes a second conductive layer 27 over the substrate 100. The second conductive layer 27 can include a first portion 271 on the first conductive portion 231 of each source structure 21 in the first region Al. In some embodiments, the first portion 271 of the second conductive layer 27 directly contacts the first conductive portion 231 of the source structure 21. The second conductive layer 27 can also include a second portion. In this exemplary embodiment, the second portion of the second conductive layer 27 is the second conductive portion 275 of the passive device D P over the first conductive portion 235.

[0098] The second conductive layer 27 can include titanium, aluminum, gold, palladium, platinum, copper, tungsten, other suitable metals, alloys thereof, or combinations of the foregoing. The fabrication process to form the second conductive layer 27 can be the same as or similar to the fabrication process to form the first conductive portion 231 of the source structure 21 and the second conductive portion 232 of the drain structure 22. For brevity, these fabrication processes are not restated here.

[0099] In some embodiments, the first conductive portion 235 of the passive device D P , the first conductive portion 231 of the source structure 21, and the second conductive portion 232 of the drain structure 22 are formed by patterning the same conductive material layer. In some embodiments, the first portion 271 (the active device D A ) and the second portion (i.e., the second conductive portion 275 of the passive device D P ) of the second conductive layer 27 are also formed by patterning the same conductive material layer.

[0100] Next, reference is made to Figure 2BIn some embodiments, a protective layer 31 is formed over the substrate 100. The protective layer 31 can be formed over the entire substrate 100 to serve as a protective blanket covering the components in the first region Al and the second region A2. In some embodiments, the protective layer 31 includes a first portion 311 and a second portion 312. In some embodiments, the first portion 311 is formed over the first dielectric portion 251 of the dielectric layer 25 and the first portion 271 of the second conductive layer. In some embodiments, the first portion 311 of the protective layer 31 covers the gate electrode 20, the source structure 21, and the drain structure 22 in the first region Al. In some embodiments, the second portion 312 of the protective layer 31 covers the second conductive portion 275 of the passive device D P in the second region A2.

[0101] In some embodiments, the protective layer 31 includes silicon nitride, silicon oxide, silicon oxynitride, aluminum nitride, aluminum oxide (AI2O3), hafnium oxide (HfO2), one or more other suitable protective materials, or a combination thereof. In some embodiments, the protective layer 31 includes aluminum oxide. The protective layer 31 can be formed using physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable methods. In some embodiments, the protective layer 31 is deposited using atomic layer deposition. In some embodiments, the protective layer 31 has a thickness in a range from about 100 angstroms to about 1000 angstroms, particularly in a range from about 300 angstroms to about 1000 angstroms, and more particularly in a range from about 500 angstroms to about 750 angstroms.

[0102] According to some embodiments, during the formation of the protective layer 31, the protective material is further deposited at the sidewall 275s of the hole 275H. As shown in FIG. 3B, in some embodiments, the protective material deposited at the sidewall 275s of the hole 275H is a protective liner 313. Figure 2B

[0103] Although the protective layer 31 provides an effective environmental barrier to protect the devices from moisture, the protective material can induce unwanted parasitic capacitance between the source / drain structures and the gate electrode, particularly when the protective layer 31 is made of a material with a high dielectric constant. Accordingly, according to some embodiments, a portion of the protective layer 31 is selectively removed to form an opening exposing the active device D A to reduce the unwanted parasitic capacitance. Meanwhile, the remaining portion of the protective layer 31 covers the passive device D P to protect the passive device D P from moisture. Details will be discussed in the following paragraphs.

[0104] Referring to Figure 2C and Figure 2D ​The diagram illustrates the steps of selectively removing the protective layer 31 according to some embodiments. In this exemplary embodiment, a shielding structure 40 is further provided in the semiconductor structure to protect the active device D. A and passive device D P It is protected from harmful contaminants such as moisture, air humidity, particulate matter, and / or ionic impurities. In some embodiments, the shielding structure 40 is formed using a wafer-level packaging manufacturing process. In some embodiments, the shielding structure 40 is formed using a dry film manufacturing process. In some embodiments, the shielding structure 40 includes a barrier layer 41 and a top cover layer 42. Figure 2E In addition, a portion of the blocking layer 41 can be used as a mask to selectively remove the protective layer 31.

[0105] Reference Figure 2C In some embodiments, the barrier layer 41 includes a first barrier portion 411 in a first region A1 and a second barrier portion 412 in a second region A2. The barrier layer 41 can be formed by providing a barrier material layer over the protective layer 31 and then patterning the barrier material layer. After patterning the barrier material layer, the remaining portions of the barrier material layer are referred to as the first barrier portion 411 in the first region A1 and the second barrier portion 412 in the second region A2. In some embodiments, the first barrier portion 411 in the first region A1 is formed above the source structure 21 as a barrier wall, while the second barrier portion 412 covers the passive device D in the second region A2. P In a top view (not shown), a barrier wall may surround the gate electrode 20 and the drain structure 22. (As shown...) Figure 2C As shown, the first blocking portion 411 in the first region A1 defines an opening 411-O, which exposes the portion of the protective layer 31 that covers the gate electrode 20 and the drain structure 22. In some embodiments, the opening 411-O also exposes another portion of the protective layer 31, which is the sidewall 271s of the first portion 271 of the second conductive layer 27, the sidewall 231s of the first conductive portion 231, and the sidewall 211s of the first covering portion 211 of the source structure 21.

[0106] like Figure 2C As shown, in some embodiments, the blocking layer 41 further includes a third blocking portion 413 located in the second region A2. As described above, the passive device D P A hole 275H may be provided between the second conductive portion 275 and the substrate 100, and a protective liner 313 may be formed at the sidewall 275s of the hole 275H. Figure 2B) In some embodiments, in the process of forming the barrier layer 41, the barrier material in the second region A2 also fills in the hole 275H, thus forming a third barrier portion 413. The third barrier portion 413 can be separated from the first conductive portion 235 and the second conductive portion 275 by the protective layer 313.

[0107] In some embodiments, the barrier layer 41 and the protective layer 31 comprise different materials. The material of the barrier layer 41 can have a lower moisture permeability than the material of the protective layer 31. For example, the barrier layer 41 is made of a material having a first water vapor transmission rate (WVTR), the protective layer 31 is made of another material having a second water vapor transmission rate, and the first water vapor transmission rate is less than the second water vapor transmission rate.

[0108] The barrier layer 41 can comprise one or more organic materials, such as polymeric materials. In an exemplary embodiment, the barrier layer 41 comprises a photoresist material. The material of the barrier layer 41 comprises, for example, polydimethylsiloxane (PDMS), SU8 (i.e., an epoxy-based photoresist material from MicroChem Inc., hereinafter referred to as SU8), ( i.e., an epoxy-based photoresist material from MicroChem Inc., hereinafter referred to as SU8), ( from Asahi Glass Company), ( a wafer photoresist from DuPont), and other suitable materials. Furthermore, a layer of barrier material can be formed over the substrate 100 by spin coating, spray coating, thermal chemical vapor deposition (TVD), or any other suitable method, and then subjected to a patterning fabrication process to form the barrier layer 41. In some embodiments, a dry film fabrication process is used to form the barrier layer 41.

[0109] In one example, the layer of barrier material is made of, but not limited to, SU8, an epoxy-based photoresist, and then SU8 is patterned by an optical lithography fabrication process to form the barrier layer 41. SU8 is a photoresist that has good mechanical durability, water impermeability, and dielectric properties, and can be easily patterned to form portions with high aspect ratios. Thus, in some embodiments, SU8 is used as the material for the first barrier portion 411 of the barrier layer 41 with high aspect ratios, so that a gas cavity 40C with sufficient height in the third direction D3 (e.g., the Z direction) can be subsequently formed. Figure 2E ).

[0110] Referring to Figure 2DIn some embodiments, a portion of the protective layer 31 is selectively removed (e.g., Figure 2C Part 3111) of the middle section, to form an exposed active device D A The opening 311-O, while the remaining portion of the protective layer 31 still covers the passive device D. P In some embodiments, after selectively removing a portion 3111 of the protective layer 31, a portion 3112 of the protective layer 31 remains on the first portion 271 of the second conductive layer 27 in the first region A1, while the second portion 312 of the protective layer and the protective liner 313 remain in the passive device D in the second region A2. P On the surface.

[0111] According to the embodiments disclosed herein, the barrier layer 41 is used as a mask to selectively remove the protective layer 31. For example... Figure 2C and Figure 2D As shown, the first blocking portion 411 of the blocking layer 41 corresponds to the active device D in the first region A1. A It can also serve as a mask for patterning the underlying protective layer 31. In some embodiments, the protective layer 31 is etched through holes in the blocking layer 41 to form openings 311-O in the protective layer 31. Therefore, according to some embodiments, no additional mask is required to pattern the protective layer 31.

[0112] Reference Figure 2D In some embodiments, only the first dielectric portion 251 of the dielectric layer 25 and the air gap 201 exist between the source structure 21 and the gate electrode 20 in the first direction D1 (e.g., the X direction). Similarly, only the first dielectric portion 251 of the dielectric layer 25 and the air gap 202 exist between the drain structure 22 and the gate electrode 20 in the first direction D1 (e.g., the X direction). Therefore, compared with conventional active devices that include metal-insulator-metal stacks (e.g., formed by source / drain electrodes and multiple dielectric layers and / or organic layers), the active device D in the embodiments has a higher dielectric density. A The unwanted parasitic capacitance generated is much less.

[0113] Next, refer to Figure 2E A top cover layer 42 is formed above the barrier layer 41, thereby forming a shielding structure 40. The top cover layer 42 can directly contact the barrier layer 41. The material and manufacturing process of forming the top cover layer 42 can be the same as or similar to the material and manufacturing process of forming the barrier layer 41. For the sake of brevity, the material and manufacturing process of the top cover layer 42 will not be repeated here.

[0114] In some embodiments, the barrier layer 41 and the cap layer 42 form an air cavity 40C above the opening 311-O of the protection layer 31. In some embodiments, the air cavity 40C is defined by the sidewall 411s of the first barrier portion 411 of the barrier layer 41 and the bottom surface 42b of the cap layer 42. In some embodiments, the air cavity 40C defined by the shielding structure 40 in the first region Al is in communication with the opening 311-O of the protection layer 31 underneath the air cavity 40C.

[0115] In some embodiments, the cap layer 42 is suspended on the first barrier portion 411 of the barrier layer 41 as a roof of the shielding structure 40. Referring to Figure 2E , according to some embodiments, the first barrier portion 411 of the barrier layer 41 is directly formed on the portion 3112 of the protection layer 31 in the first region Al. In some embodiments, the combination of the portion 3112 of the protection layer 31, the first barrier portion 411 of the barrier layer 41 and the cap layer 42 is to seal the active devices D A , thus further protecting the active devices D A from being affected by harmful contaminants such as moisture, air humidity, particulate or ionic impurities.

[0116] Although the shielding structure 40 shown in Figure 2E has the barrier wall (i.e. the first barrier portion 411 of the barrier layer 41) located above the two closest source structures 21 of the two active devices D A , the present disclosure is not limited thereto. In some other embodiments, the barrier wall is formed above the two outermost source structures 21 of a selected plurality of active devices D A , such that the barrier wall of the shielding structure 40 encloses three or more active devices D A . The location of the barrier wall of the shielding structure 40 can be determined according to the design conditions of the application, such as the size of the source structures 21, the drain structures 22 and the gate electrodes 20, the distance between the source / drain structures, and other factors.

[0117] The semiconductor structure can further include one or more additional components suitable for various purposes, such as but not limited to electrical connection components for the source electrodes, heat conduction components, and / or structural reinforcement components. Figure 3 is a schematic cross-sectional view showing a semiconductor structure according to some other embodiments. In an example, as Figure 3 shown, the plurality of source structures 21 of the active devices D A above the substrate 100 are further electrically connected by a conductive bridge.

[0118] In some embodiments, the semiconductor structure further includes electrical connection components electrically connecting the plurality of active devices D AA conductive bridge 280 of the source structure 21. For example, the conductive bridge 280 connects the source structure 21 of the pseudo-high electron mobility transistor. In some embodiments, after the protective layer 31 is formed, such as Figure 2B As shown, the first portion 311 of the protective layer 31 located on the first portion 271 of the second conductive layer 27 is partially removed to expose the top surface 271a of a portion of the first portion 271. Then, a conductive bridge 280 is formed directly on the exposed top surface 271a of the first portion 271 to electrically connect to the source structure 21. Therefore, the conductive bridge 280 can directly contact the first portion 271 of the second conductive layer 27. Subsequently, in the active device D... A With passive device D P A shielding structure 40 is formed above. It should be noted that, according to some embodiments, due to the cross-sectional position, Figure 3 The first part 311 of the protective layer 31 is not shown, but apart from the contact area between the conductive bridge 280 and the first part 271 of the second conductive layer 27, the first part 311 of the protective layer 31 covers the entire area of ​​the top surface 271a of the first part 271 below the first blocking part 411 (e.g., blocking wall).

[0119] The conductive bridge 280 may comprise titanium, aluminum, gold, palladium, platinum, copper, tungsten, other suitable metals, alloys thereof, or combinations thereof. In some embodiments, the conductive bridge 280 is also referred to as a metal bridge. The manufacturing process for forming the conductive bridge 280 may be the same as or similar to the manufacturing process for forming the second conductive layer 27. For the sake of brevity, its manufacturing process will not be repeated here.

[0120] like Figure 3 As shown, the conductive bridge 280 is confined within a cavity 40C defined by the barrier layer 41 and the top cover layer 42. The top surface 411a of the first blocking portion 411 of the barrier layer 41 may be substantially coplanar with or higher than the conductive bridge 280 without affecting its function. In some embodiments, the bottom surface 42b of the top cover layer 42 is spaced apart from the top surface 280a of the conductive bridge 280.

[0121] like Figure 2E and Figure 3 As shown, due to the selective removal of protective layer 31 ( Figure 2D To expose the active device D, except for the top surface of the source structure 21. A Therefore, the parasitic capacitance generated between the gate electrode 20 and the source structure 21 / drain structure 22 can be significantly reduced. In some embodiments, the passive device D P The top surface is covered by the remaining portion of the protective layer 31 (i.e., the second portion 312), thereby enhancing its moisture resistance. In some embodiments, a shielding structure 40 is further provided to protect the active device D.A and passive device D P from harmful contaminants such as moisture, air humidity, particulates and / or ionic impurities. Thus, in some embodiments, while some portions of the active device D A are not protected by the portion 3112 of the protective layer 31, the reliability of the active device D A may be maintained, or even enhanced, by the provision of the shielding structure 40.

[0122] Below, a comparative example and one exemplary embodiment are presented to evaluate the electronic properties and reliability of the active devices thereof. Figure 4 A cross-sectional view of an active device D A according to a comparative example is schematically shown.

[0123] Figure 5 A cross-sectional view of an active device D A according to one exemplary embodiment is schematically shown.

[0124] Figure 5 The active device D A shown is identical to the active device D A shown in Figure 2E , and thus the description of the components in Figure 5 will not be repeated here. Furthermore, identical or similar reference signs or reference labels are used to denote identical or similar components / layers in Figure 4 and Figure 5 . For brevity, the materials forming these identical or similar components / layers and the manufacturing processes will not be repeated here.

[0125] With reference to Figure 4 and Figure 5 , a dielectric layer (i.e. the first dielectric portion 251 described above) is conformally deposited over the gate electrode 20, the source structure 21 and the drain structure 22. Up to this step, the comparative example ( Figure 4 ) and the exemplary embodiment ( Figure 5 ) have the same configuration (e.g. components having the same dimensions and relative positions). Then, a protective nitride (e.g. silicon nitride) layer 252 and a polybenzoxazole (PBO) layer 253 are further deposited over the first dielectric portion 251 to form the active device D A of the comparative example in Figure 4 . Without forming the protective nitride layer and the polybenzoxazole layer, the shielding structure 40 having the air cavity 40C is formed over the gate electrode 20, the source structure 21 and the drain structure 22 to form the active device D A of the exemplary embodiment in Figure 5 .In this exemplary embodiment, the first blocking portion 11 of the blocking layer 41 of the shielding structure 40 is formed on the portion 3112 of the protective layer 31, and the protective layer 31 is made of aluminum oxide with a thickness of about 750 angstroms. The blocking layer 41 and the cap layer 42 have a thickness of 20 micrometers (pm) respectively. It should be noted that the active device D A of this exemplary embodiment can have different values of the dimensions of these components / layers.

[0126] (1) The active device D A of the comparative example and the active device D A of the exemplary embodiment.

[0127] The active device D A of the comparative example and the active device D A of the exemplary embodiment were tested to analyze their electronic properties. The test results of the capacitance between the gate and the drain (CGD), the capacitance between the gate and the source (CGS), the cut-off frequency (ft) at which the current gain is equal to 1, and the maximum oscillation frequency (fmax) at which the power gain is equal to 1, in the active devices of the comparative example and the exemplary embodiment are shown in Table 1.

[0128] Table 1:

[0129]

[0130] Although Figure 4 the active device D A of the comparative example includes the protective nitride (e.g., silicon nitride) layer 252 and the polybenzoxazole layer 253 to increase the ability to prevent moisture, the dielectric constant of silicon nitride is about 7.5, which can cause parasitic capacitance between the gate electrode and the source / drain electrode. According to the results of Table 1, the capacitance between the gate and the drain (i.e., CGD = 181.8) and the capacitance between the gate and the source (i.e., CGS = 1379.2) of the active device D A of the comparative example are greater than the capacitance between the gate and the drain (i.e., CGD = 95.9) and the capacitance between the gate and the source (i.e., CGS = 1236.9) of the active device D A of the exemplary embodiment, respectively. Therefore, according to the active device D A of the exemplary embodiment, since the gate electrode 20 and the source / drain electrodes of the source structure 21 / drain structure 22 are only surrounded by the first dielectric portion 251 and the air (with a dielectric constant of 1) in the air cavity 40C of the shielding structure 40, the parasitic capacitance between the gate electrode 20 and the source / drain electrodes of the source structure 21 / drain structure 22 of the active device D A can be significantly reduced.

[0131] Furthermore, the results in Table 1 indicate that the active device D A ' of the comparative example has a cutoff frequency of 84.8, while the active device D A of the exemplary embodiment has a cutoff frequency of 97.5. Compared to the cutoff frequency of the active device D A ' of the comparative example, the cutoff frequency of the active device D A of the exemplary embodiment is increased by about 15%.

[0132] Furthermore, the results in Table 1 indicate that the active device D A ' of the comparative example has a maximum oscillation frequency of 174.3 at a power gain of 1, while the active device D A of the exemplary embodiment has a maximum oscillation frequency of 227.1 at a power gain of 1. Thus, compared to the maximum oscillation frequency of the active device D A ' of the comparative example, the maximum oscillation frequency of the active device D A of the exemplary embodiment is significantly increased by about 30%.

[0133] Accordingly, the active device D A in some embodiments does have significantly improved electronic characteristics, such as reduced gate-to-drain capacitance and reduced gate-to-source capacitance. Furthermore, according to some embodiments, the active device D A with higher cutoff frequency and maximum oscillation frequency is suitable for use in power amplifiers (e.g., millimeter wave power amplifiers).

[0134] (2) Bias Highly Accelerated Temperature / Humidity Stress Test (bHAST) of Active Devices D A ' and D A .

[0135] Bias highly accelerated temperature / humidity stress tests were performed on the active device D A ' of the comparative example and the active device D A of the exemplary embodiment to evaluate the ability of the active devices to resist moisture ingress.

[0136] A total of 237 samples of the active device D A ' of the comparative example and 26 samples of the active device D A of the exemplary embodiment were selected for bias highly accelerated temperature / humidity stress tests.Samples were screened using a bias height-accelerated temperature / humidity stress test. The samples were mounted on a test board and subjected to a drain-source voltage of 5.0 volts (Vds) and a gate-source voltage of 0 volts (Vgs). The biased samples were then placed at 130°C and 85% relative humidity, pressurized to 2.27 atmospheres, and maintained for 96 hours. The critical voltage (Vto) and gate leakage current were measured before screening and at the end of the 96-hour test. Samples were considered failures if, after the 96-hour bias height-accelerated temperature / humidity stress test, the change in critical voltage exceeded 20% and the leakage current (Igs; the current from the gate to the source) exceeded 1 mA / mm².

[0137] Figure 6A To test the active device D of the comparative example under accelerated temperature / humidity stress at bias height, A The critical voltage (normalized) of the sample is plotted against time. Figure 6B To test the active device D of the comparative example under accelerated temperature / humidity stress at bias height, A The graph shows the relationship between the leakage current (mΩ / mm²) (i.e., Igs; gate-to-source current) of the sample and time. Figure 6A and Figure 6B As shown, the active device D of the comparative example A Of the 237 samples, 105 failed the bias height accelerated temperature / humidity stress test when completed in 96 hours; that is, about 44% of the samples failed to meet the established test criteria of a critical voltage (normalization) change of less than 20% and leakage current of less than 1 mA / mm.

[0138] Figure 7A For accelerated temperature / humidity stress testing under bias height, the active device D of an exemplary embodiment... A The critical voltage (normalized) of the sample is plotted against time. Figure 7B For accelerated temperature / humidity stress testing under bias height, the active device D of an exemplary embodiment... A The graph shows the relationship between the leakage current (mΩ / mm²) (i.e., Igs; gate-to-source current) of the sample and time. Figure 7A and Figure 7B As shown, the active device D of an exemplary embodiment A All 26 samples passed the established test criteria of less than 20% change in critical voltage (normalization) and less than 1 mA / mm.

[0139] (3) Perform bias-high accelerated temperature / humidity stress test on the capacitor.

[0140] Capacitors of comparative examples (i.e., without any shielding structure; not shown) and capacitors of exemplary embodiments (i.e., with shielding structures 40 as shown) were also subjected to bias highly accelerated temperature / humidity stress tests to evaluate the ability of the passive devices to resist moisture intrusion. Figure 2E

[0141] A total of 27 samples of capacitors of comparative examples and 78 samples of capacitors of exemplary embodiments were subjected to bias highly accelerated temperature / humidity stress tests screening. The samples were mounted on a test board and subjected to 8.0 volts bias. The biased samples were then subjected to 130 °C temperature and 85% relative humidity, and 2.27 atmospheres pressure for 96 hours. The samples of capacitors were measured for leakage current before screening and at the completion of the 96 hours test. The failure criterion was that the leakage current exceeded 100 microamperes (pA) at 8 volts bias after the completion of the 96 hours test. According to the test results, 4 out of 27 samples (i.e., about 15%) of capacitors of comparative examples failed the bias highly accelerated temperature / humidity stress test at the completion of 96 hours, while all 78 samples of capacitors of exemplary embodiments passed the above established criterion, i.e., the leakage current was less than 100 microamperes at 8 volts bias.

[0142] Figure 8 A cross-sectional view of a semiconductor structure according to some embodiments of the disclosure is shown. Figure 9 is Figure 8 An enlarged view of the circled portion 90. Figure 8 A semiconductor structure of an embodiment and Figure 5 A semiconductor structure of an embodiment differs in that, Figure 8 The dielectric layer 25 of the semiconductor structure shown includes a plurality of sub-layers. In some embodiments, as shown in Figure 8 and Figure 9 The dielectric layer 25 disposed on the active device D A includes a first sub-layer 25a, a second sub-layer 25b on the first sub-layer 25a, and a third sub-layer 25c on the second sub-layer 25b.

[0143] In some embodiments, the material of the second sub-layer 25b of the dielectric layer 25 has a dielectric constant less than that of the material of the first sub-layer 25a, and the thickness T2 of the second sub-layer 25b is greater than the thickness T1 of the first sub-layer 25a, as shown in Figure 9 Thus, the capacitance between the gate and the source and / or the capacitance between the gate and the drain can be reduced.

[0144] ​In some embodiments, the first sub-layer 25a is applied to improve the surface quality of the compound semiconductor epitaxial layer 110 (e.g., to reduce dangling bonds on the top surface 110a of the compound semiconductor epitaxial layer 110). In some embodiments, since the thickness Tl of the first sub-layer 25a is smaller than the thickness T2 of the second sub-layer 25b, the surface quality of the compound semiconductor epitaxial layer 110 can be improved without significantly increasing the parasitic capacitance (e.g., the capacitance between the gate and the source and the capacitance between the gate and the drain). The ratio of the thickness T2 to the thickness Tl can be greater than 1 (e.g., 1 < T2 / Tl ≤ 100). In some embodiments, the ratio of the thickness T2 to the thickness Tl is in the range of 4 to 25. For example, the thickness Tl is in the range of 20 angstroms to 200 angstroms, and the thickness T2 is in the range of 200 angstroms and 2000 angstroms.

[0145] In some embodiments, the material of the second sub-layer 25b of the dielectric layer 25 has a dielectric constant that is smaller than the dielectric constant of the material of the third sub-layer 25c, and the thickness T2 of the second sub-layer 25b is greater than the thickness T3 of the third sub-layer 25c, as shown in Figure 9 Thus, the capacitance between the gate and the source and / or the capacitance between the gate and the drain can be reduced.

[0146] In some embodiments, the third sub-layer 25c is applied to improve the moisture resistance. In some embodiments, the thickness T3 of the third sub-layer 25c is smaller than the thickness T2 of the second sub-layer 25b, thus improving the moisture resistance without significantly increasing the parasitic capacitance (e.g., the capacitance between the gate and the source and the capacitance between the gate and the drain). The ratio of the thickness T2 to the thickness T3 can be greater than 1 (e.g., 1 < T2 / T3 ≤ 200). In some embodiments, the ratio of the thickness T2 to the thickness T3 is in the range of 4 to 50. For example, the thickness T3 is in the range of 20 angstroms to 200 angstroms.

[0147] In some embodiments, the first sub-layer 25a is made of silicon nitride, the second sub-layer 25b is made of silicon oxide, and the third sub-layer 25c is made of silicon nitride. In some embodiments, as shown in Figure 8 and Figure 9 Thus, the parasitic capacitance can be reduced, and the surface quality of the compound semiconductor epitaxial layer 110 and the moisture resistance can be improved.

[0148] In some embodiments, the first sublayer 25a, the second sublayer 25b, and the third sublayer 25c are formed by plasma-enhanced chemical vapor deposition, atomic layer deposition, other suitable methods, or a combination thereof. In some embodiments, the second sublayer 25b is formed by plasma-enhanced chemical vapor deposition, and the thickness T of the dielectric layer 25 on the neck of the gate electrode 20 is... n The thickness T is less than that of the dielectric layer 25 on top of the gate electrode 20. h In some embodiments, due to thickness T n Less than thickness T h This can further reduce parasitic capacitance. For example, thickness T n For thickness T h The ratio is in the range of 0.15 to 0.95.

[0149] In some embodiments, such as Figure 8 and Figure 9 As shown, the neck of the gate electrode 20 is located on a recess on top of the compound semiconductor epitaxial layer 110. In some embodiments, the second sublayer 25b is formed by plasma-enhanced chemical vapor deposition, and the dielectric layer 25 in the recess of the compound semiconductor epitaxial layer 110 has a thickness T. n 'is less than thickness T' h In some embodiments, due to thickness T n 'less than thickness T h This can further reduce parasitic capacitance. For example, thickness T n For thickness T h The ratio is in the range of 0.15 to 0.95.

[0150] According to the above, the disclosure provides a semiconductor structure. The semiconductor structure includes one or more active devices and one or more passive devices over a substrate. The semiconductor structure further includes a protective layer covering top surfaces of the aforementioned passive devices, the protective layer having an opening exposing the active devices. In some embodiments, the opening of the protective layer exposes sidewalls of gate electrodes, drain structures, and at least source structures of the active devices. Thus, parasitic capacitance normally generated between source electrodes / drain electrodes and gate electrodes of the active devices (of the source structures / drain structures) can be significantly reduced, and electronic properties of the active devices can be improved. In some embodiments, remaining portions of the protective layer cover top surfaces of the passive devices to prevent the passive devices from being invaded by moisture. In addition, the semiconductor structure can further include a shielding structure (e.g., including a barrier portion as a barrier wall and a cap layer as a roof), the shielding structure having an air cavity in communication with the opening of the protective layer. The shielding structure further protects the active devices from being affected by harmful contaminants such as moisture, air humidity, particulate or ionic impurities, etc., thereby improving reliability of the active devices. The shielding structure can be further formed over the passive devices to strengthen protection of the passive devices from being affected by the aforementioned harmful contaminants. In addition, a method of forming the semiconductor structure according to some embodiments utilizes a barrier portion (e.g., the first barrier portion 411 of the barrier layer 41) of the shielding structure as a mask to selectively remove the protective layer to expose the active devices. Thus, the method of forming the semiconductor structure according to some embodiments provides a simple way to provide active devices with improved electronic properties.

[0151] It is to be understood that not necessarily all benefits and / or effects described above are required to be achieved by each embodiment.

[0152] The components of the above summary of several embodiments are provided to give those skilled in the art a more detailed understanding of the concepts of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily design or modify other manufacturing processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized by, The device includes: a substrate; an active device disposed over the substrate and in a first region of the substrate; a passive device disposed over the substrate and in a second region of the substrate; a shielding structure including a barrier layer and a cap layer, the barrier layer being disposed over the passive device and the active device, and the cap layer being disposed over the barrier layer; and a protective layer disposed under the barrier layer and covering a top surface of the passive device, wherein sidewalls of the barrier layer, a bottom surface of the cap layer, and the substrate define a cavity. The protective layer also covers at least a portion of the active device.

2. The semiconductor structure of claim 1, wherein, The active device includes a gate electrode, a source structure, and a drain structure, the source structure and the drain structure being disposed on opposite sides of the gate electrode, the gate electrode and the drain structure being disposed in the cavity.

3. The semiconductor structure of claim 1, wherein, The source structure is disposed under the barrier layer, and the protective layer covers the source structure.

4. The semiconductor structure of claim 3, wherein, The active device further includes a compound semiconductor layer, and the semiconductor structure further includes:

5. The semiconductor structure of claim 3, wherein, a dielectric layer covering the gate electrode and covering a top surface of the compound semiconductor layer. The dielectric layer also covers the drain structure.

6. The semiconductor structure of claim 5, wherein, The dielectric layer includes a first sub-layer, a second sub-layer disposed on the first sub-layer, and a third sub-layer disposed on the second sub-layer, and a thickness of the second sub-layer is greater than thicknesses of the first sub-layer and the third sub-layer.

7. The semiconductor structure of claim 5, wherein, The source structure includes:

8. The semiconductor structure of claim 5, wherein, a first covering portion; and a first conductive portion of a first conductive layer, the first conductive portion being disposed on the first covering portion, wherein the dielectric layer also covers sidewalls of the first covering portion and sidewalls of the first conductive portion. The dielectric layer also covers a top surface of the first covering portion.

9. The semiconductor structure of claim 8, wherein, The device further includes:

10. The semiconductor structure of claim 8, wherein, a second conductive layer disposed between the protective layer and the first conductive portion of the first conductive layer. The dielectric layer also covers sidewalls of the second conductive layer and a top surface of the first conductive portion of the first conductive layer.

11. The semiconductor structure of claim 10, wherein, The drain structure includes:

12. The semiconductor structure of claim 8, wherein, a second covering portion; and a second conductive portion of the first conductive layer, the second conductive portion being disposed on the second covering portion, wherein the dielectric layer also covers the second covering portion and the second conductive portion. The gate electrode includes a T-shaped body.

13. The semiconductor structure of claim 3, wherein, The passive device is a capacitor, the capacitor including:

14. The semiconductor structure of claim 1, wherein, a first conductive portion disposed on the substrate; a dielectric layer disposed on the first conductive portion; and a second conductive portion disposed on the dielectric layer. The barrier layer and the cap layer include the same material.

15. The semiconductor structure of claim 1, wherein, The shielding structure and the protective layer include different materials.

16. The semiconductor structure of claim 1, wherein, The shielding structure includes a polymer material.

17. The semiconductor structure of claim 1, wherein, The protective layer includes silicon nitride, silicon oxide, silicon oxynitride, aluminum nitride, aluminum oxide, hafnium oxide, or a combination thereof.

18. The semiconductor structure of claim 1, wherein, The active device includes a high electron mobility transistor, a heterojunction bipolar transistor, or a combination thereof.

19. The semiconductor structure of claim 1, wherein, The passive device includes a capacitor.

20. The semiconductor structure of claim 19, wherein, ​

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