A method of packaging a multi-chip module

Abstract

The application discloses a packaging method of a multi-chip module, and belongs to the technical field of multi-chip module packaging. The method is characterized in that: a middle layer is stacked in a stepped multi-layer mode to form a middle body, each middle layer is exposed to have an interconnection platform of a high integrated circuit, chips are stacked in a multi-layer mode, each high bandwidth memory chip having a high bandwidth memory is connected to the interconnection platform of the corresponding middle layer, and the middle body is directly or indirectly mounted on a substrate. In this way, the chips originally laid on one middle layer are changed to be stacked in a three-dimensional mode on the middle body, the area of the multi-chip module is greatly reduced, and the multi-chip module is more adaptable in many application environments. Meanwhile, the thickness and strength of the middle body are far greater than those of a single chip layer, the middle body has stronger warping resistance, stability and integrity, can more effectively inhibit warping of a packaging body such as a substrate combined with the middle body, and avoids internal circuit interconnection failure and scrapping of the multi-chip module.

Description

TECHNICAL FIELD

[0001] The present application relates to a packaging method of a multi-chip module, and belongs to the technical field of multi-chip module packaging. BACKGROUND

[0002] A multi-chip module is an integrated package of multiple chips with different functions and mutual correlation.

[0003] A more advanced packaging method of a multi-chip module is 2.5D packaging technology, the main technical measure of which is to place chips horizontally side by side on a silicon or glass interposer instead of directly mounting them on a packaging substrate.

[0004] The wiring of a traditional substrate (such as an organic substrate) is made by a process similar to that of a PCB, and the line width / spacing can only be made to be more than 10 microns. This precision is sufficient for ordinary chips, but for high-end chips in a multi-chip module, such as an HBM (high bandwidth memory) chip, which has thousands of data I / O ports that need to be directly and quickly communicated with a processor (such as a GPU), if the HBM and the GPU are directly placed on the substrate, the wiring of the substrate cannot bear such a dense pin on the chip, and the lines on the substrate must be "spread out" from a very dense point to a relatively sparse area, which is called "fan-out". Making this "fan-out" on the substrate requires a huge area and will result in very long wiring. The silicon / glass interposer is made by a semiconductor process, and its line width / spacing can be made to be 1 micron or even smaller, which is tens to hundreds of times the precision of the substrate. It can easily realize the direct and dense interconnection between the HBM and the GPU in a very small area, and perfectly solve the "fan-out" problem.

[0005] Using a silicon / glass interposer can also break through the electrical performance bottleneck, reduce signal loss, and avoid signal distortion.

[0006] Using a silicon / glass interposer can also break through the system integration bottleneck. It is like a miniature motherboard, on which various small chips can be "plugged in" or placed at will, and they are provided with communication capabilities comparable to those inside a single chip.

[0007] In addition, 2.5D packaging is also conducive to suppressing the warping of other packages in a multi-chip module during temperature changes.

[0008] Typical thermal expansion coefficients of key materials in a multi-chip module: silicon interposer: thermal expansion coefficient ≈ 2.3-3 ppm / °C; glass interposer: thermal expansion coefficient ≈ 3-8 ppm / °C (adjustable by composition); organic package substrate: thermal expansion coefficient ≈ 12-18 ppm / °C (in x-y plane); C4 bump / solder (key interconnect structure for connecting chips to interposer or substrate in flip-chip): thermal expansion coefficient ≈ 21-25 ppm / °C; underfill: thermal expansion coefficient ≈ 20-30 ppm / °C (below its glass transition temperature Tg). The mechanical stress problem caused by the mismatch of material properties (especially thermal expansion coefficients) is manifested as package warpage, interface delamination, and interconnect joint failure. There is a large thermal expansion coefficient mismatch between the silicon / glass interposer with very low thermal expansion coefficient and the organic substrate with relatively high thermal expansion coefficient. The substrate shrinks much more than the interposer, and the whole structure bends to the substrate side, resulting in warpage. When the package structure cools down from the high temperature at soldering (e.g., 250°C) to room temperature, or experiences temperature cycling during service, huge thermal mechanical stress is generated inside due to the different expansion and contraction of these materials, which easily leads to the misalignment failure of complex internal circuit interconnect joints and causes the module to be scrapped.

[0009] As can be seen from the above, the thermal expansion coefficient of glass or silicon as an interposer is the lowest, and when they are selected as an interposer in a multi-chip module, they can limit the other structures with high thermal expansion coefficient and large deformation with thermal changes, so that the warpage of the multi-chip module with temperature change can be effectively inhibited.

[0010] Although 2.5D packaging is so superior, there are still the following problems in the application of multi-chip modules:

[0011] Problem one: the area of the multi-chip module is too large. The existing technology generally sets a glass interposer or a silicon interposer on a substrate, and then lays all the chips on the interposer, which leads to a too large area of the multi-chip module, especially for the module with many chips. The user must leave a corresponding mounting surface in the narrow assembly environment, causing difficulties in user assembly design.

[0012] Problem two: the single glass interposer or silicon interposer of the existing technology is still difficult to achieve an ideal inhibitory effect on the warpage of the substrate and other package bodies in the multi-chip module. In addition, the outer periphery (including the top) of the multi-chip module lacks rigid inhibition of internal stress, and the anti-warpage effect during temperature change is limited. Therefore, the existing technology still has the risk of misalignment failure of complex internal circuit interconnect joints and causes the module to be scrapped. SUMMARY

[0013] The technical problem to be solved by the present application is: how to reduce the area and inhibit the warpage formed during temperature change for a multi-chip module with high-end chips such as high-bandwidth memory.

[0014] To solve the above problems, the technical scheme of the present application is:

[0015] A packaging method of a multi-chip module, which forms a mediator by stacking the interposer layers in a stepped manner, exposes the interconnection mesa of each interposer layer with high integrated circuits, stacks the chips in multiple layers, and enables each high-bandwidth memory chip with high-bandwidth memory to be connected with the interconnection mesa of the corresponding interposer layer, and directly or indirectly installs the mediator on the substrate.

[0016] Further, the rectangular space in the central region of each interposer layer is provided to be communicated with the upper and lower surfaces, so that the interposer layer becomes a rectangular annular interposer layer, and the rectangular space in the upper annular interposer layer is larger than that in the lower annular interposer layer, so that the mediator forms a stepped recessed space for assembling the chips, and the interconnection mesa of each annular interposer layer is formed around the inside of the stepped recessed space.

[0017] The formation of the mediator includes the following steps:

[0018] S1: Forming a rectangular space of an annular interposer layer by etching a whole rectangular interposer layer;

[0019] S2: Forming a plurality of through holes communicated with the upper and lower surfaces in the annular interposer layer by etching, and providing a columnar conductor in the through hole, and insulating the columnar conductor from the inner wall of the through hole;

[0020] S3: Rewiring on the upper surface and the lower surface of each annular interposer layer, and forming the upper surface circuit and the lower surface circuit according to the design, and the upper surface circuit and the lower surface circuit are communicated through the columnar conductor;

[0021] S4: Combining the upper annular interposer layer and the lower annular interposer layer together by using hybrid bonding technology, so that the lower surface circuit of the upper annular interposer layer is communicated with the upper surface circuit of the lower annular interposer layer, and the adjacent circuits between the upper and lower annular interposer layers are provided with insulating medium.

[0022] Further, the chips in the rectangular space of the upper annular interposer layer can be multiple, and the bottom surface of each high-bandwidth memory chip is partially overlapped on the exposed interconnection mesa of the lower annular interposer layer and forms interconnection with the circuit of the interconnection mesa.

[0023] Further, a copper column is planted on the lower surface circuit of the bottom annular interposer layer, and the bottom end surface of the copper column is plated with tin, and then the bottom annular interposer layer is combined with the substrate by hot-press bonding, and the chips in the rectangular space of the bottom annular interposer layer are directly connected with the substrate.

[0024] A whole interposer one is arranged between the bottom annular interposer and the substrate, the upper surface circuit and the lower surface circuit are formed on the upper surface and the lower surface of the whole interposer one respectively by the method S2 and S3, and the whole interposer one is combined with the upper annular interposer by the method S4.

[0025] Further, the copper column is planted on the lower surface circuit of the bottom whole interposer, the bottom end surface of the copper column is plated with tin, the bottom whole interposer is combined with the substrate by the hot-press bonding method, the chip arranged in the rectangular space of the bottom annular interposer is arranged on the whole interposer one and forms the interconnection with the circuit of the interconnection platform.

[0026] The silicon through hole which is communicated with the upper and lower surfaces is punched out according to the design for the chip arranged in the stepped recessed space, the columnar conductor which connects the surface circuit of the chip is arranged in the silicon through hole, and the circuit interconnection between the two chips adjacent to each other can be realized.

[0027] Further, the whole interposer two which is combined with the top annular interposer around the top is arranged on the top of the interposer, and the chip arranged in the stepped recessed space is capped.

[0028] Further, the chip is arranged on the upper surface of the whole interposer two on the top of the multi-chip module. Beneficial effects

[0029] The chips originally laid flat on one interposer are changed to be stacked in three dimensions on the interposer, which greatly reduces the area of the multi-chip module, and makes the multi-chip module more adaptable in many application environments (assembly space and adaptation with adjacent components, etc.). At the same time, the thickness and strength of the interposer are much greater than that of the single thin chip layer, and the interposer has stronger overall warpage resistance and stability. In the process of temperature change, the interposer can more effectively suppress the warpage of the substrate and other packaging bodies combined therewith, significantly reduce the deformation degree of the multi-chip module, and avoid the failure of internal circuit interconnection to make the multi-chip module scrap. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 The assembly three-dimensional view of the substrate and the interposer arranged on the substrate described in embodiment one;

[0031] Figure 2 The disassembled three-dimensional view of the substrate and the interposer described in embodiment one;

[0032] Figure 3 The exploded view of the interposer described in embodiment one;

[0033] Figure 4 The packaging three-dimensional view of the multi-chip module described in embodiment one;

[0034] Figure 5 The cross-sectional view of the packaging structure of the multi-chip module described in embodiment one;

[0035] Figure 6 is a partial enlarged view of Figure 5

[0036] Figure 7 is an assembled perspective view of the substrate, the whole interposer one and the interposer of Example 2;

[0037] Figure 8 is a disassembled view of Figure 7

[0038] Figure 9 is a sectional view of the packaging structure of the multi-chip module of Example 2;

[0039] Figure 10 is a partial enlarged view of Figure 9

[0040] Figure 11 is an assembled perspective view of the substrate, the whole interposer one, the interposer and the whole interposer two of Example 3;

[0041] Figure 12 is a disassembled view of Figure 11

[0042] Figure 13 is a packaging perspective view of the multi-chip module of Example 4;

[0043] Figure 14 is a perspective view of the interposer of Example 5.

[0044] In the figure: 1, interposer; 100, stepped recess space; 110, interconnection mesa; 101, annular interposer; 1010, rectangular space; 1011, upper surface circuit; 1012, lower surface circuit; 2, chip; 201, high bandwidth memory chip; 202, ordinary chip; 3, whole interposer one; 4, whole interposer two; 5, substrate; 6, columnar conductor; 7, copper column. DETAILED DESCRIPTION

[0045] The present application will be further described below in conjunction with examples and drawings:

[0046] Example 1: as shown in Figures 1-6 ​​​​As shown, a packaging method of a multi-chip module, a plurality of interposer layers are stacked to form an interposer 1, each interposer layer exposes an interconnection mesa 110 with high integrated circuit, and a plurality of chips 2 are stacked, each high bandwidth memory chip 201 with high bandwidth memory is connected to the interconnection mesa 110 of the corresponding interposer layer, and the interposer 1 is directly or indirectly mounted on a substrate 5. Here, the material of the interposer layer is silicon or glass with low thermal expansion coefficient, which is the most widely used in the prior art. In this way, the chips 2 originally laid on one interposer layer are stacked in three dimensions, although the thickness of the multi-chip module is increased, the area of the multi-chip module is greatly reduced, and in many application environments, the moderate increase in the thickness of the multi-chip module and the reduction in the area of the multi-chip module can make the multi-chip module more adaptable. At the same time, the interposer 1 formed by the stepped multi-layer stacking of the interposer layer has stronger overall warpage resistance and stability, and can more effectively suppress the warpage of the package such as the substrate 5 combined therewith during temperature change, significantly reduce the deformation degree of the multi-chip module, and avoid internal circuit interconnection failure to make the multi-chip module scrap.

[0047] It should be noted that the above-mentioned interconnection of each chip 2 with high bandwidth memory to the interconnection mesa 110 of the corresponding interposer layer means that some of the chips 2 in the multi-chip module may be ordinary chips 202 without high bandwidth memory, and do not necessarily need to be connected to the above-mentioned interconnection mesa 110, while all high bandwidth memory chips 201 must be connected to the interconnection mesa 110.

[0048] As a preferred embodiment, the interposer layer is made of glass or silicon.

[0049] As a preferred embodiment, a rectangular space 1010 is arranged in the central region of each interposer layer, and the interposer layer is a rectangular annular interposer layer 101, and the rectangular space 1010 in the upper annular interposer layer 101 is larger than the rectangular space 1010 in the lower annular interposer layer 101, so as to form a stepped recess space 100 for assembling the chips 2, and the interconnection mesa 110 of each annular interposer layer 101 is formed on the inner side of the stepped recess space 100.

[0050] The formation of the interposer 1 includes the following steps:

[0051] S1: forming a rectangular space 1010 of the annular interposer layer 101 by etching a whole rectangular interposer layer;

[0052] S2: forming a plurality of through holes in the annular interposer layer 101 by etching, and arranging a columnar conductor 6 in the through hole, and insulating the columnar conductor 6 from the inner wall of the through hole;

[0053] S3: Re-distribute the wirings on the upper and lower surfaces of each ring-shaped interposer 101, and form the upper surface circuit 1011 and the lower surface circuit 1012 according to the design, and the upper surface circuit 1011 and the lower surface circuit 1012 are connected through the columnar conductor 6;

[0054] S4: Combine the upper ring-shaped interposer 101 and the lower ring-shaped interposer 101 together by using the hybrid bonding technology, so that the lower surface circuit 1012 of the upper ring-shaped interposer 101 is connected with the upper surface circuit 1011 of the lower ring-shaped interposer 101, and the adjacent circuits between the upper and lower adjacent ring-shaped interposers 101 are filled with insulating medium.

[0055] The chips 2 arranged in the rectangular space 1010 of the upper ring-shaped interposer 101 can be multiple, and the bottom surface of each high bandwidth memory chip 201 is partially overlapped on the exposed interconnection mesa 110 of the lower ring-shaped interposer 101 and forms interconnection with the circuit of the interconnection mesa 110. In this way, it can be ensured that each high bandwidth memory chip 201 can be connected with the interconnection mesa 110 of the corresponding interposer which has high integrated circuit, and the connection requirement of the high density circuit of the high bandwidth memory chip 201 is met.

[0056] The copper column 7 is planted on the lower surface circuit 1012 of the bottom ring-shaped interposer 101, and the bottom end surface of the copper column 7 is plated with tin, and then the bottom ring-shaped interposer 101 is combined with the substrate 5 by using the hot-press bonding method. The chips 2 arranged in the rectangular space 1010 of the bottom ring-shaped interposer 101 are directly connected with the substrate 5, and the chips 2 directly connected with the substrate 5 must be ordinary chips 202.

[0057] According to the requirement, the chips 2 arranged in the stepped recessed space 100 can be designed to have the through silicon via which connects the upper and lower surfaces, and the columnar conductor 6 which connects the surface circuit of the chip 2 is arranged in the through silicon via, so that the circuit interconnection between the upper and lower adjacent two chips 2 can be realized.

[0058] It should be noted that the general chip 2 only has one of the upper surface or the lower surface which has the surface circuit connected to the outside (prior art, not shown in the figure), and when the upper and lower two chips 2 are stacked and interconnected, the chip 2 can be designed to have the through silicon via which connects the upper and lower surfaces, and the columnar conductor 6 which connects the surface circuit of the chip 2 is arranged in the through silicon via, and the other end of the circuit in the through silicon via is directly or indirectly connected with the adjacent chip 2. In the drawings of the present application, the surface circuit of the chip 2 is not shown.

[0059] For the chip 2 arranged on the top surface, the through silicon via and the columnar conductor 6 can not be needed when there is no need to continue to stack the chip 2 upward. Similarly, for the ring-shaped interposer 101 arranged on the top surface, the through hole and the columnar conductor 6 can not be needed when there is no need to continue to stack the chip 2 upward.

[0060] Example 2: Figures 7-10 As shown, the difference from Embodiment 1 is that a single-piece interposer 3 is disposed between the bottom annular interposer 101 and the substrate 5. Methods S2 and S3 are used to form an upper surface circuit 1011 and a lower surface circuit 1012 on the upper and lower surfaces of the single-piece interposer 3, respectively. Method S4 is used to bond the single-piece interposer 3 to the upper annular interposer 101. Copper pillars 7 are implanted on the lower surface circuit 1012 of the bottom single-piece interposer 3, and tin is plated on the bottom end face of the copper pillars 7. Then, the bottom single-piece interposer is bonded to the substrate 5 by thermoforming. The chip 2, located within the rectangular space 1010 of the bottom annular interposer 101, is disposed on the single-piece interposer 3 and interconnected with the circuit of the interconnect platform 110.

[0061] In this embodiment, the chip 2 located in the rectangular space 1010 of the bottom annular interposer 101 is also a high-bandwidth memory chip 201, so it can be connected to the entire interposer 3.

[0062] Example 3: Figures 11-12 As shown, a single intermediary layer 4, which is connected to the top annular intermediary layer 101 around the top of the intermediary 1, is provided to cover the chip 2 located in the stepped recessed space 100. This further enhances the integrity and stability of the multi-chip module.

[0063] Example 4: Figure 13 As shown, this is a further improvement of embodiment four: chips 2 are arranged on the upper surface of the entire interposer layer 2 4 on top of the multi-chip module. Based on the characteristic of partially exposed assembly of chips 2, these chips 2 can be assembled on the upper surface of the entire interposer layer 2 4, increasing the number of chips assembled in the chip module without adding an additional interposer structure, especially increasing the number of high-bandwidth memory chips 201 assembled.

[0064] Example 5: Figure 14 As shown, the difference between this embodiment and the first embodiment is that the intermediate body 1 has a tower structure, the interconnect platform 110 is set in a stepped manner around the intermediate body 1, the chip 2 with high bandwidth memory is connected to the interconnect platform 110, and the ordinary chip 202 is directly stacked on the periphery of the high bandwidth memory chip 201.

[0065] The above embodiments are only used to describe the present invention more clearly, and should not be regarded as limiting the scope of protection covered by the present invention. Any equivalent modifications should be regarded as falling within the scope of protection covered by the present invention.

Claims

1. A method of packaging a multi-chip module, comprising: The intermediate layers are stacked in steps to form an intermediate body (1), each intermediate layer exposes an interconnection mesa (110) with high integrated circuits, and the chips (2) are stacked in multiple layers, and each high bandwidth memory chip (201) with high bandwidth memory is connected to the interconnection mesa (110) of the corresponding intermediate layer, and the intermediate body (1) is directly or indirectly mounted on the substrate (5); the central region of each intermediate layer is provided with a rectangular space (1010) that is open upward and downward, so that the intermediate layer becomes a rectangular annular intermediate layer (101), and the rectangular space (1010) in the upper annular intermediate layer (101) is larger than the rectangular space (1010) in the lower annular intermediate layer (101), so that the intermediate body (1) forms a stepped recessed space (100) for assembling chips (2), and the interconnection mesa (110) of each annular intermediate layer (101) is formed around the inside of the stepped recessed space (100); the formation of the intermediate body (1) includes the following steps: S1: Forming a rectangular space (1010) of an annular intermediate layer (101) by etching a rectangular whole intermediate layer; S2: Forming a plurality of through holes in the annular intermediate layer (101) by etching, and providing a columnar conductor (6) in the through hole, and insulating the columnar conductor (6) from the inner wall of the through hole; S3: Rerouting on the upper surface and the lower surface of each annular intermediate layer (101), and forming an upper surface circuit (1011) and a lower surface circuit (1012) according to the design, the upper surface circuit (1011) and the lower surface circuit (1012) are connected through the columnar conductor (6); S4: Using hybrid bonding technology to combine the upper annular intermediate layer (101) and the lower annular intermediate layer (101) together, so that the lower surface circuit (1012) of the upper annular intermediate layer (101) is connected to the upper surface circuit (1011) of the lower annular intermediate layer (101), and the adjacent circuits between the upper and lower annular intermediate layers (101) are provided with insulating medium.

2. The packaging method of a multi-chip module according to claim 1, wherein, The chips (2) in the rectangular space (1010) of the upper annular intermediate layer (101) have a plurality of high bandwidth memory chips (201), and the bottom surface of each high bandwidth memory chip (201) is partially overlapped with the interconnection mesa (110) exposed by the lower annular intermediate layer (101) and is connected to the circuit of the interconnection mesa (110).

3. The packaging method of a multi-chip module according to claim 2, wherein, A copper pillar (7) is planted on the lower surface circuit (1012) of the bottom annular intermediate layer (101), and the bottom end surface of the copper pillar (7) is plated with tin, and the bottom annular intermediate layer (101) is combined with the substrate (5) by thermal compression bonding, and the chips (2) in the rectangular space (1010) of the bottom annular intermediate layer (101) are directly connected to the substrate (5) to form a circuit.

4. The packaging method of a multi-chip module according to claim 2, wherein, A whole interlayer one (3) is arranged between the bottom annular interlayer (101) and the substrate (5), the upper surface circuit (1011) and the lower surface circuit (1012) are formed on the upper surface and the lower surface of the whole interlayer one (3) respectively by the method S2 and S3, and the whole interlayer one (3) is combined with the upper annular interlayer (101) by the method S4.

5. The packaging method of a multi-chip module according to claim 4, wherein, The copper column (7) is planted on the lower surface circuit (1012) of the bottom whole interlayer one (3), the bottom end surface of the copper column (7) is plated with tin, the bottom whole interlayer is combined with the substrate (5) by the hot-press bonding method, the chip (2) arranged in the rectangular space (1010) of the bottom annular interlayer (101) is arranged on the whole interlayer one (3) and forms the interconnection with the circuit of the interconnection mesa (110).

6. The method of packaging a multi-chip module according to any one of claims 1-5, wherein, The silicon through hole which is communicated with the upper and lower is punched out for the chip (2) arranged in the stepped recess space (100) according to the design, the columnar conductor (6) which connects the surface circuit of the chip (2) is arranged in the silicon through hole, and the circuit interconnection between the two chips (2) which are adjacent to each other can be realized.

7. The method of packaging a multiple-chip module according to any one of claims 1 to 5, wherein The whole interlayer two (4) which is combined with the top annular interlayer (101) around the top is arranged on the interlayer body (1), and the chip (2) arranged in the stepped recess space (100) is capped.

8. The packaging method of a multi-chip module according to claim 7, wherein, The chip (2) is arranged on the upper surface of the whole interlayer two (4) on the top of the multi-chip module.

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