Bidirectional high-frequency current detection circuit and CCM TP-PFC topology circuit

Abstract

The invention provides a bidirectional high-frequency current detection circuit. The circuit comprises current (is) and voltage (Va) detection, an isolation differential detection network, a high-speed comparator (IC1), a feedback signal (Vea), a bootstrap weighting network, a level conversion network and an isolation power supply (Vcc). Wherein Va serves as a reference zero potential (PGND) of the high-speed comparator, and is obtains a differential detection voltage Vs through the resistor Rs and the isolation differential detection network and sends the differential detection voltage Vs to the high-speed comparator IC1. An analog signal Vea is superposed with the voltage of the PGND relative to the SGND through the bootstrap weighting network to obtain Veat, and the Veat is sent to the negative end of the high-speed comparator. And when the Vs voltage exceeds Veat, the output of the high-speed comparator is overturned, and then the output is reduced to about 0-3V through the level conversion circuit and is output to a rear end for processing. The circuit has the functions of high-frequency current detection and judgment, and is high in detection and judgment precision, high in response speed, simple in circuit structure, low in cost and high in universality.

Description

Technical Field

[0001] This invention relates to a bidirectional high-frequency current detection circuit and a CCM TP-PFC topology circuit, belonging to the field of high-frequency circuit technology. Background Technology

[0002] With the rise of gallium nitride (GaN) device applications, totem-pole bridgeless power factor correction circuits (TP-PFC, such as...) have become increasingly popular. Figure 1 The circuit shown (CCM TP-PFC) is widely used in circuits. It combines the rectifier circuit and the power factor correction (PFC) circuit into one, improving efficiency by approximately 2% and increasing power density compared to traditional separate rectifier and PFC circuits. Considering cost, CCM TP-PFC is particularly suitable for high-power applications above 400W. However, because this circuit operates alternately on positive and negative half-cycles with completely different operating loops, its current sensing circuit needs to operate bidirectionally, with one half-cycle always at the high-side detection level. This means the maximum common-mode voltage of the current sensing circuit can reach as high as 400V, and the reference zero potential for the positive and negative half-cycle current sensing circuits cannot be the same point. This poses significant challenges to bidirectional high-frequency current sensing.

[0003] There are four common bidirectional current sensing schemes for CCM TP-PFC. The first uses a pure resistor combined with a 600V high common-mode voltage differential operational amplifier for detection. The circuit is simple, but the bandwidth of the high common-mode voltage operational amplifier is only about 150kHz, with a delay as high as 10μs, resulting in significant control delay and failing to meet the requirements of high-frequency operation. The second uses a pure resistor voltage divider combined with a low common-mode voltage high-speed differential operational amplifier for detection. The circuit is also simple, but the voltage division ratio exceeds 10 times, and the current detection accuracy cannot meet the requirements. The third uses a Hall sensor or a giant magnetoresistive sensor for detection. These offer higher accuracy, lower power consumption, smaller size, and support for bidirectional and DC sampling, but their delay is also around 1μs, resulting in lower than ideal operating efficiency, making them a less than ideal choice. Fourth, current transformers (CTs) are used for detection. They are low-cost, support bidirectional operation, have a relatively high bandwidth of about 1MHz, and high accuracy of 0.1% to 1%. They are not easily affected by temperature. However, the current variation range of the PFC circuit is wide, especially the DC current in continuous operation mode is large. The accuracy decreases after the coil is magnetized. In order to avoid magnetic saturation, the size must be increased, which makes it difficult to meet the requirements of high power density.

[0004] The bidirectional high-frequency current detection of the TP-PFC is also closely related to control, and the control mode is associated with the working mode. Generally, the TP-PFC adopts a critical working mode (CrM or TCM), in which only the zero-crossing current needs to be detected to start the next cycle, and the zero-crossing detection is relatively easy to implement, and the comparison reference level is relatively 0V, without the need to add an additional comparison reference level. The disadvantage of this working mode is that the peak current is large, and the working frequency changes in real time. With the introduction of GaN, the TP-PFC in continuous mode (CCM) has become a key option. Regardless of the working mode, for current detection, either the peak current in the energy storage stage is detected, or the current zero-crossing in the boost stage is detected, or real-time full detection is performed. In order to save digital resources, real-time full detection is basically not used in digital control mode. In the CCM control mode, the frequency is fixed, and the pulse width is adjusted, at which time only the peak current point in the energy storage stage needs to be detected and judged, and in the BCM or TCM control mode, the on-time is usually fixed, and the off-time is adjusted, at which time only the current zero-crossing point in the boost stage needs to be detected and judged. Therefore, after the high-frequency current is detected, it still needs to be judged, and the detection, judgment and digital control program execution all require time, and if this part of the delay is too high, it will have a serious impact on the entire control, especially when doing multi-channel interleaved parallel, it may also cause the machine to explode.

[0005] In summary, the speed and accuracy of the bidirectional high-frequency current detection and judgment of the TP-PFC are the key points of the bidirectional high-frequency current detection of the TP-PFC. In order to solve this problem, the present application proposes a new bidirectional high-frequency current detection circuit, which meets the accuracy requirements, with a detection bandwidth as high as hundreds of MHz, and is as simple, low-cost and universal as possible in engineering applications. SUMMARY

[0006] The purpose of the present application is to provide a bidirectional high-frequency current detection circuit.

[0007] The purpose of the present application is achieved by the following technical solutions: A bidirectional high-frequency current detection circuit for current detection of a TP-PFC circuit, comprising a detection resistor Rs, an isolated differential detection network, a high-speed comparator IC1, a bootstrap weighting network, and a level conversion network, wherein the high-speed comparator IC1 of the detection circuit is isolated from VCC power supply, the detection resistor Rs is connected between the TP-PFC main circuit to be detected and the reference zero potential PGND of the high-speed comparator input, the current is to be detected flows through the detection resistor Rs and the isolated differential detection network to generate a differential detection voltage Vs which is sent to the high-speed comparator IC1, and an analog signal Vea is obtained by superimposing the voltage of the high-speed comparator input ground SGND on Va after passing through the bootstrap weighting network, and then sent to the negative end of the high-speed comparator IC1 to lift the comparison level of the negative input end of the high-speed comparator IC1, when the Vs voltage exceeds Vea_t, the output of the high-speed comparator IC1 flips, and the level conversion network is used to reduce the output voltage of the high-speed comparator IC1, which can be reduced to about 0-3V and output to the back-end single-chip microcomputer or DPS for processing, wherein Vea is an analog signal obtained by multiplying the error signal of the PFC input voltage and output voltage through a multiplier, as the reference voltage of current detection.

[0008] Preferably, the isolated differential detection network comprises two resistors R1 and R2, one end of the resistor R2 is connected with the positive input end of the high-speed comparator IC1, and the other end is connected with the current input end of the detection resistor Rs, one end of the resistor R1 is connected with the current output end of the detection resistor Rs, and the other end is connected with the negative input end of the high-speed comparator IC1, when the current is flows through the detection resistor Rs, the voltage drop generated across the detection resistor Rs is differentially sent to the high-speed comparator IC1 through the resistors R1 and R2.

[0009] Preferably, the isolated differential detection network further comprises two diodes D1 and D2, wherein the diode D1 is connected between the resistor R1 and the resistor Rs, so that the current direction can only flow from the resistor R1 to the resistor Rs, and the diode D2 is connected between the resistor R2 and the resistor Rs, so that the current direction can only flow from the resistor R2 to the resistor Rs.

[0010] Preferably, the bootstrap weighting network comprises resistors Ra1, Ra2 and R3, a diode Da, a capacitor Ca, and switch tubes Qa1 and Qa2, the analog signal Vea is connected to the bootstrap weighting network through the switch tube Qa1, the other end of the switch tube Qa1 is connected with one end of the resistor Ra2, one end of the capacitor Ca and one end of the switch tube Qa2, the other end of the switch tube Qa2 is connected with ground, the other end of the capacitor Ca is connected with the other end of the resistor Ra2, the negative electrode of the diode Da and one end of the resistor R3, the other end of the resistor R3 is connected between the resistor R1 and the negative input end of the high-speed comparator IC1, the positive electrode of the diode Da is connected with one end of the resistor Ra1, and the other end of the resistor Ra1 is connected to the voltage drop end of the main circuit to be detected and the detection resistor Rs.

[0011] Preferably, the level conversion network comprises resistors R4, R5, R6, R7, R8, Rx, diodes D3, D4, voltage stabilizers ZD1, ZD2, capacitors C1, C2, the output of the high-speed comparator IC1 is connected to one end of the resistor R4 and the negative electrode of the diode D3, the positive electrode of the diode is connected to one end of the resistor R7, the other end of the resistor R4 is connected to the other end of the resistor R7, one end of the capacitor C1, one end of the resistor R5 and the negative electrode of the voltage stabilizer ZD1, the positive electrode of the voltage stabilizer ZD1 is connected to one end of the resistor R6, the other end of the resistor R6 is the output of the converted level V0, the other end of the resistor R6 is also connected to the positive electrode of the diode D4, the negative electrode of the voltage stabilizer ZD2 and one end of the capacitor C2, the negative electrode of the diode D4 is connected to a 3.3V voltage, the other end of the capacitor C2 is connected to one end of the resistor R8, the other end of the resistor R8 is the output ground SGND, and the other end of the resistor R8 is also connected to the positive electrode of the voltage stabilizer ZD2, the other end of the resistor R5 and the other end of the capacitor C1, the resistor Rx is the reactance of the TP-PFC in the power loop, when the positive half cycle, Rx is the on-resistance of the power frequency MOS tube K2, when the negative half cycle, Rx is the junction capacitance of the high-frequency MOS tube S2, one end of Rx is connected to the output end of the high-speed comparator IC1 as the reference zero potential PGND output by the high-speed comparator IC1, and the other end is connected to the output ground SGND.

[0012] Preferably, the positions of the resistor R4 and the capacitor C1 are interchanged.

[0013] Preferably, two independent constant current sources QI1 and QI2 are further included for injecting the same current to both ends of the resistor Rs.

[0014] The application further discloses a high-frequency current zero-crossing detection circuit, comprising a detection resistor Rs, an isolated differential detection network, a high-speed comparator IC1 and a level conversion network, the high-speed comparator IC1 of the detection circuit is isolated from power supply, the detection resistor Rs is connected to a TP-PFC main circuit to be detected, Va is used as the reference zero potential PGND input by the high-speed comparator, a current is through the detection resistor Rs and the isolated differential detection network to generate a differential detection voltage Vs and send to the high-speed comparator IC1, and the level conversion network is used for reducing the output voltage of the high-speed comparator IC1, wherein the current input end of the resistor Rs is connected to the negative input end of the high-speed comparator IC1, the current output end of the resistor Rs is connected to the positive input end of the high-speed comparator IC1, and when the current is reduced to 0, the high-speed comparator IC1 outputs a high level.

[0015] The application further discloses a CCM TP-PFC topology circuit, which comprises the bidirectional high-frequency current detection circuit or the high-frequency current zero-crossing detection circuit, and one bidirectional high-frequency current detection circuit or one high-frequency current zero-crossing detection circuit is arranged on the L line and the N line of the TP-PFC topology circuit, and is used for detecting the peak current or the zero-crossing current of the TP-PFC topology circuit.

[0016] Preferably, the CCM TP-PFC topology circuit comprises an alternating current input Vin, an inductor L1, switch tubes S1 and S2, switch tubes K1 and K2, capacitors C3 and C4, the alternating current input Vin is connected in parallel with the capacitor C3, one end of the capacitor C3 is connected with one end of the inductor L1, the other end of the inductor L1 is connected with the source electrode of the switch tube S1 and the drain electrode of the switch tube S2, the drain electrode of the switch tube S1 is connected with the drain electrode of the switch tube K1, the source electrode of the switch tube K1 is connected with the drain electrode of the switch tube K2, the source electrode of the switch tube K2 is connected with the source electrode of the switch tube S2, the other end of the capacitor C3 is connected between the source electrode of the switch tube K1 and the drain electrode of the switch tube K2, the capacitor C4 is a polarized capacitor, and is connected in parallel with the switch tubes K1 and K2, the positive electrode of the capacitor C4 is connected with the common end of the switch tube S1 and the switch tube K1, and the negative electrode of the capacitor C4 is connected with the common end of the switch tube S2 and the switch tube K2, wherein the first bidirectional high-frequency current detection circuit or the first high-frequency current zero-crossing detection circuit detects the current passing through between the other end of the capacitor C3 and the common end of the switch tubes K1 and K2, the reference zero potential of the high-speed comparator IC1 is set at the other end of the capacitor C3, the second bidirectional high-frequency current detection circuit or the second high-frequency current zero-crossing detection circuit detects the current between the other end of the inductor L1 and the common end of the switch tubes S1 and S2, and the reference zero potential of the high-speed comparator IC1 is set at the other end of the inductor L1.

[0017] The application further discloses a method for judging the conduction duration Ton of the CCM TP-PFC topology circuit, which is realized by the CCM TP-PFC topology circuit, converts the time point at which the high-speed comparator IC1 outputs a high level into the Ton / 2 moment, and prolongs the time by one time to obtain the conduction duration Ton.

[0018] The present application is aimed at continuous mode totem pole bridgeless power factor correction circuit (TP-PFC), and proposes a bidirectional high-frequency current detection and peak and zero-crossing judgment circuit. The circuit comprises current (is) and voltage (Va) detection, isolated differential detection network, high-precision small current constant current source (QI1 and QI2), high-speed comparator (IC1), feedback signal (Vea), bootstrap weighting network, level conversion network, and isolated power supply (Vcc). Among them, Va is used as the reference zero potential (PGND) of the high-speed comparator, but the voltage of Va relative to the output ground (SGND) changes with the positive and negative half cycles, and there are two possibilities of nearly 0V and several hundred volts of high voltage. is obtains a differential detection voltage Vs through the resistance Rs and the isolated differential detection network and sends it to the high-speed comparator IC1. After the analog signal Vea is input, the voltage of PGND relative to SGND is superimposed through the bootstrap weighting network to obtain Vea_t sent to the negative end of the high-speed comparator, and the comparison level of the negative end of the high-speed comparator is lifted. When the Vs voltage exceeds Vea_t, the high-speed comparator output flips, and then is reduced to 0-3V or so through the level conversion circuit and output to the back-end single-chip microcomputer or DPS for processing.

[0019] The current detection circuit of the present application has high-frequency current detection and judgment functions, high detection and judgment accuracy, fast response speed, simple circuit composition, low cost, and strong universality. The circuit can also be extended for zero-crossing current detection and judgment.

[0020] The beneficial effects of the present application are as follows: 1. Direct high-end current detection with resistance, fast response speed, high accuracy, and good thermal stability.

[0021] 2. Use low-voltage super-high-speed comparator instead of operational amplifier, fast response speed.

[0022] 3. The feedback signal uses bootstrap weighting for judgment, and the positive and negative half cycle detection circuits can be completely the same, only the parameter settings are slightly different.

[0023] 4. High-voltage isolation can be achieved through diodes (such as Figure 4 ), and the junction capacitance is reduced by connecting multiple diodes in series, and the circuit is simple and has a high working frequency of up to 10MHz.

[0024] 5. Composite level conversion, using the parasitic capacitance or on-resistance of power devices to form a loop, saving the number of components, Ton / 2 point sampling, and avoiding the influence of high-frequency oscillation on detection. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 The existing TP-PFC topology circuit.

[0026] Figure 2The schematic diagram of the bidirectional high-frequency current detection circuit of the present application.

[0027] Figure 3 The specific structural diagram of the bidirectional high-frequency current detection circuit of the present application.

[0028] Figure 4 The schematic diagram of the multi-tube series isolation clamping.

[0029] Figure 5 The TP-PFC topology circuit applying the high-frequency current detection circuit of the present application.

[0030] Figure 6 The positive half cycle working schematic diagram of the TP-PFC topology circuit of the present application.

[0031] Figure 7 The negative half cycle working schematic diagram of the TP-PFC topology circuit of the present application.

[0032] Figure 8 The brief control block diagram of the TP-PFC topology circuit of the present application.

[0033] Figure 9 The TP-PFC current detection timing schematic diagram.

[0034] Figure 10 The waveform diagram of the Rs current and Vea comparison judgment and output Vo.

[0035] Figure 11 The C1 and Rx working waveform diagram.

[0036] Figure 12 The PCB physical board diagram.

[0037] Figure 13 The high-frequency current zero-crossing detection circuit. DETAILED DESCRIPTION

[0038] Embodiment 1 As Figures 2-3As shown, this bidirectional high-frequency current detection circuit is used for current detection in a TP-PFC circuit. It includes: a detection resistor Rs, an isolation differential detection network, a high-speed comparator IC1, a bootstrap weighting network, and a level conversion network. The high-speed comparator IC1 is powered by an isolated VCC supply. The two ends of the detection resistor Rs are connected to the TP-PFC main circuit to be detected. Va is used as the reference zero potential PGND for the high-speed comparator input. The current is to be detected generates a differential detection voltage Vs through the detection resistor Rs and the isolation differential detection network, which is sent to the high-speed comparator IC1. The analog signal Vea is superimposed on the voltage of Va relative to the input ground SGND through the bootstrap weighting network to obtain Vea_t, which is sent to the negative terminal of the high-speed comparator IC1 to raise the comparison level of the negative input terminal of the high-speed comparator IC1. When the Vs voltage exceeds Vea_t, the output of the high-speed comparator IC1 flips. The level conversion network is used to reduce the output voltage of the high-speed comparator IC1. Vea is an analog signal obtained by multiplying the PFC input voltage and output voltage error signal by a multiplier, which serves as the reference voltage for current detection.

[0039] The isolated differential detection network includes two resistors, R1 and R2. One end of resistor R2 is connected to the positive input terminal of the high-speed comparator IC1, and the other end is connected to the current input terminal of the detection resistor Rs. One end of resistor R1 is connected to the current output terminal of the detection resistor Rs, and the other end is connected to the negative input terminal of the high-speed comparator IC1. When the current is flows through the detection resistor Rs, the voltage drop across the detection resistor Rs is differentially transmitted to the high-speed comparator IC1 through resistors R1 and R2. The reference zero potential is set at V. a Point, when current i s Flow through sensing resistor R s At that time, R s The voltage drop generated at both ends is differentially fed to the high-speed comparator IC1 via R1 and R2. During detection, the voltage drops from the isolated VCC to R1... s A small current, typically less than 1mA, is injected to obtain the detection voltage V. s V s =i s ·R s。 If isolation is not required, there is no need to inject a small current from the isolation VCC to Rs, and the circuit can be further simplified.

[0040] The isolated differential detection network can also include two diodes, D1 and D2. Diode D1 is connected between resistors R1 and Rs, ensuring that current flows only from R1 to Rs. Diode D2 is connected between resistors R2 and Rs, ensuring that current flows only from R2 to Rs. D1 and D2 can be high-voltage single diodes or multiple relatively low-voltage diodes connected in series. Diodes D1 and D2 are not mandatory.

[0041] Also can include two independent power supply constant current source QI1 and QI2, for injecting the same current to the resistance Rs both ends, generally within 1mA. Constant current source QI1 and QI2 is not necessary. Set QI1 and QI2, in order to suppress oscillation, can also be given to Q I1 , Q I2 Each increase a false load, and in high speed comparator positive and negative input each to ground a voltage regulator tube or reverse a diode, such as Figure 4 As shown in the box marked is the added false load, voltage regulator tube or diode.

[0042] Among them, the bootstrap weighted network includes resistance Ra1, Ra2 and R3, diode Da, capacitor Ca, switch tube Qa1, Qa2, analog signal Vea through switch tube Qa1 access bootstrap weighted network, switch tube Qa1 the other end simultaneously access resistance Ra2 one end, capacitor Ca one end and switch tube Qa2 one end, switch tube Qa2 the other end output ground, capacitor Ca the other end simultaneously access resistance Ra2 the other end, diode Da negative, resistance R3 one end, resistance R3 the other end access between resistance R1 and high speed comparator IC1 negative input, diode Da positive and resistance Ra1 one end connection, resistance Ra1 the other end to the main circuit to be detected, detection resistance Rs voltage drop end. Because V ea The reference zero potential and the reference zero potential of high speed high speed comparator there is a large potential difference, used here can cleverly V ea Signal high frequency bootstrap V ea_t Signal. When the main power energy storage switch tube is off, Q a2 Conduction, Q a1 Off, V a Through R a1 , D a , C a , charge, C a Both ends to (V ah -V d_Da ), wherein V d_Da D a Drop. Within 50ns after the main power energy storage switch tube is on, turn off Q a2 , open Q a1 , C a Both ends of the voltage automatically become (V a -V d_Da +V ea ), namely V ea _t =V a -V d_Da +V ea , V ea _tThe voltage is fed to the negative terminal of the high-speed comparator via R3, raising the voltage level at the negative terminal of the high-speed comparator. This raised voltage level corresponds to the comparison point of the detected voltage Vs. Because V... a It is a changing power frequency "bun" wave, at which point C a The energy can be slightly released through branches R3, R1, and D1, and the additional parallel R a2 Then the auxiliary to C a The energy is released, so that in V ah C during the downward period a The voltage continues to decrease synchronously.

[0043] The level conversion network includes resistors R4, R5, R6, R7, R8, Rx, diodes D3 and D4, Zener diodes ZD1 and ZD2, and capacitors C1 and C2. The output of the high-speed comparator IC1 is connected to one end of resistor R4 and the cathode of diode D3. The anode of diode D3 is connected to one end of resistor R7. The other end of resistor R4 is connected to the other end of resistor R7, one end of capacitor C1, one end of resistor R5, and the cathode of Zener diode ZD1. The anode of Zener diode ZD1 is connected to one end of resistor R6. The other end of resistor R6 is the converted level output V0. The other end of resistor R6 is also connected to the anode of diode D4 and the cathode of Zener diode ZD2. The negative terminal of diode D2 is connected to one end of capacitor C2. The negative terminal of diode D4 is connected to a 3.3V voltage. The other end of capacitor C2 is connected to one end of resistor R8, which is the output ground SGND. Resistor R8 is also connected to the positive terminal of Zener diode ZD2, the other end of resistor R5, and the other end of capacitor C1. Resistor Rx is the reactance of the TP-PFC in the power circuit. During the positive half-cycle, Rx is the on-resistance of the mains frequency MOSFET K2; during the negative half-cycle, Rx is the junction capacitance of the high-frequency MOSFET S2. One end of Rx is connected to the output of high-speed comparator IC1 as the reference zero potential PGND of high-speed comparator IC1, and the other end is connected to the output ground SGND. When the high-speed comparator IC1 outputs a high level, assuming V... a If the voltage is 400V and the isolated VCC power supply is 12V, then the output voltage of IC1 relative to PGND will be either 12V or 412V (different for the positive and negative half-cycles). When the output voltage is 12V, R... x This is the on-resistance of the TP-PFC slow transistor, and its value is generally less than 1Ω; when the output voltage is 412V, R x For the TP-PFC fast transistor output capacitor (C) oss The capacitive reactance is typically tens to hundreds of pF. At this point, R4, C1, R5, and R... x The voltage is divided in series, and the voltage generated across C1 and R5 is sent to V through ZD1 and R5. o Actually, there are two scenarios here: when IC1 outputs 12V and R... x When exhibiting low resistance, R4, R5, R xThis forms a voltage divider network, with C1 primarily used for filtering. When the output of IC1 is 412V and R... x When the capacitance is small, R4, C1, R x This forms a resistor-capacitor (RC) step-down network. R5 primarily provides a DC path for C1. ZD1 prevents malfunctions, and R6 reduces line oscillations. ZD2 and D4 are both resistors to V. o The voltage is clamped in both forward and reverse directions. C2 and R8 are at V o The signal is fed into the RC snubber of the backend microcontroller or DSP to prevent high-frequency oscillations from interfering. D3 and R7 quickly discharge C1 when the high-speed comparator outputs a low level. R4 and C1 can be interchanged to achieve the same effect.

[0044] Recommended parameter settings for the above components: D1, D2, D3, D a ES1J; R1, R2, R3 1KΩ; R a2 1K-10KΩ; C1, C a ≤100pF 1kV; Q a1 Q a2 Si MOSFET 600V 0.5A; Q I1 Q I2 0.5mA constant current source; IC1 ultra-high-speed comparator (typically bandwidth greater than 10MHz); R4, R5 1kΩ; R6, R7 <1kΩ; ZD13-9V; ZD23V; D41N4148; R8 4.7Ω; C2470pF; V o Approximately 3V. ea It is an analog signal obtained by multiplying the error signal between the PFC input voltage and the output voltage through a multiplier. It serves as the reference voltage for current detection and is a changing power frequency "bun" wave.

[0045] Example 2 like Figure 5As shown, the CCM TP-PFC topology circuit includes an AC input Vin, an inductor L1, switch tubes S1, S2, K1, K2, capacitors C3, C4, the AC input Vin is connected in parallel with the capacitor C3, one end of the capacitor C3 is connected to one end of the inductor L1, the other end of the inductor L1 is connected to the source of the switch tube S1 and the drain of the switch tube S2, the drain of the switch tube S1 is connected to the drain of the switch tube K1, the source of the switch tube K1 is connected to the drain of the switch tube K2, the source of the switch tube K2 is connected to the source of the switch tube S2, the other end of the capacitor C3 is connected between the source of the switch tube K1 and the drain of the switch tube K2, the capacitor C4 is a polarized capacitor connected in parallel with the switch tubes K1 and K2, the positive electrode of which is connected to the common end of the switch tube S1 and the switch tube K1, and the negative electrode of which is connected to the common end of the switch tube S2 and the switch tube K2, wherein the first bidirectional high-frequency current detection circuit detects the current passing between the other end of the capacitor C3 and the common end of the switch tubes K1 and K2, and the reference zero potential of the high-speed comparator IC1 is set at the other end of the capacitor C3, the second bidirectional high-frequency current detection circuit detects the current between the other end of the inductor L1 and the common end of the switch tubes S1 and S2, and the reference zero potential of the high-speed comparator IC1 is set at the other end of the inductor L1. The designed PCB physical board is as shown in Figure 12 .

[0046] The current detection working principle of the topology circuit is as follows: one bidirectional high-frequency current detection circuit is arranged on each of the live wire and the neutral wire of the topology circuit, and the positive half cycle and the negative half cycle are detected separately, S1 and S2 form a pair of high-frequency bridge arms, and K1 and K2 form a pair of power-frequency bridge arms.

[0047] As shown in Figure 6 , in the positive half cycle energy storage stage of the circuit: S2 and K2 are turned on, the inductor L1 stores energy, and the working loop is as shown in red in Figure 6 ; The positive half cycle voltage rising stage: S1 and K2 are turned on, the inductor L1 provides energy to the output through S1, and plays a role of voltage rising, and the working loop is as shown in light green in Figure 6 ; During the positive half cycle, Rx is the on-resistance of the slow tube K2.

[0048] As shown in Figure 7 , in the negative half cycle energy storage stage of the circuit: S1 and K1 are turned on, the inductor L1 stores energy, and the working loop is as shown in red in Figure 7 ; The negative half cycle voltage rising stage: S2 and K1 are turned on, the inductor L1 provides energy to the output through S2, and plays a role of voltage rising, and the working loop is as shown in light green in Figure 7 ; At the negative half cycle, Rx is the output junction capacitor (Coss) of the fast tube S2, since the Coss of S2 is a quantity that varies with the drain-source voltage (Vds), usually in a wide range of tens of picofarads to several nanofarads. But C1 in the detection circuit is in series with Rx, so as long as the capacitance value of C1 is selected to be smaller than or even much smaller than the minimum capacitance value of Coss, the influence brought by the wide range of Coss will be effectively inhibited.

[0049] The control block diagram of the topology circuit is shown in Figure 8 , and the control logic is to multiply the output voltage feedback error signal with the input power frequency donut wave to obtain a reference signal V ea . ea The V on is compared with the real-time inductance L1 current to generate a pulse modulation signal (PWM signal) for controlling the high-frequency bridge arm, so as to realize closed-loop control. Since the CCM TP-PFC is operated at a fixed frequency, i.e., the period (T) is fixed, the comparison here is to determine the turn-off time of the energy storage tube, i.e., to determine the conduction time (Ton). on .

[0050] Considering that in the continuous mode, the peak and valley points of the inductance current in each cycle will have strong oscillation, thereby seriously affecting the implementation of sampling. In order to avoid this problem, the present application still uses the logic of sampling once at T on / 2 in each high-frequency cycle, as shown in Figure 9 , but the working mode is different. The present application still takes the ideal V ea at T on / 2 in the traditional mode as the reference point, and when the high-speed comparator output is high, the present application determines that this time corresponds to T on / 2, and after extending the time by one time, the corresponding T on can be obtained. The advantage of the present application is that it does not need to know what the current value at T on / 2 is, nor does it need to adjust the T on width according to the difference between the ideal value and the real value. The present application obtains the ideal value, which is a high-speed high-low signal. In this way, the current detection and judgment speed of the present application is very fast, and the selection of a 300MHz bandwidth super-speed high-speed comparator can control the delay within 10ns, greatly improving the precision of digital control, while the fastest delay in the traditional current detection and control means is more than 100ns.

[0051] Figure 10 The waveform diagram showing that the Rs current is compared with Vea to judge and output Vo is shown in Figure 11The C1 and Rx working waveform chart is shown. The grid fundamental voltage effective value 220V (VP49), frequency 50Hz, high-speed comparator 12V single-track power supply, Rs flows 60kHz sine current to generate a peak 2V sine voltage to the high-speed comparator positive terminal Va (VP51), V ea The injection of 1V equivalent voltage to the high-speed comparator negative terminal Vb (VP52), when Va>Vb, the high-speed comparator outputs high level, when VaVb, the high-speed comparator outputs low level. The final high-speed comparator output (VP47) 60kHz peak 12V square wave, C1 and R4 constitute a high-pass filter, filter out the grid fundamental (VP54, VP55), and transfer the 12V square wave to R5, that is, Vc (VP53), V C Convert to 3.3V square wave Vo (VP46) through the voltage stabilizing circuit.

[0052] Example 3 As shown in Figure 13 , the bidirectional high-frequency current detection circuit of example 1 is slightly changed, the bootstrap weighting network is removed, and the positive and negative inputs of the high-speed comparator are reversed to obtain a high-frequency current zero-crossing detection circuit. The detection logic of the circuit is exactly opposite to that of example 1. When the current is falls to 0, the high-speed comparator outputs high level.

[0053] The above examples are the preferred embodiments of the present application, but the embodiments of the present application are not limited by the above examples. Any changes, modifications, substitutions, combinations, simplifications made without departing from the spirit and principles of the present application are equivalent replacement methods and are included in the protection scope of the present application.

Claims

1. A bidirectional high frequency current sensing circuit for current sensing of a TP-PFC circuit, characterized in that The detection circuit comprises a detection resistor Rs, an isolated differential detection network, a high-speed comparator IC1, a bootstrap weighting network, and a level conversion network. The high-speed comparator IC1 of the detection circuit is isolated from the VCC power supply. The detection resistor Rs is connected across the TP-PFC main circuit to be detected. The voltage Va is used as the reference zero potential PGND of the high-speed comparator input. The current is to be detected is converted into a differential detection voltage Vs by the detection resistor Rs and the isolated differential detection network, and then sent to the high-speed comparator IC1. The analog signal Vea is superimposed on the voltage of the reference ground SGND of the high-speed comparator input Va by the bootstrap weighting network, and then sent to the negative input terminal of the high-speed comparator IC1 to raise the comparison level of the negative input terminal of the high-speed comparator IC1. When the voltage Vs exceeds Vea_t, the output of the high-speed comparator IC1 is inverted. The level conversion network is used to reduce the output voltage of the high-speed comparator IC1. The Vea is an analog signal obtained by multiplying the PFC input voltage and output voltage error signal by a multiplier, and is used as the reference voltage of the current detection. The isolated differential detection network comprises two resistors R1 and R2. One end of the resistor R2 is connected to the positive input terminal of the high-speed comparator IC1, and the other end is connected to the current input terminal of the detection resistor Rs. One end of the resistor R1 is connected to the current output terminal of the detection resistor Rs, and the other end is connected to the negative input terminal of the high-speed comparator IC1. When the current is to be detected flows through the detection resistor Rs, the voltage drop generated across the detection resistor Rs is sent to the high-speed comparator IC1 in a differential manner through the resistors R1 and R2.

2. The bidirectional high-frequency current sensing circuit of claim 1, wherein: The isolated differential detection network further comprises two diodes D1 and D2. The diode D1 is connected between the resistor R1 and the resistor Rs, so that the current can only flow from the resistor R1 to the resistor Rs. The diode D2 is connected between the resistor R2 and the resistor Rs, so that the current can only flow from the resistor R2 to the resistor Rs.

3. The bidirectional high-frequency current sensing circuit of claim 2, wherein: The bootstrap weighting network comprises resistors Ra1, Ra2 and R3, a diode Da, a capacitor Ca, and switching tubes Qa1 and Qa2. The analog signal Vea is connected to the bootstrap weighting network through the switching tube Qa1. The other end of the switching tube Qa1 is connected to one end of the resistor Ra2, one end of the capacitor Ca, and one end of the switching tube Qa2. The other end of the switching tube Qa2 is connected to the ground. The other end of the capacitor Ca is connected to the other end of the resistor Ra2, the negative electrode of the diode Da, and one end of the resistor R3. The other end of the resistor R3 is connected between the resistor R1 and the negative input terminal of the high-speed comparator IC1. The positive electrode of the diode Da is connected to one end of the resistor Ra1. The other end of the resistor Ra1 is connected to the main circuit to be detected and the voltage drop terminal of the detection resistor Rs.

4. The bidirectional high frequency current sensing circuit of claim 1, wherein: ​ 5. The bidirectional high frequency current sensing circuit of any one of claims 1-4, wherein: The level conversion network comprises resistors R4, R5, R6, R7, R8, Rx, diodes D3, D4, voltage stabilizers ZD1, ZD2, capacitors C1, C2, the output of the high-speed comparator IC1 is connected to one end of the resistor R4 and the negative electrode of the diode D3, the positive electrode of the diode is connected to one end of the resistor R7, the other end of the resistor R4 is connected to the other end of the resistor R7, one end of the capacitor C1, one end of the resistor R5 and the negative electrode of the voltage stabilizer ZD1, the positive electrode of the voltage stabilizer ZD1 is connected to one end of the resistor R6, the other end of the resistor R6 is the output of the converted level V0, the other end of the resistor R6 is also connected to the positive electrode of the diode D4, the negative electrode of the voltage stabilizer ZD2 and one end of the capacitor C2, the negative electrode of the diode D4 is connected to a 3.3V voltage, the other end of the capacitor C2 is connected to one end of the resistor R8, the other end of the resistor R8 is the output ground SGND, and the positive electrode of the voltage stabilizer ZD2, the other end of the resistor R5 and the other end of the capacitor C1 are also connected.

6. The bidirectional high-frequency current sensing circuit of claim 5, wherein: The positions of the resistor R4 and the capacitor C1 are interchanged.

7. The bidirectional high frequency current sensing circuit of any one of claims 1-4, wherein: Two independent constant current sources QI1 and QI2 are further included for injecting the same current to both ends of the resistor Rs.

8. A high frequency current zero-crossing detection circuit, characterized by The detection circuit comprises a detection resistor Rs, an isolated differential detection network, a high-speed comparator IC1 and a level conversion network, the high-speed comparator IC1 of the detection circuit is isolated and powered, the detection resistor Rs is connected to the main circuit of the TP-PFC to be detected, Va is used as the reference zero potential PGND of the high-speed comparator, the current is through the detection resistor Rs and the isolated differential detection network to generate a differential detection voltage Vs and send it to the high-speed comparator IC1, and the level conversion network is used to reduce the output voltage of the high-speed comparator IC1, wherein the current input end of the resistor Rs is connected to the negative input end of the high-speed comparator IC1, the current output end of the resistor Rs is connected to the positive input end of the high-speed comparator IC1, and when the current is reduced to 0, the high-speed comparator IC1 outputs a high level.

9. A CCM TP-PFC topology circuit comprising the bidirectional high-frequency current detection circuit of any one of claims 1-7 or the high-frequency current zero-crossing detection circuit of claim 8, one bidirectional high-frequency current detection circuit or high-frequency current zero-crossing detection circuit is arranged on the L line and the N line of the TP-PFC topology circuit, for detecting the peak current or the zero-crossing current of the TP-PFC topology circuit.

10. The CCM TP-PFC topology circuit according to claim 9, comprising an alternating current input Vin, an inductor LI, switch tubes SI, S2, K1, K2, capacitors C3, C4, the alternating current input Vin being connected in parallel with the capacitor C3, one end of the capacitor C3 being connected to one end of the inductor LI, the other end of the inductor LI being connected to the source of the switch tube SI and the drain of the switch tube S2, the drain of the switch tube SI being connected to the drain of the switch tube K1, the source of the switch tube K1 being connected to the drain of the switch tube K2, the source of the switch tube K2 being connected to the source of the switch tube S2, the other end of the capacitor C3 being connected between the source of the switch tube K1 and the drain of the switch tube K2, the capacitor C4 being a polar capacitor connected in parallel with the switch tubes K1, K2, the positive pole of the capacitor C4 being connected to the common end of the switch tube SI and the switch tube K1, and the negative pole of the capacitor C4 being connected to the common end of the switch tube S2 and the switch tube K2, characterized in that, Wherein the first bidirectional high-frequency current detection circuit or the first high-frequency current zero-crossing detection circuit detects the current passing between the other end of the capacitor C3 and the common end of the switch tube K1, k2, the reference zero potential of the high-speed comparator IC1 is set at the other end of the capacitor C3, the second bidirectional high-frequency current detection circuit or the second high-frequency current zero-crossing detection circuit detects the current between the other end of the inductor L1 and the common end of the switch tube S1, S2, the reference zero potential of the high-speed comparator IC1 is set at the other end of the inductor L1, during the positive half cycle, Rx of the first bidirectional high-frequency current detection circuit is the on resistance of the power frequency MOS tube K2, during the negative half cycle, Rx of the first bidirectional high-frequency current detection circuit is the junction capacitance of the high-frequency MOS tube S2.

11. A method for determining the on-time Ton of a CCM TP-PFC topology circuit, implemented by the CCM TP-PFC topology circuit of claim 9 or 10, characterized in that The time point when the output of the high-speed comparator IC1 is converted to a high level is determined as Ton / 2 moment, and the on duration Ton is obtained by extending the time by one time.

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