Display panel

Abstract

According to a pixel unit, R and G pixels are combined into a first sub-pixel group, B and W pixels are combined into a second sub-pixel group, and an arrangement mode that Y axes are alternately arranged and X axes are adjacently arranged in different colors is adopted, so that same-color interference is avoided, the picture definition and the edge sharpness are improved, meanwhile, the high penetration characteristic of the W pixels is utilized to the maximum extent, and the display effect is improved. And the overall penetration rate of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of liquid crystal display, and in particular to a display panel. BACKGROUND

[0002] LCD (English full name: Liquid Crystal Display; Chinese full name: liquid crystal display panel) display technology is widely used in various consumer electronics due to its controllable cost, stable display and other advantages. The current user's demand for high brightness, high color gamut and low power consumption of display equipment is urgent, and the transmittance of the display panel is the core index to determine these performances.

[0003] The existing LCDs mostly use RGB three-color sub-pixels arrangement, and some schemes introduce white (W) sub-pixels to form an RGBW structure, but the sub-pixel grouping and arrangement design has obvious defects, such as the traditional RGBW arrangement does not optimize the matching of color and grouping logic, which is easy to cause light efficiency interference, and the high transmittance characteristics of the W sub-pixel are not fully utilized, resulting in low transmittance of the pixel unit.

[0004] Therefore, the existing LCD has the technical problem of low transmittance, which needs to be improved. SUMMARY

[0005] The pixel arrangement scheme provided in the embodiments of the present application arranges colors uniformly on the pixel rows and columns, improves the transmittance, and at least partially solves the above technical problems.

[0006] In order to achieve the above purpose, the present application provides a display panel, comprising pixel units arranged in an array, the pixel units comprising a first pixel, a second pixel, a third pixel and a fourth pixel; the pixel units comprising a first sub-pixel group and a second sub-pixel group adjacent to the first sub-pixel group; the first sub-pixel group comprising the first pixel and the second pixel, and the second sub-pixel group comprising the third pixel and the fourth pixel; wherein the first sub-pixel group and the second sub-pixel group are alternately arranged at least in the Y-axis direction, and in the X-axis direction, adjacent sub-pixels are arranged in different colors.

[0007] Optionally, in the X-axis direction, the first sub-pixel group of the adjacent pixel units is arranged in a staggered manner, and the second sub-pixel group of the adjacent pixel units is arranged in a staggered manner; in the Y-axis direction, the first sub-pixel group and the second sub-pixel group of the adjacent pixel units are arranged in a spaced manner.

[0008] Optionally, the positions of the sub-pixels in the first sub-pixel group are interchangeable, and the positions of the sub-pixels in the second sub-pixel group are interchangeable.

[0009] Optionally, in the X-axis direction, the second pixel is arranged adjacent to the third pixel, and the first pixel is arranged adjacent to the fourth pixel.

[0010] Optionally, the first pixel is a green pixel, the second pixel is a red pixel, the third pixel is a blue pixel, and the fourth pixel is a white pixel or a cyan pixel.

[0011] Optionally, in the pixel unit, the first sub-pixel group is arranged from top to bottom along the Y-axis with a green pixel and a red pixel, and the second sub-pixel group is arranged from top to bottom along the Y-axis with a blue pixel and a white pixel or a cyan pixel; or, in the pixel unit, the first sub-pixel group is arranged from top to bottom along the Y-axis with a red pixel and a green pixel, and the second sub-pixel group is arranged from top to bottom along the Y-axis with a white pixel or a cyan pixel and a blue pixel.

[0012] Optionally, in the X-axis direction, the first sub-pixel group in the first pixel unit and the second pixel unit is arranged from top to bottom along the Y-axis with a green pixel and a red pixel, and the second sub-pixel group is arranged from top to bottom along the Y-axis with a blue pixel and a white pixel or a cyan pixel; and the first sub-pixel group in the third pixel unit and the fourth pixel unit is arranged from top to bottom along the Y-axis with a red pixel and a green pixel, and the second sub-pixel group is arranged from top to bottom along the Y-axis with a white pixel or a cyan pixel and a blue pixel.

[0013] Optionally, in the Y-axis direction, the arrangement of the first sub-pixel group in one pixel unit is different from the arrangement of the first sub-pixel group in another pixel unit; and the arrangement of the second sub-pixel group in one pixel unit is different from the arrangement of the second sub-pixel group in another pixel unit.

[0014] Optionally, the display panel provided by the present application comprises an array substrate, the array substrate comprises: a plurality of scan lines extending along the X-axis direction, a plurality of data lines extending along the Y-axis direction, a plurality of scan lines and a plurality of data lines intersecting out of plane to define a plurality of sub-pixel openings, a plurality of sub-pixels comprising the first pixel, the second pixel, the third pixel and the fourth pixel; wherein one scan line connects the pixel electrodes of one row of sub-pixels; one data line connects the pixel electrodes of two columns of sub-pixels, and the sub-pixels connected to the same data line are located in different rows; and in the X-axis direction and the Y-axis direction, the polarities of adjacent sub-pixels are opposite and different colors.

[0015] Optionally, in the X-axis direction and the Y-axis direction, the polarities of the same-color sub-pixels in two adjacent pixel units are opposite.

[0016] Optionally, the array substrate further comprises a pixel electrode, which is located in the opening of the sub-pixel and is electrically connected to the scan line and the data line through a thin film transistor respectively; the pixel electrode has a rectangular shape, and the width of the pixel electrode in the X-axis direction is greater than the length of the pixel electrode in the Y-axis direction.

[0017] Optionally, the ratio of the width W to the length L of the pixel electrode is 3 / 2.

[0018] Optionally, the pixel electrode comprises a main electrode and a sub-electrode which are spaced apart along the Y-axis direction, and the main electrode and the sub-electrode are located on opposite sides of a scan line respectively.

[0019] Optionally, in the Y-axis direction, the distance between the main electrode of a pixel electrode and the sub-electrode of an adjacent pixel electrode is less than the distance between the main electrode and the sub-electrode of the same pixel electrode.

[0020] Optionally, a first thin film transistor, a second thin film transistor and a third thin film transistor are arranged between the main electrode and the sub-electrode; the gate electrodes of the first thin film transistor, the second thin film transistor and the third thin film transistor are connected to the same scan line, the source electrodes of the first thin film transistor and the second thin film transistor are connected to the same data line, the source electrode of the third thin film transistor is connected to the drain electrode of the second thin film transistor, the drain electrode of the first thin film transistor is connected to the main electrode, the drain electrode of the second thin film transistor is connected to the sub-electrode, and the drain electrode of the third thin film transistor is connected to a shared electrode.

[0021] The display panel of the embodiment of the present application combines R and G pixels as a first sub-pixel group and combines B and W pixels as a second sub-pixel group, and adopts a Y-axis alternating arrangement and an X-axis adjacent color arrangement, thereby avoiding color interference, improving picture definition and edge sharpness, and maximizing the use of the high penetration characteristics of W pixels to improve the overall penetration rate of the display panel.

[0022] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0023] In order to more completely understand the present application and its advantages, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0024] Figure 1 is a schematic diagram of a display panel structure provided in an example embodiment of the present disclosure; Figure 2 is a schematic diagram of a pixel structure provided in an example embodiment of the present disclosure Figure 1 is a schematic diagram of a pixel structure in part A Figure 1 ; Figure 3 is a schematic diagram of a pixel electrode structure provided in an example embodiment of the present disclosure Figure 1 is a schematic diagram of a pixel structure in part A Figure 2 ; Figure 4 is a schematic diagram of a pixel electrode structure provided in an example embodiment of the present disclosure; Figure 5 is a schematic diagram of a pixel electrode width / length ratio provided in an example embodiment of the present disclosure.

[0025] Explanation of reference signs: 10, display panel; 20, array substrate; 100, scan line; 201, data line; 300, sub-pixel; 310, pixel unit; 320, first sub-pixel group; 330, second sub-pixel group; 301, main electrode; 302, sub-electrode; T1, first thin film transistor; T2, second thin film transistor; T3, third thin film transistor; SE, shared electrode; R, red pixel; G, green pixel; B, blue pixel; W, white pixel. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0027] In the prior art, LCDs mostly use RGB three-color sub-pixels arrangement, and some schemes introduce white sub-pixels W to form RGBW structure, but the sub-pixel grouping and arrangement design has obvious defects, such as the traditional RGBW arrangement does not optimize the matching of color and grouping logic, which easily causes light efficiency interference, and the high penetration characteristics of white sub-pixels are not fully utilized, resulting in low pixel unit transmittance.

[0028] Referring to Figures 1-3 , the pixel structure schematic diagram provided by the embodiments of the present application.

[0029] In order to achieve the above object, the present application provides a display panel 10, comprising pixel units 310 arranged in an array, the pixel units 310 comprising a first pixel, a second pixel, a third pixel and a fourth pixel; the pixel units 310 comprising a first sub-pixel group 320 and a second sub-pixel group 330 adjacent to the first sub-pixel group 320; the first sub-pixel group 320 comprising the first pixel and the second pixel, and the second sub-pixel group 330 comprising the third pixel and the fourth pixel; wherein the first sub-pixel group 320 and the second sub-pixel group 330 are alternately arranged at least in the Y-axis direction, and in the X-axis direction, adjacent sub-pixels are arranged in different colors.

[0030] The present application further provides that the first pixel is a green pixel G, the second pixel is a red pixel R, the third pixel is a blue pixel B, and the fourth pixel is a white pixel W or a cyan pixel.

[0031] Specifically, the pixel unit 310 comprises four sub-pixels 300 arranged continuously in the Y-axis direction, the four sub-pixels 300 comprising a red pixel R, a green pixel G, a blue pixel B and a white pixel W or a cyan pixel, wherein the red pixel R and the green pixel G are arranged adjacently to form the first sub-pixel group 320, and the blue pixel B and the white pixel W or the cyan pixel are arranged adjacently to form the second sub-pixel group 330.

[0032] The four sub-pixels 300 arranged continuously in the Y-axis direction refer to four independent light-emitting units arranged in sequence along the longitudinal direction of the display panel 10, and the red pixel R, the green pixel G, the blue pixel B and the white pixel W refer to pixel regions covering red, green, blue filters and transparent windows, respectively, wherein the white pixel W realizes the improvement of transmittance by reducing the thickness of the color resistance layer or using high-transmittance materials. The first sub-pixel group 320 and the second sub-pixel group 330 refer to a structure in which high-saturation color resistance and low-saturation color resistance are grouped and arranged, and the combination of color resistance of adjacent pixels can be realized by mask patterning process. This grouping strategy can balance the light efficiency characteristics of different color resistances.

[0033] Specifically, the four sub-pixels 300 are arranged in longitudinal succession to form a compact pixel unit 310 layout, the red pixel R and the green pixel G are adjacent to constitute a first sub-pixel group 320, and the blue pixel B and the white pixel W are adjacent to constitute a second sub-pixel group 330. By placing high-saturation red / green primary colors and low-saturation blue / white primary colors in different sub-pixel groups 300, the light transmission characteristics of the white pixel W are used to compensate for the brightness loss of the blue pixel B while ensuring the color gamut coverage. The longitudinal continuous arrangement mode shortens the extension length of the data line 201 shared path in the Y-axis direction, reducing the coupling difference in the signal transmission process. The interval arrangement of the first sub-pixel group 320 and the second sub-pixel group 330 forms a spatial complementary relationship of color resistance distribution, avoiding the visual abruptness caused by the direct adjacency of high-brightness white pixels W and low-brightness blue pixels B.

[0034] Compared with the prior art, when the traditional DLS architecture adopts RGB three-color horizontal arrangement, the color resistance layout is not compact enough and lacks a light transmission compensation mechanism. The present scheme introduces white pixels W or cyan pixels and adopts longitudinal four-color grouping arrangement, increasing the proportion of light transmission area under the same pixel area, while shortening the data line 201 shared path through longitudinal continuous arrangement. The RGB three-color horizontal arrangement in the prior art easily leads to a decrease in the transmittance of the color resistance aggregation area, while the present scheme forms a brightness balance area through the adjacent arrangement of white pixels W or cyan pixels and blue pixels B, effectively improving display uniformity.

[0035] Through the above technical scheme, the present application solves the problems of insufficient transmittance and display granularity caused by RGB three-color arrangement in the traditional DLS architecture. The longitudinal arrangement of the four-color pixel unit 310 shortens the data line 201 shared path, reducing the vertical crosstalk caused by signal coupling differences. The introduction of white pixels W improves the overall brightness uniformity through a light transmission compensation mechanism, and the grouping arrangement strategy balances the light efficiency characteristics of different color resistances, reducing the visual granularity of the color resistance aggregation area in high-resolution display scenarios.

[0036] The present application further proposes that the first sub-pixel group 320 of the adjacent pixel unit 310 in the X-axis direction is arranged in a staggered manner, and the second sub-pixel group 330 of the adjacent pixel unit 310 is arranged in a staggered manner; the first sub-pixel group 320 and the second sub-pixel group 330 of the adjacent pixel unit 310 in the Y-axis direction are arranged in an interval arrangement.

[0037] The staggered arrangement in the X-axis direction means that the same type of sub-pixel groups in adjacent pixel units 310 are not on the same vertical axis in the horizontal direction. Specifically, the sub-pixel groups can be offset by two sub-pixel 300 widths in the horizontal direction, which breaks the linear alignment of the same color sub-pixels 300 in the traditional layout. The interval arrangement in the Y-axis direction means that the sub-pixel groups of adjacent pixel units 310 are alternately distributed in the vertical direction. Specifically, the sub-pixel groups can be spaced by a distance of two sub-pixel 300 heights in the vertical direction, which avoids longitudinal signal coupling.

[0038] Specifically, in the horizontal direction, the first sub-pixel group 320 and the first sub-pixel group 320 of the adjacent pixel unit 310 form a staggered arrangement, and the second sub-pixel group 330 and the second sub-pixel group 330 of the adjacent pixel unit 310 also form a staggered arrangement. This double staggered structure makes the same color sub-pixels 300 discontinuously distributed in the horizontal direction, thereby dispersing the color resistance aggregation area. In the vertical direction, the first sub-pixel group 320 and the second sub-pixel group 330 are alternately arranged to form a longitudinal interval layout. This layout maintains the logical association between pixel units 310 and reduces the electric field interference between adjacent sub-pixel groups through non-continuous arrangement. The synergistic effect of horizontal staggering and longitudinal spacing makes the color resistance distribution more uniform, while reducing the overlap probability of the same polarity area.

[0039] Compared with the prior art, the same color sub-pixels 300 in the traditional DLS architecture are linearly aligned in the horizontal and vertical directions, resulting in a decrease in the optical transmittance of the color resistance concentrated area, and the continuous distribution of the same polarity sub-pixels 300 easily causes vertical crosstalk. The present scheme disperses the same color sub-pixels 300 to non-continuous areas through two-dimensional space interleaving arrangement, while breaking the symmetry of the polarity distribution, thereby achieving transmittance improvement and display interference suppression under the same process conditions.

[0040] Through the above technical scheme, the present application effectively solves the problem of limited transmittance caused by the insufficient compactness of color resistance in the traditional architecture, and improves the light transmittance efficiency through color resistance dispersion layout. At the same time, the display graininess caused by the aggregation of the same polarity sub-pixels 300 is suppressed, so that the picture fineness in the high resolution scenario is improved.

[0041] The present application further proposes that the positions of the sub-pixels 300 in the first sub-pixel group 320 are interchangeable, and the positions of the sub-pixels 300 in the second sub-pixel group 330 are interchangeable.

[0042] The first sub-pixel group 320 refers to a combination of sub-pixels 300 adjacent to each other, which is formed by red pixels R and green pixels G. Specifically, the red pixels R and the green pixels G can be arranged alternately in the Y-axis direction to realize the first sub-pixel group 320. The spatial distribution of red and green colors can be optimized by changing the arrangement order of the red pixels R and the green pixels G. The second sub-pixel group 330 refers to a combination of sub-pixels 300 adjacent to each other, which is formed by blue pixels B and white pixels W or cyan pixels. Specifically, the blue pixels B and the white pixels W or the cyan pixels can be arranged alternately in the Y-axis direction to realize the second sub-pixel group 330. The distribution of the transmittance can be balanced by adjusting the arrangement density of the blue and white / cyan colors.

[0043] Specifically, the positions of the red pixels R and the green pixels G are exchanged to break the aggregation of the red and green sub-pixels in fixed positions. For example, the RG and GR arrangements are arranged alternately in the adjacent pixel units 310 to avoid the continuous distribution of the same-color sub-pixels 300 in the vertical or horizontal direction, thereby reducing the graininess in high-resolution display. The positions of the blue pixels B and the white pixels W or the cyan pixels are exchanged to adjust the distribution area of the white pixels W or the cyan pixels. For example, the BW and WB arrangements are arranged alternately in the adjacent pixel units 310 to make the transmittance contribution of the white pixels W in different areas of the panel tend to be balanced, thereby improving the overall brightness consistency. At the same time, the position exchange within the sub-pixel group makes the polarity distribution of the same-color sub-pixels 300 in the adjacent pixel units 310 form reverse symmetry. For example, the RG sub-pixel group and the GR sub-pixel group in the same row adopt positive polarity and negative polarity, respectively. The dispersion of the polarity distribution reduces the risk of vertical crosstalk.

[0044] Compared with the prior art, in the traditional DLS architecture, the positions of the R, G, B, and W sub-pixels are arranged in a fixed order, which causes the dense distribution of the same-color sub-pixels 300 in the vertical or horizontal direction, resulting in uneven transmittance distribution and graininess. The present scheme allows the position exchange within the sub-pixel group 300, so that the arrangement density of the red, green, blue, and white sub-pixels can be adjusted in space, which not only optimizes the uniformity of the color resistance distribution, but also suppresses the signal coupling interference by the polarity reverse symmetry design.

[0045] Through the above technical scheme, the present application solves the problems of low transmittance and insufficient display fineness caused by the insufficient compactness of the color resistance layout in the traditional architecture. The brightness uniformity is optimized by dynamically adjusting the arrangement of the sub-pixels 300, and the vertical crosstalk risk is reduced by using the symmetry of the polarity distribution.

[0046] As Figure 2As shown, the pixel arrangement of the display panel 10 is specifically that, in the pixel unit 310, the first sub-pixel group 320 is provided with green pixels G and red pixels R from top to bottom along the Y axis, and the second sub-pixel group 330 is provided with blue pixels B and white pixels W or cyan pixels from top to bottom along the Y axis; or, in the pixel unit, the first sub-pixel group 320 is provided with red pixels R and green pixels G from top to bottom along the Y axis, and the second sub-pixel group 330 is provided with white pixels W or cyan pixels and blue pixels B from top to bottom along the Y axis.

[0047] Further, in the four pixel units arranged continuously in the X axis direction: the first sub-pixel group 320 in the first pixel unit and the second pixel unit is provided with green pixels G and red pixels R from top to bottom along the Y axis, and the second sub-pixel group 330 is provided with blue pixels B and white pixels W or cyan pixels from top to bottom along the Y axis; and the first sub-pixel group 320 in the third pixel unit and the fourth pixel unit is provided with red pixels R and green pixels G from top to bottom along the Y axis, and the second sub-pixel group 330 is provided with white pixels W or cyan pixels and blue pixels B from top to bottom along the Y axis.

[0048] Further, in the two pixel units arranged adjacently in the Y axis direction: the arrangement of the first sub-pixel group 320 of one pixel unit is different from that of the first sub-pixel group 320 of the other pixel unit; and the arrangement of the second sub-pixel group 330 of one pixel unit is different from that of the second sub-pixel group 330 of the other pixel unit.

[0049] Another aspect of the embodiments of the present application is that the DLS pixel architecture has been used in the field of LCD panel for a long time to reduce the number of data lines, but the traditional architecture has the vertical crosstalk and wobble phenomenon caused by data line sharing. Due to the double short arm design, the signal coupling of adjacent pixels is not balanced, and vertical stripe interference is easily generated during dynamic display. At the same time, the compactness of RGB three-color barrier arrangement is insufficient, resulting in limited transmittance and grainy feeling in high-resolution display. The existing solution uses multi-line driving technology to solve the interference problem, but increases the difficulty of pixel charging, and cannot balance the contradiction between cost and display performance.

[0050] As shown in Figure 3 To solve the above problems, the present application proposes a display panel comprising a scan line 100 extending along the X axis, a data line 201 extending along the Y axis, and the scan line 100 and the data line 201 intersecting in different planes to form a sub-pixel opening. A pixel electrode is located in the opening and is connected to the scan line 100 and the data line 201 through a thin film transistor. A single scan line 100 connects a row of pixel electrodes, and a single data line 201 connects two columns of pixel electrodes in different rows. Adjacent sub-pixels 300 adopt an arrangement mode of opposite polarity and different color in the X axis and Y axis directions.

[0051] The out-of-plane intersection means that the scanning line 100 and the data line 201 intersect in different plane layers to form an opening region, and the opening region can be realized by arranging an insulating layer between metal layers to avoid short circuit of the lines.

[0052] The opposite polarity means that the polarities of the voltages applied by adjacent sub-pixels 300 during driving are opposite to each other, and the opposite polarity can be realized by using a line-by-line inversion or point inversion driving mode to form an electric field balance.

[0053] The different color arrangement means that different color filters are arranged in adjacent sub-pixels 300, and the different color arrangement can be realized by using a red, green, blue, and white or cyan four-color alternating distribution mode to break the continuity of the same color pixels.

[0054] Specifically, the intersection layout of the scanning line 100 and the data line 201 on the vertical plane of the display panel 10 forms a matrix pixel array. The data line 201 drives two columns of different rows of sub-pixels 300 at the same time through a thin film transistor, so that the number of data lines 201 is reduced to one half of that of the conventional architecture. Adjacent sub-pixels 300 are arranged in combination of opposite polarity and different color in the horizontal and vertical directions, for example, the upper and lower and left and right adjacent sub-pixels 300 of a red positive polarity sub-pixel 300 are arranged as green, blue, white or cyan negative polarity. This layout makes the electric field directions of adjacent sub-pixels 300 offset each other, thereby effectively suppressing the signal coupling in the vertical direction. At the same time, the interval distribution of different color sub-pixels 300 avoids the transmittance loss caused by the continuous arrangement of the same color pixels, and improves the light transmittance efficiency through the color resistance alternating arrangement.

[0055] Compared with the prior art, the conventional DLS architecture uses a single data line 201 to connect adjacent sub-pixels 300 in the same column, resulting in the aggregation of the same color and polarity pixels in the vertical direction. The present scheme connects the data line 201 to two columns of sub-pixels 300 in different rows by staggered connection, which realizes the polarity inversion of adjacent row sub-pixels 300 while maintaining the number of data lines 201 reduced by half. In the prior art, the continuous arrangement of R, G and B pixels easily causes transmittance fluctuation, and the present scheme makes the color resistance distribution more uniform through the design of adjacent different colors, eliminating local light transmittance difference. The conventional architecture increases the driving line to solve the interference, and the present scheme realizes the crosstalk suppression under the same driving condition through the combination design of polarity inversion and different color distribution.

[0056] Through the above technical scheme, the present application effectively suppresses the vertical crosstalk and the wobble phenomenon while maintaining the data line 201 sharing cost reduction advantage. The polarity inversion of adjacent sub-pixels 300 balances the electric field distribution and eliminates the brightness difference caused by signal coupling. The interval arrangement of different color sub-pixels 300 improves the panel transmittance and avoids the graininess caused by the aggregation of the same color pixels. The staggered connection design of the data line 201 reduces the number of hardware while optimizing the line load distribution, ensuring the charging efficiency of the pixels.

[0057] The application further proposes that at least three continuous and different color sub-pixels 300 constitute a pixel unit 310, and in the X-axis direction and the Y-axis direction, the polarities of the same color sub-pixels 300 in the adjacent two pixel units 310 are opposite.

[0058] The continuous and different color sub-pixels 300 constituting the pixel unit 310 refers to arranging three or more sub-pixels 300 of different colors in sequence to form a basic display unit, which can be implemented by using a combination of red, green and blue three colors or adding a combination of four colors of white. This arrangement reduces the gap area by optimizing the color resistance distribution density and improves the aperture ratio.

[0059] The polarities of the same color sub-pixels 300 of the adjacent pixel units 310 are opposite, which means that in the horizontal and vertical directions, the same color sub-pixels 300 are driven by opposite voltage polarities, which can be achieved by alternately inverting the signal polarity of the data line 201. This design forms a symmetrical electric field distribution to offset the charge coupling effect between adjacent pixels.

[0060] Specifically, the continuous arrangement of different color sub-pixels 300 in the pixel unit 310 makes the color resistance layout more compact, reduces the area ratio of non-emitting area, and thus improves the overall light transmission efficiency of the panel. The same color sub-pixels 300 of the adjacent pixel units 310 are driven by opposite polarities in the X-axis and Y-axis directions, so that the positive and negative electric fields of the adjacent regions cancel each other out, suppressing the signal interference caused by the sharing of the data line 201. At the same time, the polarity inversion strategy of the same color sub-pixels 300 can disperse the gathering effect of the same color pixels, avoiding the graininess caused by the concentration of color resistance in high-resolution display. The polarity inversion covers both horizontal and vertical dimensions, ensuring the uniformity of the electric field distribution under different viewing angles and eliminating the head-shaking phenomenon.

[0061] Compared with the prior art, the traditional DLS architecture uses a single-line driving scheme and the same polarity of the same color sub-pixels 300, resulting in vertical direction electric field superposition causing crosstalk. This scheme uses multi-color sub-pixel 300 combination and double-axis polarity inversion to reduce the signal coupling strength while maintaining the data line 201 sharing advantage.

[0062] Through the above technical solutions, the application effectively suppresses vertical crosstalk and head-shaking phenomenon, improves the uniformity of the display picture; optimizes the color resistance layout to increase the light transmission area and improve the panel penetration rate; disperses the gathering effect of the same color pixels to enhance the display delicacy; the double-axis polarity inversion design does not need to rely on specific driving scheme or material process, so it can be adapted to different active layer materials and panel specifications. Please refer to Figure 4 , the pixel electrode structure schematic diagram provided by the application.

[0063] The outer contour of the pixel electrode is in the shape of a rectangle, and the width of the pixel electrode in the X-axis direction is greater than the length in the Y-axis direction.

[0064] The outer contour of the pixel electrode in the shape of a rectangle refers to the edge of the pixel electrode formed by four straight line segments connected end to end to form a nearly rectangular planar structure. The width of the electrode in the horizontal direction is greater than the length in the vertical direction, which makes the electrode form a wider charge storage area in the horizontal direction.

[0065] Specifically, by designing the pixel electrode as a horizontally expanded rectangular structure, the electrode edge can be more closely fitted to the trend of the adjacent data line 201, effectively reducing the invalid gap area between the electrode and the data line 201. In the data line 201 sharing architecture, when the same data line 201 needs to drive two columns of sub-pixels 300, the shorter longitudinal electrode design shortens the path of the data line 201 signal transmission to the center of the electrode, thereby reducing signal delay and improving charging efficiency. At the same time, the horizontally expanded electrode edge forms a symmetrically distributed horizontal electric field, so that the vertical direction electric field between adjacent rows of pixels is deformed to be mutually offset, significantly suppressing the vertical crosstalk phenomenon. The moderate control of the longitudinal length of the electrode avoids the increase of parasitic capacitance caused by excessive longitudinal extension, and maintains the accuracy of gray scale display under the premise of ensuring the charging speed.

[0066] Compared with the prior art, the traditional data line 201 sharing architecture mostly uses a longitudinally extended electrode form, which results in a large gap area between the electrode and the data line 201, which not only reduces the aperture ratio but also aggravates the asymmetric distribution of the vertical direction electric field. The present application realizes the optimization matching of the electrode layout and the signal transmission path while maintaining the advantages of the data line 201 sharing by the horizontally expanded rectangular electrode design, forming a more uniform electric field distribution characteristic.

[0067] Through the above technical solutions, the present application effectively improves the light transmission efficiency of the pixel opening area, significantly improves the utilization rate of the backlight source; by balancing the horizontal direction electric field distribution, the signal interference between adjacent rows of pixels is suppressed, and the vertical direction display abnormal phenomenon is eliminated; at the same time, the optimized electrode form takes into account the charging speed and signal integrity requirements, ensuring the gray scale accuracy in high resolution display scenarios.

[0068] Please refer to Figure 5 The pixel electrode width-to-length ratio diagram provided by the present application.

[0069] The present application further provides that the ratio of the width to the length of the pixel electrode is 3 / 2.

[0070] The width of the pixel electrode refers to the electrode size extending along the X-axis direction, the length of the pixel electrode refers to the electrode size extending along the Y-axis direction, and the ratio of 3 / 2 refers to the proportional relationship between the width and the length, which is used to balance the uniformity of the electric field distribution and the signal transmission efficiency.

[0071] Specifically, by setting the geometric shape of the pixel electrode to have a width-to-length ratio of 3 / 2, the coverage range of the electrode in the X-axis direction is expanded, thereby increasing the effective area of the electric field in the opening area, while shortening the extension distance of the electrode in the Y-axis direction and reducing the signal delay in the transmission path. The ratio makes the electrode shape close to a square structure, and compared with the traditional elongated electrode, the edge electric field distribution is more uniform, the edge electric field overlapping area between the electrodes of adjacent sub-pixels 300 is reduced, and the parasitic capacitance coupling effect is inhibited.

[0072] Compared with the prior art, the pixel electrode in the traditional DLS architecture usually has a 2:3 aspect ratio, which causes the electrode to excessively extend in the Y-axis direction, thereby not only increasing the signal transmission delay, but also intensifying the electric field coupling between adjacent rows of sub-pixels 300. The present scheme has a width-to-length ratio of 3:2, which not only maintains the advantages of the data line 201 sharing architecture, but also makes the electrode shape more suitable for high-resolution display requirements, thereby not only improving the utilization rate of the electric field in the opening area, but also reducing the risk of vertical signal interference.

[0073] Through the above technical scheme, the present application effectively improves the electric field distribution characteristics of the pixel electrode, reduces the vertical crosstalk caused by parasitic capacitance, optimizes the uniformity of the color resist layout, thereby improving the panel transmittance and eliminating the graininess in high-resolution display, and significantly improving the display delicacy. The design is compatible with different active layer material processes, and does not need to increase additional driving lines to balance the charging efficiency and signal integrity.

[0074] Please continue to refer to Figure 4 The present application further provides that the pixel electrode includes main electrodes 301 and sub-electrodes 302 distributed along the Y-axis direction, and the main electrodes 301 and the sub-electrodes 302 are located on opposite sides of a scan line 100, respectively.

[0075] The main electrode 301 refers to the part of the pixel electrode that bears the main electric field driving function, and the sub-electrode 302 refers to the part of the pixel electrode that assists in adjusting the electric field distribution. In the present application, the main electrode 301 and the sub-electrode 302 each have a width-to-length ratio of 1.5:2.

[0076] The pixel electrode of the present application is an eight-domain branch electrode structure, the main electrode 301 has four-domain branch electrodes, and the sub-electrode 302 has four-domain branch electrodes.

[0077] The interval distribution in the Y-axis direction means that the main electrode 301 and the sub-electrode 302 are alternately arranged in the vertical direction, which can disperse the electric field coupling path between adjacent sub-pixels 300.

[0078] The opposite sides of the scanning line 100 means that the main electrode 301 and the sub-electrode 302 are located on the upper and lower sides of the same scanning line 100, and the electrical connection between the main electrode 301, the sub-electrode 302 and the scanning line 100 can be realized by a thin film transistor. The layout makes the electrodes controlled by the same scanning line 100 form a symmetrical structure to reduce the signal delay difference.

[0079] Specifically, the interval distribution of the main electrode 301 and the sub-electrode 302 physically isolates the electric field interference of adjacent sub-pixels 300 in the vertical direction, reducing the signal crosstalk strength. The main electrode 301 and the sub-electrode 302 are arranged on the opposite sides of the scanning line 100 to form a symmetrical layout, and the scanning signal synchronously controls the charging and discharging time sequence of the electrodes on both sides to avoid voltage fluctuations caused by differences in signal transmission paths. The main electrode 301 undertakes the main charging task, and the sub-electrode 302 supplements the adjustment of the electric field distribution in the late charging period. The time-sharing charging strategy reduces the charging competition caused by the sharing of the data line 201, and ensures that the pixel unit 310 reaches the target voltage within the limited charging time. The gap design of the main electrode 301 and the sub-electrode 302 is suitable for different driving frequencies, and the penetration rate and signal coupling suppression demand are balanced by adjusting the gap width.

[0080] Compared with the prior art, the traditional data line 201 sharing architecture adopts a single continuous electrode structure, and the electric field coupling path of adjacent sub-pixels 300 is concentrated, resulting in significant vertical crosstalk and wobble. The present scheme divides the electrodes and arranges them on both sides of the scanning line 100 to form a multi-path electric field distribution. The interference signal is dispersed to different spatial regions, and the coupling strength is weakened. The prior art relies on a multi-line driving scheme to suppress interference, but increases the charging burden. The present scheme optimizes the electrode division and time-sharing charging in cooperation, maintains the single-line driving logic while improving the charging efficiency, and avoids additional circuit design. The continuous arrangement of the electrodes in the prior art limits the penetration rate improvement space; the present scheme increases the light transmission area by gap design while maintaining the effective driving area of the electrodes.

[0081] Through the above technical scheme, the present application effectively reduces the signal crosstalk in the vertical direction and suppresses the wobble phenomenon; optimizes the charging time sequence distribution and alleviates the charging shortage problem caused by the sharing of the data line 201; improves the light transmittance of the pixel area and improves the display brightness and color uniformity; the electrode division design is compatible with different active layer material processes and adapts to diversified panel specification requirements.

[0082] The application further proposes that in the Y-axis direction, the distance between the main electrode 301 of one pixel electrode and the sub-electrode 302 of the adjacent another pixel electrode is smaller than the distance between the main electrode 301 and the sub-electrode 302 of the same pixel electrode.

[0083] The main electrode 301 refers to the electrode part of the pixel electrode directly acted by the data line 201, which provides the main electric field driving signal for the sub-pixel 300; the sub-electrode 302 refers to the electrode part of the pixel electrode indirectly connected through the secondary thin film transistor, which cooperates with the main electrode 301 to form a uniformly distributed electric field.

[0084] The distance refers to the vertical distance between two conductive structures, which balances the relationship between parasitic capacitance and aperture ratio through asymmetric distance design.

[0085] Specifically, the distance between the main electrode 301 and the sub-electrode 302 of the adjacent pixel unit 310 is reduced, which can reduce the signal coupling effect between adjacent rows of pixels due to parasitic capacitance, thereby suppressing the vertical brightness crosstalk phenomenon. The larger distance between the main electrode 301 and the sub-electrode 302 in the same pixel provides space redundancy for the wiring of the shared data line 201, avoiding the risk of short circuit caused by dense wiring. In the Y-axis direction, the main electrode 301 and the sub-electrode 302 of the adjacent pixel unit 310 form a misaligned coupling structure, which reduces the impedance of the signal transmission path by shortening the distance between them, while maintaining the electrode distance within the same pixel to maintain the uniformity of the electric field. This layout breaks the symmetry constraint of the traditional equal distance design, optimizing the light transmission area of the pixel opening area while suppressing vertical crosstalk.

[0086] Compared with the prior art, the traditional DLS architecture adopts a symmetric electrode layout with equal distance, which leads to a contradictory relationship between the parasitic capacitance coupling strength between adjacent rows of pixels and the pixel aperture ratio. The present scheme establishes an asymmetric electrode layout to achieve weak coupling between adjacent rows of pixels and strong isolation between electrodes within the same pixel in the Y-axis direction, which not only reduces the vertical crosstalk strength, but also improves the aperture ratio by shortening the distance between adjacent electrodes.

[0087] Through the above technical scheme, the application effectively reduces the parasitic capacitance coupling strength between adjacent rows of pixels, and suppresses the generation of vertical crosstalk and wobble phenomenon. At the same time, the asymmetric distance design improves the light transmission efficiency of the pixel opening area by optimizing the electrode layout under the premise of ensuring the uniformity of the electric field within the pixel, solving the technical contradiction that the traditional DLS architecture cannot balance cost reduction and display performance.

[0088] The application further provides that the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are arranged between the main electrode 301 and the sub-electrode 302; the gate of the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 is connected to the same scanning line 100, the source of the first thin film transistor T1 and the second thin film transistor T2 is connected to the same data line 201, the source of the third thin film transistor T3 is connected to the drain of the second thin film transistor T2, the drain of the first thin film transistor T1 is connected to the main electrode 301, the drain of the second thin film transistor T2 is connected to the sub-electrode 302, and the drain of the third thin film transistor T3 is connected to the shared electrode SE.

[0089] The main electrode 301 refers to a core conductive area for receiving a data signal and driving pixel display, and a conduction path is formed by the first thin film transistor T1 and the data line 201. The sub-electrode 302 refers to a secondary conductive area for assisting in adjusting the pixel electric field, and independently receives a data signal through the second thin film transistor T2. The shared electrode SE refers to a common potential node for charge balance, which can be a conductive strip structure connected to a common electrode layer, and a charge discharge channel is formed by the third thin film transistor T3 and the sub-electrode 302.

[0090] Specifically, when the scanning line 100 inputs an opening signal, the three thin film transistors are turned on at the same time. The first thin film transistor T1 transmits the data line 201 voltage to the main electrode 301 to complete the main area charging, and the second thin film transistor T2 transmits the same data line 201 voltage to the sub-electrode 302 to complete the secondary area charging. After the scanning line 100 is turned off, the third thin film transistor T3 guides the excess charge remaining in the sub-electrode 302 to the shared electrode SE through the connection of the drain of the second thin film transistor T2 and the shared electrode SE. This charge discharge mechanism can eliminate the vertical direction electric field interference caused by the residual charge between adjacent pixels, and the independent driving path of the main electrode 301 and the sub-electrode 302 avoids the charging efficiency decline caused by signal coupling.

[0091] Compared with the prior art, the traditional data line 201 sharing architecture only uses two thin film transistors to drive the main electrode 301 and the sub-electrode 302, but lacks a charge discharge path, resulting in residual charge accumulation. The connection structure of the third thin film transistor T3 and the shared electrode SE added in the scheme realizes the dynamic balance of the internal electric field of the pixel through the charge redistribution mechanism without increasing the number of data lines 201.

[0092] By the technical solutions, the generation of vertical crosstalk and wobble phenomenon is effectively inhibited, and the display uniformity problem caused by uneven signal coupling in the traditional architecture is solved. The establishment of the charge discharge channel improves the potential stability of the pixel electrode, avoids the influence of residual charge on adjacent pixels after the end of the charging period, and the independent driving path of the main electrode 301 and the sub-electrode 302 ensures the charging efficiency under high refresh rate.

[0093] The display panel provided by the present application combines R and G pixels into a first sub-pixel group 320, combines B and W pixels into a second sub-pixel group 330, and adopts a Y-axis alternating arrangement and an X-axis adjacent color arrangement, thereby avoiding color interference, improving picture definition and edge sharpness, maximizing the use of the high penetration characteristics of W pixels, and improving the overall penetration rate of the display panel. In a second aspect, the display panel provided by the present application connects two columns of different row sub-pixels 300 with a single data line 201, and the adjacent row and column sub-pixels 300 are different in color and opposite in polarity. Through this architecture design, the number of data lines 201 is reduced while realizing polarity inversion and color resistance alternating arrangement of adjacent sub-pixels 300. The polarity and color resistance of each column are uniformly arranged, thereby reducing the graininess and wobble caused by the aggregation of polarity and color resistance. In addition, by adjusting the width-length ratio of the pixel electrode, the laterally expanded electrode edge forms a symmetrically distributed lateral electric field, so that the vertical direction electric field between adjacent rows of pixels is deformed to be mutually offset, thereby significantly inhibiting the vertical crosstalk phenomenon. The moderate control of the longitudinal length of the electrode avoids the increase of parasitic capacitance caused by the excessive longitudinal extension, and maintains the accuracy of gray scale display under the premise of ensuring the charging speed.

[0094] In combination with all the technical solutions and achievable technical effects of the present application, the active layer of the thin film transistor of the array substrate and the display panel mentioned in the present application is not only suitable for amorphous silicon, but also suitable for materials such as oxides; the array substrate and the display panel mentioned in the present application are suitable for panel designs of various sizes, various refresh frequencies and various resolutions.

[0095] The present application also provides a display panel, which comprises the array substrate, the counter substrate and the liquid crystal layer between the array substrate and the counter substrate. The display panel comprises all the technical solutions and technical effects of the array substrate, which will not be described here.

[0096] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first" and "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0097] In the above embodiments, the description of each embodiment is focused on, and the part not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0098] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0099] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment without departing from the technical solution content of the present application and in accordance with the technical essence of the present application still belongs to the scope of the technical solution of the present application.

Claims

1. A display panel, characterized by, The pixel unit comprises a first pixel, a second pixel, a third pixel and a fourth pixel, the first pixel, the second pixel, the third pixel and the fourth pixel are different in color; The pixel unit comprises a first sub-pixel group and a second sub-pixel group adjacent to the first sub-pixel group; The first sub-pixel group comprises the first pixel and the second pixel, and the second sub-pixel group comprises the third pixel and the fourth pixel; The first sub-pixel group and the second sub-pixel group are alternately arranged at least in the Y-axis direction, and in the X-axis direction, adjacent sub-pixels are arranged in different colors.

2. The display panel of claim 1, wherein in the X-axis direction, the first sub-pixel groups of adjacent pixel units are staggered, and the second sub-pixel groups of adjacent pixel units are staggered; in the Y-axis direction, the first sub-pixel groups and the second sub-pixel groups of adjacent pixel units are spaced apart.

3. The display panel of claim 2, wherein, The positions of the sub-pixels in the first sub-pixel group are interchangeable, and the positions of the sub-pixels in the second sub-pixel group are interchangeable.

4. The display panel of claim 3, wherein, in the X-axis direction, the second pixel is adjacent to the third pixel, and the first pixel is adjacent to the fourth pixel.

5. The display panel of claim 1, wherein, The first pixel is a green pixel, the second pixel is a red pixel, the third pixel is a blue pixel, and the fourth pixel is a white pixel or a cyan pixel.

6. The display panel of claim 5, wherein, In the pixel unit, the first sub-pixel group is provided with a green pixel and a red pixel from top to bottom along the Y-axis, and the second sub-pixel group is provided with a blue pixel and a white pixel or a cyan pixel from top to bottom along the Y-axis; or in the pixel unit, the first sub-pixel group is provided with a red pixel and a green pixel from top to bottom along the Y-axis, and the second sub-pixel group is provided with a white pixel or a cyan pixel and a blue pixel from top to bottom along the Y-axis.

7. The display panel of claim 6, wherein, Four pixel units are arranged continuously in the X-axis direction: The first sub-pixel groups in the first pixel unit and the second pixel unit are both provided with a green pixel and a red pixel from top to bottom along the Y-axis, and the second sub-pixel groups are both provided with a blue pixel and a white pixel or a cyan pixel from top to bottom along the Y-axis; and The first sub-pixel groups in the third pixel unit and the fourth pixel unit are both provided with a red pixel and a green pixel from top to bottom along the Y-axis, and the second sub-pixel groups are both provided with a white pixel or a cyan pixel and a blue pixel from top to bottom along the Y-axis. Two pixel units are arranged adjacent in the Y-axis direction:

8. The display panel of claim 6, wherein, The arrangement of the first sub-pixel group of one pixel unit is different from that of the first sub-pixel group of the other pixel unit; The arrangement of the second sub-pixel group of one pixel unit is different from that of the second sub-pixel group of the other pixel unit. The array substrate comprises:

9. The display panel of claim 1, wherein, a plurality of scan lines extending in the X-axis direction, a plurality of data lines extending in the Y-axis direction, a plurality of the scan lines and a plurality of the data lines intersecting out of plane to define a plurality of sub-pixel openings, a plurality of the sub-pixels comprising the first pixel, the second pixel, the third pixel and the fourth pixel; ​ One of the scan lines connects one row of the sub-pixels; one of the data lines connects two columns of the sub-pixels, and the sub-pixels connected to the same data line are located in different rows. In the X-axis direction and the Y-axis direction, the polarities of adjacent sub-pixels are opposite and different in color.

10. The display panel of claim 9, wherein, In the X-axis direction and the Y-axis direction, the polarities of sub-pixels of the same color in two adjacent pixel units are opposite.

11. The display panel of claim 9, wherein, The array substrate further comprises pixel electrodes, which are located in the openings of the sub-pixels and are electrically connected to the scan lines and the data lines respectively through thin film transistors. The pixel electrodes are rectangular in outer contour, and the width of the pixel electrodes in the X-axis direction is greater than the length of the pixel electrodes in the Y-axis direction.

12. The display panel of claim 11, wherein, The ratio of the width W to the length L of the pixel electrodes is 3 / 2.

13. The display panel of claim 12, wherein, The pixel electrodes comprise main electrodes and sub-electrodes which are spaced apart along the Y-axis direction, and the main electrodes and the sub-electrodes are located on opposite sides of one of the scan lines respectively.

14. The display panel of claim 13, wherein, In the Y-axis direction, the distance between the main electrode of one of the pixel electrodes and the sub-electrode of an adjacent one of the pixel electrodes is less than the distance between the main electrode and the sub-electrode of the same pixel electrode.

15. The display panel of claim 13, wherein, First, second and third thin film transistors are arranged between the main electrode and the sub-electrode. The gates of the first, second and third thin film transistors are connected to the same scan line, the sources of the first and second thin film transistors are connected to the same data line, the source of the third thin film transistor is connected to the drain of the second thin film transistor, the drain of the first thin film transistor is connected to the main electrode, the drain of the second thin film transistor is connected to the sub-electrode, and the drain of the third thin film transistor is connected to a shared electrode.

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