Method, apparatus, and storage medium for lithographic signal simulation

Abstract

According to embodiments of the present disclosure, methods, devices and storage media for lithography signal simulation are provided. The method comprises determining a simulation light signal for a substrate having at least one protruding structure, the simulation light signal indicating a signal formed on the substrate after light passing through a mask; determining a topography signal for the substrate, the topography signal being associated with the at least one protruding structure; and determining a lithography signal for the substrate based on the simulation light signal and the topography signal. In this way, the effect of the at least one protruding structure and the stack of photoresist on the signal on the substrate can be taken into account, which helps to improve the accuracy of the lithography signal.

Description

Technical Field

[0001] The exemplary embodiments disclosed herein generally relate to the field of photolithography, and particularly to methods, electronic devices, and computer-readable storage media for simulating photolithographic signals. Background Technology

[0002] Photolithography is the process of transferring integrated circuit devices from a mask pattern to the surface of a substrate, and it is crucial for the mass production of advanced chips. As the size of high-end chips continues to shrink, the diffraction effect of the photolithography system becomes more pronounced, and various process deviations and system aberrations severely affect process accuracy. With the rapid development of computer technology, computer simulation modeling of photolithography signals (also known as photolithography simulation) technology helps improve the accuracy of photolithography. Summary of the Invention

[0003] In a first aspect of this disclosure, a method for simulating photolithography signals is provided. The method includes: determining a simulated optical signal for a substrate having at least one protruding structure, the simulated optical signal indicating a signal formed on the substrate after light passes through a mask; determining a topological signal for the substrate, the topological signal being associated with at least one protruding structure; and determining a photolithography signal for the substrate based on the simulated optical signal and the topological signal.

[0004] In a second aspect of this disclosure, an electronic device is provided. The electronic device includes: at least one processor; and at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions causing the electronic device to perform the method according to the first aspect of this disclosure when executed by the at least one processor.

[0005] In a third aspect of this disclosure, a computer-readable storage medium is provided that stores computer-executable instructions thereon, which, when executed by a processor, cause the processor to perform the method according to a first aspect of this disclosure.

[0006] As will be understood from the following description, according to embodiments of this disclosure, a simulated optical signal for a substrate having at least one protruding structure is first determined, the simulated optical signal indicating the signal formed on the substrate after light passes through a mask. Further, a topological signal for the substrate is determined, the topological signal indicating at least the influence of the stacking of at least one protruding structure and photoresist on the signal on the substrate. Finally, a photolithography signal for the substrate is determined based on the simulated optical signal and the topological signal. In this way, a topological signal for the substrate is introduced into the simulation of the photolithography signal, thereby taking into account the influence of the stacking of at least one protruding structure and photoresist on the signal on the substrate. This helps to improve the accuracy of the photolithography signal simulation.

[0007] It should be understood that the content described in this content section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0008] The above and other features, advantages, and aspects of various implementations of this disclosure will become more apparent in the following detailed description, taken in conjunction with the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0009] Figure 1A A schematic diagram of an example environment in which embodiments of the present disclosure can be implemented is shown;

[0010] Figure 1B An example of a non-planar surface coated with photoresist is shown;

[0011] Figure 1C An example of photoresist shrinkage in the overlapping region is shown;

[0012] Figure 2 A flowchart of a method for simulating lithographic signals according to some embodiments of the present disclosure is shown;

[0013] Figure 3A Examples of determining edge regions according to some embodiments of this disclosure are shown;

[0014] Figure 3B Examples of non-independent stacked structures according to some embodiments of the present disclosure are shown; and

[0015] Figure 4 A block diagram of an electronic device that can implement one or more embodiments of the present disclosure is shown. Detailed Implementation

[0016] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0017] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below. In this document, unless explicitly stated otherwise, performing a step in response to A does not mean that the step is performed immediately after "A", but may include one or more intermediate steps.

[0018] The following will describe in detail various example implementations of this scheme with reference to the accompanying drawings.

[0019] First see Figure 1A , Figure 1A A schematic diagram of an example environment 100A in which embodiments of the present disclosure can be implemented is shown. For example... Figure 1A As shown, the example environment 100A may generally include electronic device 110.

[0020] In some embodiments, the electronic device 110 can interact with other devices (not shown) or users. For example, the electronic device 110 can receive input information from other devices or users and provide output information to other devices or users in response to the input information. In some embodiments, the input message may include relevant information 120 about the substrate, and the electronic device 110 can determine the photolithography signal 130 of the substrate based on the relevant information 120. The electronic device 110 can then provide the photolithography signal 130 of the substrate to other devices or users.

[0021] In example environment 100A, electronic device 110 can be any type of computing-capable device, including terminal devices and server devices. Terminal devices can be any type of mobile terminal, fixed terminal, or portable terminal, including mobile phones, desktop computers, laptop computers, notebook computers, netbook computers, tablet computers, media computers, multimedia tablets, personal communication system (PCS) devices, personal navigation devices, personal digital assistants (PDAs), audio / video players, digital cameras / camcorders, positioning devices, television receivers, radio receivers, e-book devices, gaming devices, or any combination thereof, including accessories and peripherals of these devices or any combination thereof. In some embodiments, client devices can also support any type of user-facing interface (such as "wearable" circuitry).

[0022] Server-side equipment can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks, and big data and artificial intelligence platforms. Server-side equipment may include, for example, computing systems / servers, such as mainframes, edge computing nodes, computing devices in cloud environments, and so on.

[0023] It should be understood that the structure and function of the various elements in environment 100A are described for illustrative purposes only and do not imply any limitation on the scope of this disclosure. Some exemplary embodiments of this disclosure will continue to be described below with reference to the accompanying drawings.

[0024] In the manufacturing process of flat panel display backplanes, the lack of chemical mechanical planarization (CMP) technology in integrated circuits leads to complex three-dimensional topographic structures due to the stacking of film layers. This topography causes two core problems. One problem is the photoresist thickness gradient, where the uneven surface of the substrate causes thickness differences in photoresist coating (local ΔT > 100 nm). The other problem is optical distortion in the cross-line region, where the stepped structure causes incident light scattering and reflection angle shift (Δθ > 15°) during exposure. These coupling effects ultimately lead to a systematic shrinkage of the critical dimension (CD) at the cross-line location (typically 0.3–0.5 μm), and a deterioration in CD uniformity in adjacent areas (>10%), becoming a bottleneck for micron-level linewidth control in high-generation panels.

[0025] The process by which the three-dimensional morphology causes cross-line CD shrinkage is as follows.

[0026] In the bottom pattern etching step, the first pattern layer 1 is etched to form a substrate morphology with a step height difference (ΔH).

[0027] In the dielectric layer deposition step, an inorganic dielectric layer is covered on the etched surface by chemical vapor deposition (CVD) or physical vapor deposition (PVD) to inherit the three-dimensional contour of the underlying layer.

[0028] In the photoresist coating distortion step, photoresist is coated on a non-planar surface. Due to the morphology, a local thickness gradient is caused, and the thickness of the photoresist in the overlapping area is significantly reduced.

[0029] In the abnormal exposure and development process, the step structure during exposure causes light scattering and standing wave effects, resulting in insufficient effective dose in the overlapping areas and shrinkage of the pattern after development.

[0030] In the etching process, the shrinkage of the developed pattern is transferred to the metal traces via the etching process, ultimately causing a systematic deviation in the critical dimension (CD) of the interconnect.

[0031] refer to Figure 1B and Figure 1C , Figure 1B Example 100B shows a non-planar surface coated with photoresist. Figure 1C Example 100C shows the shrinkage of photoresist in the overlapping region. (e.g.) Figure 1B As shown, structure 101 is a protruding structure on a substrate. Coating 102, coating 103, and photoresist layer 104 are sequentially coated on structure 101. Coating 102 and coating 103, for example, correspond to a CVD layer and a PVD layer, respectively. Figure 1B As shown, after the photoresist is coated, due to the height difference between structure 101 and the substrate plane, the photoresist layer 104 is thinner at the top of structure 101 and thicker at the top of the substrate plane. After etching, this photoresist will exhibit the shrinkage phenomenon shown in Figure 1C. Assuming that after etching, the horizontal cross-section of structure 101 and the remaining photoresist 105 (assuming that the other parts of the photoresist shown in photoresist layer 104 are reacted) is as follows... Figure 1C As shown, photoresist coated on protruding structures of the substrate undergoes a shrinkage reaction compared to photoresist coated on areas without protruding structures. This affects the accuracy of photolithography.

[0032] Existing lithography signal simulation techniques typically directly incorporate computational lithography models from the chip industry. Such models lack the ability to handle protrusions and photoresist stacking. While these models can consider substrate morphology, they are usually based on an n / k optical dominance mechanism after planarization, which contradicts the physical mechanisms of substrates with protrusions. This affects the accuracy of the lithography signals obtained from simulation techniques. Some solutions rely on experienced professionals to manually intervene during the lithography simulation process. However, this requires a high level of expertise from the user, and in scenarios with complex protrusion morphologies on the substrate, manual intervention has a high error rate and poor efficiency, making it difficult to meet the processing needs of complex substrates.

[0033] In view of this, the present disclosure proposes an improved scheme for simulating photolithography signals. According to an embodiment of the present disclosure, a simulated optical signal is determined for a substrate having at least one protruding structure, the simulated optical signal indicating the signal formed on the substrate after light passes through a mask. A topological signal is determined for the substrate, the topological signal indicating at least the effect of the stacking of at least one protruding structure and photoresist on the signal on the substrate. Based on the simulated optical signal and the topological signal, a photolithography signal for the substrate is determined.

[0034] In this way, a substrate-specific topological signal is introduced into the simulation of lithography signals, thus taking into account the influence of at least one protruding structure and photoresist stacking on the signal on the substrate. This helps to improve the accuracy of lithography signal simulation.

[0035] Figure 2 A flowchart of a method 200 for lithographic signal simulation according to some embodiments of the present disclosure is shown. Method 200 can be implemented at an electronic device 110. It should be noted that the operations performed by the electronic device 110 may specifically be performed by a relevant application installed on the electronic device 110. The electronic device 110 can be used for interaction by receiving operations from relevant users.

[0036] In block 210, electronic device 110 determines an analog optical signal for a substrate having at least one protruding structure, the analog optical signal indicating the signal formed on the substrate after light passes through a mask. It is understood that the analog optical signal here does not take into account the influence of the structure of the film layers on the substrate on the optical signal. In the following text, "signal_optical" will be used to refer to the analog optical signal. The protruding structure can be any "physical bump" on the substrate surface that protrudes above the surrounding plane and is sufficient to affect subsequent photolithography / etching / deposition processes. Protruding structures can include, but are not limited to, front-end process (FEOL) legacies, back-end process (BEOL) / advanced packaging, power devices, etc.

[0037] The electronic device 110 can determine the analog optical signal in any suitable manner. For example, the electronic device 110 can predict the analog optical signal for the substrate using a machine learning model. Alternatively, the electronic device 110 can determine the analog optical signal for the substrate based on the analog optical signal of a reference substrate similar to the substrate. This disclosure does not limit the specific method of determining the analog optical signal.

[0038] In block 220, electronic device 110 determines a topology signal for the substrate, the topology signal being associated with at least one protruding structure. Hereinafter, the term "signal" will be used. topo To represent topological signals.

[0039] In some embodiments, the topology signal indicates at least the effect of at least one protrusion stacked with photoresist on a signal on the substrate. In some embodiments, the electronic device 110 may determine the topology signal based on at least one stacked structure formed by at least one protrusion and photoresist. The number of at least one protrusion and the number of at least one stacked structure may be the same or different, and each stacked structure may be formed by one or more protrusions and photoresist.

[0040] In some embodiments, a reference light intensity library can be pre-constructed, and the topology signal can be determined based on the reference light intensity library. In some embodiments, the topology signal can be determined based on information such as the protruding structure of the substrate itself and the photoresist distribution. These embodiments will be described in detail below.

[0041] In block 230, electronic device 110 determines a photolithography signal for the substrate based on an analog optical signal and a topological signal. This disclosure does not limit the specific method of determining the photolithography signal; as an example only, electronic device 110 may determine the photolithography signal based on the following formula:

[0042]

[0043] Where signal optical The analog optical signal is represented by "Signal", and the lithography signal is represented by "Signal". According to formula (1), the electronic device 110 can determine the lithography signal for the substrate by accumulating the analog optical signal and the topology signal.

[0044] As briefly mentioned above, in some embodiments, a reference intensity library can be used to determine the topological signal. An example embodiment of this is described below.

[0045] In some embodiments, the electronic device 110 can acquire a reference light intensity library and determine the topological signal for the substrate using the reference light intensity library. This reference light intensity library may include multiple light intensity distributions corresponding to multiple reference stack structures, each reference stack structure having corresponding reference structure parameters. It should be noted that the reference light intensity library acquired by the electronic device 110 may be pre-created by the electronic device 110, or it may be created by another electronic device 110 and then acquired by the electronic device 110. This disclosure does not limit this; the example described herein is only exemplified by the reference light intensity library being created by the electronic device 110.

[0046] The multiple reference stack structures can be user-specified reference stack structures or multiple reference stack structures determined by the electronic device 110 based on multiple reference structure parameters. The structural parameters can include any suitable parameters; for example only, they may include, but are not limited to, substrate thickness, photoresist thickness, width of the pattern on the substrate, spacing between adjacent patterns, overlap angle between patterns, number of overlap layers between patterns, and the overlap ratio of one pattern with other patterns, etc. Here, each pattern is associated with at least one protruding structure, and each pattern can be obtained by projecting the protruding structure onto the substrate; for example only, each protruding structure can correspond to one pattern.

[0047] For illustrative purposes only, refer to Table 1, which shows examples of determining several reference structure parameters:

[0048] Table 1

[0049]

[0050] As shown in Table 1, the electronic device 110 can arrange and combine multiple structural parameters according to the value range and step size corresponding to each structural parameter to obtain multiple reference structural parameters, and then obtain multiple reference stacked structures based on the multiple reference structural parameters. For a given reference stacked structure among the multiple reference stacked structures, the electronic device 110 can determine the optical field distortion distribution caused by the given reference stacked structure through electromagnetic simulation, and can determine the light intensity distribution corresponding to the given reference stacked structure based at least on the optical field distortion distribution.

[0051] Electromagnetic simulations can include, for example, rigorous electromagnetic simulation algorithms, such as 3D RCWA (rigid coupled-wave analysis), FDTD (finite-difference time-domain) algorithms, etc. The optical field distortion distribution can indicate the height difference (ΔH) between the top of the photoresist and the bottom of the substrate in a given reference stack structure, and the photoresist thickness gradient. T / x) or incident light offset angle (Δθ). The photoresist thickness gradient can indicate the rate of change of photoresist thickness along the substrate lateral direction in a given reference stack structure, and the incident light offset angle can indicate the angular difference between the incident overlapping region and the incident non-overlapping region. The overlapping region has the overlap of protruding structure and photoresist, while the non-overlapping region does not have the overlap of protruding structure and photoresist.

[0052] Thus, the electronic device 110 can obtain a light intensity matching the substrate from a reference light intensity library based on the stacking of at least one protruding structure and photoresist on the substrate, and determine the topological signal for the substrate based on the obtained light intensity.

[0053] In other embodiments, the electronic device 110 can determine the edge region of at least one stacked structure formed by the protruding structure and the photoresist. By way of example, if the protruding structure and the photoresist are simply considered as two rectangles, the stacked structure can be considered as the overlapping area of ​​these two rectangles. The stacked structure can also be simply considered as a square. In this case, the edges of the stacked structure are the four sides of the square. Two of these four sides are part of the sides of the rectangle corresponding to the photoresist, and the other two sides are part of the sides of the rectangle corresponding to the protruding structure. The two sides corresponding to the photoresist can be considered as the edge region of the stacked structure. The electronic device 110 can determine a topological signal for the substrate based on the edge region of the stacked structure and a reference light intensity distribution. The reference light intensity distribution can be any suitable signal; by way of example, it can be a Gaussian signal.

[0054] The above describes an example process for constructing a reference light intensity library. For the substrate to be simulated or processed, the reference light intensity library can be used to determine the topological signal.

[0055] In some embodiments, the electronic device 110 can determine structural parameters of at least one protruding structure and a target stacked structure formed by photoresist at the target location on a substrate. The target location can be a location determined based on user input. For example, the electronic device 110 can determine the corresponding substrate location based on coordinates received from user input. Of course, the target location can also be any other suitable location and can be determined in any suitable manner. For example, the target location can be a location determined from the substrate based on predetermined rules.

[0056] Electronic device 110 can obtain at least one light intensity distribution matching the target stacked structure from a reference light intensity library based on the structural parameters of the target stacked structure. In some embodiments, electronic device 110 can determine the similarity between the structural parameters of multiple reference stacked structures and the structural parameters of the target stacked structure. Electronic device 110 can determine the similarity in any suitable manner; for example, electronic device 110 can determine the similarity based on predetermined rules or algorithms, or, for example, electronic device 110 can determine the similarity using a machine learning model. The similarity can, for example, be normalized to a value between 0 and 1. As an example only, electronic device 110 can determine the similarity based on a multidimensional linear interpolation algorithm (the more parameters, the higher the required dimension) or other interpolation algorithms.

[0057] Electronic device 110 can determine at least one reference stacking structure that matches the target stacking structure from multiple reference stacking structures based on the similarity of each of the reference stacking structures. In some embodiments, electronic device 110 can sort the multiple reference stacking structures in descending order based on their respective similarity, with the reference stacking structure appearing earlier in the sorting result having a higher similarity. Electronic device 110 can determine the N reference stacking structures (N can be any suitable positive integer, which can be determined based on the actual scenario, user configuration, etc.) that are in the top N of the sorting result as at least one reference stacking structure that matches the target stacking structure. In some embodiments, electronic device 110 can also obtain a threshold similarity, and electronic device 110 can determine that the reference stacking structure matches the target stacking structure when the similarity of a certain reference stacking structure reaches the threshold similarity.

[0058] In some embodiments, the electronic device 110 may also acquire a limitation on the number of at least one reference stack structure. This limitation may be determined based on the actual scenario or user configuration, etc. As an example only, the limitation may indicate that the number of at least one reference stack structure is 2. nThat is, the number of at least one reference stack structure is 2 to the power of n. The electronic device 110 can then determine at least one reference stack structure from a plurality of reference stack structures based on this limitation. As an example only, the electronic device 110 can determine a set of reference stack structures from a plurality of reference stack structures whose corresponding similarity reaches a threshold similarity based on a threshold similarity, and the electronic device 110 can then determine, based on the number of reference stack structures in a set, a set of reference stack structures that can satisfy the condition of having at least 2 to the power of n. n At least one reference stack structure, the number of which can be, for example, a set of reference stack structures satisfying 2 n The maximum number.

[0059] Electronic device 110 can then determine at least one light intensity distribution corresponding to at least one reference stack structure from a reference light intensity library. Specifically, electronic device 110 can query the reference light intensity library based on at least one reference stack structure to obtain the corresponding at least one light intensity distribution. Electronic device 110 can then determine the topology signal component for the target location based on the at least one light intensity distribution. Electronic device 110 can determine the topology signal component, for example, based on the following formula:

[0060]

[0061] It is assumed that at least one light intensity distribution comprises k light intensity distributions, signal i For at least one light intensity distribution, the weight is the i-th light intensity distribution. i The weighting coefficients corresponding to the i-th light intensity distribution are signal. topo This refers to the topology signal components for the target location.

[0062] Electronic device 110 can determine a topology signal for a substrate based at least on the topology signal components. For example, electronic device 110 can acquire multiple topology signal components corresponding to multiple locations on the substrate, and determine the topology signal for the substrate based on the multiple topology signal components. By way of example only, electronic device 110 can determine the topology signal for the substrate by accumulating multiple topology signal components.

[0063] The above describes the method of determining the topology signal using a reference light intensity library. The following, with reference to the accompanying figures, describes a method for determining the topology signal based on the substrate's own protruding structures, photoresist, and reference light intensity distribution.

[0064] In some embodiments, the electronic device 110 may define at least one stacked structure formed by at least one protruding structure and photoresist. As mentioned above, each stacked structure may be formed by one or more protruding structures and photoresist. In some embodiments, the at least one stacked structure may include independent stacked structures and / or non-independent stacked structures, wherein an independent stacked structure is formed by a single protruding structure and photoresist, and a non-independent stacked structure is formed by multiple protruding structures and photoresist having overlapping portions on the substrate.

[0065] Electronic device 110 can determine at least one edge region corresponding to at least one stacked structure. Specifically, for each of the at least one stacked structure, electronic device 110 can determine the extension range on the substrate of one or more protrusions associated with the stacked structure, and determine the projection range of the photoresist on the substrate. The projection range indicates the range of the photoresist retained on the substrate after light passes through the mask and undergoes a photochemical reaction with the photoresist. Electronic device 110 can also obtain a preset width for the edge region of the stacked structure, and determine the projection edge region of the projection range based on the preset width. This preset width can be any suitable width, which can be determined according to the actual scenario, user configuration, etc., and is not limited thereto in this disclosure.

[0066] Electronic device 110 can, for example, use matrices to represent the extension range, projection range, and projection edge region. (See reference) Figure 3A , Figure 3A Example 300A of defining edge regions according to some embodiments of the present disclosure is shown. Electronic device 110 can determine the extent of extension of protruding structure 311 on the substrate as shown in the matrix in box 310, where 0 represents the area outside the extension, 0.5 represents the edge of the extension, and 1 represents the interior of the extension. Electronic device 110 can determine the projection range of photoresist 312 on the substrate as shown in the matrix in box 320, where 0 represents the area outside the projection range, 0.5 represents the edge of the projection range, and 1 represents the interior of the projection range.

[0067] Electronic device 110 can determine the projected edge region as shown in the matrix in box 330 from the projection range (matrix in box 320) based on a preset width for the edge region of the stacked structure, where 0 represents the area outside the projected edge region, and 0.5 and 1 represent the range of the projected edge region on the substrate. Specifically, assuming the preset width is n, for each element in the matrix in box 320, electronic device 110 can determine whether there is a neighboring element with a value of 0 in the adjacent n*n region of that element. Electronic device 110 can retain the current element in response to determining its existence, and set the value of the current element to 0 in response to determining its non-existence. For example, assuming n is 2, for the third element "1" in the first row of the matrix in box 320, there is a neighboring element with a value of 0 in the 2*2 region to the left of this element, so the element "1" is retained unchanged. For the fourth element "1" in the first row of the matrix in box 320, there is no neighboring element with a value of 0 in the 2*2 region to the left of this element, so the value of this element is set to 0. Thus, electronic device 110 can obtain the matrix in box 330.

[0068] The electronic device 110 can then determine the edge region corresponding to the stacked structure based on the extension range, projection range, and projection edge region of each of the one or more protruding structures on the substrate. It should be noted that the electronic device 110 may use different methods to determine the edge region for independent stacked structures and non-independent stacked structures. In some embodiments, for independent stacked structures, since they are associated with only a single protruding structure, the electronic device 110 can directly determine the edge region corresponding to the independent stacked structure based on the extension range, projection range, and projection edge region of the single protruding structure on the substrate.

[0069] Specifically, the electronic device 110 can determine the stacking area of ​​the independent stacked structure on the substrate based on the extension range and projection range of a single protruding structure on the substrate, and further determine the edge region corresponding to the stacked structure based on the stacking area and the projection edge region. (Continue to refer to...) Figure 3A Electronic device 110 can, for example, determine the matrix in box 340 based on the matrices in box 310 and box 320, the matrix in box 340 showing an example of a stacked region 313. In the matrix in box 340, 0 represents the area outside the stacked region 313, 0.25 represents the four vertices of the stacked region 313, 0.5 represents the edge of the stacked region 313, and 1 represents the interior of the stacked region 313. Electronic device 110 can further determine the matrix in box 350 based on the matrices in box 330 and box 340, the matrix in box 350 showing an example of the edge region corresponding to the stacked structure (the two bold edges of the stacked region 313 in the figure).

[0070] In some embodiments, for a non-independent stacked structure, since it is associated with multiple protrusions, the electronic device 110 can determine the edge region component corresponding to each of the multiple protrusions based on the extension range, projection range, and projection edge region of the protrusion on the substrate. The method by which the electronic device 110 determines the edge region component corresponding to each of the multiple protrusions can be the same as the method described above for determining the edge region corresponding to an independent stacked structure, and will not be repeated here. The electronic device 110 can determine multiple edge region components corresponding to each of the multiple protrusions, and determine the edge region corresponding to the non-independent stacked structure by weighting the multiple edge region components. For example, the electronic device 110 can determine the edge region based on the following formula:

[0071]

[0072] It is assumed that there are a total of k protruding structures, and EI represents the extension range. i MI represents the extension range of the i-th protrusion on the substrate among multiple protrusions, MI_e represents the projection range of the photoresist on the substrate, and weight represents the projection edge region. i EI represents the weight coefficient corresponding to the i-th prominent structure. i ⊙MI⊙MI_e can represent the edge region component corresponding to the i-th convex structure.

[0073] Mo_e represents the edge region corresponding to a non-independent stacked structure. It should be noted that in some embodiments, EI... i By EI i-1 Obtained recursively.

[0074] refer to Figure 3B , Figure 3B Example 300B of a non-independent stacked structure according to some embodiments of the present disclosure is shown. In example 300B, the non-independent stacked structure is formed by protruding structures 372 and 374 and photoresist 371, wherein protruding structures 372 and 374 have overlapping portions 373. The edge regions of the non-independent stacked structure shown in example 300B can be obtained by weighted summation of the edge region components corresponding to protruding structures 372 and 374.

[0075] After determining at least one edge region corresponding to at least one stacked structure, the electronic device 110 can determine a topology signal based on the at least one edge region and a reference light intensity distribution. In some embodiments, for each edge region among the at least one edge region, the electronic device 110 can perform a convolution operation on the weighted edge region and the reference light intensity distribution to determine a convolution signal. The electronic device 110 can then process the convolution signal using compensation coefficients to determine the topology signal component for that edge region. For example, the electronic device 110 can determine the topology signal component for a certain edge region based on the following formula:

[0076]

[0077] Among them Mo e This represents the edge region corresponding to the stacked structure, weight represents the weight coefficient corresponding to the edge region, G(x) represents the reference light intensity distribution, convolve() represents performing convolution on the elements within the parentheses, coeff is the compensation coefficient, and signal topo For the topological signal components of this edge region. In some embodiments, the weight in formula (4) can be a linear weight proportional to the thickness of the PVD film, and the coeff can be inversely proportional to the time of the analog optical signal.

[0078] Electronic device 110 can determine at least one topology signal component corresponding to at least one edge region, and determine a topology signal based on at least one topology signal component. For example, electronic device 110 can determine a topology signal for a substrate by accumulating at least one topology signal component.

[0079] In some embodiments, to improve the accuracy of the determined topology signal, the electronic device 110 may also acquire verification information associated with the photolithography of the substrate. The verification information may include photolithography machine information, substrate layout information, substrate stack-up information, actual substrate measurement data, etc. The electronic device 110 may update the weighting coefficients, reference light intensity distribution, convolution operation, and / or compensation coefficients used to determine the weighted edge region based on the verification information. Thus, by updating the above parameters, the accuracy of the parameters can be improved, which can help improve the accuracy of the topology signal components determined based on the above parameters, thereby improving the accuracy of the topology signal.

[0080] In summary, the topological signal for the substrate can be determined, and the lithography signal can be determined by combining the analog optical signal and the topological signal. The influence of at least one protruding structure stacked with photoresist on the signal on the substrate can be taken into account, which helps ensure the accuracy of the lithography signal.

[0081] It should be understood that one or more steps in the above methods can be performed by suitable electronic devices or combinations of electronic devices. Such electronic devices or combinations of electronic devices can, for example, be used to implement... Figure 1A Electronic device 110.

[0082] Figure 4 A block diagram of an electronic device 400 in which one or more embodiments of the present disclosure may be implemented is shown. It should be understood that... Figure 4 The electronic device 400 shown is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein. Figure 4 The electronic device 400 shown can be used to achieve Figure 1A Electronic devices 110.

[0083] like Figure 4 As shown, electronic device 400 is in the form of a general-purpose electronic device. Components of electronic device 400 may include, but are not limited to, one or more processors 410 or processing units, memory 420, storage device 430, one or more communication units 440, one or more input devices 450, and one or more output devices 460. Processor 410 may be a physical or virtual processor and is capable of performing various processes according to programs stored in memory 420. In a multiprocessor system, multiple processors execute computer-executable instructions in parallel to improve the parallel processing capability of electronic device 400.

[0084] Electronic device 400 typically includes multiple computer storage media. Such media can be any available media accessible to electronic device 400, including but not limited to volatile and non-volatile media, removable and non-removable media. Memory 420 can be volatile memory (e.g., registers, cache, random access memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 430 can be removable or non-removable media and can include machine-readable media, such as flash drives, disks, or any other media capable of storing information and / or data and accessible within electronic device 400.

[0085] Electronic device 400 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not explicitly stated... Figure 4As shown, disk drives for reading from or writing to removable, non-volatile disks (e.g., "floppy disks") and optical disk drives for reading from or writing to removable, non-volatile optical disks can be provided. In these cases, each drive can be connected to a bus (not shown) via one or more data media interfaces. Memory 420 may include computer program product 425 having one or more program modules configured to perform various methods or actions of various embodiments of this disclosure.

[0086] The communication unit 440 enables communication with other electronic devices via a communication medium. Additionally, the functionality of the components of the electronic device 400 can be implemented using a single computing cluster or multiple computing machines capable of communicating via communication connections. Therefore, the electronic device 400 can operate in a networked environment using logical connections to one or more other servers, networked personal computers (PCs), or another network node.

[0087] Input device 450 can be one or more input devices, such as a mouse, keyboard, trackball, etc. Output device 460 can be one or more output devices, such as a monitor, speaker, printer, etc. Electronic device 400 can also communicate with one or more external devices (not shown) via communication unit 440 as needed. These external devices include storage devices, display devices, etc., and can communicate with one or more devices that enable user interaction with electronic device 400, or with any device that enables electronic device 400 to communicate with one or more other electronic devices (e.g., network card, modem, etc.). Such communication can be performed via input / output (I / O) interface (not shown).

[0088] According to an exemplary implementation of this disclosure, a computer-readable storage medium is provided that stores computer-executable instructions thereon, wherein the computer-executable instructions are executed by a processor to implement the methods described above. According to an exemplary implementation of this disclosure, a computer program product is also provided, which is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions, which are executed by a processor to implement the methods described above.

[0089] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatuses, devices, and computer program products implemented according to this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0090] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0091] Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0092] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0093] Various implementations of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is chosen to best explain the principles, practical applications, or improvements to technology in the market, or to enable others skilled in the art to understand the various implementations disclosed herein.

Claims

1. A method for simulating photolithographic signals, characterized in that, include: Determine a simulated optical signal for a substrate having at least one protruding structure, the simulated optical signal indicating the signal formed on the substrate after light passes through a mask; A topology signal is determined for the substrate, the topology signal being associated with the at least one protrusion, the topology signal indicating at least the effect of the at least one protrusion and the photoresist stack on the signal formed on the substrate; as well as Based on the analog optical signal and the topological signal, the photolithography signal for the substrate is determined.

2. The photolithography signal simulation method according to claim 1, characterized in that, Determining the topology signal for the substrate includes: For a target location on the substrate, determine the structural parameters of the at least one protruding structure and the target stacked structure formed by the photoresist at the target location; Based on the structural parameters of the target stacked structure, at least one light intensity distribution matching the target stacked structure is obtained from the reference light intensity library. The reference light intensity library includes multiple light intensity distributions corresponding to multiple reference stacked structures, and each reference stacked structure has corresponding reference structural parameters. Based on the at least one light intensity distribution, determine the topological signal component for the target location; and The topology signal for the substrate is determined based at least on the topology signal components.

3. The photolithography signal simulation method according to claim 2, characterized in that, Obtaining at least one light intensity distribution matching the target stacked structure from a reference light intensity library includes: Determine the similarity between each of the reference structural parameters corresponding to the plurality of reference stacked structures and the structural parameters of the target stacked structure; Based on the similarity of each of the plurality of reference stacking structures, at least one reference stacking structure that matches the target stacking structure is determined from the plurality of reference stacking structures; and Determine the at least one light intensity distribution corresponding to the at least one reference stack structure from the reference light intensity library.

4. The photolithography signal simulation method according to claim 2, characterized in that, The reference light intensity library is constructed in the following manner: For a given reference stacking structure among the plurality of reference stacking structures, Electromagnetic simulation was used to determine the optical field distortion distribution caused by the given reference stacking structure; as well as Based at least on the optical field distortion distribution, the light intensity distribution corresponding to the given reference stack structure is determined.

5. The photolithography signal simulation method according to claim 4, characterized in that, The optical field distortion distribution indicates the following: The height difference between the top of the photoresist and the bottom of the substrate in the given reference stack structure Photoresist thickness gradient, indicating the rate of change of photoresist thickness along the lateral side of the substrate in the given reference stack structure, or Incident light offset angle indicates the angular difference between the incident overlapping area and the incident non-overlapping area. The overlapping area has an overlap of protruding structure and photoresist, while the non-overlapping area does not have an overlap of protruding structure and photoresist.

6. The photolithography signal simulation method according to claim 1, characterized in that, Determining the topology signal includes: Determine at least one stacked structure formed by the at least one protruding structure and the photoresist; Determine at least one edge region corresponding to each of the at least one stacked structure; and The topological signal is determined based on the at least one edge region and the reference light intensity distribution.

7. The photolithography signal simulation method according to claim 6, characterized in that, At least one stacked structure includes at least one of the following: Independently stacked structures, wherein the independently stacked structures are formed by a single protruding structure and the photoresist, or A non-independent stacked structure, which is formed by a plurality of protruding structures having overlapping portions on the substrate and the photoresist.

8. The photolithography signal simulation method according to claim 6, characterized in that, Determining at least one edge region corresponding to each of the at least one stacked structures includes: for each of the at least one stacked structures, Determine the extent of extension of each of the at least one protruding structure associated with the stacked structure on the substrate; Determine the projection range of the photoresist on the substrate, wherein the projection range indicates the area on the substrate where the photoresist remains after light passes through the mask and undergoes a photochemical reaction with the photoresist; Based on a preset width for the edge region of the stacked structure, the projection edge region of the projection range is determined from the projection range; and Based on the extension range of each of the one or more protruding structures on the substrate, the projection range, and the projection edge region, the edge region corresponding to the stacked structure is determined.

9. The photolithography signal simulation method according to claim 8, characterized in that, Determining the edge region corresponding to this stacked structure includes: In response to determining that the stacked structure is formed by a single protrusion and the photoresist, the stacking region of the stacked structure on the substrate is determined based on the extension range of the single protrusion on the substrate and the projection range; and Based on the stacked region and the projected edge region, the edge region corresponding to the stacked structure is determined.

10. The photolithography signal simulation method according to claim 8, characterized in that, Determining the edge region corresponding to this stacked structure includes: In response to determining that the stacked structure is formed by a plurality of protruding structures with overlapping portions and the photoresist, for each of the plurality of protruding structures, an edge region component corresponding to that protruding structure is determined based on the extension range of the protruding structure on the substrate, the projection range, and the projection edge region, to obtain a plurality of edge region components corresponding to each of the plurality of protruding structures; and By weighting the multiple edge region components, the edge region corresponding to the stacked structure is determined.

11. The photolithography signal simulation method according to claim 6, characterized in that, Determining the topology signal includes: For each edge region in the at least one edge region, A convolution operation is performed on the weighted edge region and the reference light intensity distribution to determine the convolution signal; The convolutional signal is processed using compensation coefficients to determine the topological signal components for the edge region; and The topology signal is determined based at least on the topology signal components determined for each of the at least one edge region.

12. The photolithography signal simulation method according to claim 11, characterized in that, The method further includes: Obtain verification information associated with the photolithography of the substrate; and Based on the verification information, update at least one of the following: the weight coefficients for determining the weighted edge region, the reference light intensity distribution, the convolution operation, and the compensation coefficient.

13. An electronic device, characterized in that, include: At least one processor; as well as At least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions causing the electronic device to perform the method according to any one of claims 1 to 12 when executed by the at least one processor.

14. A computer-readable storage medium, characterized in that, It stores computer-executable instructions that can be executed by a processor to implement the method according to any one of claims 1 to 12.

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