A method, apparatus and device for detecting synchronization functions of a multi-thread processor

Abstract

This application relates to the field of computer technology, and in particular to a method, apparatus, and device for detecting the synchronization function of a multi-threaded processor. When it is determined that the multi-threaded processor to be detected exhibits a target behavior of processing a synchronization instruction, the target thread corresponding to the synchronization instruction is identified, and the target synchronization status identifier corresponding to the target behavior is obtained. In the instruction status queue corresponding to the target thread, the first target instruction information with the target synchronization status identifier is searched. Then, based on whether the target address corresponding to the currently detected target behavior matches the standard synchronization address recorded in the target instruction information, it is determined whether there is an anomaly in the synchronization function of the multi-threaded processor to be detected. Based on the instruction status queue added for each thread, real-time verification of whether the target address corresponding to the target behavior matches the standard synchronization address in the instruction status queue is achieved, realizing real-time detection of the synchronization function of the multi-threaded processor.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus and device for detecting the synchronization function of a multi-threaded processor. Background Technology

[0002] In multithreaded processors, a task is typically executed through coordination and synchronization among multiple threads.

[0003] To test the synchronization function of a multi-threaded processor, related technologies typically perform synchronization function testing after instruction execution is complete or during batch result comparison, which is considered "post-verification." This testing method has a coarse-grained detection range and cannot reflect internal state changes in real time. It is a black-box model, only able to reflect the internal state of the multi-threaded processor through output results, making it difficult to debug.

[0004] Therefore, how to detect the synchronization function of multi-threaded processors in a timely manner has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a method, apparatus, and device for detecting the synchronization function of multi-threaded processors, in order to solve the problem of untimely detection of the synchronization function of multi-threaded processors in the prior art.

[0006] This application provides a method for detecting the synchronization function of a multi-threaded processor, the method comprising:

[0007] If a target behavior of processing a synchronization instruction is detected in the multi-threaded processor to be detected, the target thread corresponding to the synchronization instruction is determined, and the target synchronization status identifier pre-configured for the target behavior is obtained.

[0008] In the instruction status queue corresponding to the target thread, find the first target instruction information whose synchronization status identifier is the target synchronization status identifier, wherein the target instruction information is recorded in the instruction status queue when the target thread receives an instruction;

[0009] Based on whether the target address corresponding to the currently detected target behavior matches the standard synchronization address recorded in the target instruction information, it is determined whether there is an anomaly in the synchronization function of the multi-threaded processor to be detected.

[0010] Furthermore, if the detected multi-threaded processor exhibits target behavior of processing synchronization instructions, determining the target thread corresponding to the synchronization instructions includes:

[0011] If a synchronization request is detected at the first preset interface, the thread that sent the synchronization request is identified as the target thread.

[0012] Furthermore, if the detected multi-threaded processor exhibits target behavior of processing synchronization instructions, determining the target thread corresponding to the synchronization instructions includes:

[0013] If a response to a synchronization request is detected at the second preset interface, the thread responding to the response is identified as the target thread.

[0014] Furthermore, if the detected multi-threaded processor exhibits target behavior of processing synchronization instructions, determining the target thread corresponding to the synchronization instructions includes:

[0015] If it is detected that the multi-threaded processor to be detected is executing a synchronization instruction, the thread executing the synchronization instruction will be identified as the target thread.

[0016] Further, obtaining the target synchronization state identifier pre-configured for the target behavior includes:

[0017] If the target behavior is the sending of a synchronization request, then the target synchronization status identifier is determined to be a waiting identifier;

[0018] If the target behavior is a response to a synchronization request, then the target synchronization status identifier is determined to be an in-transit identifier;

[0019] If the target behavior is to execute a synchronization instruction, then the target synchronization status identifier is determined to be a ready identifier.

[0020] Furthermore, the next state identifier of the waiting identifier is the in-transit identifier, and the next state identifier of the in-transit identifier is the ready identifier.

[0021] Furthermore, the process of determining the instruction status queue corresponding to any thread includes:

[0022] If an instruction input is detected at the third preset interface, the information of the instruction is stored in the corresponding target instruction status queue according to the thread information included in the input instruction. The information of the instruction includes: synchronization enable flag, standard synchronization address, and synchronization status flag, wherein the synchronization enable flag is used to describe whether the corresponding instruction is a synchronization instruction.

[0023] Furthermore, the method also includes:

[0024] Update the synchronization status identifier in the target instruction information to the next status identifier of the target synchronization status identifier.

[0025] This application embodiment also provides a multi-threaded processor synchronization function detection device, the device comprising:

[0026] The determination module is used to determine the target thread corresponding to the synchronization instruction if a target behavior of processing a synchronization instruction is detected in the multi-threaded processor to be detected, and to obtain a target synchronization status identifier pre-configured for the target behavior.

[0027] The lookup module is used to find the first target instruction information whose synchronization status identifier is the target synchronization status identifier in the instruction status queue corresponding to the target thread, wherein the target instruction information is recorded in the instruction status queue when the target thread receives an instruction;

[0028] The detection module is used to determine whether the synchronization function of the multi-threaded processor to be detected is abnormal by comparing the target address corresponding to the currently detected target behavior with the standard synchronization address recorded in the target instruction information.

[0029] Furthermore, the determining module is specifically used to determine the thread that sent the synchronization request as the target thread if the sending behavior of the synchronization request is detected at the first preset interface.

[0030] Furthermore, the determining module is specifically used to determine the thread responding to the synchronization request as the target thread if a response to the synchronization request is detected at the second preset interface.

[0031] Furthermore, the determining module is specifically used to determine the thread executing the synchronization instruction as the target thread when it is detected that the multi-threaded processor to be detected is executing a synchronization instruction.

[0032] Furthermore, the determining module is specifically configured to determine the target synchronization status identifier as a waiting identifier if the target behavior is a synchronization request sending behavior; determine the target synchronization status identifier as an in-transit identifier if the target behavior is a synchronization request response behavior; and determine the target synchronization status identifier as a ready identifier if the target behavior is executing a synchronization instruction.

[0033] Furthermore, the next state identifier of the waiting identifier is the in-transit identifier, and the next state identifier of the in-transit identifier is the ready identifier.

[0034] Furthermore, the determining module is also used to, if an instruction input is detected at the third preset interface, store the information of the instruction into the corresponding target instruction status queue according to the thread information included in the input instruction. The information of the instruction includes: a synchronization enable flag, a standard synchronization address, and a synchronization status flag, wherein the synchronization enable flag is used to describe whether the corresponding instruction is a synchronization instruction.

[0035] Furthermore, the device also includes:

[0036] The update module is used to update the synchronization status identifier in the target instruction information to the next status identifier of the target synchronization status identifier.

[0037] This application also provides an electronic device, which includes a processor, and the processor is used to implement the steps of the multi-threaded processor synchronization function detection method as described above when executing a computer program stored in a memory.

[0038] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the multi-threaded processor synchronization function detection method described above.

[0039] This application also provides a computer program product, which includes computer program code. When the computer program code is run on a computer, it causes the computer to perform the steps of any of the multi-threaded processor synchronization function detection methods described above.

[0040] In this embodiment, the behavior of the multi-threaded processor under test is detected in real time. When it is determined that the multi-threaded processor under test has a target behavior of processing synchronization instructions, the target thread corresponding to the synchronization instruction is identified, and a target synchronization status identifier pre-configured for the target behavior is obtained. Then, in the instruction status queue corresponding to the target thread, the first target instruction information with the target synchronization status identifier is searched. Finally, based on whether the target address corresponding to the currently detected target behavior matches the standard synchronization address recorded in the target instruction information, it is determined whether there is an anomaly in the synchronization function of the multi-threaded processor under test. By using an instruction status queue added for each thread to verify in real time whether the target address corresponding to the current target behavior matches the standard synchronization address in the instruction status queue, real-time detection of the multi-threaded processor synchronization function is achieved. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This application provides a schematic diagram of a multi-threaded processor synchronization function detection process.

[0043] Figure 2 This is a schematic diagram of an instruction status queue determination process provided in an embodiment of this application;

[0044] Figure 3 A schematic diagram illustrating a verification process during the request phase, provided as an embodiment of this application;

[0045] Figure 4 A schematic diagram illustrating a verification process during the response phase, provided as an embodiment of this application;

[0046] Figure 5 A schematic diagram illustrating an instruction execution behavior verification process provided in an embodiment of this application;

[0047] Figure 6 This application provides a schematic diagram of the structure of a multi-threaded processor synchronization function detection device according to an embodiment of the present application.

[0048] Figure 7 This is a schematic diagram of an electronic device structure provided in an embodiment of this application. Detailed Implementation

[0049] To make the objectives and implementation methods of this application clearer, the exemplary implementation methods of this application will be clearly and completely described below with reference to the accompanying drawings of the exemplary embodiments of this application. Obviously, the exemplary embodiments described are only some embodiments of this application, and not all embodiments.

[0050] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0051] The terms "first," "second," "third," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related objects or entities, and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms are interchangeable where appropriate.

[0052] The terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device that includes a range of components is not necessarily limited to all of the components that are clearly listed, but may include other components that are not clearly listed or that are inherent to such product or device.

[0053] The term "module" refers to any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code that enables the operation of the functions associated with that element.

[0054] In related technologies, when detecting the synchronization function of multi-threaded processors, it is impossible to complete a consistency check of the global synchronization state at the critical time point when the instruction begins execution. When a synchronization anomaly occurs, the problem is often only discovered in subsequent calculations, leading to difficulties in error localization, long debugging cycles, and the inability to achieve real-time verification. Furthermore, there are assertion-based local detection methods in related technologies, but due to the characteristics of assertions, they can only verify local conditions and lack the ability to track the global state across threads and cycles. Based on this, embodiments of this application provide a method, apparatus, and device for detecting the synchronization function of multi-threaded processors. In this method, if a target behavior of processing a synchronization instruction is detected in the multi-threaded processor to be detected, the target thread corresponding to the synchronization instruction is determined, and a target synchronization state identifier pre-configured for the target behavior is obtained; in the instruction state queue corresponding to the target thread, the first target instruction information with the target synchronization state identifier is searched, wherein the target instruction information is recorded in the instruction state queue when the target thread receives the instruction; based on whether the target address corresponding to the currently detected target behavior matches the standard synchronization address recorded in the target instruction information, it is determined whether there is an anomaly in the synchronization function of the multi-threaded processor to be detected.

[0055] Example 1:

[0056] Figure 1 This application provides a schematic diagram of a multi-threaded processor synchronization function detection process, which includes:

[0057] S101: If a target behavior of processing a synchronization instruction is detected in the multi-threaded processor to be detected, the target thread corresponding to the synchronization instruction is determined, and the target synchronization status identifier pre-configured for the target behavior is obtained.

[0058] The multi-threaded processor synchronization function detection method provided in this application is applied to electronic devices, such as computers (PCs), servers, etc.

[0059] In order to detect whether the synchronization function of a multi-threaded processor is normal in real time, the instruction processing behavior of the multi-threaded processor under test can be detected in real time in this embodiment of the application.

[0060] In this embodiment, information about instruction processing in the multi-threaded processor under test can be obtained in real time through a reserved interface of the processor under test. For example, the type of instruction currently being processed in the processor under test, and the type of processing being performed on that instruction, can be obtained in real time through this reserved interface. This facilitates determining whether the multi-threaded processor under test is processing a synchronization instruction. If it is determined to be a synchronization instruction, it can be further determined whether the behavior of the multi-threaded processor under test currently processing the synchronization instruction is the target behavior. The target behavior describes what operation the multi-threaded processor under test is performing on the synchronization instruction.

[0061] For example, the instructions that the multithreaded processor under test can process can be divided into synchronous instructions and asynchronous instructions. The operations that can be performed on synchronous instructions are operation 1, operation 2, operation 3, and operation 4. Then, the target behavior of the multithreaded processor under test in processing synchronous instructions is any one of operation 1, operation 2, operation 3, and operation 4.

[0062] In this embodiment, if a target behavior of processing a synchronization instruction is detected in the multi-threaded processor to be detected, the target thread corresponding to the synchronization instruction can be determined. That is, it can be determined which thread in the multi-threaded processor to be detected should process the synchronization instruction.

[0063] In this embodiment of the application, the synchronization instruction may carry the thread information of the target thread. When determining the target thread, the corresponding information can be directly obtained from the synchronization instruction for determination.

[0064] Of course, the instructions that the multi-threaded processor to be tested can process are known in advance. In this embodiment, the threads to be used when executing instructions with different functions can also be pre-configured. When determining the target thread, the target thread corresponding to the synchronization instruction can be determined based on the function that the synchronization instruction can achieve.

[0065] To facilitate subsequent determination of whether the target behavior currently being implemented by the multi-threaded processor is the operation that should be implemented in the current synchronization phase, different synchronization state flags can be pre-configured for different behaviors in this embodiment. For example, when processing synchronization instruction A, it requires four stages of synchronization processing, and the steps corresponding to different stages need to be completed sequentially. In stage 1, step 1 needs to be completed; in stage 2, step 2 needs to be completed; in stage 3, step 3 needs to be completed; and in stage 4, step 4 needs to be completed. Therefore, the target synchronization state flag can be pre-configured as stage 1 for step 1, stage 2 for step 2, stage 3 for step 3, and stage 4 for step 4.

[0066] In this embodiment of the application, after determining that the multi-threaded processor to be detected has a target behavior of processing synchronization instructions, a target synchronization status identifier pre-configured for the target behavior can be obtained. For example, when the target behavior is step 2, the target synchronization status identifier corresponding to the target behavior is stage 2; when the target behavior is step 4, the target synchronization status identifier corresponding to the target behavior is stage 4.

[0067] S102: In the instruction status queue corresponding to the target thread, find the first target instruction information whose synchronization status identifier is the target synchronization status identifier, wherein the target instruction information is recorded in the instruction status queue when the target thread receives an instruction.

[0068] The target synchronization state identifier configured for the target behavior has been obtained, which means that theoretically, the target behavior should be in which synchronization state it should be in. In other words, it has been obtained which actions the multi-threaded processor under test should theoretically complete before performing the target behavior.

[0069] To facilitate comparison between theoretical and actual progress, in this embodiment, an independent instruction status queue can be maintained for each thread in advance. This instruction status queue records the current execution progress of each instruction executed by the corresponding thread. In other words, it records the current synchronization status flag of each instruction. For example, when a thread receives an instruction, the instruction information of that instruction can be recorded in the corresponding instruction status queue.

[0070] In the embodiments of this application, instructions from different threads can be executed out of order, but instructions within the same thread must be executed in sequence.

[0071] In order to compare the execution progress, in this embodiment of the application, the first target instruction information with the target synchronization status identifier can be found in the instruction status queue corresponding to the target thread.

[0072] S103: Based on whether the target address corresponding to the currently detected target behavior matches the standard synchronization address recorded in the target instruction information, determine whether there is an abnormality in the synchronization function of the multi-threaded processor to be detected.

[0073] After obtaining the target instruction information of the first target synchronization status identifier in the instruction status queue, it can be determined whether the instruction corresponding to the target instruction information is the synchronization instruction corresponding to the target behavior.

[0074] In this embodiment, the presence of an anomaly in the synchronization function of the multi-threaded processor under test can be determined by comparing the target address corresponding to the currently detected target behavior with the standard synchronization address recorded in the target instruction information. In this embodiment, if the target address matches the standard synchronization address, it is considered a match. Otherwise, it is determined that the target address does not match the standard synchronization address.

[0075] In the embodiments of this application, when it is determined that the target address matches the standard synchronization address, it can be considered that the current processing logic of the synchronization instruction of the multi-threaded processor under test is correct, and it can be determined that the synchronization function of the multi-threaded processor under test is normal.

[0076] If the target address does not match the standard synchronization address, it can be assumed that the processing logic of the multi-threaded processor for synchronization instructions is abnormal, meaning that the synchronization function of the multi-threaded processor under test is malfunctioning. Information related to this abnormality can be recorded for subsequent error localization.

[0077] In this embodiment, the behavior of the multi-threaded processor under test is detected in real time. When it is determined that the multi-threaded processor under test has a target behavior of processing synchronization instructions, the target thread corresponding to the synchronization instruction is identified, and a target synchronization status identifier pre-configured for the target behavior is obtained. Then, in the instruction status queue corresponding to the target thread, the first target instruction information with the target synchronization status identifier is searched. Finally, based on whether the target address corresponding to the currently detected target behavior matches the standard synchronization address recorded in the target instruction information, it is determined whether there is an anomaly in the synchronization function of the multi-threaded processor under test. By using an instruction status queue added for each thread to verify in real time whether the target address corresponding to the current target behavior matches the standard synchronization address in the instruction status queue, real-time detection of the multi-threaded processor synchronization function is achieved.

[0078] Example 2:

[0079] To improve the accuracy of synchronization function detection, based on the above embodiments, in this embodiment, if a target behavior of processing a synchronization instruction is detected in the multi-threaded processor to be detected, determining the target thread corresponding to the synchronization instruction includes:

[0080] If a synchronization request is detected at the first preset interface, the thread that sent the synchronization request is identified as the target thread.

[0081] Analysis of the synchronization instruction processing reveals that after receiving a synchronization instruction, the multi-threaded processor under test sends synchronization requests to other threads that require synchronization. Only after receiving a response from one of these other threads can the synchronization instruction be executed. Therefore, in this embodiment, when determining the target thread corresponding to a synchronization instruction, different types of behavior can be detected at different interfaces, thereby determining the corresponding target thread based on that behavior.

[0082] In this embodiment, a first preset interface of the multi-threaded processor to be detected can be pre-configured as an interface for sending synchronization requests. During synchronization function detection, the first preset interface can be monitored in real time. When a synchronization request is detected on the first preset interface, the thread sending the synchronization request can be identified as the target thread.

[0083] To further improve the accuracy of synchronization function detection, based on the above embodiments, in this embodiment, if a target behavior of processing a synchronization instruction is detected in the multi-threaded processor to be detected, determining the target thread corresponding to the synchronization instruction includes:

[0084] If a response to a synchronization request is detected at the second preset interface, the thread responding to the response is identified as the target thread.

[0085] In this embodiment, the second preset interface of the processor of the thread to be detected can be pre-configured as an interface for receiving response information of synchronization requests. This second preset interface can be the same as the first preset interface, or it can be a different interface.

[0086] During synchronization function testing, the second preset interface can be monitored in real time. When a response to a synchronization request is detected on this interface, the thread responding to that response can be identified. In other words, it determines which thread sent the synchronization request the thread is responding to. After identifying the responding thread, it can be designated as the target thread.

[0087] To further improve the accuracy of synchronization function detection, based on the above embodiments, in this embodiment, if a target behavior of processing a synchronization instruction is detected in the multi-threaded processor to be detected, determining the target thread corresponding to the synchronization instruction includes:

[0088] If it is detected that the multi-threaded processor to be detected is executing a synchronization instruction, the thread executing the synchronization instruction will be identified as the target thread.

[0089] In order to determine whether the multi-threaded processor under test has performed all the preprocessing steps for any synchronization instruction when executing it, in this embodiment of the application, final permission detection can be performed at the time of execution.

[0090] In this embodiment, the instructions currently being executed by the multi-threaded processor under test can be detected in real time. When it is detected that the multi-threaded processor under test is executing a synchronization instruction, the thread executing the synchronization instruction can be identified as the target thread. Then, relevant information is compared based on the information recorded in the instruction status queue corresponding to the target thread.

[0091] Example 3:

[0092] In order to enable real-time detection of the synchronization function, based on the above embodiments, in this embodiment of the application, obtaining the target synchronization status identifier pre-configured for the target behavior includes:

[0093] If the target behavior is the sending of a synchronization request, then the target synchronization status identifier is determined to be a waiting identifier;

[0094] If the target behavior is a response to a synchronization request, then the target synchronization status identifier is determined to be an in-transit identifier;

[0095] If the target behavior is to execute a synchronization instruction, then the target synchronization status identifier is determined to be a ready identifier.

[0096] In this embodiment of the application, based on the characteristics of the life cycle of the synchronization instruction, the synchronization state of the synchronization instruction can be divided into three modes in advance: waiting, on-fly, and ready.

[0097] Among them, WAITING indicates that the synchronization command is ready and is waiting for the synchronization request to be sent;

[0098] ON_FLY indicates that a synchronization request has been sent and is waiting for a response from other components;

[0099] ACK indicates that synchronization has been successfully completed and the synchronization command is ready to be executed.

[0100] In this embodiment of the application, when obtaining the target synchronization status identifier pre-configured for the target behavior, if the target behavior is the sending behavior of a synchronization request, it can be determined that the synchronization instruction is ready and is waiting for the synchronization request to be sent, and the corresponding target synchronization status identifier can be determined as the waiting identifier, i.e., WAITING.

[0101] If the target behavior is a response to a synchronization request, then the corresponding target synchronization status can be identified as the in-transit identifier, i.e., ON_FLY.

[0102] If the target behavior is to execute a synchronization instruction, then the corresponding target synchronization status flag can be determined as the ready flag, i.e., ACK.

[0103] Since different synchronization status identifiers have an execution order, in this embodiment, the next status identifier of the waiting identifier can be pre-configured as the in-transit identifier, and the next status identifier of the in-transit identifier can be configured as the ready identifier. To indicate the completion of the synchronization instruction, in this embodiment, the next identifier of the ready identifier can also be configured as the completion identifier. That is, the completion identifier is used to indicate the completion of the corresponding synchronization instruction.

[0104] In one possible implementation, since the target instruction information uses a synchronization status identifier to describe the processing progress of the corresponding instruction, it is necessary to update the processing progress of the instruction corresponding to the target instruction information to facilitate accurate synchronization function detection of the instruction later. In this embodiment of the application, after determining whether there is an anomaly in the synchronization function based on whether the target address matches the standard synchronization address, the processing progress of the instruction corresponding to the target instruction information can also be updated.

[0105] In this embodiment of the application, the synchronization status identifier in the target instruction information can be updated to the next status identifier of the target synchronization status identifier.

[0106] Specifically, if the current target synchronization status is in transit, then the next status will be ready; if the current target synchronization status is waiting, then the next status will be in transit.

[0107] Example 4:

[0108] In order to enable real-time detection of the synchronization function, based on the above embodiments, the process of determining the instruction status queue corresponding to any thread in this embodiment includes:

[0109] If an instruction input is detected at the third preset interface, the information of the instruction is stored in the corresponding target instruction status queue according to the thread information included in the input instruction. The information of the instruction includes: synchronization enable flag, standard synchronization address, and synchronization status flag, wherein the synchronization enable flag is used to describe whether the corresponding instruction is a synchronization instruction.

[0110] In order to monitor the entire lifecycle of each synchronization instruction and thus determine whether the synchronization function of the multi-threaded processor under test is normal, each instruction received by the multi-threaded processor under test can be monitored in real time in this embodiment of the application.

[0111] In this embodiment, an independent instruction status queue can be dynamically created and maintained for each thread. This instruction status queue is used to record information about each received instruction.

[0112] In this embodiment, monitoring can be performed in real time on a third preset interface of the multi-threaded processor to be monitored. This third preset interface may be the same as or different from the first and second preset interfaces.

[0113] In this embodiment, if an instruction input is detected at the third preset interface, the instruction information can be stored in the corresponding target instruction status queue based on the thread information included in the input instruction. The instruction information may include at least: a synchronization enable flag, a standard synchronization address, and a synchronization status flag. The synchronization enable flag describes whether the corresponding instruction is a synchronous instruction. For example, when the synchronization enable flag is enabled, the corresponding instruction can be determined to be a synchronous instruction; when the synchronization enable flag is disabled, the corresponding instruction can be determined to be an asynchronous instruction. The standard synchronization address is the information of the specific hardware resources or logic units that the instruction needs to synchronize.

[0114] The multi-threaded processor synchronization function detection method provided in this application is equivalent to a white-box detection method. Specifically, the dynamic state tracking process based on instruction classification mainly includes two parts: system initialization and state modeling.

[0115] During system initialization, an independent instruction status queue can be dynamically created and maintained for each thread, and the input instruction stream can be listened to at the third preset interface for multi-threaded processing to be detected.

[0116] Each time an instruction input is detected, during state modeling, each instruction is abstracted into a standardized state table entry in the corresponding instruction state queue. Key fields include: synchronization enable flag (sync_config), standard synchronization address (sync_addr), and synchronization status flag (sync_status).

[0117] Example 5:

[0118] The process of detecting synchronization function in a multi-threaded processor will be described below with reference to a specific embodiment.

[0119] Figure 2 This is a schematic diagram of an instruction status queue determination process provided in an embodiment of this application, as shown below. Figure 2 As shown, firstly, the instruction stream input of the multi-threaded processor to be tested is detected at the third preset interface. Then, for each detected instruction... Based on the thread information included in the instruction, the instruction information is categorized and stored in the corresponding instruction status queue. In the middle. Among them, " In the quotation marks, 'i' represents the index identifier. For example, the detected third instruction can be represented as... If i=3, then the detected 6th instruction can be marked as... Therefore, i=6. Represents a thread The corresponding instruction status queue. Specifically, when it is necessary to store the information of any instruction in the instruction status queue, a new status entry can be created in the corresponding instruction status queue: synchronization enable flag, standard synchronization address, and synchronization status flag. It should be noted that within the same instruction status queue, the instruction information is stored in the order in which the detected instruction stream is processed.

[0120] During synchronization function testing, precise closed-loop verification of the synchronization handshake protocol can be performed. In other words, the entire synchronization "request-response" process can be precisely monitored.

[0121] For validation during the request phase: Figure 3 This application provides a schematic diagram of a verification process during the request phase, as illustrated in the embodiments of this application. Figure 3 As shown, the system listens for synchronization request sending behavior on the first preset interface IF2 and performs state transition checks. For example, when a synchronization request sending behavior is detected on the first preset interface IF2, the instruction state queue corresponding to the target thread sending the synchronization request can be determined. and in the instruction status queue The queue leader queries the first target instruction with a synchronization status flag of WAITING and a synchronization enable flag of "On". It then determines the target address to which the synchronization request will be sent and checks if this target address matches the standard synchronization address `sync_addr` in the target instruction information. If they match, the synchronization function of the multi-threaded processor under test is considered normal, and the target synchronization status flag in the target instruction information is updated to ON_FLY. If not, the multi-threaded processor under test does not conform to the synchronization handshake protocol, i.e., the synchronization function is abnormal.

[0122] For verification in the response phase: Figure 4 This application provides a schematic diagram of a verification process during the response phase, as illustrated in the embodiments of this application. Figure 4 As shown, the system listens for response behavior to synchronization requests on the second preset interface IF3 and performs complementary transaction loop checks. For example, when a response behavior to a synchronization request is detected on the second preset interface IF3, the thread responding to that response behavior can be determined. And in that thread The queue leader queries the first target instruction with an ON-FLY synchronization status and an ACK synchronization enable flag. Then, it determines the target address of the thread responding to the action and checks if this target address matches the standard synchronization address `sync_addr` in the target instruction information. If yes, the synchronization function of the multi-threaded processor under test is normal, and the target synchronization status flag in the target instruction information is updated to ACK. If no, the multi-threaded processor under test does not conform to the synchronization handshake protocol, i.e., the synchronization function is abnormal.

[0123] After completing the precise closed-loop verification of the synchronous handshake protocol, a final permission check can be performed when the multi-threaded processor under test executes instructions. In this embodiment, the instruction execution behavior of the multi-threaded processor under test can be monitored through white-box signals at each clock cycle.

[0124] Figure 5 This application provides a schematic diagram of an instruction execution behavior verification process, as shown in the embodiments of this application. Figure 5 As shown, key signals of the multi-threaded processor under test can be detected in real time. When it is determined that the multi-threaded processor under test is executing instructions, execution legality verification can be performed immediately based on the information recorded in the corresponding instruction status queue. It should be noted that how to detect whether the multi-threaded processor under test is executing instructions is existing technology, and this application embodiment will not elaborate on this process.

[0125] In this embodiment of the application, for the currently executed instruction, the instruction status queue corresponding to the instruction can be determined. and in the instruction status queue The system queries the first executable target instruction from the head of the queue. This means identifying the target instruction whose synchronization enable flag is off and whose synchronization status flag is ACK. Next, it determines the target address corresponding to the instruction currently being executed by the multi-threaded processor under test and checks if this target address matches the standard synchronization address `sync_addr` in the target instruction information. If they match, the multi-threaded processor under test is considered to have normal synchronization functionality, and the target synchronization status flag in the target instruction information is updated to successful. Alternatively, if a match is found, the target instruction information can be deleted from the instruction status queue. If not, the multi-threaded processor under test does not conform to synchronization processing logic, meaning its synchronization function is malfunctioning.

[0126] Based on the multi-threaded processor synchronization function detection method provided in this application embodiment, any deviation between the execution order of instructions and the order in the queue, or the premature execution of instructions that have not completed synchronization, will be captured and reported in real time.

[0127] To facilitate understanding, the following uses the tensor kernel as an example to provide an overview of the synchronization detection process for multi-threaded processors, mainly including the following:

[0128] 1. Each instruction has its own thread ID identifier. For example, in the embodiments of this application, this identifier can be represented as: warp_group_i, where the value of i ranges from [0, N-1], and N is the number of threads included in the multi-threaded processor to be detected.

[0129] 2. Each instruction has its own synchronization configuration enable flag and standard synchronization address.

[0130] 3. The prerequisite for the execution of each instruction is that the instruction is ready and the synchronization is ready. Here, synchronization ready means that the current instruction "does not enable the synchronization function" or "enables the synchronization function and its synchronization address has been synchronized".

[0131] 4. For each synchronization command, a synchronization request must be sent through interface IF2, and the synchronization must be completed and returned from interface IF3 before entering the synchronization ready state.

[0132] 5. Instructions between different threads can be synchronized out of order, but instructions within the same thread must be synchronized in order.

[0133] 6. If multiple instructions within the same thread have the same standard synchronization address, the latter will be blocked by the former until the former completes its synchronization operation.

[0134] In this embodiment of the application, the multi-threaded processor to be tested can be referred to as the Device Under Test (DUT).

[0135] In summary, the multi-threaded processor synchronization function detection method provided in this application is a lightweight white-box verification architecture. Specifically, the interaction information between the instruction stream and synchronization operations is monitored on the interface of the multi-threaded processor under test. A white-box checker component built using SystemVerilog (SV) is used to dynamically maintain the information of each instruction in the instruction state queue of each thread and to track the synchronization state of each thread with each instruction in real time. Furthermore, in this application embodiment, clock-level verification is implemented: key signals of the chip are monitored, and a state consistency check is immediately performed at the critical clock cycle when the instruction begins execution—comparing whether the instruction has completed the "synchronization function" in the white-box checker's state. If it has not completed the synchronization function but has already started execution, it indicates a functional abnormality. The chip is the multi-threaded processor under test described in the above embodiments.

[0136] The multi-threaded processor synchronization function detection method provided in this application embodiment enables the parallel execution of synchronization function detection and task execution of the multi-threaded processor under test. In other words, while the multi-threaded processor under test is executing its task normally, synchronization function detection can be performed in parallel, achieving real-time verification with "cycle-accurate" precision, and solving the debugging pain point of "invisible" synchronization state in related technologies.

[0137] The multi-threaded processor synchronization function detection method provided in this application is both abstract and portable. This architecture can not only be used for RTL verification, but its same logic and state machine can be seamlessly ported or adapted to modules written in C language or Field-Programmable Gate Arrays (FPGAs), achieving consistent verification of the same synchronization function at different design levels, thus forming a unified verification system. RTL verification refers to testing and analyzing register-transfer-level (RTL) code written in a hardware description language to ensure that its functionality, performance, and timing characteristics meet design expectations and specifications.

[0138] Example 6:

[0139] Based on the same inventive concept, embodiments of this application provide a multi-threaded processor synchronization function detection device. Figure 6 This application provides a schematic diagram of a multi-threaded processor synchronization function detection device, which includes:

[0140] The determination module 601 is used to determine the target thread corresponding to the synchronization instruction if the multi-threaded processor to be detected has a target behavior of processing the synchronization instruction, and to obtain the target synchronization status identifier pre-configured for the target behavior.

[0141] The lookup module 602 is used to look up the first target instruction information whose synchronization status identifier is the target synchronization status identifier in the instruction status queue corresponding to the target thread, wherein the target instruction information is recorded in the instruction status queue when the target thread receives an instruction;

[0142] The detection module 603 is used to determine whether the synchronization function of the multi-threaded processor to be detected is abnormal by comparing the target address corresponding to the currently detected target behavior with the standard synchronization address recorded in the target instruction information.

[0143] In one possible implementation, the determining module 601 is specifically configured to determine the thread that sent the synchronization request as the target thread if the sending behavior of the synchronization request is detected at the first preset interface.

[0144] In one possible implementation, the determining module 601 is specifically configured to determine the thread responding to the synchronization request as the target thread if a response to the synchronization request is detected at the second preset interface.

[0145] In one possible implementation, the determining module 601 is specifically used to determine the thread executing the synchronization instruction as the target thread when it is detected that the multi-threaded processor to be detected is executing a synchronization instruction.

[0146] In one possible implementation, the determining module 601 is specifically configured to: if the target behavior is sending a synchronization request, determine the target synchronization status identifier as a waiting identifier; if the target behavior is responding to a synchronization request, determine the target synchronization status identifier as an in-transit identifier; and if the target behavior is executing a synchronization instruction, determine the target synchronization status identifier as a ready identifier.

[0147] In one possible implementation, the next state identifier of the waiting identifier is an in-transit identifier, and the next state identifier of the in-transit identifier is a ready identifier.

[0148] In one possible implementation, the determining module 601 is further configured to, if an instruction input is detected at the third preset interface, store the information of the instruction into the corresponding target instruction status queue according to the thread information included in the input instruction. The information of the instruction includes: a synchronization enable flag, a standard synchronization address, and a synchronization status flag, wherein the synchronization enable flag is used to describe whether the corresponding instruction is a synchronization instruction.

[0149] In one possible implementation, the device further includes:

[0150] The update module 604 is used to update the synchronization status identifier in the target instruction information to the next status identifier of the target synchronization status identifier.

[0151] Example 7:

[0152] Based on the same inventive concept, embodiments of this application provide an electronic device that can implement the steps of the multi-threaded processor synchronization function detection method described above. Figure 7 This application provides a schematic diagram of an electronic device structure, such as... Figure 7 As shown, it includes: processor 701, communication interface 702, memory 703 and communication bus 704, wherein processor 701, communication interface 702 and memory 703 communicate with each other through communication bus 704.

[0153] The memory 703 stores a computer program. When the program is executed by the processor 701, the processor 701 performs the following steps:

[0154] If a target behavior of processing a synchronization instruction is detected in the multi-threaded processor to be detected, the target thread corresponding to the synchronization instruction is determined, and the target synchronization status identifier pre-configured for the target behavior is obtained.

[0155] In the instruction status queue corresponding to the target thread, find the first target instruction information whose synchronization status identifier is the target synchronization status identifier, wherein the target instruction information is recorded in the instruction status queue when the target thread receives an instruction;

[0156] Based on whether the target address corresponding to the currently detected target behavior matches the standard synchronization address recorded in the target instruction information, it is determined whether there is an anomaly in the synchronization function of the multi-threaded processor to be detected.

[0157] In one possible implementation, determining the target thread corresponding to the synchronization instruction if the detected multi-threaded processor exhibits target behavior of processing a synchronization instruction includes:

[0158] If a synchronization request is detected at the first preset interface, the thread that sent the synchronization request is identified as the target thread.

[0159] In one possible implementation, determining the target thread corresponding to the synchronization instruction if the detected multi-threaded processor exhibits target behavior of processing a synchronization instruction includes:

[0160] If a response to a synchronization request is detected at the second preset interface, the thread responding to the response is identified as the target thread.

[0161] In one possible implementation, determining the target thread corresponding to the synchronization instruction if the detected multi-threaded processor exhibits target behavior of processing a synchronization instruction includes:

[0162] If it is detected that the multi-threaded processor to be detected is executing a synchronization instruction, the thread executing the synchronization instruction will be identified as the target thread.

[0163] In one possible implementation, obtaining the target synchronization state identifier pre-configured for the target behavior includes:

[0164] If the target behavior is the sending of a synchronization request, then the target synchronization status identifier is determined to be a waiting identifier;

[0165] If the target behavior is a response to a synchronization request, then the target synchronization status identifier is determined to be an in-transit identifier;

[0166] If the target behavior is to execute a synchronization instruction, then the target synchronization status identifier is determined to be a ready identifier.

[0167] In one possible implementation, the next state identifier of the waiting identifier is an in-transit identifier, and the next state identifier of the in-transit identifier is a ready identifier.

[0168] In one possible implementation, the process of determining the instruction status queue corresponding to any thread includes:

[0169] If an instruction input is detected at the third preset interface, the information of the instruction is stored in the corresponding target instruction status queue according to the thread information included in the input instruction. The information of the instruction includes: synchronization enable flag, standard synchronization address, and synchronization status flag, wherein the synchronization enable flag is used to describe whether the corresponding instruction is a synchronization instruction.

[0170] In one possible implementation, the method further includes:

[0171] Update the synchronization status identifier in the target instruction information to the next status identifier of the target synchronization status identifier.

[0172] Since the principle of the above-mentioned electronic device in solving the problem is similar to that of the multi-threaded processor synchronization function detection method, the implementation of the above-mentioned electronic device can be found in the embodiments of the method, and repeated details will not be repeated.

[0173] The communication bus mentioned in the aforementioned electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used in the figure, but this does not indicate that there is only one bus or one type of bus. The communication interface 702 is used for communication between the aforementioned electronic device and other devices. The memory can include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory can also be at least one storage device located remotely from the aforementioned processor.

[0174] The processors mentioned above can be general-purpose processors, including central processing units, network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits, field-programmable gate arrays or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0175] Example 8:

[0176] Based on the same inventive concept, embodiments of this application also provide a computer-readable storage medium storing a computer program executable by a processor. When the program runs on the processor, it causes the processor to perform the following steps:

[0177] If a target behavior of processing a synchronization instruction is detected in the multi-threaded processor to be detected, the target thread corresponding to the synchronization instruction is determined, and the target synchronization status identifier pre-configured for the target behavior is obtained.

[0178] In the instruction status queue corresponding to the target thread, find the first target instruction information whose synchronization status identifier is the target synchronization status identifier, wherein the target instruction information is recorded in the instruction status queue when the target thread receives an instruction;

[0179] Based on whether the target address corresponding to the currently detected target behavior matches the standard synchronization address recorded in the target instruction information, it is determined whether there is an anomaly in the synchronization function of the multi-threaded processor to be detected.

[0180] In one possible implementation, determining the target thread corresponding to the synchronization instruction if the detected multi-threaded processor exhibits target behavior of processing a synchronization instruction includes:

[0181] If a synchronization request is detected at the first preset interface, the thread that sent the synchronization request is identified as the target thread.

[0182] In one possible implementation, determining the target thread corresponding to the synchronization instruction if the detected multi-threaded processor exhibits target behavior of processing a synchronization instruction includes:

[0183] If a response to a synchronization request is detected at the second preset interface, the thread responding to the response is identified as the target thread.

[0184] In one possible implementation, determining the target thread corresponding to the synchronization instruction if the detected multi-threaded processor exhibits target behavior of processing a synchronization instruction includes:

[0185] If it is detected that the multi-threaded processor to be detected is executing a synchronization instruction, the thread executing the synchronization instruction will be identified as the target thread.

[0186] In one possible implementation, obtaining the target synchronization state identifier pre-configured for the target behavior includes:

[0187] If the target behavior is the sending of a synchronization request, then the target synchronization status identifier is determined to be a waiting identifier;

[0188] If the target behavior is a response to a synchronization request, then the target synchronization status identifier is determined to be an in-transit identifier;

[0189] If the target behavior is to execute a synchronization instruction, then the target synchronization status identifier is determined to be a ready identifier.

[0190] In one possible implementation, the next state identifier of the waiting identifier is an in-transit identifier, and the next state identifier of the in-transit identifier is a ready identifier.

[0191] In one possible implementation, the process of determining the instruction status queue corresponding to any thread includes:

[0192] If an instruction input is detected at the third preset interface, the information of the instruction is stored in the corresponding target instruction status queue according to the thread information included in the input instruction. The information of the instruction includes: synchronization enable flag, standard synchronization address, and synchronization status flag, wherein the synchronization enable flag is used to describe whether the corresponding instruction is a synchronization instruction.

[0193] In one possible implementation, the method further includes:

[0194] Update the synchronization status identifier in the target instruction information to the next status identifier of the target synchronization status identifier.

[0195] Since the principle of the computer-readable storage medium in solving the problem is similar to that of the multi-threaded processor synchronization function detection method, the implementation of the computer-readable storage medium can be found in the embodiments of the method, and repeated details will not be repeated.

[0196] Example 9:

[0197] Based on the same inventive concept, this application also provides a computer program product, which includes computer program code. When the computer program code is run on a computer, it causes the computer to execute any of the multi-threaded processor synchronization function detection methods discussed above. Since the principle by which the above computer program product solves the problem is similar to that of the multi-threaded processor synchronization function detection method, the implementation of the above computer program product can refer to the implementation of the method, and repeated details will not be described again.

[0198] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0199] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0200] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0201] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of user-operated steps to be executed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0202] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for detecting synchronization function in a multi-threaded processor, characterized in that, The method includes: If a target behavior of processing a synchronization instruction is detected in the multi-threaded processor to be detected, the target thread corresponding to the synchronization instruction is determined, and the target synchronization status identifier pre-configured for the target behavior is obtained. In the instruction status queue corresponding to the target thread, find the first target instruction information whose synchronization status identifier is the target synchronization status identifier, wherein the target instruction information is recorded in the instruction status queue when the target thread receives an instruction; Based on whether the target address corresponding to the currently detected target behavior matches the standard synchronization address recorded in the target instruction information, it is determined whether there is an anomaly in the synchronization function of the multi-threaded processor to be detected.

2. The method according to claim 1, characterized in that, If the detected multi-threaded processor exhibits target behavior of processing synchronization instructions, determining the target thread corresponding to the synchronization instructions includes: If a synchronization request is detected at the first preset interface, the thread that sent the synchronization request is identified as the target thread.

3. The method according to claim 1, characterized in that, If the detected multi-threaded processor exhibits target behavior of processing synchronization instructions, determining the target thread corresponding to the synchronization instructions includes: If a response to a synchronization request is detected at the second preset interface, the thread responding to the response is identified as the target thread.

4. The method according to claim 1, characterized in that, If the detected multi-threaded processor exhibits target behavior of processing synchronization instructions, determining the target thread corresponding to the synchronization instructions includes: If it is detected that the multi-threaded processor to be detected is executing a synchronization instruction, the thread executing the synchronization instruction will be identified as the target thread.

5. The method according to claim 1, characterized in that, The step of obtaining the target synchronization state identifier pre-configured for the target behavior includes: If the target behavior is the sending of a synchronization request, then the target synchronization status identifier is determined to be a waiting identifier; If the target behavior is a response to a synchronization request, then the target synchronization status identifier is determined to be an in-transit identifier; If the target behavior is to execute a synchronization instruction, then the target synchronization status identifier is determined to be a ready identifier.

6. The method according to claim 5, characterized in that, The next state identifier of the waiting identifier is the in-transit identifier, and the next state identifier of the in-transit identifier is the ready identifier.

7. The method according to claim 1, characterized in that, The process of determining the instruction status queue for any thread includes: If an instruction input is detected at the third preset interface, the information of the instruction is stored in the corresponding target instruction status queue according to the thread information included in the input instruction. The information of the instruction includes: synchronization enable flag, standard synchronization address, and synchronization status flag, wherein the synchronization enable flag is used to describe whether the corresponding instruction is a synchronization instruction.

8. The method according to claim 1, characterized in that, The method further includes: Update the synchronization status identifier in the target instruction information to the next status identifier of the target synchronization status identifier.

9. A multi-threaded processor synchronization function detection device, characterized in that, The device includes: The determination module is used to determine the target thread corresponding to the synchronization instruction if a target behavior of processing a synchronization instruction is detected in the multi-threaded processor to be detected, and to obtain a target synchronization status identifier pre-configured for the target behavior. The lookup module is used to find the first target instruction information whose synchronization status identifier is the target synchronization status identifier in the instruction status queue corresponding to the target thread, wherein the target instruction information is recorded in the instruction status queue when the target thread receives an instruction; The detection module is used to determine whether the synchronization function of the multi-threaded processor to be detected is abnormal by comparing the target address corresponding to the currently detected target behavior with the standard synchronization address recorded in the target instruction information.

10. An electronic device, characterized in that, The electronic device includes a processor that executes a computer program stored in a memory to implement the steps of the multi-threaded processor synchronization function detection method as described in any one of claims 1-8.

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