Data processing methods, apparatus, system direct memory access modules, devices, storage media, and program products

Abstract

This application relates to a data processing method, apparatus, system direct memory access module, device, storage medium, and program product, and pertains to the field of artificial intelligence chip technology. This application can improve the data processing efficiency of a system direct memory access module. The method includes: receiving a data transfer instruction; responding to the data transfer instruction, triggering a read state machine in the system direct memory access module to generate a read command carrying a bus read address and storing it in a read command cache in the system direct memory access module; and triggering a write state machine in the system direct memory access module to generate a write command carrying a bus write address and storing it in a write command cache in the system direct memory access module. The read state machine is used to send the read command in the read command cache to the bus and to store the data returned from the bus in a data cache in the system direct memory access module. The write state machine is used to send the write command in the write command cache and the data in the data cache to the bus.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of artificial intelligence chip, in particular to a data processing method, device and system, a system direct memory access module, equipment, a storage medium and a program product. BACKGROUND

[0002] A large amount of data transfer is required for training and reasoning of large models of artificial intelligence chips. The artificial intelligence chip is a hardware chip specially designed and optimized for artificial intelligence tasks, including but not limited to GPU (Graphics Processing Unit), NPU (Neural Network Processing Unit), GPGPU (General-Purpose computing on Graphics Processing Unit).

[0003] The SDMA (system direct memory access) module on the artificial intelligence chip can transfer training data from the host to the device, or transfer data between devices. Improving the data transfer efficiency of the system direct memory access module is conducive to improving the data transmission efficiency of the artificial intelligence chip.

[0004] In the current technology, the system direct memory access module adopts a read-write serial mode of reading first and writing later to perform data transfer, and the data processing efficiency still needs to be improved. SUMMARY

[0005] Therefore, it is necessary to provide a data processing method, device and system, a system direct memory access module, equipment, a storage medium and a program product to solve the above technical problems.

[0006] In a first aspect, the present application provides a data processing method, comprising:

[0007] receiving a data transfer instruction;

[0008] in response to the data transfer instruction, triggering a read state machine in a system direct memory access module to generate a read command and store it in a read command cache in the system direct memory access module, and triggering a write state machine in the system direct memory access module to generate a write command and store it in a write command cache in the system direct memory access module; wherein the read command carries a bus read address, and the write command carries a bus write address;

[0009] The read state machine is configured to send the read command in the read command cache to the bus and store data returned by the bus to a data cache in the system direct memory access module.

[0010] The write state machine is configured to send the write command in the write command cache and the data in the data cache to the bus.

[0011] In one embodiment, the read state machine is configured to detect whether a ready signal of the bus is received; if the ready signal of the bus is received, the read command in the read command cache is sent to the bus.

[0012] In one embodiment, the write state machine is configured to detect whether the write command cache and the data cache are both in a non-empty state; if the write command cache and the data cache are both in the non-empty state, the write command in the write command cache and the data in the data cache are sent to the bus.

[0013] In one embodiment, the write state machine is configured to control a synchronization module in the system direct memory access module to synchronize and then send the write command in the write command cache and the data in the data cache to the bus.

[0014] In one embodiment, the read state machine is configured to control a read command generation module in the system direct memory access module to generate a read command; and the write state machine is configured to control a write command generation module in the system direct memory access module to generate a write command.

[0015] In a second aspect, the present application provides a data processing apparatus, comprising:

[0016] An instruction receiving module is configured to receive a data carrying instruction.

[0017] An instruction responding module is configured to, in response to the data carrying instruction, trigger a read state machine in a system direct memory access module to generate a read command and store the read command to a read command cache in the system direct memory access module, and trigger a write state machine in the system direct memory access module to generate a write command and store the write command to a write command cache in the system direct memory access module; wherein the read command carries a bus read address and the write command carries a bus write address.

[0018] The read state machine is configured to send the read command in the read command cache to the bus and store data returned by the bus to a data cache in the system direct memory access module.

[0019] The write state machine is configured to send the write command in the write command cache and the data in the data cache to the bus.

[0020] In a third aspect, the present application also provides a system direct memory access module, comprising: an instruction controller, a read state machine, a write state machine, a read command cache, a write command cache and a data cache; wherein the instruction controller is configured to perform the steps in the above method.

[0021] In a fourth aspect, the present application also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method.

[0022] In a fifth aspect, the present application also provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps in the above method.

[0023] In a sixth aspect, the present application also provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the steps in the above method.

[0024] The above data processing method, device, system direct memory access module, equipment, storage medium and program product receive a data transfer instruction, in response to the data transfer instruction, trigger the read state machine in the system direct memory access module to generate a read command carrying a bus read address and store it in the read command cache in the system direct memory access module, and trigger the write state machine in the system direct memory access module to generate a write command carrying a bus write address and store it in the write command cache in the system direct memory access module, the read state machine is configured to send the read command in the read command cache to the bus and store the data returned by the bus in the data cache in the system direct memory access module, and the write state machine is configured to send the write command in the write command cache and the data in the data cache to the bus. Thus, during data reading and writing, the read and write commands can be generated by the respective state machines and stored in the respective caches at the same time, without affecting each other, and the read and write state machines are not coupled. As long as the read data is returned, the write command in the write command cache and the data in the data cache can be sent to the bus by the write state machine, without generating a read command first and then generating a write command, i.e. without waiting for reading first and then writing. The write channel can directly receive the returned data for writing operation, realizing read and write in parallel, increasing the read and write bandwidth. At the same time, since there is no need to back pressure the data return channel of the read data, the data bandwidth of the data return channel of the read data is increased, thereby improving the data processing efficiency of the system direct memory access module. BRIEF DESCRIPTION OF DRAWINGS

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of data processing in the system's direct memory access module in related technologies;

[0027] Figure 2 This is a diagram illustrating the application environment of a data processing method in one embodiment.

[0028] Figure 3 This is a flowchart illustrating a data processing method in one embodiment;

[0029] Figure 4 This is a schematic diagram of the structure of the system's direct memory access module in one embodiment;

[0030] Figure 5 This is a structural block diagram of a data processing device in one embodiment;

[0031] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0033] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various objects, but these objects are not limited by these terms. These terms are only used to distinguish the first object from the second object. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the solutions, or any combination of multiple solutions.

[0034] The system direct memory access module on the artificial intelligence chip can participate in the large amount of data transfer required for training and inference of large models of artificial intelligence chips. The system direct memory access module can move data from the host to the device, and can also move data between devices.

[0035] In the design of the system's direct memory access module, it can be divided into read operations and write operations. Read operations are responsible for reading the data back, and write operations are responsible for writing the read data to the destination address.

[0036] For data reading and writing, in current technologies, such as Figure 1 As shown, the system's direct memory access module (DMI) executes read and write operations serially, i.e., read first and then write, using a single set of control logic. This prevents read and write operations from occurring simultaneously, significantly impacting the DMI's data processing efficiency, which still needs improvement. Specifically, the instruction controller can control the read command generation module to generate read commands and store them in the command cache, then send the read commands from the command cache to the bus, and read the returned data from the bus into the data cache. The instruction controller can also control the write command generation module to generate write commands and store them in the command cache. The synchronization module synchronizes the write commands in the command cache and the data in the data cache, sends the write commands and data to the bus, and then generates the next read command to continue the process. Therefore, in current technology, the DMI's read and write operations are executed serially, i.e., read first and then write, using a single set of control logic. Read and write operations cannot occur simultaneously, and read and write commands share a single cache. Only one operation responds to on the bus at any given time, preventing parallel bus read and write operations, wasting bus bandwidth, and impacting the DMI's data processing efficiency.

[0037] The data processing method provided in this application embodiment can be applied to, for example... Figure 2 The application environment shown can include a system direct memory access module (SDRAM) of an AI chip. This SDRAM can be connected to the AI ​​chip's bus, which may be, but is not limited to, an AXI (Advanced eXtensible Interface) bus. The SDRAM can include components such as an instruction controller, a read state machine, a write state machine, a read command cache, a write command cache, and a data cache. The data processing method provided in this application embodiment allows read and write commands to be generated simultaneously by their respective state machines and stored in their respective caches during data read and write operations, without interference. The read and write state machines are not coupled; as long as read data is returned, the write state machine can send the write command from the write command cache and the data from the data cache to the bus. There is no need to generate a read command before generating a write command, i.e., there is no need to wait for a read-then-write sequence. The write channel can continuously receive returned data for write operations, achieving parallel read and write operations and increasing read and write bandwidth. Simultaneously, since there is no need to backpressure the read data return channel, the data bandwidth of the read data return channel is increased, thereby improving the data processing efficiency of the SDRAM.

[0038] In one exemplary embodiment, such asFigure 3 As shown, a data processing method is provided, which can be applied to... Figure 2 The method may include the following steps:

[0039] Step S301: Receive data transfer instructions.

[0040] In this step, the instruction controller in the System Direct Memory Access (SDRAM) module on the AI ​​chip receives data transfer instructions. These instructions can originate from the host computer. These instructions can be used to instruct the SDRAM module to read or write data.

[0041] In step S302, in response to the data transfer instruction, the read state machine in the system direct memory access module is triggered to generate a read command and store it in the read command cache of the system direct memory access module, and the write state machine in the system direct memory access module is triggered to generate a write command and store it in the write command cache of the system direct memory access module.

[0042] Combination Figure 2 In this step, the instruction controller in the system's direct memory access module responds to data transfer instructions. The instruction controller triggers the read state machine in the system's direct memory access module to generate read commands. There can be multiple read commands; the instruction controller can trigger the read state machine to generate multiple read commands sequentially according to the data transfer instructions, and store them in a read command cache in the form of a read command queue. Each read command carries a bus read address. The read command cache can employ a FIFO (First-In-First-Out) module. Simultaneously, the instruction controller in the system's direct memory access module responds to data transfer instructions and triggers the write state machine in the system's direct memory access module to generate write commands. There can be multiple write commands; the instruction controller can trigger the write state machine to generate multiple write commands sequentially according to the data transfer instructions, and store them in a write command cache in the form of a write command queue. Each write command carries a bus write address. The write command cache can also employ a FIFO module.

[0043] In this step, the read state machine is used to send read commands from the read command cache to the bus and to store the data returned by the bus in the data cache of the system's direct memory access module. Specifically, the read state machine can sequentially send each read command stored in the read command cache as a read command queue to the bus. The bus will return the read data based on the received read commands, and the read state machine can store the data returned from the bus in the data cache of the system's direct memory access module as a data queue. The data cache can employ a FIFO module.

[0044] In this step, the write state machine is used to send write commands from the write command buffer and data from the data buffer to the bus. Specifically, the write state machine can sequentially send each piece of data stored in the data buffer as a data queue and each write command stored in the write command buffer as a write command queue to the bus.

[0045] The data processing method of this embodiment receives a data transfer instruction, and in response to the data transfer instruction, triggers the read state machine in the system direct memory access module to generate a read command carrying the bus read address and stores it in the read command cache in the system direct memory access module, and triggers the write state machine in the system direct memory access module to generate a write command carrying the bus write address and store it in the write command cache in the system direct memory access module. The read state machine is used to send the read command in the read command cache to the bus and to store the data returned by the bus in the data cache in the system direct memory access module. The write state machine is used to send the write command in the write command cache and the data in the data cache to the bus. Therefore, during data read and write operations, read and write commands can be generated simultaneously by their respective state machines and stored in their respective caches without affecting each other. The read and write state machines are not coupled. As long as read data is returned, the write state machine can send the write command in the write command cache and the data in the data cache to the bus without having to generate a read command first and then a write command. That is, there is no need to wait for the read to be written. The write channel can continuously receive returned data for write operations, realizing parallel read and write operations and increasing read and write bandwidth. At the same time, since there is no need to backpressure the read data return channel, the data bandwidth of the read data return channel is increased, thereby improving the data processing efficiency of the system's direct memory access module.

[0046] In an exemplary embodiment, a read state machine is used to detect whether a bus ready signal has been received; if a bus ready signal is received, the read command in the read command buffer is sent to the bus.

[0047] In this embodiment, combined with Figure 2 The instruction controller can trigger the read state machine to sequentially generate multiple read commands based on data transfer instructions. These commands are stored in a read command buffer as a read command queue. Before sending a read command to the bus, the read state machine checks whether it has received a bus ready signal. If it receives the bus ready signal, the read state machine can send the read commands from the read command buffer to the bus to perform the data reading operation. If it does not receive the bus ready signal, the read state machine can continue to wait for the bus ready signal. The solution in this embodiment can smoothly and orderly control the sending of read commands.

[0048] In an exemplary embodiment, a write state machine is used to detect whether both the write command cache and the data cache are in a non-empty state; if both the write command cache and the data cache are in a non-empty state, the write command in the write command cache and the data in the data cache are sent to the bus.

[0049] In this embodiment, combined with Figure 2 The read-returned data can be stored in a data buffer as a data queue, and the write command can be stored in a write command buffer as a write command queue. When the write state machine executes a write operation, it first checks whether both the write command buffer and the data buffer are in a non-empty state. If both the write command buffer and the data buffer are detected to be in a non-empty state, the write command in the write command buffer and the data in the data buffer can be simultaneously ejected, and the write command and data can be sent to the bus. If the write command buffer or the data buffer is detected to be in a non-empty state, the write operation stops, and the machine waits for the write command in the write command buffer or the data in the data buffer. The scheme in this embodiment can smoothly and orderly control the transmission of write commands and data.

[0050] In an exemplary embodiment, a write state machine is used to control the synchronization module in the system direct memory access module to synchronize the write commands in the write command cache and the data in the data cache before sending them to the bus.

[0051] In this embodiment, combined with Figure 2 The system's direct memory access module can also include a synchronization module. When the write state machine performs a write operation, it can control the synchronization module within the system's direct memory access module to synchronize the write commands in the write command cache and the data in the data cache before sending them to the bus. Specifically, when the write state machine performs a write operation, it can control the synchronization module to check if both the write command cache and the data cache are non-empty. If both are detected to be non-empty, it indicates that the previously read data and the previously generated write commands are available. Simultaneously, the write commands in the write command cache and the data in the data cache can be flushed. The write state machine can then control the synchronization module to synchronize these write commands and data before sending them to the bus. Conversely, if the write command cache or the data cache is not detected to be non-empty, the write operation stops, and the system waits for the write commands in the write command cache or the data in the data cache.

[0052] In an exemplary embodiment, a read state machine is used to control the read command generation module in the system direct memory access module to generate read commands; a write state machine is used to control the write command generation module in the system direct memory access module to generate write commands.

[0053] In this embodiment, combined with Figure 2The system's direct memory access module may further include a read command generation module and a write command generation module. The read state machine can control the read command generation module within the system's direct memory access module to generate multiple read commands based on data transfer instructions, and store these commands in a read command cache as a read command queue. Similarly, the write state machine can control the write command generation module within the system's direct memory access module to generate multiple write commands based on data transfer instructions, and store these commands in a write command cache as a write command queue. The generation of read and write commands can be parallel and independent of each other.

[0054] In one exemplary embodiment, combined with Figure 2 After the read operation is completed, the read state machine can jump back to the idle state. Upon receiving the last read data and completing the write operation, and after receiving all write responses, the write state machine can jump back to the idle state. This completes the data transfer task for the entire system's direct memory access module, allowing it to wait for the next data transfer task from the system's direct memory access module.

[0055] In one exemplary embodiment, such as Figure 4 As shown, a system direct memory access module is provided. This system direct memory access module may include an instruction controller, a read state machine, a write state machine, a read command cache, a write command cache, and a data cache. The instruction controller can be used to execute the steps of the data processing method of any of the above embodiments. Further, the system direct memory access module may also include a read command generation module, a write command generation module, and a synchronization module.

[0056] Specifically, the read state machine can be used to control the generation of read commands, the read command generation module can be used to generate read commands carrying bus read addresses such as the AXI bus read address, the read command cache can be used to cache read commands, the data cache can be used to cache the data returned from reading, the read state machine can be used to control the generation of write commands, the write command generation module can be used to generate write commands carrying bus write addresses such as the AXI bus write address, the write command cache can be used to cache write commands, and the synchronization module can be used to synchronize the write commands in the write command cache and the data in the data cache, etc.

[0057] Combination Figure 2The instruction controller can simultaneously start the read state machine and the write state machine based on data transfer instructions. After the read state machine starts, it can control the read command generation module to generate read commands, and similarly, after the write state machine starts, it can control the write command generation module to generate write commands. The read command generation module and the write command generation module can respectively generate read commands carrying the AXI bus read address and cache them in the read command cache, and write commands carrying the AXI bus write address and cache them in the write command cache. After the AXI bus is ready, the read commands in the read command cache are sent to the AXI bus, waiting for the read data to return. The returned data is cached in the data cache and sent to the AXI bus as write data for the write operation. The synchronization module synchronizes the data in the data cache and the write commands in the write command cache before sending them to the AXI bus for the write operation. After all read commands are generated, the read state machine can return to the idle state. After the last read data returns, the last write command is issued, and all write responses are received, the write state machine can return to the idle state, completing the data transfer task for direct memory access.

[0058] In the above process, when the instruction controller of the system's direct memory access module receives a data transfer instruction, it can simultaneously start the read state machine and the write state machine, generating read commands and write commands respectively for caching. For read operations, the read command is sent directly to the bus, and the returned data is cached in the data cache. For write operations, the read command must wait for the returned data. When both the write command cache and the data cache are not empty, the write command in the write command cache, along with the data in the data cache, is sent to the bus. The generation of read and write commands in the read and write state machines is independent and occurs in parallel. After the read and write operations are completed, the read and write state machines return to the idle state, waiting for the next data transfer task from the system's direct memory access module.

[0059] This embodiment of the application can simultaneously implement two sets of system control logic for reading and writing in the system's direct memory access module, and simultaneously cache read commands and write commands, independently control read and write operations, use a data cache for synchronous read and write, and employ two sets of state machines for control. After receiving a data transfer instruction, the read state machine and the write state machine can start simultaneously. The read state machine can control the read command generation module to generate AXI bus read commands and cache them in the read command cache (which can be a FIFO module). Once the AXI bus is ready, the read commands in the read command cache are sent to the AXI bus. The write state machine can control the write command generation module to generate AXI bus write commands and cache them in the write command cache (which can be a FIFO module). The data returned from reading can be cached in the data cache (which can be a FIFO module). During a write operation, if the data cache and the write command cache are detected to be non-empty, the data and write command are simultaneously ejected and sent to the AXI bus. This system utilizes a data cache for synchronized read and write operations. When the data cache is not empty, it indicates that the previously read data is available, allowing for a write operation. If the data cache is empty, write operations cease, awaiting the return of the read data. After a read operation is complete, the read state machine returns to the idle state. Upon receiving the last read data, the write operation is completed, and after receiving all write responses, the write state machine returns to the idle state. During read and write operations, read and write commands can be generated by their respective state machines without interference. During a read operation, as long as previously read data is returned, the write state machine can perform the write operation; there is no need to generate read commands first and then write commands, allowing read and write commands to be generated simultaneously. Because there is no need to wait for a read before a write, the write channel can continuously receive read data for write operations, achieving parallel read and write operations and increasing read and write bandwidth. Furthermore, the absence of backpressure on the read data return channel increases the data bandwidth of the read data return channel. The control logic is simple, the read and write state machines are decoupled, and read and write operations can be synchronized using the data cache. In AI chip design, this reduces the number of verification iterations and enhances chip reliability.

[0060] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0061] Based on the same inventive concept, this application also provides a data processing apparatus for implementing the data processing method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more data processing apparatus embodiments provided below can be found in the limitations of the data processing method described above, and will not be repeated here.

[0062] In one exemplary embodiment, such as Figure 5 As shown, a data processing apparatus 500 is provided, which may include:

[0063] Instruction receiving module 501 is used to receive data transfer instructions;

[0064] The instruction response module 502 is used to respond to the data transfer instruction by triggering the read state machine in the system direct memory access module to generate a read command and store it in the read command cache of the system direct memory access module, and triggering the write state machine in the system direct memory access module to generate a write command and store it in the write command cache of the system direct memory access module; wherein, the read command carries the bus read address, and the write command carries the bus write address;

[0065] The read state machine is used to send read commands from the read command cache to the bus and to store the data returned by the bus to the data cache in the system direct memory access module.

[0066] The write state machine is used to send the write commands in the write command cache and the data in the data cache to the bus.

[0067] In an exemplary embodiment, the read state machine is used to detect whether a bus ready signal has been received; if a bus ready signal is received, the read command in the read command cache is sent to the bus.

[0068] In an exemplary embodiment, the write state machine is used to detect whether both the write command cache and the data cache are in a non-empty state; if both the write command cache and the data cache are in a non-empty state, then the write command in the write command cache and the data in the data cache are sent to the bus.

[0069] In an exemplary embodiment, the write state machine is used to control the synchronization module in the system direct memory access module to synchronize the write commands in the write command cache and the data in the data cache and then send them to the bus.

[0070] In an exemplary embodiment, the read state machine is used to control the read command generation module in the system direct memory access module to generate read commands; the write state machine is used to control the write command generation module in the system direct memory access module to generate write commands.

[0071] Each module in the aforementioned data processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0072] In one exemplary embodiment, a computer device is provided, which may be a server or a terminal, and its internal structure diagram may be as follows. Figure 6 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a data processing method.

[0073] Those skilled in the art will understand that Figure 6The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0074] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0075] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0076] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0077] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0078] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0079] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0080] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data processing method, characterized in that, The method includes: Receive data transfer instructions; In response to the data transfer instruction, the read state machine in the system direct memory access module is triggered to generate a read command and store it in the read command cache of the system direct memory access module, and the write state machine in the system direct memory access module is triggered to generate a write command and store it in the write command cache of the system direct memory access module; wherein, the read command carries the bus read address, and the write command carries the bus write address; The read state machine is used to send read commands from the read command cache to the bus and to store the data returned by the bus in the data cache of the system direct memory access module. The write state machine is used to send the write commands in the write command cache and the data in the data cache to the bus.

2. The method according to claim 1, characterized in that, The read state machine is used to detect whether a ready signal from the bus has been received; if a ready signal from the bus is received, the read command in the read command cache is sent to the bus.

3. The method according to claim 1, characterized in that, The write state machine is used to detect whether both the write command cache and the data cache are in a non-empty state; if both the write command cache and the data cache are in a non-empty state, the write command in the write command cache and the data in the data cache are sent to the bus.

4. The method according to claim 1, characterized in that, The write state machine is used to control the synchronization module in the system's direct memory access module to synchronize the write commands in the write command cache and the data in the data cache before sending them to the bus.

5. The method according to any one of claims 1 to 4, characterized in that, The read state machine is used to control the read command generation module in the system's direct memory access module to generate read commands; the write state machine is used to control the write command generation module in the system's direct memory access module to generate write commands.

6. A data processing apparatus, characterized in that, The device includes: The instruction receiving module is used to receive data transfer instructions; The instruction response module is used to respond to the data transfer instruction by triggering the read state machine in the system direct memory access module to generate a read command and store it in the read command cache of the system direct memory access module, and triggering the write state machine in the system direct memory access module to generate a write command and store it in the write command cache of the system direct memory access module; wherein, the read command carries the bus read address, and the write command carries the bus write address; The read state machine is used to send read commands from the read command cache to the bus and to store the data returned by the bus in the data cache of the system direct memory access module. The write state machine is used to send the write commands in the write command cache and the data in the data cache to the bus.

7. A system direct memory access module, characterized in that, The module includes: an instruction controller, a read state machine, a write state machine, a read command cache, a write command cache, and a data cache; wherein, the instruction controller is used to execute the steps of the method according to any one of claims 1 to 5.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

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