Instruction verification method and device, equipment and storage medium

Abstract

The invention provides an instruction verification method and device, equipment and a storage medium, and relates to the technical field of chip design verification, and the method comprises the steps: dividing a to-be-verified instruction according to a preset multi-layer instruction structure, and obtaining at least one instruction block corresponding to the multi-layer instruction structure; the to-be-verified instruction is a composite instruction comprising a plurality of basic instructions; the multi-layer instruction structure is used for representing a basis for dividing instruction blocks from the perspective of instruction functions, and each instruction block has a respective function; randomly generating a first verification instruction block based on the first instruction block, and generating a second verification instruction block based on the first verification instruction block and the second instruction block; wherein the first instruction block is an instruction block having no constraint relation with other instruction blocks, and the second instruction block is constrained by the first instruction block; obtaining a verification instruction based on each verification instruction block corresponding to the at least one instruction block; and verifying the to-be-verified instruction through the verification instruction. And the random efficiency and fairness of instruction verification are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip design verification technical field, and particularly relates to an instruction verification method, device, equipment and storage medium. BACKGROUND

[0002] In the technical field of chip design or GPU, the correctness of instructions needs to be verified after the design of the instructions. In the instruction verification process, a verification instruction is randomly generated from the numerous types, formats or addresses of the instructions, and the correctness of the instruction behavior is determined through the verification instruction.

[0003] However, due to the large number of instructions, the complex format and the mutual constraints between different types of instructions, the efficiency of randomly generating a verification instruction is low, and some instructions cannot be randomly generated due to the constraints, which affects the fairness of instruction randomization. SUMMARY

[0004] The embodiments of the present application provide an instruction verification method, device, equipment and storage medium, which are used to improve the efficiency of instruction verification.

[0005] In a first aspect, the embodiments of the present application provide an instruction verification method, comprising: dividing a to-be-verified instruction according to a preset multi-layer instruction structure to obtain at least one instruction block corresponding to the multi-layer instruction structure; the to-be-verified instruction is a composite instruction comprising a plurality of basic instructions; the multi-layer instruction structure is used to represent the basis for dividing the instruction block from the perspective of instruction function, and each instruction block has its own function; randomly generating a first verification instruction block based on a first instruction block, and generating a second verification instruction block based on the first verification instruction block and a second instruction block; wherein the first instruction block is an instruction block having no constraint relationship with other instruction blocks, and the second instruction block is constrained by the first instruction block; obtaining a verification instruction based on each verification instruction block corresponding to the at least one instruction block; verifying the to-be-verified instruction through the verification instruction.

[0006] In the embodiments of the present application, by dividing the to-be-verified instruction according to the preset instruction structure, the instruction block corresponding to each layer of instruction structure is obtained, the function of each part of the instruction can be clearly understood, and when the instruction is randomly generated, the instruction block can be randomly generated, thereby avoiding that some instruction blocks cannot be randomly generated, improving the fairness of instruction randomization; the random order between the instruction blocks is determined according to the constraint relationship between the instruction blocks, so that the instruction blocks constrained are randomly generated later, and the instruction blocks not constrained are randomly generated first, thereby avoiding that the randomly generated instruction is incorrect due to the constraint problem, and improving the efficiency of instruction randomization.

[0007] Optionally, the multi-layer instruction structure comprises an infrastructure layer, a formatting layer and a resource management layer. The infrastructure layer represents an instruction block composed of basic instructions irrelevant to execution behavior of the instructions. The formatting layer represents an instruction block composed of basic instructions relevant to execution behavior of the instructions. The resource management layer represents an instruction block composed of basic instructions relevant to resources required by the instructions.

[0008] In the embodiments of the present application, the instruction structure is divided into the infrastructure layer, the formatting layer and the resource management layer, so that it can be determined from the multi-layer instruction structure which instruction blocks are unconstrained instruction blocks and which instruction blocks are constrained instruction blocks by other instruction blocks, and the subsequent random order of the instructions can be determined.

[0009] Optionally, the formatting layer comprises a parameter meta-information layer and a hardware execution information layer; the parameter meta-information layer represents meta-information of an execution object of the instructions; and the hardware execution information layer represents basic information of hardware where the instructions are executed.

[0010] In the embodiments of the present application, the instruction structure of the formatting layer is further divided into layers to obtain instruction blocks corresponding to the layers, so that the instructions can be randomly generated in each instruction block in the complex instruction structure, and the fairness of the instruction randomization is further ensured.

[0011] Optionally, for each first instruction block without a constraint relationship, a corresponding first verification instruction block is randomly generated in parallel.

[0012] In the embodiments of the present application, the instructions without the constraint relationship are randomly generated in parallel, and the instructions do not need to wait for the randomization of other instructions to end, so that the speed of the instruction randomization can be improved.

[0013] Optionally, after the at least one instruction block corresponding to the multi-layer instruction structure is obtained, and before the corresponding first verification instruction block is randomly generated in parallel, the method further comprises: The at least one instruction block and the random generation mode are summarized as a verification instruction code set. The verification instruction block corresponding to each instruction block in the at least one instruction block is randomly generated, comprising: The verification instruction block corresponding to each instruction block in the at least one instruction block is randomly generated by using the verification instruction code set.

[0014] In the embodiments of the present application, the instruction blocks and the random generation mode are summarized as the verification instruction code set, and the verification instruction block is generated by using the verification instruction code set, so that each instruction block of the to-be-verified instruction can be clearly identified, and the verification instruction block can be quickly generated.

[0015] Optionally, the infrastructure layer comprises one or more of instruction type, instruction code, and synchronization mode; the formatting layer comprises one or more of data type, data size, and operand; and the resource management layer comprises one or more of register and memory access address.

[0016] In a second aspect, an embodiment of the present application provides an instruction verification apparatus, comprising: a division module configured to divide a to-be-verified instruction according to a preset multi-layer instruction structure to obtain at least one instruction block corresponding to the multi-layer instruction structure; the to-be-verified instruction is a composite instruction comprising a plurality of basic instructions; and the multi-layer instruction structure is used to represent a basis for dividing the instruction blocks from the perspective of instruction function, and each instruction block has a respective function; a generation module configured to randomly generate a first verification instruction block based on a first instruction block, and generate a second verification instruction block based on the first verification instruction block and a second instruction block; the first instruction block is an instruction block having no constraint relationship with other instruction blocks, and the second instruction block is constrained by the first instruction block; a verification module configured to obtain a verification instruction based on respective verification instruction blocks corresponding to the at least one instruction block; The verification module is further configured to verify the to-be-verified instruction by using the verification instruction.

[0017] Optionally, the multi-layer instruction structure comprises an infrastructure layer, a formatting layer, and a resource management layer. The infrastructure layer represents an instruction block composed of basic instructions irrelevant to execution behavior of instructions. The formatting layer represents an instruction block composed of basic instructions relevant to execution behavior of instructions. The resource management layer represents an instruction block composed of basic instructions relevant to resources required by instructions.

[0018] Optionally, the formatting layer comprises a parameter meta-information layer and a hardware execution information layer. The parameter meta-information layer represents meta-information of an instruction execution object. The hardware execution information layer represents basic information of hardware where an instruction is executed.

[0019] Optionally, the generation module is specifically configured to: For each first instruction block having no constraint relationship, a respective first verification instruction block is randomly generated in parallel.

[0020] Optionally, the generation module is further configured to: The at least one instruction block and the random generation mode are summarized as a verification instruction code set. Optionally, the generation module is specifically configured to: By the verification instruction code set, a verification instruction block corresponding to each of the at least one instruction block is randomly generated.

[0021] Optionally, the infrastructure layer comprises one or more of an instruction type, an instruction code, a synchronization mode; The formatting layer comprises one or more of a data type, a data size, an operand; The resource management layer comprises one or more of a register, a memory access address.

[0022] In a third aspect, an embodiment of the present application provides a computer device, comprising a memory, an artificial intelligence chip, and a computer program stored in the memory and capable of running on the artificial intelligence chip, and the artificial intelligence chip implements the steps of the instruction verification method when executing the computer program.

[0023] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program capable of being executed by a computer device, and when the computer program runs on the computer device, the computer device executes the steps of the instruction verification method.

[0024] In a fifth aspect, an embodiment of the present application provides a computer program product, which comprises a computer program stored on a computer readable storage medium, and the computer program comprises program instructions, and when the program instructions are executed by a computer device, the computer device executes the steps of the instruction verification method.

[0025] In the embodiment of the present application, by dividing the to-be-verified instruction according to the preset instruction structure, the instruction block corresponding to each layer of instruction structure is obtained, the functions of each part in the instruction can be clearly understood, when the instruction is randomly generated, each divided instruction block can be randomly generated, so that the fairness of instruction randomization is improved; the random order between the instruction blocks is determined according to the constraint relationship between the instruction blocks, so that the instruction blocks under constraint are randomly generated after the instruction blocks not under constraint, the efficiency of instruction randomization is improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0027] Figure 1A structural diagram of an artificial intelligence chip provided by an embodiment of the present application; Figure 2 A flowchart of an instruction verification method provided by an embodiment of the present application; Figure 3 A flowchart of a method for randomly generating a verification instruction block provided by an embodiment of the present application; Figure 4 A structural diagram of an instruction verification device provided by an embodiment of the present application; Figure 5 A structural diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and beneficial effects of the present application clearer, the present application is further described in detail below in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0029] Reference Figure 1 It is a structural diagram of an artificial intelligence chip applicable to an embodiment of the present application, which includes at least a plurality of computing cores 101, an on-chip cache 102 and a display memory 103. The computing core 101 includes a register 1011.

[0030] The artificial intelligence chip 100 can be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose computing on graphics processing units (GPGPU), a domain specific architecture (DSA) and the like.

[0031] The computing core 101 obtains instructions from the register 1011 or the on-chip cache 102 or the display memory 103.

[0032] If the instructions cached in the register 1011 can meet the computing requirements of the computing core 101, the register 1011 provides the instructions to the computing core 101.

[0033] If the instructions cached in the register 1011 cannot meet the computing requirements of the computing core 101, the on-chip cache 102 provides the instructions to the computing core 101.

[0034] If the cached instructions in the on-chip cache 102 cannot meet the computing requirements of the computing core 101, the computing core 101 is provided with instructions through the display memory 103.

[0035] In instruction verification, the randomly generated instructions are not randomly generated, but are randomly generated according to constraints. When generating instructions randomly, first, the hardware and syntax rules of the instructions are determined, then the instructions are randomly generated from the smallest field, and finally, the instructions are spliced and verified to ensure that the instructions can be used for verification and have randomness and effectiveness.

[0036] Instructions are the smallest operation units that can be recognized and executed by computing cores, and are the interface bridge between software and hardware. The essence of instructions is binary encoding, which includes “operation type”, “operand address / value”, and “execution control information”. The core components of instructions include operation code, operand, and control field.

[0037] The operation code specifies the operation type of the instruction execution (such as addition, multiplication, memory read / write, branch jump). The operand specifies the object of the operation, which can be divided into: register operand (such as the general-purpose registers X0-X31 of the CPU, the SIMD registers R0-R255 of the GPU); immediate number (a constant directly embedded in the instruction, such as #10 in ADD W0, W0, #10); memory address (calculated through addressing mode, such as LDR W0, [X1, #8] indicating loading data from the memory address of X1+8). Control field, such as conditional execution bit, privilege level flag, exception suppression bit, etc.

[0038] When generating instructions randomly, the generation constraints and basic rules need to be determined in advance, such as: Extract hardware and instruction information: first, obtain the key configurations of the computing core (Core) to be tested, such as supported instruction types (such as FMA, ADD, atomic instructions, etc.), register model (GPR number, access permission, data type corresponding to register group), immediate number value range (such as INT32 immediate number -2^31~2^31 -1). At the same time, the core rules are determined, such as FP64 instructions only adapt to 64-bit registers, atomic instructions require memory address alignment, etc.

[0039] Define multiple constraint conditions: divide constraints according to the hierarchy of instructions, limit the value of each field at the field level (such as the operation code field only supports 0x0D corresponding to FMA.F32); at the instruction level, the instruction format is determined (such as the order of operation code + source register 1 + source register 2 + destination register); if subsequent instruction blocks need to be combined, the association constraints between instructions also need to be defined (such as whether resource dependency is allowed, whether exception scenarios need to be simulated).

[0040] Step-by-step generation of random instructions: random construction of fields to complete instructions. The essence of the instruction is to splice the fields such as operation code, register address, immediate number, etc. according to the fixed format, and the generation can be operated in the order of "field random generation → field compliant splicing", and the specific steps are as follows: Randomly generate instruction fields: For each field of the instruction, call the corresponding generation function to randomly take values within the constraint range. For example, when generating the operation code, according to the coding rules, a legal operation code is randomly selected, such as randomly selecting 0x0A for the ADD.I32 instruction; when generating the register field, a random address is selected from the register group supported by the computing core, such as selecting R10 as the source register 1 from R0-R255; when generating the immediate number, a value is randomly generated according to the data type, such as randomly generating the immediate number 123 for the ADD.I32 instruction. If you need to simulate abnormal scenarios, you can also deliberately generate some out-of-range fields (such as out-of-range register addresses).

[0041] Compliant splicing into complete instructions: According to the format rules corresponding to the instruction type, splice the randomly generated fields. For example, the format of the ADD.I32 instruction is "operation code + source register 1 + source register 2 + destination register", and if the generated fields are 0x0A, R10, 123, and R20 in turn, the instruction "ADD.I32 R20, R10,123" is obtained after splicing; then it is converted into a binary instruction code that can be recognized by Core, completing the construction of a single instruction.

[0042] Randomly spliced instructions may have implicit violations (such as individual compliance of fields but conflict after combination), which need to be additionally checked and filtered to avoid invalid instructions flowing into the verification link.

[0043] Perform compliance checks. Use pre-set constraint rules to traverse and check the instructions, such as judging whether the operand type and register of the instruction match (such as whether the FP32 instruction misuses integer registers) and whether the immediate number exceeds the support range of the current instruction. If there is a violation, discard it and generate it again.

[0044] Simple function pre-checking. The instruction can be input into a simple instruction simulator to quickly determine whether there is an obvious logical error (such as null pointer access, overflow caused by invalid results). For example, if the generated subtraction instruction is "SUB R5, R5,R5", although it is compliant, it is logically repetitive, and can be selected to be retained or regenerated according to the verification requirements.

[0045] The constraints of the instruction are essentially the limitations of hardware design, operation range, resource occupation, and coordination rules. These constraints determine what the instruction can do, what it cannot do, and what conditions must be met for correct execution, so the constraints of the instruction directly affect software compilation and hardware resource utilization.

[0046] The constraints of instructions generally need to comply with the following specifications: In terms of syntax and format, the instruction constraints comply with the following specifications: Opcode.

[0047] An opcode only corresponds to one fixed operation and cannot be customized (e.g., ADD can only do addition and cannot be used for memory access; TMA_LOAD can only trigger batch loading and cannot perform calculations). The operand type of the operation code is usually explicitly specified, such as FMA.F32 (32-bit floating-point multiplication and addition) only supports register operands (R0-R255) and cannot directly use memory addresses; the target register of LD.U8 (8-bit unsigned load) must be a "low 8-bit independently accessible" register (some GPU registers support byte-level operations, and some only support 32 / 64-bit aligned operations).

[0048] The number and range of operands.

[0049] Quantity constraint: The number of operands of most instructions is fixed (e.g., "3-operand instruction" ADDR1, R2, R3 in RISC architecture, which cannot transmit more / less operands).

[0050] Range constraint: Register operands can only be the relevant specified register group (e.g., the number of general-purpose registers GPR of a GPU is 65536 per SM, and warp threads share this resource, and a single thread can use up to 255 GPR). Immediate numbers have bit length restrictions (e.g., GPU instructions usually have 16-bit or 32-bit immediate numbers, and exceeding them requires reading from memory through "load instructions" and cannot be directly embedded). Memory address: must be an "aligned address" (e.g., 64-bit data load LD.E.64 address is aligned by 8 bytes, otherwise it triggers a hardware exception or performance degradation — unaligned addresses will be split into multiple memory transactions by hardware).

[0051] Fixed length of instructions.

[0052] Under the same relevant specification, the length of instructions is uniform (e.g., some instructions are 32 bits long, and some are 64 bits long), and cannot be dynamically adjusted. Short instructions cannot carry complex parameters (e.g., the transmission parameters of TMA instructions need to be stored in memory / registers through "descriptors", and the instruction only carries the descriptor address, not all parameters directly).

[0053] In hardware, the instruction constraints comply with the following specifications: The execution of instructions depends on the physical hardware units (ALU, register, TMA engine, etc.) of the chip, and the number and performance of these units directly limit the execution efficiency and parallelism of instructions: The number and type of functional units are constrained.

[0054] Instructions must be executed by corresponding hardware units, and the number of units is limited, for example: (1) Compute instructions (ADD / FMA) depend on CUDA Cores (ALU / FPU), and the number of CUDA Cores per SM is fixed (e.g., 128 FP32 Cores, 64 FP64 Cores per SM, etc.), and a Warp needs to queue for Cores when executing compute instructions; (2) Memory instructions (LD / ST) depend on LD / ST units (about 32 per SM), and TMA instructions depend on TMA engines (usually 1-2 per SM), and if multiple Warps simultaneously initiate TMA requests, arbitration of the TMA engine will be triggered, and some Warps need to wait.

[0055] The bandwidth and capacity of the register file (RF) are constrained.

[0056] Capacity constraint: the total number of registers per SM is fixed, and the total number of registers occupied by all threads in a Warp cannot exceed this upper limit (e.g., a SM has 65,536 32-bit GPRs, a Warp of 32 threads, if a single thread uses 2,048 GPRs, the total is 65,536, which is just full, at this time, no other Warp can be started); Bandwidth constraint: the read-write bandwidth of registers is limited, and if the instructions of the threads in a Warp simultaneously read and write a large number of registers (e.g., in “multi-instruction pipelining”, the previous instruction writes a register, and the next instruction reads the same register), a “register port conflict” may be triggered, causing instruction blocking.

[0057] The bandwidth / delay constraints of cache and memory.

[0058] Cache constraint: the capacity of the instruction cache (ICache) is limited (e.g., the ICache of each SM is 32KB), and if the instruction sequence is too long (e.g., a complex loop), the ICache hit rate will decrease, and the instruction fetching delay will increase; Memory bandwidth constraint: the transmission speed of memory instructions (LD / ST) and TMA instructions is limited by the memory bandwidth, and if multiple Warps simultaneously initiate high-bandwidth requests (e.g., loading GB-level data in batches), the bandwidth will be saturated, and the instruction execution delay will rise; Latency constraint: Inherent latency of memory access (e.g. global memory access latency is about 100-200ns), instructions need to wait for data return before continue execution (unless latency is hidden by “instruction reordering” or “TMA parallel with computation”).

[0059] In instruction verification, the following verification methods are commonly used: 1. Software simulation: Through instruction-level simulator, simulate the instruction execution process, no real hardware is needed, according to the relevant specification, decode, execute, result calculation logic of the instruction, at the same time, simulate the state change of hardware resources (registers, shared memory, TMA engine), output the instruction execution log (such as register value, memory data, module interaction timing). This method can quickly locate the instruction logic error, but it cannot simulate the hardware timing and performance.

[0060] 2. Formal verification: Through mathematical logic to prove that the execution behavior of the instruction conforms to the specification, covering all possible inputs (such as all legal operands, addresses, constraint parameters). Ensure that there is no blind angle verification. This method can find extreme scene errors that are difficult to cover by simulation, but the complexity is high, time-consuming, suitable for key logic verification of core instructions (such as TMA, FMA).

[0061] 3. Hardware measurement verification. Execute the instruction sequence on real GPU hardware, collect data through hardware counters and debugging tools, verify the function and performance of the instruction. In real scenarios, verify the impact on the normal work of the GPU, and cannot achieve large-scale batch verification.

[0062] 4. Random testing. Generate a large number of random instruction sequences (such as random register values, random TMA descriptors, random branch conditions). But in the scene where the number of instruction types or quantity is large, the format and constraint are complex, the efficiency of randomly generating an instruction is also low; And randomly generating instructions is easy to constantly randomize in a certain local position, while some positions are never randomly generated, which leads to the fact that some functions are repeatedly verified or some functions can never be verified, that is, the fairness of instruction verification cannot be guaranteed.

[0063] To address the aforementioned issues, this application proposes an instruction verification method. Before verifying the instruction, it first divides the instruction to be verified into a multi-layered instruction structure based on its function. Each layer corresponds to an instruction block, and different instruction blocks have their own functions. Then, a verification instruction block is randomly generated for each instruction block. Specifically, when randomly generating the verification instruction block, if there are no constraints between the instruction blocks, a verification instruction block is randomly generated for each instruction block simultaneously. If there are instruction blocks with constraints, the verification instruction blocks for the unconstrained instruction blocks are generated first, followed by the verification instruction blocks for the constrained instruction blocks. Finally, after randomly generating the verification instruction block for each instruction block, the verification instruction blocks are concatenated to obtain the verification instruction, which is then used to verify the instruction to be verified.

[0064] like Figure 2 The illustration shows an instruction verification method provided in an embodiment of this application, which specifically includes the following steps: Step 201: According to the preset multi-level instruction structure, divide the instruction to be verified into at least one instruction block corresponding to the multi-level instruction structure; the instruction to be verified is a composite instruction including multiple basic instructions; the multi-level instruction structure is used to characterize the basis for dividing the instruction block from the perspective of instruction function, and each instruction block has its own function.

[0065] In one optional implementation, the instruction to be verified is a compound instruction. A compound instruction is a high-level instruction capable of performing multiple low-level operations. It encapsulates a set of related basic instructions (such as load, compute, and store) into a single instruction, which can reduce code size and improve execution efficiency. A compound instruction is composed of multiple basic instructions combined in a specific order, completes a complex sequence of operations within a single instruction cycle, typically corresponds to an operation in a high-level language (such as matrix access), and can directly manipulate complex data structures (such as matrices) without requiring manual handling of low-level details.

[0066] This application's embodiments target composite instructions, dividing them into multi-layered instruction structures, with each layer corresponding to an instruction block. The multi-layered instruction structure is based on instruction function; therefore, each layer's instruction block has its own specific function.

[0067] In some embodiments, the multi-layer instruction structure includes an infrastructure layer, a formatting layer, and a resource management layer; the infrastructure layer represents an instruction block composed of basic instructions that are independent of the execution behavior of the instruction; the formatting layer represents an instruction block composed of basic instructions that are related to the execution behavior of the instruction; and the resource management layer represents an instruction block composed of basic instructions that are related to the resources required by the instruction.

[0068] An optional embodiment, the multi-layer instruction structure includes an infrastructure layer, a formatting layer, and a resource management layer. The infrastructure layer is basic instruction irrelevant to instruction execution behavior, generally parameters common to instructions, the formatting layer is basic instruction relevant to instruction execution behavior, and the structure is relatively complex; the resource management layer is generally resources required by the instruction, such as registers accessed by the instruction, memory addresses or coordinates, etc.

[0069] In some embodiments, the infrastructure layer includes one or more of instruction type, instruction code, and synchronization mode; the formatting layer includes one or more of data type, data size, and operand; and the resource management layer includes one or more of register and memory address.

[0070] The infrastructure layer can be some common and general parameters such as instruction type, instruction code, and synchronization mode. Among them, the instruction type can be an operation instruction, a memory instruction, a flow instruction, etc. The infrastructure layer is usually used to guide the generation of the instruction formatting layer and does not affect the actual execution behavior of the instruction.

[0071] The formatting layer will have different parameters according to different instruction types, which need to be carried by different classes. The formatting layer usually contains parameters strongly related to the instruction, such as source operand 1, source operand 2, and destination operand, data type, data size, etc. for an arithmetic addition instruction; and data size, storage type, level 1 cache access mode, level 2 cache access mode, etc. for a memory instruction.

[0072] For example, registers, memory addresses or coordinates, address alignment, etc. These information are also large bit width information, which can be calculated or constrained according to the result of the instruction formatting layer, so as to reduce the coupling with the information of the instruction formatting layer.

[0073] It should be understood that the above division of the multi-layer instruction structure into the infrastructure layer, the formatting layer, and the resource management layer is an optional embodiment provided by the embodiments of the present application, and is not used to limit the present application.

[0074] In some embodiments, the formatting layer includes a parameter meta-information layer and a hardware execution information layer; the parameter meta-information layer represents meta-information of an instruction execution object; and the hardware execution information layer represents basic information of hardware where the instruction is executed.

[0075] An optional embodiment, for complex instructions, the formatting layer can be further abstracted into a two-layer structure: a parameter meta-information layer and a hardware execution information layer. For example, a matrix memory instruction has a relatively complex instruction format, involves mathematical calculation, and involves key factors such as large bit width, which needs to be abstracted into a two-layer structure again: The first layer is a hardware execution information layer, because these are usually some large bit width information, if coupled with other information, it is not friendly to the simulator to be unbound.

[0076] The second layer is a parameter meta information layer, such as matrix data type, size, etc. The length and width information of the matrix and the information of the tile are subjected to mathematical operations, and the operation results are constrained.

[0077] Through the two-layer structure, the mathematical calculation and the problem of simulator unbinding efficiency and unfairness caused by the simultaneous occurrence of large bit width are simplified.

[0078] It should be understood that the above re-layering of the formatting layer into a parameter meta information layer and a hardware execution information layer is an optional implementation provided by the embodiments of the present application, and is not used to limit the present application.

[0079] Step 202, randomly generating a first verification instruction block based on a first instruction block, and generating a second verification instruction block based on the first verification instruction block and a second instruction block; wherein the first instruction block is an instruction block having no constraint relationship with other instruction blocks, and the second instruction block is constrained by the first instruction block.

[0080] An optional implementation is that after the instructions are divided into a multi-layer instruction structure, a plurality of instruction blocks are obtained. Some of the plurality of instruction blocks are not constrained by other instruction blocks, and some of the plurality of instruction blocks are constrained by other instruction blocks. The instruction block not constrained by other instruction blocks is taken as a first instruction block, and the instruction block constrained by other instruction blocks is taken as a second instruction block.

[0081] For the first instruction block, a first verification instruction block is randomly generated, and after the first verification instruction block is obtained, a second verification instruction block is generated according to the first verification instruction block and the second instruction block.

[0082] Taking the multi-layer instruction structure as an infrastructure layer, a formatting layer and a resource management layer as an example, the infrastructure layer is a basic instruction irrelevant to the execution behavior of the instruction, so the infrastructure layer is a first instruction block, not constrained by other instruction blocks, and starts randomly first. The formatting layer constrains the resource management layer, so the formatting layer and the resource management layer are second instruction blocks, and the resource management layer is constrained by the formatting layer, so after the verification instruction block of the formatting layer is randomly generated, the verification instruction block of the resource management layer is randomly generated.

[0083] Step 203, obtaining a verification instruction based on each verification instruction block corresponding to at least one instruction block.

[0084] Step 204, verifying the to-be-verified instruction through the verification instruction.

[0085] An optional embodiment splices multiple verification instruction blocks to obtain a verification instruction, and uses the verification instruction to verify the to-be-verified instruction. In the verification of the to-be-verified instruction using the verification instruction, a random test manner can be adopted.

[0086] Optionally, if there is no constraint relationship between the instructions. First, the to-be-verified instruction is divided into multiple instruction structures in the above manner to obtain an instruction block corresponding to each instruction structure. Then, each instruction block is randomly generated in parallel to obtain a verification instruction block corresponding to each instruction block. Optionally, if there is a constraint relationship between the instructions. First, the to-be-verified instruction is divided into multiple instruction structures in the above manner to obtain an instruction block corresponding to each instruction structure. Then, the instruction blocks without constraint relationship are randomly generated first, and the instruction blocks with constraint relationship are randomly generated first for the instruction blocks without constraint relationship and then for the instruction blocks with constraint relationship, so as to obtain a verification instruction block corresponding to each instruction block.

[0087] Finally, each verification instruction block is spliced to obtain a verification instruction, which is run on a corresponding hardware device according to the format requirement of the to-be-verified instruction, and whether the to-be-verified instruction is legal is judged according to the running result. For example, in an addition instruction "c=a+b", "int a=3, int b=5" are randomly generated. If the running result is "8", the to-be-verified instruction "c=a+b" is legal; if the running result is an error, the to-be-verified instruction "c=a+b" is an illegal instruction.

[0088] In some embodiments, the random generation of the verification instruction block corresponding to each of the at least one instruction block includes: for each first instruction block without constraint relationship, the first verification instruction block corresponding thereto is randomly generated in parallel.

[0089] An optional embodiment, since the first instruction block is not constrained by other instruction blocks, the first instruction block can randomly generate the verification instruction block corresponding thereto in parallel. For example, the infrastructure layer and the formatting layer can randomly generate the verification instruction block corresponding thereto at the same time.

[0090] In some embodiments, after obtaining the at least one instruction block corresponding to the multiple instruction structures and before randomly generating the first verification instruction block corresponding thereto in parallel, as shown in Figure 3 , it further includes: Step 301: The at least one instruction block and the random generation manner are summarized into a verification instruction code set.

[0091] An optional embodiment, after dividing the instruction to be verified into a multi-layer instruction structure, a plurality of instruction blocks are obtained, and according to the random generation mode implemented on each instruction block, the verification instruction code set is obtained by aggregating each instruction block. For example, after dividing the instruction to be verified into an infrastructure layer, a formatting layer and a resource management layer, instruction blocks corresponding to the instruction structure are obtained respectively.

[0092] Step 302, by verifying the instruction code set, the verification instruction block corresponding to each instruction block in at least one instruction block is randomly generated.

[0093] An optional embodiment, according to the verification instruction code set, the verification instruction block of each instruction block in each instruction block is randomly generated. For example, in the verification instruction code set, the corresponding verification instruction block is generated according to the infrastructure layer code block, the corresponding verification instruction block is generated according to the formatting layer code block, and the corresponding verification instruction block is generated according to the resource management layer code block. The verification code block of the resource management layer is generated after the verification code block of the formatting layer.

[0094] In order to facilitate the understanding of the scheme, the specific operation steps of the embodiments of the application are explained below in a specific application scenario. Since the matrix access instruction format is relatively complex and involves mathematical calculation and large bit width and other key factors, the instruction to be verified is taken as a matrix access instruction as an example for description. The following is the verification instruction code set of the matrix access instruction: Class BasicInfo; Rand bit[2:0] op_type; Rand bit[2:0] opcode; Rand bit[2:0] sync_mode; …. Some constraint Endclass Class TileInfo; Rand int w; Rand int c; Rand int stride_w; … some constraint Endclass Class MatrixOpFmt; Rand bit[2:0] data_type; Rand bit[2:0] row; Rand bit[2:0] col; Rand bit[2:0] ns; Rand bit[2:0] data_size; TileInfo u_tileinfo; …. Some constraint; Endclass Class MatrixaddrInfo; Rand bit[2:0] alignment; Rand bit[2:0] coord_x; Rand bit[2:0] coord_y; TileInfo u_tileinfo; MatrixOpFmt u_matrix_op; … some constraint endclass Class Opfmt; BasicInfo u_basicinfo TileInfo u_tileinfo; MatrixOpFmt u_matrixop; MatrixaddrInfo u_matrix_addr; Function void pre_randomize(); U_basicinfo.randomize(); U_tileinfo.randomize(); U_matrixop.u_tileinfo = u_tileinfo U_matrixop.randomize(); U_matrix_addr.u_tileinfo = u_tileinfo; U_matrix_addr.u_matrix_op = u_matrixop; U_matrix_addr.randomize(); endfunction endclass The above code is a verification instruction code set in the embodiment of the present application, and the to-be-verified instruction is split into multiple classes. Class BasicInfo is a basic infrastructure layer of the matrix access instruction, which is class A, including instruction type (op_type), operation code (opcode), and synchronization mode (sync_mode). Class TileInfo is a hardware execution information layer in the formatting layer of the matrix access instruction, which is class B. Class MatrixOpFmt is a parameter meta-information layer in the formatting layer, which is class C, including data type (data_type) of the matrix, number of rows (row) of the matrix, and number of columns (col) of the matrix. In the matrix operation, a large matrix is split into a fixed-size sub-matrix by Tile, and the information of Tile is a core parameter set for describing "how to split, locate, and load / store the sub-matrix" in the matrix access instruction. Therefore, Tile is split into a class. Class MatrixaddrInfo is a resource management layer of the matrix access instruction, which is class D, such as address alignment (alignment), address coordinates (coord_x / coord_y), and the like. Class Opfmt is class E of the instruction, and the above classes are instantiated in class E. In class E, A->B->C->D are randomized according to a randomized order. Since C class needs to rely on the randomization result of B class when being randomized, the randomization result of B class needs to be obtained before C class is randomized. Similarly, D class needs the randomization results of B class and C class. The information of A / B / C / D classes is packaged into a complete instruction and placed in class E.

[0095] Function void pre_randomize() is used to randomly generate the above instruction block, and the above instruction block is randomly generated in the following manner: U_basicinfo.randomize() is used to randomly generate the basic infrastructure layer; U_tileinfo.randomize() is used to randomly generate the hardware execution information layer in the formatting layer; U_matrixop.u_tileinfo = u_tileinfo, U_matrixop.randomize() is used to randomly generate the parameter meta-information layer in the formatting layer; U_matrix_addr.u_tileinfo = u_tileinfo, U_matrix_addr.u_matrix_op = u_matrixop, U_matrix_addr.randomize() is used to randomly generate the resource management layer.

[0096] In the embodiments of the present application, by dividing the to-be-verified instruction according to the preset instruction structure, the instruction block corresponding to each layer of instruction structure is obtained, the functions of each part in the instruction can be clearly understood, and when the instruction is randomized, the divided instruction block can be randomized, so that the fairness of instruction randomization is improved; the random order between the instruction blocks is determined according to the constraint relationship between the instruction blocks, so that the instruction block after being constrained is randomized first, and the instruction block not being constrained is randomized first, the error of the generated random instruction caused by the constraint problem is avoided, and the efficiency of instruction randomization is improved.

[0097] Based on the same technical concept, the embodiments of the present application provide an instruction verification device 400, as shown in the following table, comprising: Figure 4 The division module 401 is configured to divide the to-be-verified instruction according to a preset multi-layer instruction structure, and obtain at least one instruction block corresponding to the multi-layer instruction structure; the to-be-verified instruction is a composite instruction comprising a plurality of basic instructions; the multi-layer instruction structure is used to represent the basis for dividing the instruction block from the perspective of instruction function, and each instruction block has its own function; The generation module 402 is configured to randomly generate a first verification instruction block based on a first instruction block, and generate a second verification instruction block based on the first verification instruction block and a second instruction block; wherein the first instruction block is an instruction block having no constraint relationship with other instruction blocks, and the second instruction block is constrained by the first instruction block; The verification module 403 is configured to obtain a verification instruction based on each verification instruction block corresponding to the at least one instruction block; the verification instruction is used to verify the to-be-verified instruction.

[0098] Optionally, the multi-layer instruction structure comprises an infrastructure layer, a formatting layer and a resource management layer; The infrastructure layer represents an instruction block composed of basic instructions irrelevant to the execution behavior of the instruction; The formatting layer represents an instruction block composed of basic instructions related to the execution behavior of the instruction; The resource management layer represents an instruction block composed of basic instructions related to the resources required by the instruction.

[0099] Optionally, the formatting layer comprises a parameter meta-information layer and a hardware execution information layer; The parameter meta-information layer represents the meta-information of the instruction execution object; The hardware execution information layer represents the basic information of the hardware where the instruction is executed.

[0100] Optionally, the generation module 402 is specifically configured to: ​For each first instruction block without constraint relationship, a corresponding first verification instruction block is randomly generated in parallel.

[0101] Optionally, the generating module is further configured to: aggregate the at least one instruction block and the random generation manner into a verification instruction code set; Optionally, the generating module 402 is specifically configured to: randomly generate, through the verification instruction code set, a verification instruction block corresponding to each of the at least one instruction block.

[0102] Optionally, the infrastructure layer includes one or more of an instruction type, an instruction code, and a synchronization manner. The formatting layer includes one or more of a data type, a data size, and an operand. The resource management layer includes one or more of a register and a memory access address.

[0103] Based on the same technical concept, the embodiments of the present application provide a computer device, as shown in the accompanying drawings, which includes at least one artificial intelligence chip 100 and a memory 104 connected to the at least one artificial intelligence chip 100. Figure 5 In the embodiments of the present application, the specific connection medium between the artificial intelligence chip 100 and the memory 104 is not limited, Figure 5 for example, the artificial intelligence chip 100 and the memory 104 are connected through a bus. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0104] In the embodiments of the present application, the memory 104 stores instructions executable by the at least one artificial intelligence chip 100, and the at least one artificial intelligence chip 100 can execute the steps of the execution method of the instruction verification by executing the instructions stored in the memory 104.

[0105] The artificial intelligence chip 100 is the control center of the computer device and can connect various parts of the computer device through various interfaces and lines, and implement the execution of instruction verification by running or executing instructions stored in the memory 104 and calling data stored in the memory 104. Optionally, the artificial intelligence chip 100 can include one or more processing units, and the artificial intelligence chip 100 can integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, the user interface and the application program, etc., and the modem processor mainly processes wireless communication. It can be understood that the above-mentioned modem processor can also not be integrated into the artificial intelligence chip 100. In some embodiments, the artificial intelligence chip 100 and the memory 104 can be implemented on the same chip, and in some embodiments, they can also be implemented on separate chips respectively.

[0106] The artificial intelligence chip 100 can be a general processor, such as a digital signal processor, an application specific integrated circuit (ASIC), a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as execution completed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0107] The memory 104 is a non-volatile computer readable storage medium, which can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 104 can include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card type memory, random access memory (RAM), static random access memory (SRAM), programmable read only memory (PROM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), magnetic memory, magnetic disk, optical disk, etc. The memory 104 is any other medium capable of carrying or storing desired program code in the form of instructions or data structures and capable of being accessed by a computer device, but is not limited thereto. The memory 104 in the embodiments of the present application can also be a circuit or any other device capable of realizing a storage function, used for storing program instructions and / or data.

[0108] Based on the same inventive concept, the embodiments of the present application provide a computer readable storage medium storing a computer program executable by a computer device, which, when executed on the computer device, causes the computer device to perform the steps of the instruction verification method.

[0109] Based on the same inventive concept, the embodiments of the present application provide a computer program product, which includes a computer program stored on a computer readable storage medium, and the computer program includes program instructions, which, when executed by a computer device, cause the computer device to perform the steps of the instruction verification method.

[0110] Those skilled in the art will appreciate that embodiments of the present application can be readily used as software, hardware, or a combination of software and hardware. In a software embodiment, the methods can be tangibly embodied in a machine-readable storage medium having stored thereon instructions that can be used to program a processing machine (or multiple machines) to perform the methods. The term "storage medium" as used herein shall accordingly include one or both of material storage and carrier waves with the types of storage media that are mentioned above. The software can be implemented using any high level, high speed

[0111] The present application is described in reference to the drawings using a flowchart and / or a block diagram of the method, apparatus (system) and computer program product according to embodiments of the application. It will be understood that each block of the flowchart and / or block diagram, and combinations of blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processing machine, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0112] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0113] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0114] While preferred embodiments of the application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims shall be construed to include all such embodiments and modifications as falling within the scope of the present application.

[0115] Obviously, many modifications and variations of the present application are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. An instruction verification method, characterized by, The method comprises the following steps: According to a preset multi-layer instruction structure, the to-be-verified instruction is divided to obtain at least one instruction block corresponding to the multi-layer instruction structure; The to-be-verified instruction is a composite instruction comprising a plurality of basic instructions; the multi-layer instruction structure is used to represent the basis for dividing the instruction block from the perspective of instruction function, and each instruction block has its own function; A first verification instruction block is randomly generated based on a first instruction block, and a second verification instruction block is generated based on the first verification instruction block and a second instruction block; wherein the first instruction block is an instruction block having no constraint relationship with other instruction blocks, and the second instruction block is constrained by the first instruction block; Verification instructions are obtained based on the respective verification instruction blocks corresponding to the at least one instruction block; The to-be-verified instruction is verified through the verification instructions.

2. The method of claim 1, wherein, The method comprises the following steps: The multi-layer instruction structure comprises an infrastructure layer, a formatting layer and a resource management layer; The infrastructure layer represents an instruction block composed of basic instructions irrelevant to the execution behavior of the instruction; The formatting layer represents an instruction block composed of basic instructions related to the execution behavior of the instruction; The resource management layer represents an instruction block composed of basic instructions related to the resources required by the instruction.

3. The method of claim 2, wherein, The method comprises the following steps: The formatting layer comprises a parameter meta-information layer and a hardware execution information layer; The parameter meta-information layer represents the meta-information of the instruction execution object; The hardware execution information layer represents the basic information of the hardware where the instruction is executed.

4. The method according to any one of claims 1 to 3, characterized in that, The method comprises the following steps: For each first instruction block having no constraint relationship, a corresponding first verification instruction block is randomly generated in parallel.

5. The method of claim 4, wherein, After the at least one instruction block corresponding to the multi-layer instruction structure is obtained, and before the corresponding first verification instruction block is randomly generated in parallel, the method further comprises the following steps: The at least one instruction block and the random generation mode are summarized as a verification instruction code set; Randomly generating the verification instruction block corresponding to each instruction block in the at least one instruction block comprises the following steps: Randomly generating the verification instruction block corresponding to each instruction block in the at least one instruction block through the verification instruction code set.

6. The method of any one of claims 2-3, wherein, The infrastructure layer comprises one or more of instruction type, instruction code and synchronization mode; The formatting layer comprises one or more of data type, data size and operand; The resource management layer comprises one or more of register and memory access address.

7. An instruction verification apparatus characterized by comprising: The method comprises the following steps: A division module is configured to divide the to-be-verified instruction according to a preset multi-layer instruction structure to obtain at least one instruction block corresponding to the multi-layer instruction structure; The to-be-verified instruction is a composite instruction comprising a plurality of basic instructions; the multi-layer instruction structure is used to represent the basis for dividing the instruction block from the perspective of instruction function, and each instruction block has its own function; A generation module is configured to randomly generate a first verification instruction block based on a first instruction block, and generate a second verification instruction block based on the first verification instruction block and a second instruction block; wherein the first instruction block is an instruction block having no constraint relationship with other instruction blocks, and the second instruction block is constrained by the first instruction block; A verification module is configured to obtain verification instructions based on the respective verification instruction blocks corresponding to the at least one instruction block. The verification module is further configured to verify the to-be-verified instruction by the verification instruction.

8. A computer device comprising a memory, an artificial intelligence chip, and a computer program stored on the memory and running on the artificial intelligence chip, characterized in that, The artificial intelligence chip implements the steps of the method of any one of claims 1-6 when executing the computer program.

9. A computer-readable storage medium, characterized in that, The computer program product comprises a computer program stored in a computer readable storage medium, and the computer program comprises program instructions, which, when executed by a computer device, cause the computer device to perform the steps of the method of any one of claims 1-6.

10. A computer program product, characterised in that, The computer program product comprises a computer program stored in a computer readable storage medium, and the computer program comprises program instructions, which, when executed by a computer device, cause the computer device to perform the steps of the method of any one of claims 1-6.

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