Chip layout correction method based on double graphic process and related equipment

Abstract

The invention belongs to the technical field of semiconductor design automation, and provides a chip layout correction method based on a dual graphic process and related equipment. The method comprises the steps that a to-be-processed chip layout is acquired, graph pairs with conflicts are determined in a target metal layer of the chip layout, and the target metal layer is a metal layer to be applied to a double-graph process; constructing a conflict graph in the target metal layer by taking the graphs in the graph pair as nodes and the conflict relationship between the graphs as connecting edges, and detecting odd rings in the conflict graph; if an odd ring is detected in the conflict graph, dividing the target metal layer into a plurality of correction areas; and resolving the odd rings in the plurality of correction areas in parallel, and returning to execute the step of determining the graph pairs with conflicts in the target metal layer of the chip layout until no odd ring exists in the constructed conflict graph. Through the technical scheme provided by the invention, the correction efficiency of the chip layout can be improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor design automation, and particularly relates to a chip layout correction method based on double patterning technology and a related device. BACKGROUND

[0002] In the field of semiconductor chip manufacturing, with the continuous improvement of chip integration and the continuous reduction of transistor feature size, the traditional photolithography process has been difficult to meet the demand of high-precision pattern preparation. As a key technology to break through the resolution limit of photolithography, double patterning technology effectively reduces the pattern spacing and improves the precision and density of pattern preparation by dividing the target metal layer of the chip layout into two sub-metal layers for photolithography and etching, and has become one of the core technologies in advanced process chip manufacturing.

[0003] In the practical application of double patterning technology, the metal layer of the chip layout needs to meet strict process rule requirements, and the pattern spacing is a key factor affecting the process feasibility and yield. If the spacing of adjacent patterns does not meet the process rule, it will cause pattern distortion, bridging and other defects in the photolithography process, which seriously affects the performance and reliability of the chip. Therefore, before applying double patterning technology, the chip layout must be corrected to ensure the feasibility of the divided layout and ensure that all patterns meet the process rule requirements, and the correction efficiency of the chip layout directly determines the research and development cycle and manufacturing cost of the chip. SUMMARY

[0004] Embodiments of the present application provide a chip layout correction method based on double patterning technology, device, computer program product, computer readable storage medium and electronic equipment, which can improve the correction efficiency of the chip layout to a certain extent.

[0005] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0006] According to a first aspect of the embodiments of the present application, a chip layout correction method based on double patterning technology is provided, the method comprising: obtaining a chip layout to be processed, and determining a pair of conflicting patterns in a target metal layer of the chip layout, the target metal layer being a metal layer to be applied to double patterning technology; taking patterns in the pair of conflicting patterns as nodes and a conflict relationship between the patterns as a connection edge, constructing a conflict graph in the target metal layer, and detecting an odd ring in the conflict graph, the odd ring being a closed loop formed by an odd number of patterns through connection edges; if an odd ring is detected in the conflict graph, dividing the target metal layer into a plurality of correction regions; and parallelly eliminating the odd rings in the plurality of correction regions, and returning to execute the step of determining a pair of conflicting patterns in the target metal layer of the chip layout until there is no odd ring in the constructed conflict graph.

[0007] In some embodiments of the present application, based on the foregoing scheme, the determining of the pair of conflicting patterns in the target metal layer of the chip layout comprises: obtaining a process rule spacing of the target metal layer, the process rule spacing being a minimum pattern spacing satisfying a process production condition; and determining any adjacent patterns in the target metal layer as the pair of conflicting patterns if an actual spacing of the any adjacent patterns is less than a set multiple of the process rule spacing.

[0008] In some embodiments of the present application, based on the foregoing scheme, the determining of the pair of conflicting patterns in the target metal layer of the chip layout comprises: obtaining a process rule spacing of the target metal layer, and a factor weight of the target metal layer on a plurality of process risk factors, the process rule spacing being a minimum pattern spacing satisfying a process production condition; calculating a conflict risk value of any adjacent patterns in the target metal layer under double pattern process by a conflict quantification model based on the process rule spacing, the factor weight, and an actual spacing of the any adjacent patterns; and determining the any adjacent patterns as the pair of conflicting patterns if the conflict risk value is greater than a set risk value.

[0009] In some embodiments of the present application, based on the foregoing scheme, the conflict quantification model comprises: wherein, represents the conflict risk value of the any adjacent patterns under double pattern process; represents a process rule spacing set for the target metal layer, being a constant; represents a factor weight of a lithography risk, being a constant; represents a factor weight of a pattern type, being a constant; represents an actual spacing of the any adjacent patterns in the target metal layer, being a variable.

[0010] In some embodiments of the present application, based on the foregoing scheme, the detecting of the odd ring in the conflict graph comprises: calling a graph theory loop extraction algorithm to traverse each closed loop in the conflict graph, and counting a node number of the each closed loop; and determining a closed loop with an odd node number as the odd ring.

[0011] In some embodiments of the present application, based on the foregoing scheme, the dividing the target metal layer into multiple correction regions comprises: dividing the target metal layer into multiple first regions with similar number of odd loops, and the number of odd loops in each first region is less than a set number; dividing each first region into at least two second regions with similar size, and defining the second regions as the correction regions.

[0012] In some embodiments of the present application, based on the foregoing scheme, the dividing the target metal layer into multiple first regions with similar number of odd loops comprises: sequentially traversing the grid regions in the target metal layer in a set traversal order; whenever a current grid region is traversed, counting the total number of odd loops of the grid regions that have been traversed, and if the total number of odd loops exceeds a set number, marking the grid regions that have been traversed before the current grid region as a first region, and resetting the grid regions that have been traversed and the total number of odd loops; taking the current grid region as the first grid region that has not been traversed, and repeating the traversal process of the grid regions until all grid regions are traversed.

[0013] In some embodiments of the present application, based on the foregoing scheme, the eliminating the odd loops in the correction regions comprises: determining at least one target connection edge to be repaired in the correction regions; performing shift processing and / or cutting processing on one of the graphs associated with each target connection edge to eliminate the odd loop to which the each target connection edge belongs.

[0014] In some embodiments of the present application, based on the foregoing scheme, the determining at least one target connection edge to be repaired in the correction regions comprises: traversing each connection edge in the correction regions, and recording the correspondence between each connection edge and the odd loop to which the each connection edge belongs in a temporary table; in the temporary table, counting the connection edge with the largest number of odd loops as the target connection edge to be repaired; hiding the odd loop to which the target connection edge belongs in the temporary table, and returning to the step of counting the connection edge with the largest number of odd loops in the temporary table until all odd loops recorded in the temporary table are hidden.

[0015] In some embodiments of the present application, based on the foregoing scheme, the method further comprises: if the connection edge with the largest number of odd loops counted in the temporary table includes multiple connection edges, obtaining the actual distance between the adjacent graphs associated with each of the multiple connection edges; and determining the connection edge corresponding to the adjacent graphs with the largest actual distance as the target connection edge.

[0016] According to a second aspect of the embodiments of the present application, a chip layout correction device based on a double patterning process is provided, the device comprising: an obtaining unit configured to obtain a chip layout to be processed, and determine a pair of conflicting patterns in a target metal layer of the chip layout, the target metal layer being a metal layer to be applied to the double patterning process; a detecting unit configured to construct a conflict graph in the target metal layer by taking the patterns in the pair of conflicting patterns as nodes and the conflict relationship between the patterns as connecting edges, and detect an odd cycle in the conflict graph, the odd cycle being a closed loop formed by odd-numbered patterns through connecting edges in sequence; a dividing unit configured to divide the target metal layer into a plurality of correction regions if there is an odd cycle in the conflict graph; and a resolving unit configured to resolve the odd cycles in the plurality of correction regions in parallel, and return to perform the step of determining a pair of conflicting patterns in the target metal layer of the chip layout until there is no odd cycle in the conflict graph.

[0017] According to a third aspect of the embodiments of the present application, a computer program product is provided, the computer program product comprising computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform operations to implement the operations performed by the method according to the first aspect.

[0018] According to a fourth aspect of the embodiments of the present application, a computer readable storage medium is provided, the computer readable storage medium storing at least one computer program instruction, the at least one computer program instruction being loaded and executed by a processor to implement the operations performed by the method according to the first aspect.

[0019] According to a fifth aspect of the embodiments of the present application, an electronic device is provided, the electronic device comprising one or more processors and one or more memories, the one or more memories storing at least one computer program instruction, the at least one computer program instruction being loaded and executed by the one or more processors to implement the operations performed by the method according to the first aspect.

[0020] Based on the technical scheme provided in the present application, through the complete process of constructing a conflict graph, detecting odd cycles, partitioning and parallel resolving, and cyclic iteration, the orderliness and integrity of the chip layout modification process can be guaranteed. Among them, the partitioning and parallel processing mode can fully exert the parallel computing capability of modern computing devices, and can decompose the modification task of a large-scale layout into multiple sub-tasks to be promoted synchronously, compared with the traditional overall serial processing mode, the data processing amount and the modification time can be greatly reduced, the rapid modification demand of a large-scale chip layout can be met, and the modification efficiency of the chip layout is improved. In addition, the odd cycle detection carried out by the present application relying on the conflict graph can accurately locate the object to be modified, provide a clear target for subsequent resolution operation, reduce invalid operation, and enhance the stability and reliability of the modification. After each odd cycle resolution, the conflict detection is carried out again, new conflicts and new odd cycles generated in the resolution process can be found and processed in time, potential problems are avoided, and the reliability of the chip layout modification is significantly improved, and the final chip layout completely meets the process rule requirement.

[0021] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0022] The drawings herein are incorporated into the specification and form part of the specification, show embodiments consistent with the present application, and together with the specification serve to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained from these drawings without creative labor for those skilled in the art. In the drawings: Figure 1 A flowchart of a chip layout modification method based on a double patterning process in an embodiment of the present application is shown; Figure 2 A schematic diagram of a target metal layer in a chip layout in an embodiment of the present application is shown; Figure 3 A schematic diagram of a target metal layer in a chip layout in an embodiment of the present application is shown; Figure 4 A schematic diagram of a target metal layer in a chip layout in an embodiment of the present application is shown; Figure 5 A block diagram of a chip layout modification device based on a double patterning process in an embodiment of the present application is shown; Figure 6 A structural schematic diagram of an electronic device in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] With reference to the drawings, the technical solutions in the embodiments of the present application will be clearly and completely described, obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work belong to the protection scope of the present application.

[0024] In addition, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to give a full understanding of the embodiments of the present application. However, one skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be used. In other cases, well-known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0025] The block diagrams shown in the drawings are only functional entities, which do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. It should be noted that in the drawings, in order to ensure the simplicity of the drawings, some components in the drawings are omitted, which do not affect the explanation of the technical solutions of the present application.

[0026] The flowcharts shown in the drawings are only exemplary illustrations, which do not necessarily include all contents and operations / steps, and are not necessarily executed in the described order. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order can be changed according to the actual situation.

[0027] In the description of the present application, it should be understood that the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, unless otherwise specified, the meaning of "multiple" is two or more.

[0028] In order for those skilled in the art to better understand the present application, first, the technical concepts and application background related to the present application are briefly described.

[0029] Integrated Circuit (IC): Integrated Circuit, also known as microchip or chip, refers to a microelectronic device with specific circuit functions, which is formed by concentrating a large number of transistors, diodes, resistors, capacitors, inductors and interconnections between these components on one or more semiconductor wafers (which can be silicon wafers), insulating substrates and other carriers through semiconductor manufacturing processes (such as photolithography, etching, doping, deposition, etc.), and packaging in an outer shell.

[0030] Chip Layout (CL): Chip Layout, also known as chip physical layout, is a core intermediate carrier in the transition from logic design to physical manufacturing in the semiconductor chip design process, which converts the logic function and circuit structure of the chip into a two-dimensional / three-dimensional graphical description file that meets the requirements of semiconductor process manufacturing, and is also the direct basis for chip manufacturing and packaging testing.

[0031] Double Patterning Technology (DPT): Double Patterning Technology is a core process technology developed in the field of semiconductor chip manufacturing to break through the resolution limit of traditional photolithography, i.e. Deep Ultraviolet Lithography (DUV), and meet the high-precision pattern preparation needs of advanced process chips. Its core logic is to divide the complex high-density patterns of the same metal layer (such as metal wiring layer, dielectric layer, etc.) in the chip layout into two independent sub-metal layers (sub-layouts), and then through two independent photolithography and etching processes, the two sub-metal layers are transferred to the wafer surface, and finally the high-precision, small-pitch target pattern that cannot be realized by single photolithography is formed by superposition.

[0032] The applicant finds that in the prior art, after the metal layer wiring is completed, the odd ring resolution efficiency is low, and as the size of the chip layout expands, the number of odd rings increases and the distribution is complex. The traditional correction method adopts a whole processing method to resolve the odd ring, which leads to excessive data processing and long correction period in the correction process, and cannot meet the rapid correction needs of large-scale chip layout, and in the odd ring resolution process, the prior art randomly selects the connection edge to be resolved, which leads to the need for multiple repeated resolution operations, increasing the complexity of the correction process, greatly affecting the correction efficiency of the chip layout, and at the same time, the unreasonable connection edge processing may cause excessive deformation of the pattern, affecting the original design function of the chip layout, further reducing the overall correction efficiency. In this case, the present application proposes a chip layout correction scheme based on double patterning technology to improve the correction efficiency of the chip layout.

[0033] The implementation details of the technical solutions of the embodiments of the present application are described below: Referring toFigure 1 FIG. 1 shows a flowchart of a chip layout modification method based on a double patterning process in an embodiment of the present application, which can be executed by a device with computing processing function. Referring to FIG. 1, the chip layout modification method based on a double patterning process comprises at least steps 110-140, which are described in detail as follows: Figure 1 FIG. 1 shows a flowchart of a chip layout modification method based on a double patterning process in an embodiment of the present application, which can be executed by a device with computing processing function. Referring to FIG. 1, the chip layout modification method based on a double patterning process comprises at least steps 110-140, which are described in detail as follows: FIG. 1 shows a flowchart of a chip layout modification method based on a double patterning process in an embodiment of the present application, which can be executed by a device with computing processing function. Referring to FIG. 1, the chip layout modification method based on a double patterning process comprises at least steps 110-140, which are described in detail as follows: Figure 1 In step 110, a chip layout to be processed is obtained, and a pair of conflicting patterns in a target metal layer of the chip layout is determined, wherein the target metal layer is a metal layer to be applied to a double patterning process.

[0034] In actual chip manufacturing process, the target metal layer is a key layer for realizing specific electrical functions of the chip, such as a metal wiring layer for realizing signal connection between transistors in a 12 nm process logic chip. Determining the pair of conflicting patterns is the basis for subsequent modification work, and the core purpose is to accurately identify the pattern combination that may cause lithography defects.

[0035] In an embodiment of the present application, the determination of the pair of conflicting patterns in the target metal layer of the chip layout can be performed according to the following steps 111-112: In step 111, a process rule spacing of the target metal layer is obtained, wherein the process rule spacing is the minimum pattern spacing that meets the process production conditions.

[0036] In step 112, if the actual spacing of any adjacent patterns in the target metal layer is less than a set multiple of the process rule spacing, the any adjacent patterns are determined as the pair of conflicting patterns.

[0037] In the present application, the process rule spacing is the minimum pattern spacing that meets the process production conditions. Specifically, the process rule spacing is a key parameter determined by chip manufacturing process, and the process rule spacing varies for different processes and different metal layers. For example, the process rule spacing of a 14 nm process metal layer can be 50 nm, while the process rule spacing of a 7 nm process metal layer can be reduced to 30 nm. This parameter can be determined by chip manufacturers according to their lithography equipment performance, etching process level and other factors. Further, if the actual spacing of any adjacent patterns in the target metal layer is less than a set multiple of the process rule spacing, the any adjacent patterns are determined as the pair of conflicting patterns. Wherein, In the embodiment, the set multiple is a flexible adjustable parameter, and the value of the set multiple needs to comprehensively consider factors such as process stability and precision redundancy of the photolithography equipment. The set multiple can be set to be between 1-1.5, for example, for a mature process with high manufacturing process stability, the set multiple can be set to 1.1. For an advanced process with high process difficulty, the set multiple can be set to 1.5. The core logic of the determination mode of the conflict pattern pair can be that when the actual spacing of the adjacent patterns is less than the set multiple of the process rule spacing, the risk of pattern distortion, bridge connection and other defects in the photolithography process is significantly increased, and therefore the conflict pattern pair needs to be determined and corrected subsequently.

[0038] Based on the technical solutions of steps 111-112, only two parameters, the process rule spacing and the actual spacing of the adjacent patterns, need to be obtained, and the conflict determination can be completed through simple multiplication and size comparison operations, without complex model calculation, so that the calculation amount is small, the implementation difficulty and the calculation complexity of the algorithm are reduced, the algorithm is convenient to integrate into various chip layout design verification tools, large-scale chip layout data can be quickly processed, and the conflict screening of all adjacent patterns can be completed in a short time, so that time is saved for subsequent odd ring detection and elimination, and the overall layout correction efficiency is improved. The determination mode has high flexibility and practicability, and the adjustability of the set multiple enables the determination mode to adapt to chip layout correction requirements of different manufacturing processes, equipment conditions, processes and reliability requirements. The set multiple can be low in mature processes to improve the correction efficiency, and the set multiple can be high in advanced processes to improve the manufacturing reliability. When the process level is improved and the precision of the photolithography equipment is improved, the set multiple can be appropriately reduced to reduce unnecessary correction operations. When the process stability is insufficient, the set multiple can be increased to ensure that all potential conflict risks can be identified. In addition, the determination result has high reliability. The process rule spacing is the minimum safe spacing determined based on the actual production conditions, the introduction of the set multiple reserves a certain redundancy space for process execution, can accurately identify the explicit conflict caused by too small spacing, effectively avoids manufacturing defects such as photolithography distortion and bridge connection caused by small process fluctuations, layout measurement errors and the explicit conflict, ensures the basic manufacturing feasibility of the chip, and improves the yield of chip manufacturing.

[0039] In another embodiment of the present application, the determination of the conflict pattern pair existing in the target metal layer of the chip layout can also be performed according to steps 113-115 as follows: Step 113: obtaining a process rule spacing of the target metal layer and factor weights of the target metal layer on a plurality of process risk factors, the process rule spacing being a minimum pattern spacing meeting process production conditions.

[0040] Step 114, based on the process rule spacing, the factor weight, and the actual spacing of any adjacent patterns in the target metal layer, the conflict risk value of the any adjacent patterns under the double patterning process is calculated by a conflict quantification model.

[0041] Step 115, if the conflict risk value is greater than a set risk value, the any adjacent patterns are determined as a conflict pattern pair.

[0042] In the embodiment, another more accurate conflict pattern pair determination method is provided, which comprehensively considers the process rule spacing and multiple process risk factors, and realizes accurate identification of conflict pattern pairs through quantitative calculation.

[0043] Specifically, in the embodiment, in addition to the basic parameter of process rule spacing, multiple process risk factors are introduced, which are key factors affecting the quality of lithography and the feasibility of the process. For example, it can include a lithography risk factor and a pattern type factor. Among them, the lithography risk factor reflects the risk degree of pattern distortion caused by factors such as equipment precision and light intensity uniformity in the lithography process. The pattern type factor is related to the geometric shape, size ratio and the like of the pattern. For example, the lithography difficulty of an elongated pattern is usually higher than that of a rectangular pattern, and the lithography difficulty of a metal line pattern is usually higher than that of a metal via pattern. The factor weight is a quantitative representation of the importance of each process risk factor, and its value range can be between 0-1. The greater the weight value, the greater the impact of the factor on the conflict risk. The determination of the factor weight needs to be based on a large amount of process experimental data and statistical analysis, such as studying the influence degree of different factors on the lithography defect rate by orthogonal experiment method, and then determining the reasonable weight distribution.

[0044] In the embodiment, the conflict quantification model is the core of the embodiment scheme, which can associate the process rule spacing, the factor weight, and the actual spacing and other parameters with the conflict risk value through a mathematical formula, and can realize quantitative evaluation of the conflict risk. The design of the model can fully consider the internal logical relationship between the parameters, and can comprehensively and objectively reflect the actual conflict risk of the pattern pair.

[0045] In the embodiment, the set risk value is a critical value for distinguishing whether there is an actual conflict risk of the pattern pair, and its determination needs to consider factors such as the performance requirements, manufacturing costs, and yield targets of the chip. For example, for a chip with high performance and high reliability requirements, the set risk value can be set to a lower level (such as between -0.001 and 0.001) to strictly control the conflict risk. For a chip with low performance and low reliability requirements, the set risk value can be appropriately increased (such as between 0.001 and 0.1) to reduce the subsequent layout modification cost on the premise of ensuring basic performance.

[0046] In the embodiment, after the conflict risk value of any adjacent pattern under the double pattern process is calculated, the calculated conflict risk value is compared with the set risk value. If the conflict risk value is greater than the set risk value, it indicates that the adjacent pattern has a higher actual conflict risk in the manufacturing process, and is determined as a pattern pair with conflict.

[0047] Based on the technical solutions of steps 113 to 115, the process rule spacing, multiple key process risk factors, and actual spacing and other factors can be comprehensively considered. The process risk factors and spacing parameters are organically combined through the quantitative model, which can more comprehensively and objectively evaluate the actual conflict risk of the pattern pair, effectively avoid the missed judgment of potential conflicts and the misjudgment of patterns without actual risk, for example, for a pattern pair with an actual spacing slightly greater than the set multiple of the process rule spacing but a higher lithography risk, the conflict risk value after model calculation may exceed the set threshold and be accurately determined as a conflict pattern pair. For a pattern pair with a smaller actual spacing but a simple pattern type and a very low lithography risk, the conflict risk value may be lower than the set threshold, thereby avoiding unnecessary modification operations. The determination method is suitable for complex process scenarios, introduces multiple process risk factors and their weights, can fully consider the influence of various factors on manufacturing conflicts, and is consistent with the characteristics of complex process risks in advanced processes, improving the pertinence and effectiveness of conflict determination. It is flexible, and the factor weight and the set risk value can be flexibly adjusted and individually configured according to different process requirements, chip types, performance targets, and reliability requirements, etc. The lithography risk factor weight can be increased and the determination standard can be strictly determined in a high-risk advanced process with a higher lithography process difficulty, or the set risk value can be appropriately increased and the standard can be relaxed in a low-risk scene with a higher cost control requirement, balancing the modification efficiency and manufacturing reliability. At the same time, accurate conflict determination can clearly determine the modification object, provide a more reliable basis for subsequent conflict graph construction and odd ring detection, avoid confusion in the modification process caused by false conflicts or missed conflicts, reduce the complexity of the modification process, ensure that the modification resources are concentrated for processing pattern pairs with real risks, improve the overall modification efficiency, and the calculation result of the conflict risk value can also provide data support for chip manufacturing process optimization. By analyzing the conflict risk value distribution of different pattern pairs, the weak links in the process can be identified, and the lithography process parameters or pattern design rules can be optimized, thereby fundamentally reducing the conflict risk.

[0048] Specifically, in the embodiment, the conflict quantification model can be as shown in formula (1): (1) wherein, represents the conflict risk value of the arbitrary adjacent pattern under the double pattern process; represents the process rule spacing set for the target metal layer, which is a constant; a factor weight representing a lithography risk, is a quantitative value; a factor weight representing a pattern type, is a quantitative value; is a variable value representing an actual spacing of any adjacent patterns in the target metal layer.

[0049] In the present application, for the above conflict quantification model, can comprehensively reflect the process rule requirements and the comprehensive requirements of various risk factors on the pattern spacing, and can be regarded as an equivalent safety spacing considering the risk factors; The difference between the equivalent safety spacing and the actual spacing is converted by an exponential function, and then 1 is subtracted to obtain the conflict risk value. When is less than the equivalent safety spacing, the difference is positive, the result of the exponential function is greater than 1, is greater than 0, and the greater the difference is, the greater the conflict risk is; when is greater than or equal to the equivalent safety spacing, the difference is negative or zero, the result of the exponential function is less than or equal to 1, is less than or equal to 0, indicating that the conflict risk is low or there is no conflict risk.

[0050] In the present application, in order for those skilled in the art to better understand the conflict quantification model shown in formula (1) above, the following will be described in combination with several specific embodiments: In an embodiment of the present application, assuming that a logic chip of a 7nm process, the process rule spacing of the target metal layer is According to the lithography process conditions of the chip, the lithography risk factor weight is determined, since the patterns of the layer are mainly regular rectangles, the pattern type factor weight is determined. The actual spacing of adjacent patterns N and O is , which is substituted into the model for calculation: If the risk value is set to 0, then is much greater than the set risk value, and it can be determined that the patterns N and O are a conflict pattern pair.

[0051] In an embodiment of the present application, assuming that a radio frequency chip of a 14nm process, the target metal layer , the lithography equipment precision is relatively high, , the patterns are all regular squares, . The actual spacing of adjacent patterns R and S is , which is substituted into the model for calculation: If the risk value is set to 0, then If the conflict risk value is less than the set risk value, it can be determined that the patterns R and S do not constitute a conflict pair.

[0052] As can be seen from the above examples, the greater the factor weight of the process risk factor, the greater the equivalent safety distance calculated, and the higher the conflict risk value under the same actual distance.

[0053] Based on the above conflict quantification model, the process rule distance and the two process risk factor weights are nonlinearly fused by an exponential function, which can sensitively reflect the comprehensive influence of each factor. Compared with the linear model, it is more in line with the law of risk accumulation in actual manufacturing. At the same time, the process rule distance, multiple process risk factors and actual distance are organically combined. Abstract conflict risk is converted into specific numerical value, so that conflict judgment is upgraded from qualitative judgment to quantitative analysis, which greatly improves the scientificity and accuracy of conflict judgment. In addition, the characteristics of the exponential function also enable the model to respond significantly to changes in the comprehensive risk coefficient. Even a small change in the process risk factor weight or the actual distance can be reflected in the conflict risk value, effectively distinguishing different degrees of conflict risk, and further improving the accuracy and sensitivity of risk assessment.

[0054] The calculation process of the above conflict quantification model is relatively simple, only involving basic four arithmetic operations and exponential operation, without complex matrix operation or iterative solution, and the calculation complexity is moderate. While ensuring the evaluation accuracy, it can quickly process large-scale chip layout data to meet the rapid calculation demand, and will not affect the overall correction efficiency due to excessive calculation amount. The conflict risk value calculated by the model can objectively and quantitatively reflect the conflict risk of adjacent pattern pairs, providing a scientific and unified standard for conflict pattern pair judgment, avoiding the uncertainty brought by subjective judgment. At the same time, by analyzing the influence of each parameter in the model on the risk value, it can also provide data support for the optimization of chip manufacturing process and the improvement of pattern design rules, and evaluate the influence effect of different process improvement measures on conflict risk, providing guidance for process optimization direction.

[0055] With reference to Figure 1 In step 120, a conflict graph is constructed in the target metal layer with the patterns in the pattern pair as nodes and the conflict relationship between the patterns as connecting edges, and an odd cycle is detected in the conflict graph. The odd cycle is a closed loop formed by an odd number of patterns through connecting edges.

[0056] In the present application, the odd ring is a closed loop formed by an odd number of patterns through connection edges. The conflict graph is a visualized abstraction of the conflict relationship between patterns, and each node represents an independent pattern. The existence of the connection edge indicates that there is a process conflict risk between the two patterns. The detection of the odd ring is a key link of the correction work, because this kind of closed loop composed of an odd number of patterns cannot meet the process requirements through the conventional double pattern segmentation method, and must be processed through a special correction means.

[0057] In the present application, the detection of the odd ring in the conflict graph can be performed according to the following steps 121 to 122: Step 121, calling a graph theory loop extraction algorithm to traverse each closed loop in the conflict graph, and counting the number of nodes of each closed loop.

[0058] Step 122, determining the closed loop with an odd number of nodes as an odd ring.

[0059] In the present application, the graph theory loop extraction algorithm is a kind of algorithm specially used to identify the closed loop in the pattern, and the common ones include the depth-first search (DFS) algorithm, the breadth-first search (BFS) algorithm, etc. In the present application, a suitable algorithm can be selected according to the size and complexity of the conflict graph. For example, for a conflict graph with small size and relatively simple structure, the BFS algorithm can be used, which has the advantages of fast traversal speed and low memory occupation; for a conflict graph with large size and complex loop structure, the DFS algorithm can be used, which is more advantageous in the integrity of loop identification. In the traversal process, the algorithm starts from an arbitrary node of the conflict graph, and successively visits other nodes along the connection edges. When returning to the starting node again, a closed loop is formed. At the same time, the number of nodes contained in each loop is recorded in the traversal process, which provides a basis for the subsequent odd ring judgment.

[0060] Further, the closed loop with an odd number of nodes can be determined as an odd ring. The core feature of the odd ring is a closed loop formed by an odd number of nodes (patterns) through connection edges (conflict relationships), which is the fundamental reason why the odd ring cannot meet the process requirements through the conventional double pattern segmentation method. By counting the number of nodes of each closed loop, the odd ring can be quickly and accurately screened out, and the target of the subsequent elimination operation is clear.

[0061] In order to enable those skilled in the art to better understand the above steps 121 to 122, the following will be described in combination with Figure 2 with a specific embodiment.

[0062] Referring to Figure 2 , a schematic diagram of a target metal layer in a chip layout in an embodiment of the present application is shown. As shown in Figure 2In the target metal layer shown, assume that the conflict risk values of each adjacent pattern are as shown in Table 1.

[0063] Table 1: Example table of conflict risk values of adjacent patterns In this embodiment, assume that the risk value is set to 0, then based on Table 1, it can be determined that the pattern pairs in the target metal layer 200 that have conflicts are: A-B, A-F, A-G, A-H, B-C, B-H, C-D, D-E, D-G, E-F, and E-G.

[0064] Further, in the conflict graph, the patterns in the conflict pattern pairs are nodes, and the conflict relationship between the patterns is a connecting edge. Then, a graph theory loop extraction algorithm is called to traverse each closed loop in the conflict graph, and the number of nodes in each closed loop is counted. The closed loop with an odd number of nodes is determined as an odd loop, such as Figure 2 As shown, the determined odd loops specifically include: Odd loop 1: A-B-H-A; Odd loop 2: A-B-C-D-G-A; Odd loop 3: A-B-C-D-G-E-F-A; Odd loop 4: A-H-B-C-D-E-F-A; Odd loop 5: D-E-G-D; Odd loop 6: D-E-F-A-G-D.

[0065] Based on the technical solutions of steps 121 to 122, the odd loop detection work is carried out based on the graph theory loop extraction algorithm, which can systematically and comprehensively traverse all closed loops in the conflict graph, accurately count the number of nodes in each loop, and filter out the odd loop, so as to effectively avoid the omission or misjudgment problems that are prone to occur in manual detection or simple logical judgment, guarantee the accuracy of the odd loop detection result, and provide a precise target for subsequent odd loop resolution. For conflict graphs of different sizes and complexities, this kind of graph theory loop extraction algorithm can select appropriate algorithms such as depth-first search and breadth-first search. For large-scale conflict graphs, pruning parallel traversal and other optimization strategies can be combined to introduce a marked array queue management method to improve traversal speed and reduce repeated calculations, so that the detection can be completed within a reasonable time and meet the efficiency requirements of large-scale chip layout modification. In addition, this method can also clearly indicate the nodes and connecting edges included in each odd loop, providing clear target information for subsequent modification region division and target connecting edge selection, and can clearly indicate the key objects for subsequent modification, avoid waste of modification resources, and improve the pertinence and effectiveness of subsequent modification operations and the efficiency of the overall modification process.

[0066] Continuing to refer to Figure 1In step 130, if a loop is detected in the conflict graph, the target metal layer is divided into multiple correction regions.

[0067] In the present application, reasonable region division is a prerequisite for parallel processing. By dividing a large-scale target metal layer into multiple independent correction regions, the computing resources of multi-thread and multi-processor can be fully utilized, and the efficiency bottleneck caused by overall processing can be avoided.

[0068] In the present application, the division of the target metal layer into multiple correction regions can be performed according to the following steps 131 to 132: Step 131, the target metal layer is divided into multiple first regions with similar number of loops, and the number of loops in each first region is less than a set number.

[0069] Step 132, each first region is divided into at least two second regions with similar size, and the second regions are defined as the correction regions.

[0070] In the present application, the set number is a critical value determined according to the computing power of the computing device, the correction efficiency target and other factors, for example, set to 35-45. The core purpose of this step is to relatively uniformly distribute loops in each first region, avoid too concentrated loops in a region, and cause too large correction difficulty. At the same time, it is ensured that the number of loops in each first region is within a controllable range, which lays a foundation for subsequent subdivision and parallel processing. In the division process, the distribution position, adjacent relationship and other factors of the loop are considered to ensure that the division of the first region does not damage the integrity of the loop, and to facilitate subsequent processing.

[0071] Further, each first region can be divided into at least two second regions with similar size, and the second regions are defined as the correction regions. The purpose of this step is to further reduce the number of loops to be processed by a single thread, and to realize the uniformity of the size of the correction region, so that the number of graphs and the area size of each correction region are relatively consistent, so that the correction workload of each region is equivalent when parallel processing, avoiding the situation that some regions are still processed for a long time after the correction of other regions is completed, and fully exerting the efficiency advantage of parallel processing.

[0072] In order for those skilled in the art to better understand the above steps 131 to 132, the following will be described with reference to a specific embodiment. Figure 3

[0073] Referring to Figure 3 , a schematic diagram of a target metal layer in a chip layout in an embodiment of the present application is shown.

[0074] As Figure 3 ​As shown, the metal layer pattern 300 of a certain double patterning process contains 120 odd rings, and the number of odd rings in each first region is set to be no more than 45. The layout is divided into three first regions FR1, FR2 and FR3 by a region division algorithm, and the number of odd rings in each region is 42, 41 and 37 respectively. Then, the first regions FR1, FR2 and FR3 are divided into second regions FR1-1 and FR1-2, second regions FR2-1 and FR2-2, and second regions FR3-1 and FR3-2 respectively as correction regions, and the number of odd rings in each correction region is between 18 and 22, and the region sizes are similar, which provides a basis for parallel elimination.

[0075] Based on the technical solutions of steps 121 to 122, the two-stage division method lays a good foundation for parallel processing. The first-stage division divides the target metal layer into multiple first regions with similar number of odd rings and each first region having a number of odd rings less than the set number, achieving balanced distribution of odd rings, avoiding the problem of excessive concentration of odd rings in a single region leading to excessive correction difficulty of the single region, and ensuring the correction workload of each region within a controllable range, reducing the overall correction difficulty. The second-stage division divides each first region into second regions with similar sizes, i.e., final correction regions, making the number of patterns in each correction region relatively consistent, ensuring that the correction time of each region is similar and the load of each processing unit is balanced during subsequent parallel processing. Multiple correction regions can be allocated to different processing units for parallel elimination, greatly improving the overall efficiency of odd ring elimination and avoiding the problem of low parallel efficiency caused by excessive difference in region size or number of odd rings, thereby greatly shortening the overall correction period. At the same time, this balanced region division also improves the utilization rate of correction resources, avoids the situation where some regions have insufficient correction resources while others have idle resources, maximizes the efficiency of hardware processing resources, and makes the correction difficulty of each correction region relatively balanced, avoiding the problems of correction failure or excessive pattern deformation caused by excessive correction difficulty of a certain region, improving the stability and reliability of the overall correction process. In addition, the logic of this division method is clear and the operation is simple, and the two-stage division has clear goals and steps, with the first stage focusing on balanced distribution of odd rings and the second stage focusing on balanced region size, making the operation process easy to implement and control. Moreover, the division parameters such as the set number and the number of second regions can be flexibly adjusted according to actual conditions, which can adapt to various chip layouts from small to large scales, and has strong versatility and flexibility.

[0076] In the above step 131, the target metal layer can be divided into multiple first regions with similar number of odd rings according to the following steps 1311 to 1312: Step 1311: According to a set traversal order, the grid regions that have not been traversed are traversed in the target metal layer in sequence.

[0077] Step 1312, whenever the current grid region is traversed, the total number of odd loops of the grid regions accumulated in the traversal is counted, and if the total number of odd loops exceeds a set number, the grid regions accumulated in the traversal before the current grid region are marked as a first region, and the grid regions accumulated in the traversal and the total number of odd loops are reset.

[0078] Step 1313, the current grid region is taken as the first grid region not traversed, and the grid region traversal process is repeated until all grid regions are traversed.

[0079] In the present application, the target metal layer is divided into multiple uniform grid regions according to a preset grid size. The setting of the grid size needs to consider the area, pattern density and odd loop distribution of the target metal layer. For example, for a target metal layer with a large area and high pattern density, the grid size can be set to 50 μm x 50 μm; for a target metal layer with a small area and low pattern density, the grid size can be set to 100 μm x 100 μm. The traversal order can be row priority traversal from left to right and from top to bottom, or column priority traversal from top to bottom and from left to right. When selecting the traversal order, it is necessary to ensure that all grid regions can be fully and orderly covered to avoid omission.

[0080] In the traversal process, the number of odd loops in each grid region is added to the total number of odd loops when the grid region is traversed. When the total number of odd loops exceeds a set number, it indicates that the number of odd loops contained in the currently accumulated grid regions has reached a reasonable range, and these grid regions need to be divided into an independent first region. Then, the list of grid regions accumulated in the traversal and the total number of odd loops are reset, and the accumulation is restarted from the current grid region to ensure that the subsequent divided first regions also meet the odd loop number requirement. After that, the current grid region can be taken as the first grid region not traversed, and the grid region traversal process is repeated until all grid regions are traversed. This step can ensure that all grid regions can be orderly divided into various first regions, avoiding the omission of grid regions. For the grid regions traversed in the last part, if the accumulated number of odd loops does not exceed the set number, they are still marked as an independent first region to ensure that all odd loops can be contained in the first region.

[0081] For example, in a specific embodiment, the target metal layer is divided into a grid area of 100 μm x 100 μm, and the number of odd loops in each first area is set to be no more than 40, and the traversal order is from left to right and from top to bottom. After starting traversal, the grid areas (1, 1), (1, 2), (1, 3), (1, 4), and (1, 5) are traversed in turn, and the total number of odd loops of the grid areas traversed is 38, which does not exceed the set number 40. The grid area (1, 6) is continuously traversed, and the total number of odd loops is 42, which exceeds the set number 40. At this time, the grid areas (1, 1) to (1, 5) are marked as the first area 1, and the grid areas traversed and the total number of odd loops are reset. Then, the grid area (1, 6) is taken as the first grid area not traversed, and the grid areas (1, 7) and (1, 8) are continuously traversed, and the above-mentioned statistical and marking process is repeated. When the grid area (5, 10) is traversed, the cumulative number of odd loops reaches 40, and the corresponding cumulative grid area is marked as the first area n. The remaining grid areas are continuously traversed until all 100 grid areas are traversed, and finally the target metal layer is divided into a plurality of first areas with similar number of odd loops.

[0082] Based on the technical solutions of steps 1311 to 1313, the division work is carried out in a grid traversal manner, which can be operated according to the preset traversal order and rules, so that the division process has good order and standard, and can effectively avoid the problems of chaotic region boundaries caused by uneven distribution of odd loops in manual division or simple random division. The method can automatically complete the division of the first area by setting the traversal order and the statistical rule, without manual intervention, and has high automation degree, which reduces the operation complexity and improves the division efficiency. In the division process, the method can accurately control the number of odd loops in each first area and ensure that the number of odd loops in each first area does not exceed the set number and the overall distribution is similar, avoiding the problems of too concentrated or too sparse odd loops in some areas, realizing the balance of odd loop distribution, reducing the correction difficulty of a single area, and being able to flexibly select the traversal order to adapt to chip layouts of different shapes and odd loops of different distribution densities, ensuring the comprehensiveness and rationality of the division process.

[0083] In addition, the grid traversal manner can quickly cover the entire target metal layer, and the cumulative calculation process of the number of odd loops is simple and efficient, without complex analysis and judgment, so that the division efficiency is high, the first region division can be quickly completed, the efficiency requirement of large-scale chip layout correction is met, and the steps of the method are clear and explicit. The setting of the traversal order of the grid region and the statistics of the number of odd loops are easy to program and implement, and the operability is strong, so that the method can be quickly integrated into the chip layout correction tool. The process of the division method is based on clear rules and steps, and the same result can be obtained by dividing the same target metal layer each time. The division result has good consistency and repeatability, provides a stable foundation for subsequent correction operations, and based on the grid region division, the boundary of the first region is clear and regular. The uniform first region division also provides a good foundation for the second-level region division, so that the second-level division can more easily achieve the balance of region size, further guarantee the efficiency of parallel processing, and ensure the rationality and efficiency of the entire correction region division.

[0084] With reference to the foregoing Figure 1 In step 140, the odd loops in the plurality of correction regions are parallelly resolved, and the step of determining the pair of conflicting patterns existing in the target metal layer of the chip layout is returned to be executed until there is no odd loop in the constructed conflict graph.

[0085] In the present application, parallel resolution can greatly shorten the correction time, and the process of cyclic iteration ensures that all potential odd loop conflicts can be completely eliminated, and finally the chip layout meeting the process rule requirement is obtained.

[0086] In the present application, specifically, the odd loops in the correction region can be resolved according to the following steps 141 to 142: Step 141, determining at least one target connection edge to be repaired in the correction region.

[0087] Step 142, performing displacement processing and / or cutting processing on one of the patterns associated with each target connection edge to resolve the odd loop to which each target connection edge belongs.

[0088] In the present application, the core of odd loop resolution is to break the closed structure of the odd loop by processing the patterns associated with the target connection edge, so as to eliminate the odd loop. First, the target connection edge to be resolved can be determined in the correction region. The target connection edge refers to the connection edge that plays a key role in odd loop resolution, which can be the connection edge that belongs to multiple odd loops and can resolve multiple odd loops by a single processing. Determining the target connection edge is a key link of odd loop resolution, and the core purpose is to resolve the most odd loops by processing the least connection edges, improve the correction efficiency, and reduce the pattern deformation.

[0089] Further, a shift processing and / or a cutting processing can be performed on one of the graphs associated with each target connection edge. The shift processing refers to moving the graphs in a certain direction (e.g., horizontal direction, vertical direction) by a certain distance, increasing or adjusting the spacing between the graphs, and eliminating the conflict relationship. The cutting processing refers to cutting the edges of the graphs, reducing the size of the graphs, and thus increasing the spacing between the adjacent graphs, and eliminating the conflict relationship. According to the shape, position and conflict of the graphs, the shift processing, the cutting processing or the combination of the two processing modes can be selected. For example, for the graphs with a large adjustable space, the shift processing can be used; for the graphs with limited adjustable space but with redundant size, the cutting processing can be used; for the serious conflict, the shift and cutting processing can be used to achieve better resolution.

[0090] In order to make the person skilled in the art better understand the above steps 141 to 142, the following will be described in combination with Figure 4 a specific embodiment.

[0091] Referring to Figure 4 , a schematic diagram of a target metal layer in a chip layout in an embodiment of the present application is shown.

[0092] As shown in Figure 4 , in the target metal layer 400, a graph I, a graph J and a graph K form an odd ring. For example Figure 4 , as shown in subgraph (a), by cutting the graph K, the odd ring is eliminated, and a target metal layer as shown in subgraph (b) of Figure 4 is obtained. For example Figure 4 , as shown in subgraph (c), by shifting the graph K, the odd ring is eliminated, and a target metal layer as shown in subgraph (d) of Figure 4 is obtained. For example Figure 4 , as shown in subgraph (e), by cutting and shifting the graph K, the odd ring is eliminated, and a target metal layer as shown in subgraph (f) of Figure 4 is obtained.

[0093] Based on the technical solutions in steps 141 to 142, the closed structure of the odd cycle can be directly broken by determining the target connection edge and processing the graph associated with the target connection edge. The method provides three processing modes of displacement cutting and combination, and can select a suitable processing mode according to the actual situation of the graph, that is, the shape, size, periphery layout and other specific conditions of the graph. The method can adapt to graphs of different shapes, positions and conflict degrees, adapt to the elimination needs of different types of odd cycles, and improve the adaptability and effectiveness of odd cycle elimination. In the graph processing layer, the displacement processing and cutting processing are both local and small adjustments of the graph, and the processing process is only performed on a single graph associated with the target connection edge. The processing range and degree can be accurately controlled. Compared with the way of overall graph reconstruction or simultaneous adjustment of multiple graphs, the original design features and size ratio of the graph can be maximally retained, the degree of graph deformation is further reduced, the influence of graph deformation on chip performance is reduced, and the original design function of the graph is retained. The determination of the target connection edge and the selection of the processing mode of the elimination method are based on clear logic and rules. In the processing process, the processing direction, distance and range can also be reasonably selected according to the layout of the surrounding graph, avoiding the uncertainty brought by random processing, effectively avoiding new conflicts or graph function failure caused by improper processing, reducing the risk of new conflict, and ensuring the controllability and stability of the elimination process, improving the stability and reliability of the correction.

[0094] In step 141, the at least one target connection edge to be repaired in the correction area can be determined according to steps 1411 to 1413 as follows: Step 1411: Traverse each connection edge in the correction area, and record the corresponding relationship between each connection edge and the odd cycle to which the connection edge belongs in a temporary table.

[0095] Step 1412: In the temporary table, count the connection edge with the most odd cycles as the target connection edge to be repaired.

[0096] Step 1413: In the temporary table, hide the odd cycle to which the target connection edge belongs, and return to step 1412 until all the odd cycles recorded in the temporary table are hidden.

[0097] In this application, first, each connection edge in the correction area can be traversed, and the corresponding relationship between each connection edge and its odd ring is recorded in a temporary table, which is a data structure for storing connection edge and odd ring association information, and its fields can include connection edge identifier, odd ring identifier list, etc. For example, the odd ring identifier list of connection edge A-B is odd ring 1 and odd ring 3, which means that connection edge AB belongs to odd ring 1 and odd ring 3 at the same time. Each connection edge is checked one by one during the traversal process to determine all the odd rings it belongs to, and the related information is recorded accurately and no association between any connection edge and odd ring is missed.

[0098] Next, the connection edge with the most number of odd rings is counted in the temporary table, and it is taken as the target connection edge to be repaired. The number of odd rings is a key indicator to measure the importance of the connection edge. The more the number is, the greater the influence of the connection edge on the odd ring resolution. Processing such connection edge can resolve multiple odd rings at the same time, so it needs to be determined as the target connection edge first. When counting the number of odd rings to which each connection edge belongs, the connection edge with the most number of odd rings is filtered out. If there are multiple connection edges with the same number of odd rings and the number is the most, these connection edges can be listed as candidate target connection edges first, and the final target connection edge can be determined through further rule filtering.

[0099] Finally, the odd rings to which the selected target connection edge belongs are hidden in the temporary table. Hiding the odd ring means removing the corresponding odd ring from the odd ring list in the temporary table, so that it no longer participates in the subsequent statistics of the number of odd rings to which the connection edge belongs. This is because the odd ring to which the target connection edge belongs will be resolved after the target connection edge is processed, and there is no need to consider other connection edges corresponding to these odd rings. Then return to execute the step of counting the connection edge with the most number of odd rings in the temporary table. Through iterative execution of the selection and hiding process, the connection edge that plays a key role in the resolution of the remaining odd rings is continuously filtered out, until all the odd rings recorded in the temporary table are hidden, that is, all the odd rings can be resolved by processing the selected target connection edge.

[0100] In order to make those skilled in the art better understand the above steps 1411 to 1413, the following will continue to combine the above Figure 2 A specific embodiment is described.

[0101] As Figure 2 shown, the correction area 200 includes: Odd ring 1: A-B-H-A; Odd ring 2: A-B-C-D-G-A; Odd ring 3: A-B-C-D-G-E-F-A; Odd ring 4: A-H-B-C-D-E-F-A; Odd ring 5: D-E-G-D; Odd ring 6: D-E-F-A-G-D.

[0102] The correspondence between each connection edge in the correction region 200 and the odd ring to which it belongs is recorded in a temporary table, as shown in Table 2 below: Table 2: Correspondence between connection edges and the odd rings to which they belong According to the above step logic, based on the temporary table as shown in Table 2, it can be determined that the connection edges D-G and B-H can be determined as target connection edges to be resolved, or the connection edges D-G and A-H can be determined as target connection edges to be resolved.

[0103] Based on the technical solutions of steps 1411 to 1413 described above, by counting the number of odd rings to which the connection edges belong, the connection edges that play a key role in the resolution of odd rings, especially those that belong to multiple odd rings, can be processed, and after processing, multiple odd rings can be resolved at the same time. The resolution efficiency is higher than that of the traditional overall adjustment method, and the resolution is more targeted, which can reduce the number of resolution operations and improve the efficiency of odd ring resolution. The efficient odd ring resolution method reduces the number of resolution operations and the amplitude of the graph adjustment, reduces the complexity of the correction process, saves time for subsequent cycle iteration correction, and helps to shorten the correction cycle of the overall chip layout.

[0104] The method can continuously filter out connection edges that play a key role in the remaining odd rings by iteratively performing the steps of statistical selection and hiding, ensuring that all odd rings can be covered, and ultimately resolving all odd rings by processing the selected target connection edges. This avoids missing odd rings, and the logic of prioritizing the processing of key connection edges can reduce the number of resolution operations and the number of subsequent cycle iterations, avoid repeated resolution and invalid operations caused by random selection of connection edges, not only reduce the complexity of the overall correction process, but also reduce the risk of accumulated graph distortion and new conflict caused by multiple operations.

[0105] The process of selecting target connection edges of the method has good operability and repeatability. The statistical and screening process based on the temporary table has clear steps and rules, is easy to operate and is not affected by human factors. The same target connection edge selection results can be obtained every time the same correction region is processed, ensuring the repeatability and stability of the selection process. The steps are clear, and the construction of the temporary table, the counting of the number of odd rings, and the selection of target connection edges are easy to program and implement, which can be quickly integrated into an automated correction tool to realize the automated processing of odd ring resolution.

[0106] In addition, the determined target connection edge explicitly indicates the conflict relationship that needs to be processed, provides a clear target for subsequent displacement and cutting processing, and improves the pertinence and effectiveness of subsequent processing. Meanwhile, by selecting the target connection edge in a targeted manner, the influence on non-key connection edges and patterns can be minimized while ensuring the resolution of odd loops, thereby protecting the original design function and manufacturing precision of the chip layout.

[0107] In step 141 of the above embodiment, the following steps 1414 and 1415 can also be performed: In step 1414, if the connection edge with the largest number of odd loops in the temporary table includes multiple connection edges, the actual distance between the adjacent patterns associated with each of the multiple connection edges is obtained.

[0108] In step 1415, the connection edge corresponding to the adjacent patterns with the largest actual distance is determined as the target connection edge.

[0109] In the present application, when the connection edge with the largest number of odd loops in the temporary table includes multiple connection edges, the actual distance between the adjacent patterns associated with each of the multiple connection edges is first obtained. The actual distance between the adjacent patterns associated with the connection edge refers to the actual distance between the two patterns corresponding to the connection edge. This parameter can be directly obtained from the chip layout data by a layout measurement tool, and is an important indicator reflecting the conflict degree between patterns.

[0110] Then, the connection edge corresponding to the adjacent patterns with the largest actual distance is determined as the target connection edge. The logical basis for selecting the connection edge with the largest actual distance as the target connection edge is that the larger the actual distance of a pattern pair, the lower the conflict risk. By slightly displacing or cutting one of the patterns, the conflict relationship can be eliminated, and the degree of pattern deformation is smaller. On the other hand, for a pattern pair with a small actual distance, the conflict risk is high, and a large amount of pattern adjustment may be required to eliminate the conflict, which can easily lead to excessive pattern deformation. Therefore, by preferentially selecting the connection edge with the largest actual distance as the target connection edge, the odd loop can be resolved while minimizing pattern deformation and ensuring the original design function of the chip layout. At the same time, it is also less likely to cause new conflicts with surrounding patterns.

[0111] For example, based on the above embodiment, the actual distance between pattern B and pattern H associated with connection edge B-H is 45 nm, and the actual distance between pattern A and pattern H associated with connection edge A-H is 48 nm. Therefore, connection edges D-G and A-H can be selected as the final target connection edges to be resolved.

[0112] Based on the technical solutions of steps 1414 to 1415, the target connection edge selection can be further optimized and rationality of the selection can be improved. In the case that the number of odd cycles to which the multiple connection edges belong is the same, the actual spacing is introduced as a supplementary screening standard, the actual spacing of the connection edge associated graph is compared, and the connection edge with the maximum spacing is selected as the target connection edge. It can be ensured that the graph pair corresponding to the selected connection edge has relatively low conflict risk, and the required graph adjustment range is smaller. The adjustment range of the correction process to the graph can be minimized, thereby minimizing the graph deformation and ensuring the original design features and original design functions of the chip layout. At the same time, the graph pair with a larger actual spacing only needs to be adjusted slightly to eliminate the conflict relationship. When performing the shifting or cutting process, the required adjustment amount is small, and it is not easy to cause new overlap or too small spacing with the surrounding graph. This can avoid problems such as excessive graph deformation and function failure caused by large adjustment of the graph pair with a small actual spacing, reduce the probability of new conflicts, improve the safety and reliability of the correction process, and further improve the reliability of the odd cycle resolution.

[0113] The screening scheme is simple, clear, and easy to implement. The actual spacing of the connection edge associated graph is only needed to be obtained and compared to determine the final target connection edge. No complex calculation or analysis is required. The screening process is simple and efficient, and is easy to integrate into the overall correction process. The target connection edge selected by the screening scheme can resolve the odd cycle while minimizing the graph deformation. The minimized graph adjustment can maximize the original layout and dimensional accuracy of the chip layout, balance the correction efficiency and correction quality, ensure the performance and reliability of the final chip layout, and ensure that the corrected chip layout meets the manufacturing requirements of the double graph process, thereby ensuring the manufacturing precision and performance of the chip. In addition, the screening scheme provides a clear solution for the case of multiple candidate connection edges, avoids the uncertainty caused by random selection, makes the selection process of the target connection edge more perfect, enhances the adaptability and flexibility of the overall correction method, and makes the selection of the target connection edge more scientific and accurate.

[0114] The device embodiments of the present application are described below, which can be used to execute the chip layout correction method based on the double graph process in the embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the embodiments of the chip layout correction method based on the double graph process described above.

[0115] Referring to Figure 5 , a block diagram of a chip layout correction device based on a double graph process in an embodiment of the present application is shown.

[0116] As Figure 5As shown, the chip layout correction device 500 based on the double patterning process according to the embodiment of the present application comprises: an acquisition unit 501, a detection unit 502, a division unit 503 and a resolution unit 504.

[0117] The acquisition unit 501 is configured to acquire a chip layout to be processed, and determine a pair of conflicting patterns in a target metal layer of the chip layout, the target metal layer being a metal layer to be applied to a double patterning process.The detection unit 502 is configured to construct a conflict graph in the target metal layer by taking the patterns in the pair of conflicting patterns as nodes and the conflict relationship between the patterns as connecting edges, and detect an odd ring in the conflict graph, the odd ring being a closed loop formed by odd number of patterns in sequence through connecting edges.The division unit 503 is configured to divide the target metal layer into a plurality of correction regions if there is an odd ring in the conflict graph.The resolution unit 504 is configured to resolve the odd rings in the plurality of correction regions in parallel, and return to execute the step of determining a pair of conflicting patterns in the target metal layer of the chip layout until there is no odd ring in the conflict graph.

[0118] In some embodiments of the present application, based on the foregoing scheme, the acquisition unit 501 is configured to acquire a process rule spacing of the target metal layer, the process rule spacing being a minimum pattern spacing that meets process production conditions; and determine the pair of conflicting patterns if an actual spacing of any adjacent patterns in the target metal layer is less than a set multiple of the process rule spacing.

[0119] In some embodiments of the present application, based on the foregoing scheme, the acquisition unit 501 is configured to acquire a process rule spacing of the target metal layer, and a factor weight of the target metal layer on a plurality of process risk factors, the process rule spacing being a minimum pattern spacing that meets process production conditions; calculate a conflict risk value of any adjacent patterns in the target metal layer under the double patterning process by a conflict quantification model based on the process rule spacing, the factor weight and an actual spacing of the any adjacent patterns; and determine the pair of conflicting patterns if the conflict risk value is greater than a set risk value.

[0120] In some embodiments of the present application, based on the foregoing scheme, the conflict quantification model comprises: In the formula, the conflict risk value of the any adjacent patterns under the double patterning process is represented by R, the process rule spacing of the target metal layer is represented by S, the factor weight of the lithography risk is represented by W, and the factor weight of the etching risk is represented by W. ​a factor weight representing a pattern type, , for quantification; , for quantification;

[0121] In some embodiments of the present application, based on the foregoing scheme, the detection unit 502 is configured to: call a graph theory loop extraction algorithm to traverse each closed loop in the conflict graph, and count the number of nodes of each closed loop; and determine the closed loop with an odd number of nodes as an odd loop.

[0122] In some embodiments of the present application, based on the foregoing scheme, the division unit 503 is configured to: divide the target metal layer into a plurality of first regions with similar number of odd loops, and the number of odd loops in each first region is less than a set number; divide each first region into at least two second regions with similar region size, and define the second region as the modified region.

[0123] In some embodiments of the present application, based on the foregoing scheme, the division unit 503 is configured to: traverse the grid regions in the target metal layer in a set traversal order in sequence, and whenever a current grid region is traversed, count the total number of odd loops of the grid regions that have been traversed, and if the total number of odd loops exceeds a set number, mark the grid regions that have been traversed before the current grid region as a first region, and reset the grid regions that have been traversed and the total number of odd loops; take the current grid region as the first grid region that has not been traversed, repeat the traversal process of the grid regions, and until all grid regions are traversed.

[0124] In some embodiments of the present application, based on the foregoing scheme, the elimination unit 504 is configured to: determine at least one target connection edge to be repaired in the modified region; and perform a shift processing and / or a cutting processing on one of the patterns associated with each target connection edge, to eliminate the odd loop to which the each target connection edge belongs.

[0125] In some embodiments of the present application, based on the foregoing scheme, the elimination unit 504 is configured to: traverse each connection edge in the modified region, and record the corresponding relationship between each connection edge and the odd loop to which it belongs in a temporary table; count the connection edge with the largest number of odd loops in the temporary table as a target connection edge to be repaired; hide the odd loop to which the target connection edge belongs in the temporary table, and return to the step of counting the connection edge with the largest number of odd loops in the temporary table until all the odd loops recorded in the temporary table are hidden.

[0126] In some embodiments of the present application, based on the foregoing scheme, the digestion unit 504 is configured to: if the connection edge with the largest number of odd rings in the temporary table includes multiple connection edges, obtain the actual distance between adjacent graphs associated with each of the multiple connection edges; and determine the connection edge corresponding to the adjacent graphs with the largest actual distance as the target connection edge.

[0127] Based on the same inventive concept, the embodiments of the present application provide a computer program product, which comprises computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to enable a computer device having the processor to perform the operations performed by the chip layout correction method based on a double graph process as described above.

[0128] Based on the same inventive concept, the embodiments of the present application provide a computer readable storage medium, which stores at least one computer program instruction, the at least one computer program instruction is loaded and executed by a processor to enable the processor to perform the operations performed by the chip layout correction method based on a double graph process as described above.

[0129] Based on the same inventive concept, the embodiments of the present application further provide an electronic device, which refers to Figure 6 , shows a structural schematic diagram of the electronic device in the embodiments of the present application, the electronic device comprises one or more memories 604, one or more processors 602, and at least one computer program (computer program instructions) stored in the memory 604 and executable on the processor 602, and the processor 602 executes the computer program to implement the chip layout correction method based on a double graph process as described above.

[0130] In the above-mentioned embodiments of the present application, Figure 6 , a bus architecture (represented by bus 600), the bus 600 can include any number of interconnected buses and bridges, the bus 600 links various circuits including one or more processors represented by processor 602 and memory represented by memory 604. The bus 600 can also link various other circuits such as peripheral devices, voltage stabilizers and power management circuits, which are well known in the art, and therefore, they will not be further described herein. The bus interface 605 provides an interface between the bus 600 and the receiver 601 and the transmitter 603. The receiver 601 and the transmitter 603 can be the same element, i.e. a transceiver, which provides a unit for communicating with various other devices on a transmission medium. The processor 602 is responsible for managing the bus 600 and general processing, while the memory 604 can be used to store data used by the processor 602 in performing operations.

[0131] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope and spirit of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items prefaced by "comprising" to indicate a disjunctive list means each single item in the list has been recited before "or" one or more additional disjunctive items also have been recited. However, "or" in such a phrase does not mean that the list is inclusive of at least one of the items. Further, as used herein, "comprising" is to be interpreted as including the more restrictive terms "consisting of" and "consisting essentially of."

[0132] In several embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. Among them, the above-mentioned device embodiments are only schematic, such as the division of the units, which can be a logical function division, and other division methods can be used in actual implementation, such as the combination or integration of multiple units or components into another system, or the omission or non-execution of some features. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be indirect coupling or communication connection through some interface, unit or module, which can be electrical or other forms.

[0133] The units described as separate components can or can not be physically separated, and the components of the control device can or can not be physical units, i.e. they can be located in one place or distributed on multiple units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0134] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part of the prior art that contributes to the technical solutions or the whole or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer program instructions.

[0135] The above merely provides an example of the present application, and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall fall into the scope of claims of the present application.

Claims

1. A method for correcting a chip layout based on a double patterning process, characterized in that, The method comprises: acquiring a chip layout to be processed, and determining a pair of conflicting patterns in a target metal layer of the chip layout, the target metal layer being a metal layer to be applied to a double pattern process; constructing a conflict graph in the target metal layer by taking patterns in the pair of conflicting patterns as nodes and a conflict relationship between the patterns as a connecting edge, and detecting an odd cycle in the conflict graph, the odd cycle being a closed loop formed by an odd number of patterns through the connecting edge; if an odd cycle is detected in the conflict graph, dividing the target metal layer into a plurality of correction regions; parallel resolving of the odd cycles in the plurality of correction regions, and returning to the step of determining a pair of conflicting patterns in a target metal layer of the chip layout until no odd cycle is detected in the constructed conflict graph.

2. The method of claim 1, wherein, The step of determining a pair of conflicting patterns in a target metal layer of the chip layout comprises: acquiring a process rule spacing of the target metal layer, the process rule spacing being a minimum pattern spacing meeting process production conditions; if an actual spacing of any adjacent patterns in the target metal layer is less than a set multiple of the process rule spacing, determining the any adjacent patterns as a pair of conflicting patterns.

3. The method of claim 1, wherein, The step of determining a pair of conflicting patterns in a target metal layer of the chip layout comprises: acquiring a process rule spacing of the target metal layer and a factor weight of the target metal layer on a plurality of process risk factors, the process rule spacing being a minimum pattern spacing meeting process production conditions; calculating a conflict risk value of any adjacent patterns in the target metal layer under a double pattern process through a conflict quantification model based on the process rule spacing, the factor weight, and an actual spacing of the any adjacent patterns; if the conflict risk value is greater than a set risk value, determining the any adjacent patterns as a pair of conflicting patterns.

4. The method of claim 3, wherein, The conflict quantification model comprises: wherein, represents the conflict risk value of the arbitrary adjacent pattern under the double patterning process; represents the process rule spacing set for the target metal layer, which is a constant; represents the factor weight of the lithography risk, which is a constant; represents the factor weight of the pattern type, which is a constant; represents the actual spacing of the arbitrary adjacent pattern in the target metal layer, which is a variable.

5. The method of claim 1, wherein, The step of detecting an odd cycle in the conflict graph comprises: calling a graph theory loop extraction algorithm to traverse each closed loop in the conflict graph and counting a number of nodes of the each closed loop; determining a closed loop with an odd number of nodes as an odd cycle.

6. The method of claim 1, wherein, The step of dividing the target metal layer into a plurality of correction regions comprises: dividing the target metal layer into a plurality of first regions with similar numbers of odd cycles, a number of odd cycles in each first region being less than a set number; dividing each first region into at least two second regions with similar sizes, and defining the second regions as the correction regions.

7. The method of claim 6, wherein, The step of dividing the target metal layer into a plurality of first regions with similar numbers of odd cycles comprises: traversing grid regions that have not been traversed in the target metal layer in a set traversal order; each time a current grid region is traversed, counting a total number of odd cycles of the grid regions that have been traversed, if the total number of odd cycles exceeds a set number, marking the grid regions that have been traversed before the current grid region as a first region, and resetting the grid regions that have been traversed and the total number of odd cycles; taking the current grid region as a first grid region that has not been traversed, repeating the traversal process of the grid regions until all the grid regions are traversed.

8. The method of claim 1, wherein, The method comprises: determining at least one target connection edge to be repaired in the correction region; performing displacement processing and / or cutting processing on one of the graphs associated with each target connection edge to eliminate the odd ring to which each target connection edge belongs.

9. The method of claim 8, wherein, The method comprises: traversing each connection edge in the correction region, and recording the correspondence between each connection edge and the odd ring to which it belongs in a temporary table; counting the connection edge with the largest number of odd rings in the temporary table as the target connection edge to be repaired; hiding the odd ring to which the target connection edge belongs in the temporary table, and returning to the step of counting the connection edge with the largest number of odd rings in the temporary table until all the odd rings recorded in the temporary table are hidden.

10. The method of claim 9, wherein, The method further comprises: if the connection edge with the largest number of odd rings counted in the temporary table includes multiple connection edges, obtaining the actual distance between the adjacent graphs associated with each of the multiple connection edges; determining the connection edge corresponding to the adjacent graphs with the largest actual distance as the target connection edge.

11. A device for modifying a chip layout, characterized by The apparatus comprises: an obtaining unit configured to obtain a chip layout to be processed, and determine a pair of conflicting graphs in a target metal layer of the chip layout, the target metal layer being a metal layer to be applied to a double patterning process; a detecting unit configured to construct a conflict graph in the target metal layer by taking the graphs in the pair of conflicting graphs as nodes and the conflict relationship between the graphs as connection edges, and detect an odd ring in the conflict graph, the odd ring being a closed loop formed by an odd number of graphs associated in sequence by connection edges; a dividing unit configured to divide the target metal layer into a plurality of correction regions if the conflict graph includes an odd ring; an eliminating unit configured to eliminate the odd rings in the plurality of correction regions in parallel, and return to the step of determining a pair of conflicting graphs in a target metal layer of the chip layout until there is no odd ring in the conflict graph.

12. A computer program product, characterised in that, The computer program product comprises computer instructions stored in a computer-readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform the method of any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one program code, which is loaded and executed by a processor to implement the operations performed by the method of any one of claims 1 to 10.

14. An electronic device, comprising: The electronic device comprises one or more processors and one or more memories, and the one or more memories store at least one program code, which is loaded and executed by the one or more processors to implement the method of any one of claims 1 to 10.

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