Nor Flash and read operation module and power supply circuit thereof

Abstract

The invention provides a Nor Flash and a read operation module and a power supply circuit thereof. The power supply circuit of the Nor Flash read operation module comprises a first charge pump unit, a second charge pump unit and a read operation voltage generation unit, the first charge pump unit is used for outputting a first voltage to the read operation voltage generation unit, and the second charge pump unit is used for outputting a second voltage to the read operation voltage generation unit; the read operation voltage generating unit is used for outputting a read operation voltage to the storage array module based on the first voltage and the second voltage so as to provide a read operation standby voltage in a standby state or a read operation working voltage in a read operation state for the storage array module. Due to the fact that the read operation standby voltage is basically equal to the read operation working voltage, when the Nor Flash is switched to the read operation state from the standby state at any moment, the read operation voltage is stable and does not change along with the chip power supply voltage of the Nor Flash.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of non-volatile memory, in particular to a Nor Flash (a kind of non-volatile flash memory technology) and its read operation module and its power supply circuit. BACKGROUND

[0002] Nor Flash memory technology is a kind of non-volatile memory technology, mainly used for storing program code and data, compared with the traditional Electrically Erasable Programmable Read Only Memory (EEPROM), has the advantages of large capacity, small size, low power consumption, stable performance and high localization rate. Therefore, Nor Flash is widely used in various intelligent fields, including motherboard basic input / output system, digital set-top box, home gateway, router, Internet of Things, automotive electronics, wearable devices, security monitoring and artificial intelligence, etc. Code storage medium, its versatility and reliability make our life more convenient and intelligent.

[0003] Nor Flash read operation needs high voltage, while in standby state it needs low power consumption, Nor Flash Array (array) has a large capacitance on the read operation path, from standby to normal working time is only tens of nanoseconds (nanoseconds), so it is difficult to charge this large capacitance to the required high voltage in this time, the existing Nor Flash read operation module power supply circuit adopts voltage refresh mechanism. Suppose the target value of the voltage is 6v (volt), when the Nor Flash is powered on, it is charged to 6v, then the charge pump circuit is turned off, the internal parasitic leakage path will make the voltage slowly decrease, the low power consumption detection circuit detects this voltage, and once the voltage drops to 5.6v, the charge pump circuit is started again to charge it to 6v.

[0004] The main problem of this design is that when the Nor Flash read operation module switches from standby to work, there may be two extreme cases, the first is that the high voltage required for read operation has reached 6v, and the second is at 5.6v. Because the next read operation is to be done, the first one does not need to supplement much charge, and the second one needs to supplement a large amount of charge. The charge is provided by a very powerful charge pump. Since the establishment of the reference voltage, voltage detection, and whether the charge needs to be supplemented, a certain time is needed, so that the first read operation working voltage is not very stable, especially under different Nor Flash chip power supply voltage (VDD), since the read operation working voltage is sensitive to the change of VDD, it may be overcharged when VDD is high, and it may be insufficient when VDD is low, so that the read operation working voltage changes greatly with the change of chip power supply voltage (VDD), which may cause read operation errors. SUMMARY

[0005] The technical problem to be solved by the present disclosure is to overcome the defect that the read operation working voltage is sensitive to the change of VDD caused by the large difference between the read operation standby voltage and the read operation working voltage in the Nor Flash read operation module of the prior art, and to provide a Nor Flash, a read operation module thereof, and a power supply circuit thereof.

[0006] The present disclosure solves the above technical problem by the following technical scheme:

[0007] In a first aspect, a power supply circuit of a Nor Flash read operation module is provided, the Nor Flash comprising a storage array module composed of a plurality of storage array groups;

[0008] The power supply circuit comprises a first charge pump unit, a second charge pump unit, and a read operation voltage generation unit;

[0009] The read operation voltage generation unit is electrically connected to the first charge pump unit, the second charge pump unit, and the storage array module, respectively;

[0010] The first charge pump unit is configured to convert a chip power supply voltage of the Nor Flash to a first voltage based on a read operation signal and a first standby refresh signal, and output the first voltage to the read operation voltage generation unit;

[0011] The second charge pump unit is configured to convert the chip power supply voltage to a second voltage based on the read operation signal and a second standby refresh signal, and output the second voltage to the read operation voltage generation unit;

[0012] The read operation voltage generation unit is configured to output a read operation voltage to the storage array module based on the first voltage and the second voltage, so as to provide the storage array module with a read operation standby voltage when the Nor Flash is in a standby state, or a read operation working voltage when the Nor Flash is in a read operation state;

[0013] The actual difference between the read operation standby voltage and the read operation working voltage is less than or equal to a first preset value.

[0014] Optionally, the read operation voltage generation unit comprises a capacitor, a first MOS tube, a second MOS tube, and a first switch;

[0015] The width-to-length ratio of the second MOS tube is greater than the width-to-length ratio of the first MOS tube;

[0016] The output end of the second charge pump unit is electrically connected to the gate of the first MOS tube and the gate of the second MOS tube, respectively;

[0017] The drain of the first MOS transistor is electrically connected with the output terminal of the first charge pump unit;

[0018] The drain of the second MOS transistor is electrically connected with the output terminal of the first charge pump unit through the first switch;

[0019] The source of the first MOS transistor and the source of the second MOS transistor are respectively electrically connected with the storage array module;

[0020] One end of the capacitor is electrically connected with the output terminal of the second charge pump unit, and the other end of the capacitor is grounded.

[0021] Optionally, the read operation voltage generating unit further comprises a second switch and a current source;

[0022] One end of the current source is grounded, and the other end of the current source is electrically connected with one end of the second switch;

[0023] The other end of the second switch is electrically connected with the source of the second MOS transistor;

[0024] The current value output by the current source is the same as the current value flowing through the second MOS transistor when a target storage unit in a target storage array is in a read operation state.

[0025] Optionally, the standby state comprises a standby non-refresh state and a standby refresh state;

[0026] When the Nor Flash is in the standby non-refresh state, the read operation signal is in an invalid state, the first standby refresh signal and the second standby refresh signal are both in an invalid state, the first switch and the second switch are both in an open state, and the current voltage difference between the first voltage and the read operation voltage is greater than or equal to a second preset value;

[0027] Or, when the Nor Flash is in the standby refresh state, the read operation signal is in an invalid state, and if the current voltage difference between the first voltage and the read operation voltage is less than the second preset value, then the first standby refresh signal and the second standby refresh signal are both in an effective state, the first switch and the second switch are both in a closed state, and the first charge pump unit and the second charge pump unit are in a working state, so that the current voltage difference is greater than or equal to the second preset value.

[0028] Optionally, when the Nor Flash is in a read operation state, the read operation signal is in an active state, the first standby refresh signal and the second standby refresh signal are both in an inactive state, the first switch and the second switch are both in a closed state, and the first charge pump unit and the second charge pump unit are both in a working state, so that the current voltage difference between the first voltage and the read operation voltage is greater than or equal to a second preset value.

[0029] Optionally, the power supply circuit further comprises a voltage detection unit.

[0030] The voltage detection unit is electrically connected with the first charge pump unit, the second charge pump unit and the read operation voltage generation unit respectively.

[0031] The voltage detection unit is configured to detect the current voltage difference between the first voltage and the read operation voltage, and set the first standby refresh signal and the second standby refresh signal to be in an inactive state or an active state based on the read operation signal and the current voltage difference.

[0032] Optionally, the power supply circuit further comprises a frequency divider.

[0033] The frequency divider is configured to receive the first standby refresh signal and output the second standby refresh signal after frequency division.

[0034] Optionally, each storage array is provided with a third switch and a fourth switch.

[0035] One end of the third switch is electrically connected with the storage unit, and the other end of the third switch is configured to receive a write operation power supply voltage.

[0036] One end of the fourth switch is electrically connected with the storage unit, and the other end of the fourth switch is electrically connected with an output end of the read operation voltage generation unit.

[0037] In a second aspect, a Nor Flash read operation module is provided, which comprises a read operation signal generation circuit configured to generate a read operation signal.

[0038] The Nor Flash read operation module further comprises the power supply circuit of the Nor Flash read operation module as described above.

[0039] In a third aspect, a Nor Flash is provided, which comprises the Nor Flash read operation module and a storage array module composed of a plurality of storage arrays as described above.

[0040] On the basis of common knowledge in the art, the above-mentioned preferred conditions can be combined arbitrarily, i.e. to obtain each preferred example of the present disclosure.

[0041] The positive progress effect of the present disclosure is that:

[0042] The Nor Flash and its read operation module and its power supply circuit of the present disclosure, the power supply circuit includes a first charge pump unit, a second charge pump unit and a read operation voltage generation unit; the read operation voltage generation unit is electrically connected with the first charge pump unit, the second charge pump unit and the storage array module respectively; the read operation voltage generation unit is used to output a read operation voltage to the storage array module in the Nor Flash based on a first voltage output by the first charge pump unit and a second voltage output by the second charge pump unit, so as to provide the storage array module with a read operation standby voltage when the Nor Flash is in a standby state, or a read operation working voltage when the Nor Flash is in a read operation state. Since the actual difference between the read operation standby voltage and the read operation working voltage is less than or equal to a first preset value, the read operation standby voltage and the read operation working voltage are basically equal, so that the read operation voltage is stable when the system switches from any moment of the standby state to the read operation state, and will not change with the chip power supply voltage of the Nor Flash, solving the problem that the read operation working voltage is relatively sensitive to the change of the chip power supply voltage of the Nor Flash due to the large difference between the read operation standby voltage and the read operation working voltage in the existing read operation module. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 It is a first structural schematic diagram of the power supply circuit of the existing Nor Flash read operation module;

[0044] Figure 2 It is a second structural schematic diagram of the power supply circuit of the existing Nor Flash read operation module;

[0045] Figure 3 It is a first structural schematic diagram of the power supply circuit of the Nor Flash read operation module provided by Embodiment 1 of the present disclosure;

[0046] Figure 4 It is a second structural schematic diagram of the power supply circuit of the Nor Flash read operation module provided by Embodiment 1 of the present disclosure;

[0047] Figure 5 It is a third structural schematic diagram of the power supply circuit of the Nor Flash read operation module provided by Embodiment 1 of the present disclosure;

[0048] Figure 6 It is a fourth structural schematic diagram of the power supply circuit of the Nor Flash read operation module provided by Embodiment 1 of the present disclosure;

[0049] Figure 7 A fifth structural schematic diagram of a power supply circuit of a Nor Flash read operation module provided for Embodiment 1 of the present disclosure is provided.

[0050] Figure 8 A structural schematic diagram of a Nor Flash read operation module provided for Embodiment 2 of the present disclosure is provided.

[0051] Figure 9 A structural schematic diagram of a Nor Flash provided for Embodiment 3 of the present disclosure is provided. DETAILED DESCRIPTION

[0052] The present disclosure is further illustrated by way of examples below, but the present disclosure is not limited to the scope of the examples.

[0053] The prefix words such as "first", "second" are used in the embodiments of the present disclosure only for the purpose of distinguishing different described objects, and have no limiting effect on the position, order, priority, number or content of the described objects. The use of ordinal words such as ordinal words in the embodiments of the present disclosure does not constitute a limitation on the described objects, and the description of the described objects should be seen in the context of the claims or embodiments, and should not constitute an unnecessary limitation because of the use of such prefix words. In addition, in the description of the embodiments, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0054] Figure 1For the working condition of the existing Nor Flash read operation module in standby, read pump (read charge pump) and standby pump (standby charge pump) are high-voltage power supplies, and the storage array module has N+1 storage arrays (Array), respectively from Array 0 to Array N, each Array has two high-voltage switches (read switch and standby switch) outside, which are used to select different high-voltage power supplies, the read switch corresponds to S0…SN, and the standby switch corresponds to S0B…SNB. In standby, the read operation signal is invalid (that is, read_en=0), the standby pump works, and the output voltage of the standby pump is read_stb (read operation standby voltage), at this time the standby switch is connected to read_stb, and read_stb is provided by the standby pump. There is a low-power detection circuit (Detector) on read_stb, in standby, the Array end will have a parasitic leakage current of 50nA (nanoampere) level, which makes the read_stb voltage, which has reached the target value at power-on, slowly decrease, when the Detector detects that read_stb decreases by a preset value (for example, 0.4v) from the target voltage, the refresh control signal is set to 1 (refresh_en=1), so that the standby pump works again, and the read_stb voltage returns to the target value, so in standby, read_stb will have a fluctuation of about 0.4v; the read pump does not work during the entire standby period.

[0055] Figure 2 For the working condition of the existing Nor Flash read operation module in read active, and Figure 1 Compared with the standby state shown in the figure, at this time the read operation signal is valid (that is, read_en=1), the read pump and the standby pump work at the same time, and the target voltages of the two are consistent, which are the target values described above, that is, the output voltage of the read pump read_act (read operation working voltage) is equal to the output voltage of the standby pump read_stb, both are equal to read_act (read operation working voltage). Assuming that the Array to be read at this time is Array 0, then the S0 and S0B switches of Array 0 change compared with standby, S0 is closed and S0B is opened, and the power supply of Array 0 is switched to read_act output by the read pump, and the other unselected Arrays remain unchanged.

[0056] The problem of the existing Nor Flash read operation module is that a sufficient margin (i.e., the aforementioned preset value) must be left between read_stb and read_act to ensure standby power consumption, so the difference between the two cannot be too small, and is generally 0.4v. Therefore, when read active, the read pump needs to additionally supplement charges in addition to supporting WL (word line) switch consumption. The capacitance load of an Array is generally 30~50P. If the chip power supply voltage VDD of the Nor Flash is 2.6v, read_stb is 5.6v, and the target value of read_act is 6v, that is, the chip power supply voltage is low, and the difference between read_stb and read_act is large. Since the capacity of the pump is strongly related to VDD, the capacity of the read pump is weak at this time, and it is insufficient to make the read_act of Array 0 reach the target value at the beginning of the read operation. If the chip power supply voltage VDD of the Nor Flash is 3.7v, read_stb is already 6v, and the target value of read_act is 6v, that is, the chip power supply voltage is high, and there is no difference between read_stb and read_act. At this time, the capacity of the read pump is very strong. Since there is only tens of nanoseconds from receiving the read instruction from the chip to starting the first read operation internally, the charge pump cannot be started until all internal signals are fully established. Therefore, the charge pump may be misoperated for a few nanoseconds, which will cause the read_act of Array 0 to exceed the target value of 6V, resulting in overshoot.

[0057] That is, in the prior art, a sufficient margin must be left between read_stb and read_act, and the read operation working voltage read_act is not very stable, especially under different Nor Flash chip power supply voltages VDD. Since the read operation working voltage read_act is sensitive to changes in VDD, it may overshoot when VDD is high, and it may be insufficient when VDD is low. Therefore, the read operation working voltage read_act changes greatly with the chip power supply voltage VDD, resulting in read operation errors.

[0058] To solve this problem, the present disclosure provides a Nor Flash and its read operation module and its power supply circuit to at least solve the above technical problems, and the specific content is as follows:

[0059] Embodiment 1

[0060] The embodiment provides a power supply circuit of a Nor Flash read operation module, as shown in Figure 3 The Nor Flash includes a plurality of storage array modules composed of storage arrays;

[0061] The power supply circuit comprises a first charge pump unit 1, a second charge pump unit 2 and a read operation voltage generation unit 3.

[0062] The read operation voltage generation unit 3 is electrically connected with the first charge pump unit 1, the second charge pump unit 2 and the storage array module respectively.

[0063] The first charge pump unit 1 is configured to convert the chip power supply voltage VDD of the Nor Flash into a first voltage read_vd based on a read operation signal read_en and a first standby refresh signal Refresh_en_drain, and output the first voltage read_vd to the read operation voltage generation unit 3.

[0064] The second charge pump unit 2 is configured to convert the chip power supply voltage VDD into a second voltage read_vg based on a read operation signal read_en and a second standby refresh signal Refresh_en_gate, and output the second voltage read_vg to the read operation voltage generation unit 3.

[0065] The read operation voltage generation unit 3 is configured to output a read operation voltage read_power to the storage array module based on the first voltage read_vd and the second voltage read_vg, so as to provide the read operation standby voltage of the Nor Flash in a standby state or the read operation working voltage of the Nor Flash in a read operation state to the storage array module.

[0066] The actual difference between the read operation standby voltage and the read operation working voltage is less than or equal to a first preset value, and the first preset value needs to be as small as possible to ensure that the read operation standby voltage is equal to or substantially equal to the read operation working voltage. For example, the first preset difference is in the range of -0.1V to +0.1V, and the first preset value can be 0.1V.

[0067] The storage array module of the Nor Flash comprises a plurality of storage arrays, each of which comprises a plurality of storage cells, and the storage array module has a certain density (storage capacity). Each storage array has a certain size. If the capacity of a storage array is 4Mbit (bit), if the storage array module comprises 4 storage arrays, the storage capacity is 16M, and if the storage array module comprises 32 storage arrays, the storage capacity is 128M. In actual use, the corresponding storage array needs to be read according to the demand.

[0068] The read operation voltage read_power in the embodiment is standby read operation voltage in standby state and is read operation working voltage in read active state. In the two different states, the values are basically equal, so that the read operation voltage is stable when the Nor Flash is switched from standby state to read operation state at any time, and the read operation voltage does not change with the chip power supply voltage of the Nor Flash, thereby solving the problem that the read operation working voltage is sensitive to the change of the chip power supply voltage of the Nor Flash due to the large difference between the standby read operation voltage and the read operation working voltage in the existing read operation module.

[0069] In an alternative embodiment, as shown in FIGS. 1, 2, 3, 4, 5, 6, the read operation voltage generating unit 3 comprises a capacitor C0 and a first MOS transistor NM0, a second MOS transistor NM1 and a first switch K1. Figure 4 、 5 The read operation voltage generating unit 3 comprises a capacitor C0 and a first MOS transistor NM0, a second MOS transistor NM1 and a first switch K1.

[0070] The width-length ratio of the second MOS transistor NM1 is greater than the width-length ratio of the first MOS transistor NM0.

[0071] The output terminals of the second charge pump unit 2 are electrically connected to the gate of the first MOS transistor NM0 and the gate of the second MOS transistor NM1, respectively.

[0072] The drain of the first MOS transistor NM0 is electrically connected to the output terminal of the first charge pump unit 1.

[0073] The drain of the second MOS transistor NM1 is electrically connected to the output terminal of the first charge pump unit 1 through the first switch K1.

[0074] The source of the first MOS transistor NM0 and the source of the second MOS transistor NM1 are electrically connected to the storage array module, respectively.

[0075] One end of the capacitor C0 is electrically connected to the output terminal of the second charge pump unit 2, and the other end of the capacitor C0 is grounded. As shown in FIGS. 1, 2, 3, 4, 5, 6, the capacitor C0 is connected between the output terminal of the second charge pump unit 2 and the ground. Figure 4 、 5 The gate voltage of NM0 and NM1 is the second voltage read_vg, the drain voltage of NM0 and NM1 is the first voltage read_vd, and the source voltage of NM0 and NM1 is the read operation voltage read_power. NM0 and NM1 constitute a source follower. By virtue of the characteristic of the MOS transistor in the saturation region, although the first voltage read_vd fluctuates, the first charge pump unit is driven to work by the first standby refresh signal and the read operation signal, read_vd is supplemented, and the read operation voltage read_power can also be kept stable.

[0076] In an alternative embodiment, as shown in FIGS. 1, 2, 3, 4, 5, 6, the read operation voltage generating unit 3 comprises a capacitor C0 and a first MOS transistor NM0, a second MOS transistor NM1 and a first switch K1. Figure 4 、 5As shown in FIG. 6, the read operation voltage generating unit 3 further comprises a second switch K2 and a current source Ib0.

[0077] One end of the current source Ib0 is grounded, and the other end of the current source Ib0 is electrically connected to one end of the second switch K2.

[0078] The other end of the second switch K2 is electrically connected to the source electrode of the second MOS transistor NM1.

[0079] The current value output by the current source Ib0 is the same as the current value flowing through the second MOS transistor NM1 when the target storage unit in the target storage array is in a read operation state.

[0080] The target storage array is any one of the storage arrays in the storage array module, i.e., any one of Array0-ArrayN. The target storage unit can be any one of the storage units in the target storage array, or the storage units in a certain row, or the storage units in a certain column, or all the storage units in the target storage array. The definition is made according to the rules of the read operation of the Nor Flash.

[0081] In the read active state, the target storage array end has a real read current (for the current in the word line setup stage), and the current mainly flows through the second MOS transistor NM1. In the standby refresh phase, there is no real read operation, so no real read current is generated. Therefore, the current source Ib0 is used to simulate the read current at the target storage array end in the read active state. By setting the current source, it is further ensured that the standby read operation standby voltage is equal to the read operation working voltage in the read active state, and the fluctuation of the read operation voltage is further reduced.

[0082] In an optional embodiment, the standby state includes a standby no refresh state and a standby refresh state. When the Nor Flash is in the standby no refresh state (i.e., in the standby no refresh phase), the read operation signal is in an invalid state, i.e., read_en=0. The first standby refresh signal and the second standby refresh signal are both in an invalid state, i.e., Refresh_en_drain=0 and Refresh_en_gate=0. The first switch K1 and the second switch K2 are both in an open state, and the current voltage difference between the first voltage read_vd and the read operation voltage read_power is greater than or equal to the second preset value vth, so as to ensure that the first MOS transistor is in a saturated state.

[0083] Among them, the first charge pump unit 1 is in a standby state under the control of the read operation signal read_en and the first standby refresh signal Refresh_en_drain; the second charge pump unit 2 is in a standby state under the control of the read operation signal read_en and the second standby refresh signal Refresh_en_gate.

[0084] When the Nor Flash is in the standby non-refresh state, read_en = 0, read_vd - read_power > vth, and the second preset value vth is the threshold voltage vth(NM0) corresponding to the first MOS transistor NM0, as Figure 4 shown. At this time, both the first switch K1 and the second switch K2 are disconnected, the second MOS transistor NM1 does not work, and the power supplies of all Arrays are connected to read_power. Since read_power = read_vg - vth(NM0) - vov(NM0), where vov(NM0) is the overdrive voltage (Overdrive Voltage) corresponding to the first MOS transistor NM0, the parasitic leakage current at the storage array module end will cause the first voltage read_vd to slowly decrease. However, since the first MOS transistor NM0 operates in the saturation region, the read operation standby voltage read_power is stable at this time.

[0085] In an optional embodiment, when the Nor Flash is in the standby refresh state (standby refresh phase), the read operation signal is in an invalid state, that is, read_en = 0. If the current voltage difference between the first voltage read_vd and the read operation voltage read_power is less than the second preset value, then both the first standby refresh signal Refresh_en_drain and the second standby refresh signal Refresh_en_gate are in an effective state, that is, Refresh_en_drain = 1 and Refresh_en_gate = 1, and both the first switch K1 and the second switch K1 are in a closed state. The first charge pump unit 1 is in a working state under the control of the read operation signal read_en and the first standby refresh signal Refresh_en_drain; the second charge pump unit 2 is in a working state under the control of the read operation signal read_en and the second standby refresh signal Refresh_en_gate, so that the current voltage difference is greater than or equal to the second preset value to ensure that both the first MOS transistor and the second MOS transistor are in the saturation state.

[0086] When the Nor Flash is in the standby refresh state, read_en = 0. If read_vd - read_power < vth, as Figure 5As shown, at this time, the first switch K1 and the second switch K2 are both closed, the first MOS transistor NM0 and the second MOS transistor NM1 are both working and in a saturated state, and the bias current flowing through the second switch K2 is in the order of several uA (microamperes), so that the voltage difference between the read_power of the standby no refresh phase and the standby refresh phase will become small.

[0087] Specifically, because read_vg remains unchanged, NM0 and NM1 both work in the saturation region, and the threshold voltages vth of NM0 and NM1 are also equal, i.e., vth(NM1)=vth(NM0), read_power=read_vg-vth(NM1)-vov(NM1), the second preset value is the threshold voltage vth(NM0) corresponding to the first MOS NM0, and the threshold voltage vth(NM1) corresponding to the second MOS NM1 is also the same, vov(NM1) is the overdrive voltage corresponding to the second MOS NM1, the only difference is the overdrive voltage vov of NM0 and NM1, and vov is related to the width-length ratio of the MOS and the current flowing through the MOS. There is a big difference in the current flowing through NM0 and NM1 in standby no refresh phase and standby refresh phase. At standby no refresh, the current flowing through NM0 is very small, but at standby refresh phase, the current flowing through NM1 is relatively large, for example, 100 times larger. Therefore, the width-length ratio of the second MOS NM1 needs to be greater than that of the first MOS NM0, for example, NM1 is 100 times larger than NM0, to ensure that the overdrive voltage vov of NM0 and NM1 is also equal, i.e., vov(NM1)=vov(NM0), so that at standby no refresh phase, a smaller MOS (NM0) is used to adapt to a small current (leakage current of Array), and at standby refresh phase, an additional current source (Ib0) is used to adapt to a large MOS (NM1), so that the read_power voltage difference between standby no refresh phase and standby refresh phase becomes small, and they are basically equal. During this period, the first charge pump unit 1 is in working state, the second charge pump unit 2 is in intermittent working state (i.e., working when read_vd-read_power

[0088] In an optional implementation, when the Nor Flash is in read active state, when the read operation signal is valid (read_en=1), the first standby refresh signal and the second standby refresh signal are both invalid (Refresh_en_drain=0 and Refresh_en_gate=0), the first switch K1 and the second switch K2 are both closed, and the first charge pump unit 1 and the second charge pump unit 2 are both in working state. The first charge pump unit 1 is in working state under the control of the read operation signal read_en and the first standby refresh signal Refresh_en_drain; the second charge pump unit 2 is in working state under the control of the read operation signal read_en and the second standby refresh signal Refresh_en_gate, so that the current voltage difference is greater than or equal to the second preset value, so as to ensure that the first MOSFET and the second MOSFET are both in saturation state.

[0089] When the Nor Flash is in read operation mode, read_en=1, read_vd-read_power > vth, as in Figure 6 As shown, the power supply circuit of the Nor Flash read operation module is in a state close to the standby refresh phase at this time. Figure 4 (As shown), the only difference is that the first charge pump unit 1 and the second charge pump unit 2 operate simultaneously, both controlled only by read_en=1, without the intervention of the first standby refresh signal Refresh_en_drain and the second standby refresh signal Refresh_en_gate. At this time, the first standby refresh signal Refresh_en_drain and the second standby refresh signal Refresh_en_gate are both in an invalid state, i.e., Refresh_en_drain=0 and Refresh_en_gate=0. The first charge pump unit 1, based on the read operation signal read_en, converts the Nor Flash chip power supply voltage VDD to the first voltage read_vd and outputs it to the read operation voltage generation unit 3. The second charge pump unit 2, based on the read operation signal read_en, converts the chip power supply voltage VDD to the second voltage read_vg and outputs it to the read operation voltage generation unit 3. read_power is well clamped by read_vg, read_vd-read_power >vth, the read power is stable and does not overshoot. And because the current source Ib0 is used to simulate the read current at the target memory array end during the standby refresh phase, the read power during read active is almost equal to the value during standby.

[0090] Meanwhile, when a read operation is performed on a selected target memory array, the corresponding capacitive load of the read operation voltage read_power end of the present disclosure is (N+1)*C1, where C1 is the capacitive load of a single memory array Array, and N+1 is the total number of memory arrays in the memory array module; while the corresponding capacitive load of the read operation working voltage read_act end of the read pump (read operation charge pump) of the power supply circuit of the existing Nor Flash read operation module is 1*C1, that is, the load capacitance of the read operation of the present disclosure is significantly increased. Large capacitance makes the read_vd response not so fast to supplement the charge. Due to the charge sharing of large capacitance, the charge consumed by a single WL switch will not cause the read_power to drop much, so the read_power is neither overshoot nor too low, and the read_power is very stable and will not change with the chip power supply voltage VDD of the Nor Flash, which provides a guarantee for high-speed read operation.

[0091] In an optional embodiment, as shown in Figure 7 The power supply circuit further includes a voltage detection unit 4;

[0092] The voltage detection unit 4 is electrically connected with the first charge pump unit 1, the second charge pump unit 2 and the read operation voltage generation unit 3 respectively;

[0093] The voltage detection unit 4 is configured to detect the current voltage difference between the first voltage read_vd and the read operation voltage read_power, and based on the read operation signal read_en, the first voltage read_vd and the read operation voltage read_power, set the first standby refresh signal and the second standby refresh signal to the invalid state or the effective state.

[0094] Specifically, the voltage detection unit 4 is configured to set both the first standby refresh signal Refresh_en_drain and the second standby refresh signal Refresh_en_gate to an invalid state (i.e., Refresh_en_drain=0, Refresh_en_gate=0) when the read operation signal is invalid (i.e., read_en=0) and the current voltage difference between the first voltage read_vd and the read operation voltage read_power is greater than or equal to the second preset value vth. Conversely, when the read operation signal is invalid (i.e., read_en=0) and the current voltage difference between the first voltage read_vd and the read operation voltage read_power is less than the second preset value, the first standby refresh signal Refresh_en_drain and the second standby refresh signal Refresh_en_gate are set to an active state (i.e., Refresh_en_drain=1, Refresh_en_gate=1). When the read operation signal is active (read_en=1), both the first standby refresh signal and the second standby refresh signal are set to inactive (Refresh_en_drain=0, Refresh_en_gate=0).

[0095] The power supply circuit of the Nor Flash read operation module in this embodiment detects the first voltage output by the first charge pump unit and the read operation voltage output by the read operation voltage generation unit through the voltage detection unit. It accurately controls the first standby refresh signal and the second standby refresh signal, thereby controlling the working state of the first charge pump unit and the second charge pump unit. This ensures that when the Nor Flash switches from the standby state to the read operation state at any time, the read operation voltage is stable and does not change with the Nor Flash chip power supply voltage.

[0096] In an alternative implementation, such as Figure 4 , 5 As shown in Figures 6 and 7, the power supply circuit also includes a frequency divider 5.

[0097] Frequency divider 5 is used to receive the first standby refresh signal refresh_en_drain, perform frequency division, and then output the second standby refresh signal refresh_en_gate.

[0098] For example, the input terminal of the frequency divider 5 is electrically connected to the output terminal of the voltage detection unit 4, and the output terminal of the frequency divider 5 is electrically connected to the second charge pump 2 unit. The first standby refresh signal refresh_en_drain is divided in parallel and then the second standby refresh signal refresh_en_gate is output.

[0099] When read_vd - read_power < vt, refresh_en_drain = 1. The first standby refresh signal refresh_en_drain is fed into a frequency divider for frequency division operation, and then the second standby refresh signal Refresh_en_gate is output. That is, refresh_en_gate = 1 is obtained by dividing refresh_en_drain = 1. For example, the first standby refresh signal refreshes read_vd 16 times (assuming a 16 - frequency division), and the second standby refresh signal refreshes read_vg only 1 time. Since the leakage voltage of read_vg is very small, power consumption during standby can be saved.

[0100] Specifically, set the frequency division parameters according to actual needs, such as 32 - frequency division or others.

[0101] In an optional implementation manner, as Figure 4 、 5 shown in Figure 6, each memory array is provided with a third switch and a fourth switch;

[0102] One end of the third switch is electrically connected to the memory array, and the other end of the third switch is used to receive the write - operation supply voltage write_power;

[0103] One end of the fourth switch is electrically connected to the memory array, and the other end of the third switch is electrically connected to the output end of the read - operation voltage generation unit.

[0104] Taking the memory array Array0 as an example, its third switch is S0 and its fourth switch is S0B. Taking the memory array ArrayN as an example, its third switch is SN and its fourth switch is SNB. One end of the third switch is electrically connected to the memory array, and the other end of the third switch is used to receive the write - operation supply voltage write_power; one end of the fourth switch is electrically connected to the memory array, and the other end of the fourth switch is electrically connected to the output end of the read - operation voltage generation unit and is used to receive the read - operation voltage read_power.

[0105] Embodiment 2

[0106] This embodiment provides a Nor Flash read - operation module. As Figure 8 shown, the Nor Flash read - operation module includes a read - operation signal generation circuit 6. The read - operation signal generation circuit 6 is used to generate a read - operation signal read_en; the Nor Flash read - operation module further includes the power - supply circuit of the Nor Flash read - operation module provided in Embodiment 1.

[0107] The Nor Flash read operation module of the embodiment includes the power supply circuit of the Nor Flash read operation module in Embodiment 1. The read operation voltage read_power provided by the power supply circuit of the Nor Flash read operation module is standby read operation standby voltage in standby and read operation working voltage in read active. Since the actual difference between the standby read operation standby voltage and the read operation working voltage is less than or equal to the first preset value, the values are basically equal in the two different states. When the Nor Flash is switched from any moment of standby state to read operation state, the read operation voltage is stable and will not change with the chip power supply voltage of the Nor Flash. The problem that the read operation working voltage is sensitive to the change of the chip power supply voltage of the Nor Flash due to the large difference between the standby read operation standby voltage and the read operation working voltage in the existing read operation module is solved, and the high-speed reading of the Nor Flash read operation module is ensured.

[0108] Embodiment 3

[0109] The embodiment provides a Nor Flash, as shown in the figure. Figure 9 The Nor Flash includes the Nor Flash read operation module provided in Embodiment 2 and a storage array module composed of a plurality of storage arrays.

[0110] The Nor Flash of the embodiment includes the Nor Flash read operation module in Embodiment 2. The read operation voltage read_power provided by the power supply circuit of the Nor Flash read operation module is standby read operation standby voltage in standby and read operation working voltage in read active. Since the actual difference between the standby read operation standby voltage and the read operation working voltage is less than or equal to the first preset value, the values are basically equal in the two different states. When the Nor Flash is switched from any moment of standby state to read operation state, the read operation voltage is stable and will not change with the chip power supply voltage of the Nor Flash. The problem that the read operation working voltage is sensitive to the change of the chip power supply voltage of the Nor Flash due to the large difference between the standby read operation standby voltage and the read operation working voltage in the existing read operation module is solved, the high-speed reading of the Nor Flash read operation module is ensured, and the stability of the Nor Flash is improved.

[0111] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to the embodiments without departing from the principles and essence of the present disclosure, and such changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A power supply circuit for a Nor Flash read operation module, characterized in that, The Nor Flash comprises a storage array module consisting of several storage arrays; The power supply circuit includes a first charge pump unit, a second charge pump unit, and a read operation voltage generation unit; The read operation voltage generation unit is electrically connected to the first charge pump unit, the second charge pump unit, and the storage array module, respectively. The first charge pump unit is used to convert the chip power supply voltage of the Nor Flash to a first voltage and output it to the read operation voltage generation unit based on the read operation signal and the first standby refresh signal; The second charge pump unit is used to convert the chip power supply voltage into a second voltage and output it to the read operation voltage generation unit based on the read operation signal and the second standby refresh signal; The read operation voltage generating unit is used to output a read operation voltage to the storage array module based on the first voltage and the second voltage, so as to provide the storage array module with the read operation standby voltage of the Nor Flash in standby state or the read operation working voltage in read operation state. Wherein, the actual difference between the standby voltage of the read operation and the working voltage of the read operation is less than or equal to a first preset value.

2. The power supply circuit according to claim 1, characterized in that, The read operation voltage generation unit includes a capacitor and a first MOS transistor, a second MOS transistor and a first switch; The width-to-length ratio of the second MOS transistor is greater than that of the first MOS transistor; The output terminal of the second charge pump unit is electrically connected to the gate of the first MOS transistor and the gate of the second MOS transistor, respectively. The drain of the first MOS transistor is electrically connected to the output terminal of the first charge pump unit; The drain of the second MOS transistor is electrically connected to the output terminal of the first charge pump unit via the first switch; The source of the first MOS transistor and the source of the second MOS transistor are electrically connected to the memory array module, respectively. One end of the capacitor is electrically connected to the output terminal of the second charge pump unit, and the other end of the capacitor is grounded.

3. The power supply circuit according to claim 2, characterized in that, The read operation voltage generation unit also includes a second switch and a current source; One end of the current source is grounded, and the other end of the current source is electrically connected to one end of the second switch; The other end of the second switch is electrically connected to the source of the second MOSFET; The current value output by the current source is the same as the current value flowing through the second MOS transistor when the target memory cell in the target memory array is in the read operation state.

4. The power supply circuit according to claim 3, characterized in that, The standby state includes standby without refresh state and standby refresh state; When the Nor Flash is in a standby no-refresh state, the read operation signal is invalid, the first standby refresh signal and the second standby refresh signal are both invalid, the first switch and the second switch are both in the off state, and the current voltage difference between the first voltage and the read operation voltage is greater than or equal to the second preset value. Alternatively, when the Nor Flash is in standby refresh state, the read operation signal is invalid. If the current voltage difference between the first voltage and the read operation voltage is less than the second preset value, then both the first standby refresh signal and the second standby refresh signal are valid, the first switch and the second switch are both closed, and the first charge pump unit and the second charge pump unit are in working state, so that the current voltage difference is greater than or equal to the second preset value.

5. The power supply circuit according to claim 3, characterized in that, When the Nor Flash is in read operation mode, the read operation signal is valid, the first standby refresh signal and the second standby refresh signal are invalid, the first switch and the second switch are both closed, and the first charge pump unit and the second charge pump unit are both in working mode, so that the current voltage difference between the first voltage and the read operation voltage is greater than or equal to the second preset value.

6. The power supply circuit according to claim 1, characterized in that, The power supply circuit also includes a voltage detection unit; The voltage detection unit is electrically connected to the first charge pump unit, the second charge pump unit, and the read operation voltage generation unit, respectively. The voltage detection unit is used to detect the current voltage difference between the first voltage and the read operation voltage, and based on the read operation signal and the current voltage difference, to set both the first standby refresh signal and the second standby refresh signal to an invalid state or an effective state.

7. The power supply circuit according to claim 1, characterized in that, The power supply circuit also includes a frequency divider; The frequency divider is used to receive the first standby refresh signal, perform a frequency division operation, and then output the second standby refresh signal.

8. The power supply circuit according to claim 1, characterized in that, Each storage array is equipped with a third switch and a fourth switch; One end of the third switch is electrically connected to the storage array, and the other end of the third switch is used to receive the write operation power supply voltage; One end of the fourth switch is electrically connected to the storage array, and the other end of the fourth switch is electrically connected to the output terminal of the read operation voltage generating unit.

9. A Nor Flash read operation module, characterized in that, The Nor Flash read operation module includes a read operation signal generation circuit, which is used to generate a read operation signal. The Nor Flash read operation module further includes a power supply circuit for the Nor Flash read operation module as described in any one of claims 1-8.

10. A Nor Flash memory, characterized in that, The Nor Flash includes the Nor Flash read operation module as described in claim 9 and a storage array module consisting of several storage arrays.

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