Power supply reverse connection prevention circuit and solid state disk

Abstract

The invention relates to the technical field of emergency protection circuit devices, and discloses a power supply reverse connection prevention circuit and a solid state disk. The circuit comprises an input voltage polarity detection unit, a transient jitter filtering and delay integration unit, a bistable latch control unit and a main power switch unit, reverse connection duration is discriminated through delay integral, latch protection is triggered only when a preset threshold value is exceeded, and power supply is cut off. The solid state disk integrates the circuits and is located between a power interface and a core function module, reliable isolation of real reverse connection faults is achieved, and meanwhile instantaneous jitter false triggering is avoided. The scheme has the advantages of high stability, low power consumption and strong environmental adaptability, and the reliability and safety of the solid state disk in a complex power supply scene are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of emergency protection circuit devices, and particularly relates to a power reverse connection prevention circuit and a solid state disk. BACKGROUND

[0002] With the increasing requirements of data centers and enterprise-level storage systems for high availability and maintenance convenience, solid state disks (SSDs) supporting hot plugging have become key components in servers and storage arrays. The hot plugging function allows storage devices to be inserted or removed during system operation without interrupting the overall service, which puts high requirements on power management, signal integrity, and hardware protection mechanisms of the system.

[0003] In such systems, solid state disks are usually connected to the main power supply and data bus through backplane connectors, and the power supply path needs to have multiple safety features such as transient response capability, overcurrent protection, and reverse connection protection.

[0004] The power reverse connection prevention circuit, as a basic link to ensure the reliable operation of the solid state disk, aims to prevent power polarity errors caused by human error or abnormal connector contact.

[0005] Traditional solutions mostly use diodes or unidirectional MOSFETs to achieve reverse connection isolation, although the structure is simple, but there are problems such as large conduction voltage drop, high power consumption, and inability to distinguish between transient jitter and real reverse connection.

[0006] Especially in the hot plugging scenario, the connector often produces millisecond-level voltage polarity reversal or power glitches due to mechanical bounce during insertion. Such transient disturbances are easily misjudged as continuous reverse connection faults by traditional reverse connection prevention circuits, triggering unnecessary shutdown actions, not only interrupting the normal power-on process, but also possibly causing power bus oscillation, affecting the stability of other devices on the backplane.

[0007] Although the hot plugging controller in the prior art can provide surge current limiting and overcurrent protection, its reverse connection prevention function is usually designed independently and operates independently. When both exist in the same power supply path, there is a lack of cooperative control logic, making it difficult to suppress power-on impact while accurately identifying and responding to real power reverse connection events.

[0008] In addition, most solutions do not have an effective state feedback mechanism, making it difficult for maintenance personnel to locate the root cause of the fault.

[0009] Therefore, in high-density storage systems that support hot plugging, there is an urgent need for a power protection architecture that can integrate reverse connection prevention and hot plugging control functions, have intelligent discrimination capabilities, and enable system-level cascading, in order to balance safety, reliability, and maintainability. SUMMARY

[0010] The technical problem solved by the present application is to provide a power reverse connection prevention circuit and a solid state disk, aiming to overcome the power reverse connection mis-protection and system power oscillation caused by connector transient jitter in hot plug application scenarios.

[0011] To solve the above technical problems, the present application provides a power reverse connection prevention circuit, which integrates a judgment logic with transient jitter filtering and delay integration functions, and combines a bistable latch control unit to identify the duration of power polarity abnormal events.

[0012] Only when the duration of the reverse connection state exceeds the preset time threshold that can cover the typical connector jitter time, the circuit triggers an irreversible latch protection action to cut off the main power path.

[0013] This design ensures that the circuit does not respond to short-term, non-destructive power fluctuations, maintaining the stability of the hot plug process, while providing a definite and reliable protection for real, continuous reverse connection faults.

[0014] The present application provides a power reverse connection prevention circuit, which includes: An input voltage polarity detection unit, a transient jitter filtering and delay integration unit, a bistable latch control unit, and a main power switch unit.

[0015] The input end of the input voltage polarity detection unit is electrically connected with the external power input end, for real-time monitoring of the polarity of the input voltage, and outputting an original polarity state signal according to the monitoring result.

[0016] The input end of the transient jitter filtering and delay integration unit is electrically connected with the output end of the input voltage polarity detection unit, for receiving the original polarity state signal, and integrating the time length of the reverse connection state represented by the signal, and outputting a confirmed fault trigger signal only when the duration of the reverse connection state reaches the preset time threshold.

[0017] The set input end of the bistable latch control unit is electrically connected with the output end of the transient jitter filtering and delay integration unit, for flipping its output state to a locked protection state and outputting an off control signal after receiving the confirmed fault trigger signal.

[0018] The control end of the main power switch unit is electrically connected with the output end of the bistable latch control unit, and its main current path is connected in series between the external power input end and the protected power output end of the circuit, for disconnecting its main current path and interrupting the power supply to the subsequent circuit after receiving the off control signal.

[0019] Further, the input voltage polarity detection unit comprises a precision voltage comparator and a reference voltage generation circuit.

[0020] The reference voltage generation circuit is configured to generate a reference voltage of zero potential or close to zero potential and apply it to one input terminal of the precision voltage comparator.

[0021] The other input terminal of the precision voltage comparator is connected to the external power supply input terminal through a voltage dividing resistor network.

[0022] When the voltage of the external power supply input terminal is positive, the precision voltage comparator outputs a first logic level of original polarity state signal; When the voltage of the external power supply input terminal is negative, the precision voltage comparator outputs a second logic level of original polarity state signal.

[0023] Further, the transient jitter filtering and delay integration unit comprises a resistor-capacitor integration network composed of a first resistor and a first capacitor in series, and a threshold flip-flop.

[0024] The input terminal of the resistor-capacitor integration network receives the original polarity state signal.

[0025] One end of the first capacitor is grounded, and the other end is connected to one end of the first resistor and the input terminal of the threshold flip-flop at the same time.

[0026] The second logic level in the original polarity state signal representing the reverse connection state charges the first capacitor through the first resistor.

[0027] The threshold flip-flop has a preset trigger voltage threshold.

[0028] When the voltage across the first capacitor reaches or exceeds the trigger voltage threshold due to continuous charging, the output state of the threshold flip-flop flips, thereby generating the confirmed fault trigger signal.

[0029] The time constant determined by the product of the resistance value of the first resistor and the capacitance value of the first capacitor defines the preset time threshold.

[0030] As an embodiment of the present application, the set value of the preset time threshold is greater than the maximum duration of power supply polarity reversal caused by physical connector jitter during hot plug of the solid state disk, and less than the minimum reverse connection duration that can cause irreversible damage to the internal circuit of the solid state disk.

[0031] The specific numerical range of the preset time threshold is 1 millisecond to 10 milliseconds.

[0032] Further, the bistable latch control unit is a set-reset latch composed of two cross-coupled NAND gates or NOR gates.

[0033] The set input of the set-reset latch is connected to the output of the threshold flip-flop.

[0034] The set-reset latch further comprises a reset input connected to the output of a power-on reset signal generation circuit.

[0035] The power-on reset signal generation circuit is configured to generate a short reset pulse signal for initializing the set-reset latch to an unprotected on state when detecting that the external input power supply rises from zero voltage or below an under-voltage lockout threshold to a normal operating voltage range.

[0036] Once the set input receives the confirmed fault trigger signal, the output state of the set-reset latch is locked in the protected state until the next reset pulse signal generated by the power-on reset signal generation circuit arrives.

[0037] Further, the main power switch unit is an N-channel metal oxide semiconductor field effect transistor.

[0038] The source of the N-channel metal oxide semiconductor field effect transistor is connected to the external power input, and the drain is connected to the protected power output. The circuit further comprises a gate drive circuit.

[0039] The input of the gate drive circuit is electrically connected to the output of the bistable latch control unit, and the output is connected to the gate of the N-channel metal oxide semiconductor field effect transistor.

[0040] The gate drive circuit is configured to provide an on voltage higher than the source voltage of the gate or an off voltage equal to the source voltage of the gate according to the output state of the bistable latch control unit.

[0041] As an embodiment of the present application, the gate drive circuit comprises a charge pump circuit and a control switch.

[0042] The charge pump circuit is composed of a clock oscillator, a plurality of diodes, and a plurality of capacitors, and is configured to boost the input power voltage to generate a driving voltage higher than the voltage of the external power input.

[0043] The control switch is controlled by the off control signal output by the bistable latch control unit, and in the non-protection state, the driving voltage is applied to the gate of the N-channel metal oxide semiconductor field effect transistor to make it fully conductive; in the protection state, the gate of the N-channel metal oxide semiconductor field effect transistor is short-circuited with the source to make it fully off.

[0044] According to another aspect of the present application, a solid state disk is provided, comprising a power interface, a main controller, a non-volatile storage array, a data buffer, and the anti-reverse connection circuit of any one of the preceding aspects.

[0045] The external power input end of the anti-reverse connection circuit is electrically connected with the power pin of the power interface.

[0046] The protected power output end of the anti-reverse connection circuit uniformly provides working power for the main controller, the non-volatile storage array, and the data buffer.

[0047] The anti-reverse connection circuit is integrated on the main printed circuit board of the solid state disk between the power interface and the main functional circuit.

[0048] Compared with the prior art, the present application has the following beneficial effects: 1. By introducing the transient jitter filtering and delay integration unit, the protection circuit of the present application has time dimension perception ability for fault events, can accurately distinguish between the connector jitter reverse connection which is harmless in the hot plug process and the persistent power reverse connection fault which is actually destructive, fundamentally eliminates the false protection action caused by transient jitter, and guarantees the success rate of hot plug operation and the online stability of the system.

[0049] 2. The application of the bistable latch control unit ensures that once a real persistent reverse connection fault is detected, the protection state is decisively locked, and the power supply to the sensitive circuit at the back end is completely cut off until the system is completely powered off and powered on again. This latch mechanism avoids the oscillation between protection and recovery that may occur in the circuit under critical fault conditions, provides definite and one-way protection logic, and greatly improves the protection reliability of the core components of the solid state disk.

[0050] 3. By using an N-channel metal oxide semiconductor field effect transistor with low on-resistance as the main power switch unit and providing it with a dedicated gate drive circuit containing a charge pump, the present application ensures that the power path has extremely low energy loss and voltage drop in the normal working mode while achieving reliable protection, maintains the overall energy efficiency of the solid state disk, reduces the working temperature, and meets the stringent requirements of high-performance storage devices for power integrity.

[0051] 4. The entire reverse power connection protection circuit is integrated inside the solid-state drive, forming a self-sustaining, front-end protection barrier. This makes the solid-state drive itself immune to harsh power environments, eliminating the need to rely on external backplanes or host systems for protection, thus enhancing the environmental adaptability and versatility of solid-state drive products. Attached Figure Description

[0052] Figure 1 This is a schematic diagram of the overall technical solution architecture of the anti-reverse power connection circuit and solid-state drive proposed in this invention. Figure 2 This is a schematic diagram of the core principle framework of transient jitter filtering and delayed integration with bistable latch control in this invention; Figure 3 This is a flowchart illustrating the logic flow of input voltage polarity detection and original state signal generation in this invention. Figure 4 This is a flowchart of the delay integral determination logic composed of the resistor-capacitor integral network and the threshold trigger in this invention. Figure 5 This is a schematic diagram illustrating the interaction between the bistable latch control unit and the power-on reset mechanism, as well as the state locking principle in this invention. Figure 6 This is a schematic diagram of the power supply path control framework of the main power switching unit and its gate drive circuit (including charge pump) in this invention. Detailed Implementation

[0053] Please refer to Figures 1 to 6 This invention provides a reverse power supply circuit and a solid-state drive. Its core is to solve the problem of false protection and system power oscillation caused by instantaneous power polarity reversal due to connector physical jitter during hot-plugging by introducing a time-dimensional fault identification mechanism.

[0054] The circuit structure consists of an input voltage polarity detection unit, a transient jitter filtering and delay integration unit, a bistable latch control unit, and a main power switching unit. A strict signal transmission link is formed between the units to ensure that irreversible protection action is triggered only when a persistent reverse connection fault is confirmed.

[0055] The input terminal of the input voltage polarity detection unit is directly connected to the external power supply input terminal to monitor the polarity state of the input voltage in real time.

[0056] This unit contains a precision voltage comparator and a reference voltage generation circuit.

[0057] The reference voltage generation circuit is configured to output a reference voltage at or near zero potential and apply it to the non-inverting input of a precision voltage comparator.

[0058] The inverting input of the precision voltage comparator is connected to the external power input through a voltage divider network composed of two high-precision resistors.

[0059] When the external power input presents positive polarity, the voltage output by the voltage divider network is higher than the reference voltage, and the precision voltage comparator outputs a first logic level, defined as low level; When the external power input presents negative polarity, the voltage output by the voltage divider network is lower than the reference voltage, and the precision voltage comparator outputs a second logic level, defined as high level.

[0060] The original polarity state signal serves as the initial criterion for subsequent processing, and the definition of its logic level ensures that the reverse connection state is represented in the form of high level, facilitating the charging operation of the subsequent integration network.

[0061] The transient jitter filtering and delay integration unit receives the original polarity state signal from the input voltage polarity detection unit and performs time accumulation processing on the high level in the signal representing the reverse connection state.

[0062] This unit is composed of a resistance-capacitance integration network and a threshold flip-flop.

[0063] The resistance-capacitance integration network includes a first resistor and a first capacitor connected in series, where one end of the first resistor receives the original polarity state signal, the other end is connected to one end of the first capacitor, and the other end of the first capacitor is grounded.

[0064] The input end of the threshold flip-flop is connected to the common node of the first resistor and the first capacitor.

[0065] When the original polarity state signal is at low level, the first capacitor discharges through the first resistor, and the voltage across the two terminals is maintained at low level; when the original polarity state signal is at high level, the first resistor charges the first capacitor with constant current, and the voltage across the two terminals of the first capacitor rises exponentially with time.

[0066] The threshold flip-flop has a fixed trigger voltage threshold set inside, which corresponds to the capacitor charging voltage at the preset time threshold.

[0067] Only when the voltage across the two terminals of the first capacitor reaches or exceeds the trigger voltage threshold, the output state of the threshold flip-flop will flip, from low level to high level, thereby generating a confirmed fault trigger signal.

[0068] The resistance value of the first resistor and the capacitance value of the first capacitor jointly determine the time constant of the integration process , which is the core parameter of the preset time threshold.

[0069] The setting of the preset time threshold must satisfy the dual constraint conditions: The value must be greater than the maximum duration of power polarity reversal caused by mechanical connector jolt during hot plug process of solid state drive, and must be less than the minimum duration of reversible electromigration or gate oxide breakdown of integrated circuits inside solid state drive.

[0070] According to the measured data of typical SATA or U.2 interface solid state drive hot plug process, the duration of instantaneous reversal caused by connector jolt is usually no more than 500 microseconds, while the lower limit of reversal duration which can cause substantial damage to CMOS process controller chip is about 5 milliseconds. Therefore, the specific value range of preset time threshold is limited between 1 millisecond and 10 milliseconds.

[0071] Within this range, 3 milliseconds is preferred as the typical design value, which is sufficient to cover the jolt period of most industrial connectors under vibration or non-ideal insertion conditions, while far below the safe tolerance limit of semiconductor devices.

[0072] The set input of the bistable latch control unit is connected to the output of the threshold flip-flop for receiving the confirmed fault trigger signal.

[0073] The unit adopts a set-reset latch structure composed of two cross-coupled NAND gates.

[0074] The set-reset latch has two stable states: Non-protection state and protection state.

[0075] In the non-protection state, the latch output is low to turn off the control signal; In the protection state, the latch output is high to turn off the control signal.

[0076] The set input of the set-reset latch receives a high level signal from the threshold flip-flop. Once the signal is valid, the latch immediately flips to the protection state and latches, even if the subsequent threshold flip-flop output returns to low level, the latch state does not change.

[0077] The reset input of the set-reset latch is connected to the output of the power-on reset signal generation circuit. The power-on reset signal generation circuit is composed of an undervoltage lockout comparator, a delay capacitor and an inverter.

[0078] The reference voltage of the undervoltage lockout comparator is set to 90% of the normal operating voltage of the system, for example, for a 12-volt power supply system, the reference voltage is set to 10.8 volts.

[0079] When the external input power supply starts to rise from zero voltage, the undervoltage lockout comparator outputs high level when the voltage is lower than 10.8 volts, and low level after the inverter; When the voltage stabilizes over 10.8 volts and maintains for enough time to complete the charging of the delay capacitor, the under-voltage lockout comparator output flips to low level, the inverter output generates a short high level pulse, which acts as a reset signal to the reset input of the set-reset latch, forcing it to initialize to the non-protected state.

[0080] The reset mechanism ensures that the protection circuit is in the on standby state every time the system is powered on, avoiding new power-on failure caused by historical fault state.

[0081] The control end of the main power switch unit is connected to the output end of the bistable latch control unit, and its main current path is connected in series between the external power input end and the protected power output end.

[0082] The unit uses an N-channel metal oxide semiconductor field effect transistor as a power switch device.

[0083] The source of the N-channel metal oxide semiconductor field effect transistor is connected to the external power input end, and the drain is connected to the protected power output end, providing a unified working power supply for the main controller, non-volatile storage array and data buffer of the solid state disk.

[0084] Since the conduction condition of the N-channel device requires the gate voltage to be higher than the source voltage, and the source voltage is the input power voltage, a dedicated gate drive circuit must be provided to provide a driving level higher than the input voltage.

[0085] The gate drive circuit includes a charge pump circuit and a control switch. The charge pump circuit is composed of a clock oscillator composed of a ring oscillator, three diodes and two flying capacitors.

[0086] The clock oscillator generates a square wave signal with a frequency of 100 kHz to drive the flying capacitors to alternately charge and discharge, and the input power voltage is boosted to about 1.8 times the driving voltage through the diode rectifier network.

[0087] The control switch is composed of two complementary MOSFETs, and its control end receives the off control signal output by the bistable latch control unit.

[0088] In the non-protected state, the off control signal is low, and the control switch applies the driving voltage generated by the charge pump to the gate of the N-channel metal oxide semiconductor field effect transistor, so that the gate-source voltage difference reaches more than 10 volts, ensuring that the device is fully on and the on-resistance is less than 5 mΩ.

[0089] In the protected state, the off control signal is high, and the control switch shorts the gate of the N-channel metal oxide semiconductor field effect transistor to its source, the gate-source voltage difference is 0, the device is completely off, and the leakage current is less than 1 μA.

[0090] The driving scheme ensures reliable turn-off while minimizing the conduction loss during normal operation, avoiding the extra power consumption caused by the body diode voltage drop in the traditional P-channel scheme.

[0091] The entire anti-reverse connection circuit is integrated on the main printed circuit board of the solid state disk, on the power supply wiring between the power supply interface pad and the main controller power supply pin.

[0092] All passive components of the circuit use 0402 packaging to save space. The precision voltage comparator, threshold trigger, and set-reset latch are integrated into the same analog front-end chip. The charge pump and clock oscillator are integrated into the gate drive dedicated chip.

[0093] The N-channel metal oxide semiconductor field effect transistor is selected with a withstand voltage of 30 volts and a continuous drain current of 20 amperes to cope with possible surge current.

[0094] This layout ensures that the protection circuit is adjacent to the power supply inlet and can complete the shutdown action before the fault current enters the core functional circuit.

[0095] In the actual scenario of hot plug operation, when the solid state disk is inserted into the backplane connector, due to the elastic collision of the metal contacts, the power supply pin may appear multiple short-term contacts and separations, causing the input voltage to rapidly switch between positive and negative polarity.

[0096] During this process, the input voltage polarity detection unit outputs a series of high-level pulses with a width less than 500 microseconds.

[0097] These pulses act on the RC integration network, but since the duration is much less than the preset time threshold, the first capacitor cannot be charged to the trigger voltage threshold, the threshold trigger maintains a low-level output, the bistable latch control unit maintains the non-protection state, and the main power switch unit remains on, the system power supply is not affected.

[0098] If a real reverse connection of the power cable occurs, the input voltage will maintain a negative polarity for a long time, and the original polarity state signal will continuously output a high level.

[0099] After 3 milliseconds of integration time, the first capacitor voltage reaches the threshold, the threshold trigger outputs a high level, the bistable latch control unit flips and locks to the protection state, and the main power switch unit immediately turns off, completely isolating the reverse connection power supply from the back-end circuit.

[0100] After that, even if the power polarity is corrected manually, the circuit will remain off due to the latch in the self-locking state. It must be completely powered off and re-powered, and the reset pulse must be sent by the power-on reset signal generation circuit to remove the protection state and restore power supply.

[0101] This mechanism eliminates the possibility of repeated on-off oscillation under critical fault conditions, and provides deterministic unidirectional protection logic.

[0102] Time constant of the resistive-capacitive network defined by the equation wherein is the resistance value of the first resistor, is the capacitance value of the first capacitor. Trigger voltage threshold is related to the time threshold by the capacitor charging equation: ; wherein is the voltage amplitude of the high level of the original polarity state signal, usually 3.3 volts or 5 volts. By setting to be 63.2% of , it can be made that is exactly equal to . In actual design, is taken as 100 kilo-ohms, is taken as 30 nano-farads, then is 3 milliseconds, which meets the requirement of the preset time threshold.

[0103] The threshold trigger adopts a hysteresis comparator structure, and there is a 50 millivolt hysteresis between the positive threshold voltage and the negative threshold voltage to prevent the output from jittering due to noise interference near the trigger voltage. This hysteresis characteristic ensures that the edge of the confirmed fault trigger signal is steep and unique, avoiding injecting an uncertain state into the bistable latch control unit.

[0104] The delay capacitor in the power-on reset signal generation circuit is taken as 100 pico-farads, and the equivalent resistance at the output end of the under-voltage lockout comparator constitutes a delay time of about 10 microseconds, ensuring that the reset pulse is sent only after the power supply voltage is stable, preventing accidental release of the protection state caused by early reset during the power supply ramp-up process.

[0105] The output voltage ripple of the charge pump circuit is limited within 200 millivolts peak-to-peak, and filtering is achieved by connecting a 10 micro-farad ceramic capacitor in parallel at the driving voltage output end. This low ripple characteristic ensures the stability of the N-channel metal oxide semiconductor field effect transistor gate voltage, avoiding changes in the on-resistance caused by fluctuations in the driving voltage, which in turn affects the power integrity.

[0106]

[0106] In summary, the application introduces time dimension into the power polarity fault judgment logic, and constructs the anti-reverse connection protection mechanism with the jitter immunity. The mechanism quantitatively discriminates the duration of the fault event at the physical layer, combines the irreversible protection characteristics of the bistable latch and the efficient and low-loss power switch design, realizes the comprehensive protection of the solid state disk under the hot plug and abnormal power supply environment, and improves the reliability and environmental adaptability of the product.

[0107] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0108] Although the embodiments of the present application have been shown and described, it is to be understood that various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A circuit for preventing reverse power connection, characterized in that, The application relates to a power supply polarity detection and protection circuit. The application comprises: an input voltage polarity detection unit for monitoring the voltage polarity of an external power supply input in real time and outputting an original polarity state signal according to the monitoring result; a transient jitter filtering and delay integration unit for receiving the original polarity state signal and performing time integration accumulation on the signal representing the reverse connection state, and outputting a confirmed fault trigger signal only when the duration of the reverse connection state reaches a preset time threshold; a bistable latch control unit, the set input end of which is electrically connected with the output end of the transient jitter filtering and delay integration unit, for locking the output state to a protection state after receiving the confirmed fault trigger signal and outputting a shutdown control signal; 2. The reverse battery connection prevention circuit of claim 1, wherein, a main power switch unit, the control end of which is electrically connected with the output end of the bistable latch control unit, and the main current path of which is connected in series between the external power supply input and a protected power supply output, for breaking the main current path and interrupting the power supply of subsequent circuits after receiving the shutdown control signal. The input voltage polarity detection unit comprises a precision voltage comparator and a reference voltage generation circuit; the reference voltage generation circuit is used for generating a reference voltage of zero potential or close to zero potential and applying the reference voltage to one input end of the precision voltage comparator; the other input end of the precision voltage comparator is connected to the external power supply input through a voltage dividing resistor network; when the external power supply input is of positive polarity, the precision voltage comparator outputs a first logic level; 3. The reverse battery connection prevention circuit of claim 1, wherein when the external power supply input is of negative polarity, the precision voltage comparator outputs a second logic level as the original polarity state signal. The transient jitter filtering and delay integration unit comprises a resistance-capacitance integration network composed of a first resistor and a first capacitor and a threshold flip-flop; the input end of the resistance-capacitance integration network receives the original polarity state signal, one end of the first capacitor is grounded, and the other end is connected to one end of the first resistor and the input end of the threshold flip-flop; the second logic level representing the reverse connection state in the original polarity state signal charges the first capacitor through the first resistor; when the voltage across the first capacitor reaches or exceeds the trigger voltage threshold of the threshold flip-flop, the output state of the threshold flip-flop is reversed to generate the confirmed fault trigger signal; 4. The reverse battery protection circuit of claim 3, wherein, the product of the resistance value of the first resistor and the capacitance value of the first capacitor defines the preset time threshold.

5. The reverse battery protection circuit of claim 1, wherein, The preset time threshold is greater than the maximum duration of the power supply polarity reversal caused by the connector jitter in the hot plug process of the solid state disk and is less than the minimum reverse connection duration causing irreversible damage to the internal circuit of the solid state disk. The bistable latch control unit is a set-reset latch composed of two cross-coupled NAND gates; the set input end of the set-reset latch is connected to the output end of the threshold flip-flop, and the reset input end is connected to the output end of a power-on reset signal generation circuit; the power-on reset signal generation circuit is used for generating a reset pulse signal to initialize the set-reset latch to a non-protection state when the external input power supply is stably raised from an under-voltage state to a normal working voltage range.

6. The reverse battery protection circuit of claim 1, wherein The main power switch unit is an N-channel metal oxide semiconductor field effect transistor; The source of the N-channel metal oxide semiconductor field effect transistor is connected to the external power input terminal, and the drain is connected to the protected power output terminal; The circuit further comprises a gate drive circuit, the input of which is electrically connected to the output of the bistable latch control unit, and the output is connected to the gate of the N-channel metal oxide semiconductor field effect transistor.

7. The reverse battery protection circuit of claim 6, wherein, The gate drive circuit comprises a charge pump circuit and a control switch; The charge pump circuit is composed of a clock oscillator, a plurality of diodes and a plurality of capacitors, which is used to boost the input power voltage to generate a driving voltage higher than the voltage of the external power input terminal; The control switch is controlled by the off control signal output by the bistable latch control unit, and in the non-protection state, the driving voltage is applied to the gate of the N-channel metal oxide semiconductor field effect transistor, and in the protection state, the gate of the N-channel metal oxide semiconductor field effect transistor is short-circuited with its source.

8. The reverse battery protection circuit of claim 5, wherein, The threshold trigger adopts a hysteresis comparator structure, which has a 50 millivolt hysteresis between the positive threshold voltage and the negative threshold voltage, to prevent output jitter caused by noise interference near the trigger voltage.

9. A solid state drive, comprising: It comprises: a power interface, a main controller, a non-volatile storage array, a data buffer, and a reverse connection protection circuit as claimed in any one of claims 1 to 8; The external power input terminal of the reverse connection protection circuit is electrically connected to the power pin of the power interface; The protected power output terminal of the reverse connection protection circuit provides working power for the main controller, the non-volatile storage array and the data buffer; The reverse connection protection circuit is integrated on the main printed circuit board of the solid state disk and located between the power interface and the main functional circuit.

10. The solid state drive of claim 9, wherein, The passive components in the reverse connection protection circuit adopt 0402 packaging, the input voltage polarity detection unit, the transient jitter filtering and delay integration unit and the bistable latch control unit are integrated on the same analog front-end chip, and the gate drive circuit is integrated on a dedicated gate drive chip.

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