A pulse stable output control method and system of an ns-level high-repetition-rate fast pulse power supply

Abstract

The application discloses a pulse stable output control method and system of an ns-level high-repetition-frequency fast pulse power supply, and relates to the technical field of automatic control. The system is composed of a plurality of function modules, and comprises: an adaptive absorption module which acquires power supply parameters, including load impedance and switch tube parasitic parameters, through real-time sampling, and dynamically optimizes R, C parameters of an RCD absorption circuit and an active clamp circuit based on the power supply parameters; a feedforward prediction module which extracts derived state information according to the power supply parameters, acquires load current feedforward and resonant loop state based on the derived state information, models based on the load current feedforward and the resonant loop state, and predicts a switch tube drain-source voltage valley time; and a multi-section variable impedance transmission module which adopts a three-section variable impedance structure, performs wide-band impedance matching based on the optimized R, C parameters of the RCD absorption circuit and the active clamp circuit, suppresses pulse front edge reflection distortion, and outputs a distortion-free pulse signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of automatic control, in particular to a pulse stable output control method and system of an ns-level high-repetition-rate fast pulse power supply. BACKGROUND

[0002] The high-repetition-rate fast pulse power supply is a special power supply with high repetition frequency and fast pulse dynamic characteristics, which can continuously output narrow pulse width, steep front and back edges, and high power density of electric energy. The essence is to convert conventional electric energy into short-time, high-intensity and high-frequency pulse electric energy through precise circuit control, break through the energy transmission limitation of traditional continuous wave power supply, and widely apply to frontier fields such as scientific research exploration and high-end manufacturing based on the characteristics of short pulse, high frequency and low heat damage. It is the core power source of key equipment and the key basic equipment for technological breakthrough in frontier science and technology fields such as chip manufacturing and quantum physics. Its performance directly determines the accuracy, efficiency and reliability of the downstream system.

[0003] The traditional ns-level high-repetition-rate fast pulse power supply technology still has multi-dimensional bottlenecks, which is difficult to meet the needs of high-end scenes for stability, efficiency and precision. The R and C parameters of the RCD snubber circuit and the active clamp circuit are mostly fixed values, which cannot dynamically respond to the load impedance, such as the real-time changes of the plasma load time-varying impedance and the parasitic parameters of the switching tube, the parasitic capacitance and the parasitic inductance of the drain-source parasitic capacitance, which leads to unstable voltage spike suppression effect, such as high peak voltage or energy loss of the peak suppression device when the load suddenly changes, and single working condition of static parameter adaptation. At the same time, the voltage sharing and current sharing of high-power scenes are difficult for IGBT and other switching devices, which are easy to damage due to uneven stress of the devices. The traditional method is directly based on the original power supply parameter calculation, and does not consider the influence of impedance dynamic change rate and parasitic parameter coupling characteristics, which leads to large prediction deviation of load current peak value and rising slope. Most of them use fixed impedance matching scheme, which cannot adapt to the pulse characteristics of different frequency components in wide frequency band, and is easy to produce front reflection distortion at the transmission interface. SUMMARY

[0004] In order to achieve the above purpose, the present application is realized by the following technical scheme:

[0005] A pulse stable output control system of an ns-level high-repetition-rate fast pulse power supply, comprising:

[0006] An adaptive absorption module acquires power supply parameters through real-time sampling, including load impedance and switching tube parasitic parameters, and dynamically optimizes the R and C parameters of the RCD snubber circuit and the active clamp circuit based on the power supply parameters;

[0007] A feedforward prediction module derives state information from the power supply parameters, obtains load current feedforward and resonant loop state based on the derived state information, models based on the load current feedforward and resonant loop state, and predicts the switch tube drain-source voltage valley bottom time;

[0008] A multi-section variable impedance transmission module adopts a three-section variable impedance structure, performs wideband impedance matching based on the R and C parameters of the optimized RCD absorption circuit and active clamping circuit, and outputs a distortionless pulse signal;

[0009] A cooperative protection module adjusts the dynamic threshold and controls the high-speed circuit based on the distortionless pulse signal and the predicted switch tube drain-source voltage valley bottom time.

[0010] Further, the load impedance is obtained by collecting the voltage and current signals across the load and converting the voltage and current signals into digital sequences.

[0011] The switch tube parasitic parameters include drain-source parasitic capacitance, gate-source and gate-drain parasitic capacitance, and parasitic inductance.

[0012] Further, the process of dynamically optimizing the R and C parameters of the RCD absorption circuit and the active clamping circuit is as follows:

[0013] Based on the power supply parameters, a simulation model is used to simulate the working behavior of the RCD absorption circuit and the active clamping circuit under different R and C parameters, an adaptive intelligent optimization algorithm is used to search for the optimal R and C combination within the preset parameter range, the actual circuit parameters are dynamically adjusted, and the actual working state of the circuit is continuously monitored. Real-time data is fed back to the simulation model for continuous iteration and optimization of the R and C parameters.

[0014] Further, the process of deriving state information from the power supply parameters is as follows:

[0015] The power supply parameters are preprocessed to eliminate sampling noise and timing deviation, effective signal components matching the power supply working frequency band are retained through bandpass filtering, time axis is completely aligned through timing synchronization calibration, and the derived state information is extracted.

[0016] Further, the process of obtaining the load current feedforward and resonant loop state is as follows:

[0017] An adaptive load current feedforward prediction model is constructed with the derived state information as input, and pulse drive characteristics are output. Based on the pulse drive characteristics, the dynamic change rate of the load impedance and the amplitude correlation law of the current are analyzed to predict the peak value, rising edge, falling edge slope, and duration of the current. The coupling characteristics of the switch tube parasitic parameters are used to correct the influence of parasitic effects on current transmission to output the load current feedforward.

[0018] Based on the derived state information, the state of the resonant circuit under the combined effect of the switching transistor parasitic parameters and the load impedance is analyzed; the resonant circuit state frequency is calculated using the switching transistor parasitic parameters, and the resonant energy loss between the resonant circuit state frequency and the power supply operating frequency is determined; the current phase position is determined by the timing correlation characteristics between the load impedance and the switching transistor parasitic parameters; and the resonant circuit state is determined based on the correspondence between the current phase position and the resonant energy loss.

[0019] Furthermore, the process of modeling the load current feedforward and resonant circuit state is as follows:

[0020] Key features such as peak value, rising or falling edge slope, and duration of load current feedforward are extracted; real-time resonant frequency and current phase position parameters of resonant circuit state are extracted; time axis alignment is performed based on timing synchronization mechanism to eliminate timing deviation;

[0021] A collaborative adaptive prediction model for load current feedforward and resonant circuit state is constructed, including time-series correlation modeling and energy change modeling; the phase correlation law between load current feedforward characteristics and resonant circuit is analyzed, the time-series coupling coefficient is quantified, the mapping relationship between current characteristics and phase change is established, and time-series correlation modeling is constructed.

[0022] The relationship between the energy exchange process of the resonant circuit and the rise and fall trend of the drain-source voltage of the switching transistor is analyzed. The influence of load current feedforward on energy loss is combined with dynamic modeling based on the resonant energy state and the rise and fall trend of the drain-source voltage of the switching transistor to construct an energy change model.

[0023] Furthermore, the process of predicting the valley moment of the drain-source voltage of the switching transistor is as follows:

[0024] Leveraging the parallel computing capabilities of FPGAs, the timing correlation model and energy change model are rapidly computed, outputting the dynamic change curve of the drain-source voltage of the switching transistor, with the computation delay controlled within a single pulse cycle. Based on the voltage change curve, the moment when the voltage drop rate slows down, approaches 0, and is about to rise is identified as the drain-source voltage valley. Combined with real-time phase position verification of the resonant circuit, if there is a deviation, the phase correction coefficient is finely adjusted to ensure that the valley moment is completely matched with the energy state of the resonant circuit.

[0025] Furthermore, the process of outputting a distortion-free pulse signal is as follows:

[0026] Wideband impedance matching based on a three-segment variable impedance structure: the input matching segment precisely matches the equivalent output impedance after optimizing the R and C parameters of the preceding stage; the intermediate transition segment achieves a smooth impedance transition with a uniform gradient; and the output matching segment matches the load impedance in real time. The three segments form an impedance transmission link without abrupt changes, and the lengths of the three transmission lines are all based on the characteristic wavelengths of the corresponding operating frequency bands.

[0027] A transmission medium is selected, and a high-frequency compensation structure is added in the intermediate transition section to collect the pulse leading edge morphology and reflection coefficient distortion index in real time. The monitoring data is fed back to the FPGA control unit, and the impedance values ​​of the three-segment structure and the transmission line compensation parameters are dynamically adjusted in combination with the optimized R and C parameters of the previous stage and the load impedance change trend. Based on the predicted timing of the bottom moment of the drain-source voltage of the switching transistor, the output pulse timing is calibrated by delay line fine-tuning technology to ensure that the leading edge trigger moment and the bottom moment are accurately synchronized. After each pulse cycle, the measured waveform of the output pulse is compared with the preset distortion-free standard waveform to quantify the degree of distortion. If the distortion index exceeds the allowable range, the impedance matching algorithm and transmission line compensation parameters are updated by DSP to iteratively optimize the dynamic response characteristics of the three-segment variable impedance structure, and finally output a distortion-free pulse signal.

[0028] Furthermore, the process of dynamic threshold adjustment and high-speed circuit control is as follows:

[0029] Based on both the distortion-free pulse reference characteristics and the timing of the valley moment, the overvoltage threshold and overcurrent threshold are dynamically adjusted. The overvoltage threshold is adjusted based on the pulse amplitude and combined with the valley voltage characteristics. The overcurrent threshold is dynamically set according to the pulse leading edge slope and load current feedforward, with the threshold being relaxed at the valley moment and tightened when it deviates. Both the overvoltage threshold and the overcurrent threshold are linked and adapted to the optimized R and C parameters.

[0030] During normal operation, within the distortion-free pulse timing window, the main switch is controlled to turn on at the valley bottom based on the valley bottom moment, and the active clamp circuit switch is controlled synchronously. In case of abnormality, if the parameter exceeds the threshold, the FPGA outputs a shutdown signal and strengthens RCD absorption. If the valley bottom moment deviates, the turn-on timing is adjusted and the threshold is temporarily tightened.

[0031] Real-time monitoring of control performance; adjustment of thresholds or timing calibration parameters after deviation analysis; solidification of optimized parameters and retention of real-time update channels after each preset pulse cycle.

[0032] A pulse-stabilized output control method for a nanosecond-level high repetition rate fast pulse power supply includes the following steps:

[0033] Step 1: Obtain power supply parameters, including load impedance and parasitic parameters of the switching transistor, through real-time sampling; and dynamically optimize the R and C parameters of the RCD snubber circuit and the active clamping circuit based on the power supply parameters.

[0034] Step 2: Extract derived state information based on power supply parameters, obtain the load current feedforward and resonant circuit state based on the derived state information, model the load current feedforward and resonant circuit state, and predict the time of the bottom of the drain-source voltage of the switching transistor.

[0035] Step 3: Using a three-segment variable impedance structure, based on the optimized R and C parameters of the RCD absorption circuit and the active clamping circuit, wideband impedance matching is performed to suppress pulse leading-edge reflection distortion and output a distortion-free pulse signal.

[0036] Step 4: Based on the distortion-free pulse signal and combined with the predicted bottom moment of the drain-source voltage of the switching transistor, perform dynamic threshold adjustment and high-speed circuit control.

[0037] The present invention provides a pulse-stabilized output control method and system for a nanosecond-level high repetition rate fast pulse power supply, which has the following beneficial effects:

[0038] (1) By optimizing the R and C parameters of the RCD absorption circuit and the active clamping circuit in real time, the present invention can dynamically match the changes in load impedance and switching transistor parasitic parameters, effectively suppressing voltage spikes and ensuring that the voltage stress of the switching transistor is within the safe threshold, reducing the energy loss of the absorption circuit, improving the overall efficiency of the power supply, and greatly enhancing the circuit's adaptability to dynamic loads, ensuring the long-term stable operation of the switching transistor.

[0039] (2) The load current feedforward and resonant circuit state model constructed by the present invention through the derived state information can accurately predict the time of the bottom of the drain-source voltage of the switch tube, realize the zero voltage turn-on of the switch tube, and reduce the switching loss; at the same time, the accurate control of the load current and resonant circuit state also significantly improves the output stability of the power supply under high repetition frequency conditions.

[0040] (3) This invention can achieve wideband impedance matching through a three-stage variable impedance structure and dynamic optimization mechanism, effectively suppress pulse front reflection distortion, output distortionless pulse signal, steep front without oscillation, and stable amplitude without fluctuation; combined with distortionless pulse and dynamic threshold adjustment at the valley moment and high-speed circuit control, it avoids the problem of false protection or untimely protection, and can respond quickly under abnormal conditions, greatly enhancing the overall reliability and anti-interference capability of the power supply, and meeting the stringent requirements of high-end scientific research and industrial scenarios. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the system flow of the present invention;

[0042] Figure 2 This is a schematic diagram of the overall method of the present invention. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0044] Example 1:

[0045] Please see Figure 1 Embodiment 1 of this application provides a pulse-stabilized output control system for a nanosecond-level high repetition rate fast pulse power supply. The system includes:

[0046] The adaptive absorption module obtains power supply parameters, including load impedance and switching transistor parasitic parameters, through real-time sampling, and dynamically optimizes the R and C parameters of the RCD absorption circuit and the active clamping circuit based on the power supply parameters.

[0047] By using an ultra-high bandwidth, high sampling rate analog-to-digital converter and a high-sensitivity sensor to collect multi-terminal signals of load voltage, load current and switching transistors, a picosecond-level synchronous clock is constructed to provide synchronous trigger signals for all sampling channels, ensuring that the sampling time deviation of voltage, current and switching transistor signals is minimal, and performing time alignment of multiple parameters.

[0048] Real-time acquisition and calculation of load impedance:

[0049] The voltage and current signals at both ends of the load are acquired synchronously, the analog signals are converted into digital sequences, the digital sequences are bandpass filtered to remove electromagnetic interference outside the power supply frequency band, the amplitude ratio and phase difference of the filtered voltage and current signals are analyzed, and the load impedance is calculated pulse by pulse. Since the power supply has a high repetition rate in the nanosecond range, the load impedance needs to be updated once in each pulse cycle to ensure real-time performance.

[0050] Real-time extraction of parasitic parameters of switching transistors:

[0051] Parasitic parameters of a switching transistor include drain-source parasitic capacitance, gate-source and gate-drain parasitic capacitance, and parasitic inductance. Taking drain-source parasitic capacitance as an example, during the turn-off phase of the transistor, the rate of change of the drain-source voltage is observed, and the magnitude of the drain-source parasitic capacitance is calculated by combining the turn-off status of the drain current. The gate-source and gate-drain parasitic capacitance is extracted through the coupling characteristics between the gate drive signal and the drain voltage. For parasitic inductance, during the turn-on phase of the transistor, the rising slope of the drain current and the corresponding transient voltage drop are observed, and then the parasitic inductance is calculated. Since these parameters are affected by factors such as temperature, they need to be corrected through online calibration to ensure their accuracy.

[0052] The process of dynamically optimizing the R and C parameters of the RCD snubber circuit and the active clamping circuit is as follows:

[0053] By acquiring the load impedance and parasitic parameters of the switching transistor in the sampling stage, the load characteristics of the current power supply and the inherent electrical characteristics of the switching transistor are reflected. Based on the acquired power supply parameters, a dynamic simulation model of the RCD snubber circuit and the active clamping circuit is built to accurately simulate the circuit's operating behavior under different R and C parameters, including the suppression effect of the RCD snubber circuit on the voltage spike when the switching transistor is turned off and its energy absorption efficiency; the optimization of the switching transistor's turn-on or turn-off timing by the active clamping circuit and the stability of the clamping voltage; and the impact of changes in load impedance and parasitic parameters of the switching transistor on circuit characteristics, such as changes in spike voltage amplitude and circuit losses.

[0054] Adaptive intelligent optimization algorithms, such as adaptive genetic algorithms and particle swarm optimization algorithms, are employed to determine the optimal combination within the preset R and C parameter range, taking into account the physical characteristics of circuit components and the power supply operating frequency band. The search maximizes voltage spike suppression capability, ensuring that the voltage stress of the switching transistor is within a safe threshold; minimizes the energy loss of the absorption circuit, improving the overall efficiency of the power supply; and adapts to the current load impedance and parasitic parameters of the switching transistor to optimize the dynamic characteristics of the circuit, such as response speed and stability.

[0055] Based on the optimized R and C parameters, a high-speed digital control circuit drives programmable components to update the parameters. A digital potentiometer is used to change its resistance value in real time via digital signals. A programmable capacitor array is used to dynamically adjust the capacitance value by switching different combinations of capacitors. The entire adjustment process must be completed within nanoseconds to match the high repetition rate characteristics of the power supply. After parameter adjustment, the module continuously monitors the actual operating status of the circuit, such as the amplitude of the drain-source voltage spike of the switching transistor, the power consumption of the absorption circuit, and the integrity of the pulse waveform. The R and C parameters of the RCD absorption circuit and the active clamping circuit can match the dynamic characteristics of the load and the switching transistor in real time, effectively suppressing voltage spikes, ensuring the safety of the switching transistor, and reducing energy loss, ultimately achieving stable output of the nanosecond-level high repetition rate fast pulse power supply.

[0056] The feedforward prediction module extracts derived state information based on power supply parameters, obtains the load current feedforward and resonant circuit state based on the derived state information, and models the load current feedforward and resonant circuit state to predict the bottom moment of the drain-source voltage of the switching transistor.

[0057] Extracting derived state information from power supply parameters:

[0058] The power supply parameters acquired through real-time sampling, including load impedance and parasitic parameters of the switching transistors, undergo high-precision preprocessing to eliminate sampling noise and timing deviations. Bandpass filtering preserves effective signal components matching the power supply's operating frequency band, and picosecond-level timing synchronization calibration ensures complete alignment of the time axes for both types of parameters. Key derived state information is extracted, including the dynamic rate of change of load impedance, reflecting the real-time fluctuation trend of load characteristics; the coupling characteristics of the switching transistor's parasitic parameters; the equivalent combined effect of parasitic inductance and capacitance; and the timing correlation characteristics of impedance and parasitic parameters, as well as their coordinated change with the pulse period.

[0059] Construct a load current feedforward model based on derived state information:

[0060] Using the extracted derived state information as the core input, an adaptive load current feedforward prediction model is constructed. Combining the inherent driving characteristics of the power supply output pulse, such as the timing parameters of the gate drive signal, the model predicts the peak value, rising or falling edge slope, and duration of the load current by analyzing the correlation between the dynamic change rate of the load impedance and the current amplitude. Simultaneously, by utilizing the coupling characteristics of the parasitic parameters of the switching transistor, the model corrects the impact of parasitic effects on current transmission, such as current delay caused by parasitic inductance and current fluctuations caused by parasitic capacitance. The model adopts a dual-dimensional prediction logic of real-time features and historical trends, and outputs the feedforward signal quickly through parallel computing on an FPGA, ensuring that the timing deviation between the feedforward current and the actual load current is controlled within the nanosecond level, thus achieving early prediction of load current changes.

[0061] Analysis of resonant circuit state based on derived state information:

[0062] The core components of the resonant circuit, including equivalent inductance and equivalent capacitance, are determined by the parasitic parameters of the switching transistor, including parasitic inductance and capacitance, and the load impedance. The real-time state of the resonant circuit can be accurately analyzed through derived state information. Utilizing the equivalent resonance characteristics of the switching transistor's parasitic parameters, including the combined resonant frequency of parasitic inductance and capacitance, and combining this with the damping effect of the load impedance on resonance, the actual resonant frequency of the circuit is calculated, determining whether it matches the power supply's operating frequency. Through the time-series correlation characteristics of impedance and parasitic parameters, the phase synchronization state of the resonant circuit is analyzed, determining the current phase position within the resonant period, such as the rising, peak, and decaying segments. Based on the correlation between the dynamic change rate of the load impedance and the resonant energy loss, the energy exchange efficiency of the circuit is evaluated, assessing whether there is a risk of excessively rapid resonant decay or resonant runaway. The derived state information is processed rapidly by a DSP, ensuring that the analytical results of the resonant circuit state are updated synchronously with the power supply pulse cycle, reflecting the dynamic changes of the circuit in real time.

[0063] Feature extraction and timing calibration of input load current feedforward and resonant circuit states:

[0064] The acquired load current feedforward signal and resonant circuit state information are preprocessed to ensure the validity of the modeling input. For the load current feedforward signal, key features such as peak value, rising or falling edge slope, duration, and dynamic fluctuation amplitude are extracted to reflect the changes in the load's current demand. For the resonant circuit state, core feature parameters are extracted, including real-time resonant frequency, current phase position, energy exchange efficiency, and resonant decay rate, to clarify the dynamic working state of the circuit. At the same time, based on a picosecond-level timing synchronization mechanism, the time axes of the two types of parameters are fully aligned to eliminate timing deviations and avoid modeling errors caused by time asynchrony.

[0065] Construct a predictive model that coordinates load current feedforward and resonant circuit state adaptation:

[0066] Using the preprocessed feature parameters as input, an adaptive prediction model coordinating load current feedforward and resonant circuit state is constructed, and time-series correlation modeling and energy change modeling are performed respectively.

[0067] Timing-related modeling: This study analyzes the correlation between the load current feedforward characteristics and the phase of the resonant circuit. Changes in the load current affect the phase evolution of the resonant circuit through impedance coupling. For example, a rise in current peak value accelerates the resonant phase advance, while a decrease in current decays slows down the phase change. By quantifying the timing coupling coefficient between the two, a mapping relationship between current characteristics and phase changes is established, determining the phase evolution rate of the resonant circuit under different current conditions.

[0068] Energy change modeling: The energy exchange process of the resonant circuit directly determines the rise and fall trend of the drain-source voltage of the switching transistor. When the circuit is in the energy charging stage, the drain-source voltage shows an upward trend; when it is in the energy releasing stage, the drain-source voltage shows a downward trend; the valley moment corresponds to the critical state where the circuit energy is released to the minimum and is about to enter the next round of charging. Combining the energy exchange efficiency, decay rate, and the influence of load current feedforward on energy loss of the resonant circuit, such as the increase in load current leading to an increase in circuit energy loss and a slight increase in valley voltage, a dynamic model of the resonant energy state and drain-source voltage change is established to quantify the rate of voltage change with energy.

[0069] The model employs an adaptive update mechanism. After each pulse cycle, it adjusts the timing coupling coefficient and energy mapping parameters based on the measured drain-source voltage change data to ensure that the model always adapts to the dynamic changes in load and circuit state.

[0070] Predict the lowest point of the drain-source voltage of the switching transistor:

[0071] A heterogeneous computing architecture combining FPGA and DSP is used to solve the collaborative prediction model at high speed, predicting the valley moment of the drain-source voltage of the switching transistor. Utilizing the parallel computing capabilities of the FPGA, the timing correlation model and energy change model are rapidly computed, outputting the dynamic change curve of the drain-source voltage of the switching transistor. The computational delay is controlled within a single pulse cycle. Verification is performed using the real-time phase position of the resonant circuit. If the valley moment corresponds to the zero point of the resonant circuit phase (i.e., the critical phase of energy exchange), then the moment is confirmed as a valid valley. If a deviation exists, the phase correction coefficient is fine-tuned to ensure a perfect match between the locked valley moment and the energy state of the resonant circuit. After each pulse cycle, the measured valley moment of the drain-source voltage of the switching transistor is acquired and compared with the model's predicted moment to calculate the deviation. If the deviation exceeds a preset threshold, the cause is analyzed. If it is due to inaccurate load current feedforward feature extraction, the current feature extraction algorithm is optimized. If it is due to drift in the resonant circuit state parameters, the energy mapping parameters in the model are adjusted, and the corrected parameters are updated to the prediction model in real time, achieving dynamic iteration of the model and ensuring that the deviation between the predicted valley moment and the measured value is stably controlled within ≤2ns during long-term operation.

[0072] The multi-segment variable impedance transmission module adopts a three-segment variable impedance structure. Based on the optimized R and C parameters of the RCD absorption circuit and the active clamping circuit, it performs wideband impedance matching to suppress pulse leading-edge reflection distortion and output a distortion-free pulse signal.

[0073] A three-stage variable impedance structure is adopted:

[0074] A three-segment variable impedance transmission topology is constructed, consisting of an input matching segment, an intermediate transition segment, and an output matching segment. These three segments are connected in series between the preamplifier circuit and the load, forming a continuous impedance gradient path. The preamplifier circuit comprises an RCD snubber circuit and an active clamping circuit. Based on optimized R and C parameters, the goal of wideband impedance matching is clearly defined: on the one hand, to adapt to the effective operating bandwidth of the output pulse after parameter optimization of the preamplifier circuit, covering the 100MHz to GHz frequency band corresponding to the high repetition rate of the power supply; on the other hand, to eliminate impedance abrupt changes between different segments through impedance gradient, suppressing reflection and distortion at the pulse leading edge, ensuring efficient pulse energy transfer to the load, and maintaining waveform integrity. The optimized R and C parameters significantly reduce voltage spikes and energy losses in the preamplifier circuit, resulting in stable dynamic characteristics of the preamplifier output impedance. This provides a low-distortion, highly stable reference for impedance matching of the three-segment structure, avoiding the insufficient matching accuracy problem caused by preamplifier pulse distortion in traditional fixed impedance matching.

[0075] Wideband impedance matching:

[0076] Using the optimized R and C parameters and the real-time sampled load impedance as input, the DSP quickly calculates the target impedance value of the three-segment structure to ensure that the gradual change logic of each impedance segment is adapted to the characteristics of the preceding circuit and the load characteristics.

[0077] The input matching section determines the equivalent output impedance of the front-end circuit through optimized R and C parameters. This impedance is dynamically adjusted with the R and C parameters, and the impedance value of the input matching section must be matched with this equivalent output impedance in real time. When the R and C parameters are adjusted to suppress voltage spikes and configured for high absorption capability, the output impedance of the front-end will change accordingly. The input matching section dynamically adjusts its own impedance to avoid pulse reflection caused by impedance mismatch between the front-end and the transmission module.

[0078] The intermediate transition section adopts a linear gradient impedance value and high-frequency compensation method. Based on the impedance difference between the input matching section and the output matching section, the gradient impedance is distributed in a uniform gradient. At the same time, the gradient curve is fine-tuned by combining the optimized R and C parameters corresponding to the proportion of high-frequency pulse components, so as to ensure that pulses of different frequency components in the wide bandwidth can transition smoothly and avoid waveform distortion caused by high-frequency component reflection.

[0079] The output matching section directly matches the load impedance sampled in real time. At the same time, it takes into account the stabilizing effect of the optimized R and C parameters on the pulse amplitude. When the pulse amplitude fluctuation is ≤5% due to the optimization of the R and C parameters, the output matching section does not need to frequently and significantly adjust the impedance. It only needs to make small corrections according to the dynamic change rate of the load impedance to maintain the matching accuracy and ensure that the pulse energy is efficiently injected into the load.

[0080] Based on the power supply operating frequency band and pulse characteristics, the input and output matching sections use microstrip lines or coaxial lines with excellent high-frequency characteristics to reduce transmission loss. The intermediate transition section adopts a programmable tapered transmission line structure. The lengths of the three transmission lines are designed according to 1 / 4 or 1 / 8 wavelength of the corresponding frequency band to ensure impedance matching consistency of each frequency component within a wide bandwidth. Each section integrates programmable impedance components, such as digitally controlled microstrip line impedance regulators, high-frequency programmable capacitor and inductor arrays. The FPGA controls the component parameters in real time through high-speed digital signals based on the target impedance value calculated by the DSP to achieve nanosecond-level adjustment of the impedance value. This is synchronized with the update frequency of optimized R and C parameters, updating once per pulse cycle to ensure that the impedance matching always adapts to the dynamic characteristics of the preceding circuit.

[0081] To address the impedance characteristics differences of different frequency components within a wide bandwidth, a frequency adaptive gradient algorithm is introduced in the intermediate transition section. By monitoring and optimizing the intensity of the pulse high-frequency components corresponding to the R and C parameters, the gradient density of the gradient impedance is dynamically adjusted. When the proportion of high-frequency components is high, the gradient density is increased to improve high-frequency matching accuracy; when the proportion of low-frequency components is high, the gradient density is appropriately reduced to balance transmission efficiency and achieve low-reflection and low-loss transmission across the entire frequency band.

[0082] After each pulse cycle of impedance matching is completed, the reflection coefficient, waveform distortion rate, and energy transmission efficiency of the output pulse of the transmission module are monitored in real time. If the reflection coefficient exceeds the standard, it indicates that there is an impedance mismatch or the waveform has leading-edge distortion. Then, the impedance value of the three-segment structure is finely adjusted in reverse by combining the current configuration of the R and C parameters and the trend of load impedance changes. For example, if the reflection is caused by the increase of the output impedance of the front stage due to the adjustment of the R and C parameters, the impedance value of the input matching segment can be increased simultaneously. If the output reflection is caused by the sudden change of the load impedance, the gradual gradient of the output matching segment and the intermediate transition segment can be corrected.

[0083] Output distortion-free pulse signal:

[0084] Based on the wideband impedance matching results of the three-segment variable impedance structure, the causes of pulse reflection are eliminated through a continuously gradually changing impedance path. The input matching segment precisely matches the equivalent output impedance after optimizing the R and C parameters of the preceding stage. The intermediate transition segment achieves a smooth impedance transition with a uniform gradient. The output matching segment matches the load impedance in real time. The three-segment structure forms an impedance transmission link without abrupt changes, avoiding reflection waves caused by impedance abrupt changes at different segment interfaces. For the high-frequency characteristics of nanosecond-level pulses, the length of each of the three transmission lines is designed according to the characteristic wavelength of the corresponding operating frequency band, ensuring that the pulses of each frequency component in the wideband can achieve impedance matching, thus suppressing leading-edge reflections at the source.

[0085] By selecting low-loss, high-frequency stable transmission media, such as PTFE microstrip lines and silver-plated coaxial lines, energy loss and dispersion during pulse transmission are reduced, and leading-edge distortion caused by uneven media properties is avoided. All three sections of the structure adopt a shielded design, with an outer grounded shielding layer to isolate the influence of external electromagnetic interference on the pulse leading edge, while suppressing the radiation interference of the transmission line itself. The wiring process of the transmission line is optimized, shortening the lead length and reducing the bending angle to reduce the influence of parasitic inductance and capacitance on the pulse leading edge. A high-frequency compensation structure is added in the intermediate transition section to offset the leading-edge delay and distortion caused by parasitic parameters of the transmission line, ensuring the steepness and integrity of the pulse leading edge.

[0086] A high-speed monitoring unit is integrated at the output of the three-segment variable impedance transmission module to collect real-time indicators such as the leading edge shape, reflection coefficient, and amplitude fluctuation of the pulse signal. It monitors whether there are distortion phenomena such as overshoot, oscillation, and delay at the leading edge, and whether the reflection coefficient exceeds the preset threshold. The monitoring data is fed back to the FPGA control unit via a high-speed bus. Combined with the optimized R and C parameters of the previous stage and the load impedance change trend, the impedance value of the three-segment structure and the transmission line compensation parameters are dynamically adjusted. If oscillation distortion caused by leading edge reflection is detected, the impedance gradient of the intermediate transition segment is finely adjusted to increase the gradient density and enhance the matching accuracy of high-frequency components. If leading edge delay distortion occurs, the impedance fit between the input matching segment and the previous stage circuit is optimized to reduce energy transmission loss and improve the leading edge rise rate. If amplitude fluctuation distortion is caused by a sudden change in load impedance, the impedance of the output matching segment is quickly adjusted, and the gradient curve of the intermediate transition segment is corrected simultaneously to maintain the stability of the pulse amplitude.

[0087] By leveraging the high stability of the pulse after optimizing the R and C parameters in the pre-amplifier stage, a leading edge shaping unit is added to the output of the transmission module. Through high-speed switching devices and an RC buffer network, the rise time of the pulse leading edge is compressed, while suppressing overshoot, making the leading edge steeper and more regular. After each pulse cycle, the measured waveform of the output pulse is compared with the preset distortion-free standard waveform to quantify the degree of distortion, such as the leading edge distortion rate, amplitude fluctuation, and reflected energy ratio. If the distortion index exceeds the allowable range, the impedance matching algorithm and transmission line compensation parameters are updated by DSP to iteratively optimize the dynamic response characteristics of the three-segment variable impedance structure.

[0088] The collaborative protection module, based on distortion-free pulse signals and combined with the predicted bottom moment of the drain-source voltage of the switching transistor, performs dynamic threshold adjustment and high-speed circuit control.

[0089] Based on both the baseline characteristics of the distortionless pulse signal and the timing characteristics at the valley moment, the protection thresholds for overvoltage, overcurrent, and overtemperature are dynamically adjusted. The amplitude stability of the distortionless pulse provides a dynamic reference for the overvoltage threshold. The basic overvoltage threshold is set at 1.1 to 1.2 times the pulse amplitude. At the same time, the voltage characteristics at the valley moment are considered. If the voltage at the valley moment is low, it indicates that the switching loss of the switching transistor is small and the circuit stress is low, so the threshold is appropriately relaxed to 1.2 times. If the voltage fluctuation at the valley moment increases, it indicates that the circuit stress is rising, so the threshold is tightened to 1.1 times. This avoids false protection and ensures the voltage withstand safety of the switching transistor.

[0090] Based on the correlation between the leading edge slope of the distortionless pulse and the load current feedforward signal, the overcurrent threshold is dynamically set. The larger the leading edge slope of the pulse, the faster the load current rises and the faster the trigger response speed of the overcurrent threshold. At the same time, the threshold curve is optimized before and after the valley moment. At the valley moment, the conduction loss of the switching transistor is the smallest, so the threshold tolerance can be temporarily relaxed, allowing the current to approach the upper limit of the threshold for a short time. When deviating from the valley moment, the threshold is tightened to prevent the switching transistor from being damaged by overcurrent under high loss conditions.

[0091] All threshold adjustments are linked to the optimized R and C parameter states. If the R and C parameters are in a high absorption capacity configuration, it indicates that the circuit has a strong stress suppression capability, and the dynamic range of the threshold can be appropriately expanded. If the parameters are in a basic configuration, the threshold range is narrowed to ensure accurate protection adaptation.

[0092] Combined with high-speed circuit control execution at the valley moment:

[0093] By using FPGA and high-speed driving circuits to construct a control link with nanosecond-level response, the timing advantages of dynamic threshold and valley moment are transformed into actual control actions. Within the preset timing window of the distortionless pulse signal, based on the calibrated valley moment, the main switch is controlled to turn on at the moment of voltage valley. At this time, the drain-source voltage of the switch is the lowest and the switching loss is the least. At the same time, the stable timing of the distortionless pulse is used to synchronously control the action of the clamping switch of the active clamping circuit, ensuring that the clamping voltage matches the working state of the main switch, further reducing circuit stress.

[0094] High-speed protection and control optimization under abnormal conditions:

[0095] The system compares measured circuit parameters in real time, such as drain-source voltage of the switching transistor and load current, with dynamic thresholds. If any parameter exceeds the dynamic threshold, such as a sudden rise in drain-source voltage to the overvoltage threshold or a load current exceeding the overcurrent threshold, it is considered abnormal and immediately triggers high-speed protection: the FPGA outputs a nanosecond-level shutdown signal to cut off the main switching transistor drive, while controlling the RCD absorption circuit to enhance energy absorption and suppress fault expansion; if the valley moment deviates from the predicted range, such as a delay in the valley moment due to a sudden load change, the control timing is quickly adjusted to advance or delay the switching transistor turn-on time to avoid voltage spikes and loss surges caused by turning on at non-valley moments, while triggering temporary threshold tightening to prevent potential faults.

[0096] High-speed sensors collect data on the operating status of the switching transistor, including drain-source voltage, current, integrity of the distortion-free pulse waveform, and threshold trigger count. This data is used to determine whether the dynamic threshold is reasonable and whether the valley moment control is accurate. If frequent threshold triggers are detected without actual faults, it indicates that the threshold is too strict, so the dynamic range of the threshold is expanded. If a fault occurs and triggers are not timely, it indicates that the threshold is too loose, so the threshold is tightened. If the valley moment control causes slight pulse distortion, the timing calibration parameters are fine-tuned. After a preset number of pulse cycles, such as 100 cycles, the optimized threshold parameters and control timing are cached, while a real-time update channel is maintained to ensure that the circuit can quickly adapt and maintain stable control under scenarios such as sudden load changes and ambient temperature changes.

[0097] Example 2:

[0098] Please see Figure 2 Based on Example 1, Example 2 of this application also provides a pulse stable output control method for a nanosecond-level high repetition rate fast pulse power supply, including the following specific steps:

[0099] Step 1: Obtain power supply parameters, including load impedance and parasitic parameters of the switching transistor, through real-time sampling; and dynamically optimize the R and C parameters of the RCD snubber circuit and the active clamping circuit based on the power supply parameters.

[0100] Step 2: Extract derived state information based on power supply parameters, obtain the load current feedforward and resonant circuit state based on the derived state information, model the load current feedforward and resonant circuit state, and predict the time of the bottom of the drain-source voltage of the switching transistor.

[0101] Step 3: Using a three-segment variable impedance structure, based on the optimized R and C parameters of the RCD absorption circuit and the active clamping circuit, wideband impedance matching is performed to suppress pulse leading-edge reflection distortion and output a distortion-free pulse signal.

[0102] Step 4: Based on the distortion-free pulse signal and combined with the predicted bottom moment of the drain-source voltage of the switching transistor, perform dynamic threshold adjustment and high-speed circuit control.

[0103] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented in software, the above embodiments can be implemented, in whole or in part, as a computer program product. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution.

[0104] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0105] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A pulse-stabilized output control system for a nanosecond-level high repetition rate fast pulse power supply, characterized in that, The system includes: The adaptive absorption module obtains power supply parameters, including load impedance and switching transistor parasitic parameters, through real-time sampling, and dynamically optimizes the R and C parameters of the RCD absorption circuit and the active clamping circuit based on the power supply parameters. The feedforward prediction module extracts derived state information based on power supply parameters, obtains the load current feedforward and resonant circuit state based on the derived state information, and models the load current feedforward and resonant circuit state to predict the bottom moment of the drain-source voltage of the switching transistor. The process of extracting derived state information from power supply parameters is as follows: The power supply parameters are acquired and preprocessed to eliminate sampling noise and timing deviations. The effective signal components that match the power supply operating frequency band are retained by bandpass filtering. Combined with timing synchronization calibration, the time axis is fully aligned and the derived state information is extracted. The process of obtaining the load current feedforward and resonant circuit state is as follows: Using derived state information as input, an adaptive load current feedforward prediction model is constructed, and the output pulse drive characteristics are analyzed. Based on the pulse drive characteristics, the correlation between the dynamic change rate of load impedance and the amplitude of current is analyzed, and the peak value, rising edge and falling edge slope and duration of current are predicted. By utilizing the coupling characteristics of the parasitic parameters of the switching transistor, the parasitic effect on current transmission is corrected, and the load current feedforward is output. Based on the derived state information, the state of the resonant circuit under the combined effect of the switching transistor parasitic parameters and the load impedance is analyzed; the resonant circuit state frequency is calculated using the switching transistor parasitic parameters, and the resonant energy loss between the resonant circuit state frequency and the power supply operating frequency is determined; the current phase position is determined by the timing correlation characteristics between the load impedance and the switching transistor parasitic parameters; and the resonant circuit state is determined based on the correspondence between the current phase position and the resonant energy loss. The process of modeling the load current feedforward and resonant circuit state is as follows: Key features such as peak value, rising or falling edge slope, and duration of load current feedforward are extracted; real-time resonant frequency and current phase position parameters of resonant circuit state are extracted; time axis alignment is performed based on timing synchronization mechanism to eliminate timing deviation; A collaborative adaptive prediction model for load current feedforward and resonant circuit state is constructed, including time-series correlation modeling and energy change modeling; the phase correlation law between load current feedforward characteristics and resonant circuit is analyzed, the time-series coupling coefficient is quantified, the mapping relationship between current characteristics and phase change is established, and time-series correlation modeling is constructed. The relationship between the energy exchange process of the resonant circuit and the rise and fall trend of the drain-source voltage of the switching transistor is analyzed. The influence of load current feedforward on energy loss is combined with dynamic modeling based on the resonant energy state and the rise and fall trend of the drain-source voltage of the switching transistor to construct an energy change model. The process of predicting the valley moment of the drain-source voltage of the switching transistor is as follows: Leveraging the parallel computing capabilities of FPGAs, the timing correlation model and energy change model are rapidly computed, outputting the dynamic change curve of the drain-source voltage of the switching transistor, with the computation delay controlled within a single pulse cycle. Based on the voltage change curve, the moment when the voltage drop rate slows down, approaches 0, and is about to rise is identified as the drain-source voltage valley. Combined with real-time phase position verification of the resonant circuit, if there is a deviation, the phase correction coefficient is finely adjusted to ensure that the valley moment perfectly matches the energy state of the resonant circuit. The multi-segment variable impedance transmission module adopts a three-segment variable impedance structure. Based on the optimized R and C parameters of the RCD absorption circuit and the active clamping circuit, it performs wideband impedance matching and outputs a distortion-free pulse signal. The collaborative protection module, based on distortion-free pulse signals and combined with the predicted bottom moment of the drain-source voltage of the switching transistor, performs dynamic threshold adjustment and high-speed circuit control.

2. The pulse-stabilized output control system for a nanosecond-level high repetition rate fast pulse power supply according to claim 1, characterized in that, The load impedance is obtained by acquiring the voltage and current signals across the load and converting them into a digital sequence. The parasitic parameters of the switching transistor include drain-source parasitic capacitance, gate-source gate-drain parasitic capacitance, and parasitic inductance.

3. The pulse-stabilized output control system for a nanosecond-level high repetition rate fast pulse power supply according to claim 1, characterized in that, The process of dynamically optimizing the R and C parameters of the RCD snubber circuit and the active clamping circuit is as follows: Based on power supply parameters, a simulation model is used to model the working behavior of RCD snubber circuit and active clamping circuit under different R and C parameters. An adaptive intelligent optimization algorithm is adopted to search for the optimal R and C combination within the preset parameter range, dynamically adjust the actual circuit parameters, continuously monitor the actual working state of the circuit, and feed the real-time data back to the simulation model to continuously iterate and optimize the R and C parameters.

4. The pulse-stabilized output control system for a nanosecond-level high repetition rate fast pulse power supply according to claim 1, characterized in that, The process of outputting a distortion-free pulse signal is as follows: Wideband impedance matching based on a three-segment variable impedance structure: the input matching segment precisely matches the equivalent output impedance after optimizing the R and C parameters of the preceding stage; the intermediate transition segment achieves a smooth impedance transition with a uniform gradient; and the output matching segment matches the load impedance in real time. The three segments form an impedance transmission link without abrupt changes, and the lengths of the three transmission lines are all based on the characteristic wavelengths of the corresponding operating frequency bands. Select the transmission medium and add a high-frequency compensation structure in the intermediate transition section to collect the pulse leading edge morphology and reflection coefficient distortion index in real time. Feed the monitoring data back to the FPGA control unit, and dynamically adjust the impedance value of the three-segment structure and the transmission line compensation parameters in combination with the optimized R and C parameters of the previous stage and the load impedance change trend. Based on the predicted timing of the bottom moment of the drain-source voltage of the switching transistor, the output pulse timing is calibrated by delay line fine-tuning technology to ensure that the leading edge trigger moment and the bottom moment are accurately synchronized. After each pulse cycle, the measured waveform of the output pulse is compared with the preset distortion-free standard waveform to quantify the degree of distortion. If the distortion index exceeds the allowable range, the impedance matching algorithm and transmission line compensation parameters are updated by DSP, and the dynamic response characteristics of the three-segment variable impedance structure are iteratively optimized to finally output a distortion-free pulse signal.

5. The pulse-stabilized output control system for a nanosecond-level high repetition rate fast pulse power supply according to claim 1, characterized in that, The process of dynamic threshold adjustment and high-speed circuit control is as follows: Based on both the distortion-free pulse reference characteristics and the timing of the valley moment, the overvoltage threshold and overcurrent threshold are dynamically adjusted. The overvoltage threshold is adjusted based on the pulse amplitude and combined with the valley voltage characteristics. The overcurrent threshold is dynamically set according to the pulse leading edge slope and load current feedforward, with the threshold being relaxed at the valley moment and tightened when it deviates. Both the overvoltage threshold and the overcurrent threshold are linked and adapted to the optimized R and C parameters. During normal operation, within the distortion-free pulse timing window, the main switch is controlled to turn on at the valley bottom based on the valley bottom moment, and the active clamp circuit switch is controlled synchronously. In case of abnormality, if the parameter exceeds the threshold, the FPGA outputs a shutdown signal and strengthens RCD absorption. If the valley bottom moment deviates, the turn-on timing is adjusted and the threshold is temporarily tightened. The system monitors the control effect in real time, and adjusts the threshold or timing calibration parameters after deviation analysis. After each preset pulse cycle, the optimized parameters are fixed and the real-time update channel is retained.

6. A pulse-stabilized output control method for a nanosecond-level high repetition rate fast pulse power supply, characterized in that, Includes the following steps: Step 1: Obtain power supply parameters, including load impedance and switching transistor parasitic parameters, through real-time sampling; and dynamically optimize the R and C parameters of the RCD snubber circuit and the active clamping circuit based on the power supply parameters. Step 2: Extract derived state information based on power supply parameters; obtain the load current feedforward and resonant circuit states based on the derived state information; model the load current feedforward and resonant circuit states; and predict the valley moment of the drain-source voltage of the switching transistor. The process of extracting derived state information from power supply parameters is as follows: The power supply parameters are acquired and preprocessed to eliminate sampling noise and timing deviations. The effective signal components that match the power supply operating frequency band are retained by bandpass filtering. Combined with timing synchronization calibration, the time axis is fully aligned and the derived state information is extracted. The process of obtaining the load current feedforward and resonant circuit state is as follows: Using derived state information as input, an adaptive load current feedforward prediction model is constructed, and the output pulse drive characteristics are analyzed. Based on the pulse drive characteristics, the correlation between the dynamic change rate of load impedance and the amplitude of current is analyzed, and the peak value, rising edge and falling edge slope and duration of current are predicted. By utilizing the coupling characteristics of the parasitic parameters of the switching transistor, the parasitic effect on current transmission is corrected, and the load current feedforward is output. Based on the derived state information, the state of the resonant circuit under the combined effect of the switching transistor parasitic parameters and the load impedance is analyzed; the resonant circuit state frequency is calculated using the switching transistor parasitic parameters, and the resonant energy loss between the resonant circuit state frequency and the power supply operating frequency is determined; the current phase position is determined by the timing correlation characteristics between the load impedance and the switching transistor parasitic parameters; and the resonant circuit state is determined based on the correspondence between the current phase position and the resonant energy loss. The process of modeling the load current feedforward and resonant circuit state is as follows: Key features such as peak value, rising or falling edge slope, and duration of load current feedforward are extracted; real-time resonant frequency and current phase position parameters of resonant circuit state are extracted; time axis alignment is performed based on timing synchronization mechanism to eliminate timing deviation; A collaborative adaptive prediction model for load current feedforward and resonant circuit state is constructed, including time-series correlation modeling and energy change modeling; the phase correlation law between load current feedforward characteristics and resonant circuit is analyzed, the time-series coupling coefficient is quantified, the mapping relationship between current characteristics and phase change is established, and time-series correlation modeling is constructed. The relationship between the energy exchange process of the resonant circuit and the rise and fall trend of the drain-source voltage of the switching transistor is analyzed. The influence of load current feedforward on energy loss is combined with dynamic modeling based on the resonant energy state and the rise and fall trend of the drain-source voltage of the switching transistor to construct an energy change model. The process of predicting the valley moment of the drain-source voltage of the switching transistor is as follows: Leveraging the parallel computing capabilities of FPGAs, the timing correlation model and energy change model are rapidly computed, outputting the dynamic change curve of the drain-source voltage of the switching transistor, with the computation delay controlled within a single pulse cycle. Based on the voltage change curve, the moment when the voltage drop rate slows down, approaches 0, and is about to rise is identified as the drain-source voltage valley. Combined with real-time phase position verification of the resonant circuit, if there is a deviation, the phase correction coefficient is finely adjusted to ensure that the valley moment perfectly matches the energy state of the resonant circuit. Step 3: Using a three-segment variable impedance structure, based on the optimized R and C parameters of the RCD absorption circuit and the active clamping circuit, wideband impedance matching is performed to suppress pulse leading-edge reflection distortion and output a distortion-free pulse signal. Step 4: Based on the distortion-free pulse signal and combined with the predicted bottom moment of the drain-source voltage of the switching transistor, perform dynamic threshold adjustment and high-speed circuit control.

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