Circuit board and preparation method thereof

Abstract

The invention discloses a circuit board and a preparation method thereof. The preparation method of the circuit board comprises the following steps: preparing a to-be-processed board; wherein the to-be-processed plate is marked with an identification point, and the to-be-processed plate is divided into a gold-plated area and a non-gold-plated area by taking the identification point as a boundary; adding solid copper at the edge of the gold-plating pinch point corresponding to the non-gold-plating area to form a solid copper area; performing first gold plating on the partial gold plating area; and carrying out second-time gold plating on the gold plating area after the first-time gold plating. By means of the method, the problem that the identification points are excessively etched in the two-time gold plating process can be effectively solved, and the product rejection rate is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit board manufacturing, in particular to a circuit board and a preparation method thereof. BACKGROUND

[0002] The circuit board often needs to be treated by gold plating for multiple times during preparation to form a gold-plated board. The surface of the gold-plated board is divided into a gold-plated area and a non-gold-plated area according to a recognition point. At this time, when the board enters an etching line for subsequent processing, an obvious potential difference exists between the gold-plated area and the non-gold-plated recognition point, which will cause a galvanic effect, that is, when two different metals are in contact in an electrolyte (such as a humid environment or salt water), an electric current is generated due to the difference in electrode potential. This will cause one of the metals to be corroded (anode), while the other metal is protected (cathode), resulting in problems such as size deviation, shape distortion, or even complete loss of the recognition point, and ultimately causing product scrap.

[0003] At present, although some production technologies adjust process parameters such as etching chemical concentration, conveying speed, or etching time to alleviate the problem, the corrosion phenomenon caused by the potential difference between materials has not been fundamentally eliminated. SUMMARY

[0004] The present application provides a circuit board and a preparation method thereof, which can effectively protect the recognition point around the gold-plated area and the non-gold-plated area of the to-be-processed board from being over-etched during the etching process after gold plating, solve the size deviation and shape distortion risks caused by the two gold plating processes, and reduce the product scrap rate.

[0005] To solve the above technical problems, the present application provides a preparation method of a circuit board, comprising: preparing a to-be-processed board; wherein the to-be-processed board is marked with a recognition point, and the to-be-processed board is divided into a gold-plated area and a non-gold-plated area with the recognition point as a boundary; increasing solid copper at the edge of the gold-plated clamp point corresponding to the non-gold-plated area to form a solid copper area; performing first gold plating on part of the gold-plated area; and performing second gold plating on the gold-plated area after the first gold plating.

[0006] The width of the solid copper area should be greater than or equal to 1.8 mm, and the length range is 11.5-16.5 mm.

[0007] The minimum distance between the recognition point and the edge of the gold-plated clamp point is less than 15 mm.

[0008] The step of increasing solid copper at the edge of the gold-plated clamp point corresponding to the non-gold-plated area to form a solid copper area and performing first gold plating on part of the gold-plated area comprises: increasing the solid copper at the outer layer circuit of the to-be-processed board to form the solid copper area.

[0009] Before the step of performing the second plating on the gold-plated region after the first plating, the method further comprises: covering the solid copper region of the to-be-processed board with a second dry film; and the step of performing the second plating on the gold-plated region after the first plating further comprises: performing a windowing process on the second dry film to remove the second dry film.

[0010] Before the step of performing the second plating on the gold-plated region after the first plating, the method further comprises: covering the solid copper region of the to-be-processed board with a second dry film; and the step of performing the second plating on the gold-plated region after the first plating further comprises: performing a windowing process on the second dry film to remove the second dry film.

[0011] The step of performing the windowing process on the second dry film to remove the second dry film comprises: performing an exposure offset process on the second dry film of the solid copper region.

[0012] The step of performing the second plating on the gold-plated region after the first plating comprises: performing plating on the non-gold-plated region in the gold-plated region.

[0013] After the step of performing the second plating on the gold-plated region after the first plating, the method further comprises: removing the solid copper of the solid copper region during etching of the to-be-processed board.

[0014] To solve the above problems, the application provides a circuit board prepared by the preparation method of any one of the above circuit boards.

[0015] The application has the following beneficial effects: a to-be-processed board is prepared; the to-be-processed board is marked with an identification point, and the to-be-processed board is divided into a gold-plated region and a non-gold-plated region by the identification point; solid copper is added at the edge of a gold-plated pinch point corresponding to the non-gold-plated region to form a solid copper region; the gold-plated region is plated for the first time; and the gold-plated region after the first plating is plated for the second time. By setting a solid copper region with a specific size at the edge of a gold-plated pinch point, the Jovanni effect of the etching process after the second plating is concentrated on the solid copper region, so that the identification point is prevented from being subjected to excessive etching due to a potential difference, the shape of the identification point is ensured to be complete during the etching process, the size deviation and shape distortion problems caused by the two plating processes are effectively alleviated, and the product rejection rate is significantly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1is a flow chart of an embodiment of the preparation method of the circuit board provided in the present application;

[0017] Figures 2a-2d is Figure 1 is a flow chart of an embodiment of the preparation method of the circuit board provided in the present application;

[0018] Figure 3 is a flow chart of an embodiment of the preparation method of the circuit board provided in the present application;

[0019] Figures 4a-4h is Figure 3 is a flow chart of an embodiment of the preparation method of the circuit board provided in the present application;

[0020] Figure 5 is a flow chart of an embodiment of the preparation method of the circuit board provided in the present application; DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0022] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative positional relationship, movement condition, etc. between components in a certain posture (as shown in the drawings). If the certain posture changes, the directional indications also change accordingly.

[0023] In addition, if the embodiments of the present application involve descriptions of “first”, “second”, etc., the descriptions of “first”, “second”, etc. are only for description purposes, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by “first”, “second” can explicitly or implicitly include at least one of the features. In addition, the technical solutions of the various embodiments can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it. When the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the scope of protection claimed by the present application.

[0024] In order to solve the problem that the identification points of the gold-plated area and the periphery of the non-gold-plated area of the circuit board are easily over-etched in the etching process when the circuit board is gold-plated, thereby causing size deviation and shape distortion and resulting in high product rejection rate, the application provides a preparation method of a circuit board, which increases solid copper at the edge of the corresponding gold-plated pinch point of the non-gold-plated area to form a solid copper area, and after gold plating is completed, the dry film of the solid copper area is processed to open a window, so that the Jovanni effect of the etching process after gold plating is concentrated on the solid copper area, thereby avoiding the over-etching of the identification points due to the potential difference, ensuring that the identification points remain complete in shape during the etching process, effectively alleviating the size deviation and shape distortion problems caused by the two gold plating processes, and significantly reducing the product rejection rate.

[0025] Specifically, refer to Figure 1 and Figures 2a-2d , Figure 1 is a flowchart of an embodiment of the preparation method of the circuit board provided by the application, Figures 2a-2d is Figure 1 a structural diagram corresponding to each step of the preparation method.

[0026] S11: preparing a to-be-processed board; wherein the to-be-processed board is marked with identification points, and the to-be-processed board is divided into a gold-plated area and a non-gold-plated area by the identification points.

[0027] The to-be-processed board includes ordinary soft and hard gold process boards, two times of soft gold process boards, etc., and its structure mainly includes a substrate, a circuit layer, an insulating layer, a solder resist layer, a silk screen layer and the like arranged in layers, and in some specific embodiments, it can include a circuit layer formed by etching, an insulating layer for electrical isolation, a solder resist layer for insulation protection and preventing short circuit during welding, and a silk screen layer for identifying the position of components. According to the electrical complexity, the to-be-processed board can be divided into a single-sided board, a double-sided board and a multi-layer board with multiple inner layers (such as a power layer and a ground layer). The manufacturing materials of the to-be-processed board include but are not limited to FR-4 epoxy glass cloth board, polytetrafluoroethylene (PTFE / Teflon), polyimide (PI) and the like.

[0028] In high-reliability electronic equipment or high-frequency signal transmission applications, it is often necessary to perform gold plating on the circuit board to achieve excellent conductivity, oxidation resistance and wear resistance. In order to control production costs, avoid gold material waste, or meet the specific functional needs of different areas (such as only the connector fingers need to be wear-resistant, and other areas only need to be oxidation-resistant), it is often necessary to perform gold plating only on part of the area of the to-be-processed board. In order to clearly define the boundary of gold plating and improve the accuracy of the circuit board, identification points are generally provided on the surface of the to-be-processed board. The identification points are used to identify the boundary position of the gold-plated area or the quality of the gold-plated area, and the surface of the to-be-processed board is divided into a gold-plated area and a non-gold-plated area by the identification points, thereby providing a standardized boundary reference for subsequent gold plating process.

[0029] Due to the process limitations such as different gold plating types (e.g. common soft gold, hard gold), gold plating area exceeding the process capacity or thickness requirement difference being too large, etc., it is necessary to perform gold plating operation on the gold plating area selectively in multiple times. In this process, when the minimum distance between the identification point and the gold plating clamp point is too small, such as more than 15 mm, during the first time of gold plating on the gold plating area and etching process, the etching solution as a strong electrolyte will form a huge potential difference between the gold plated area (anode) and the nearby and connected identification point (cathode) on the to-be-processed board, causing the Javanyl effect, resulting in accelerated corrosion of the identification point, causing unintended transition etching, and in severe cases, the integrity of the identification point may be completely destroyed, resulting in the product failing to meet the quality detection requirements and finally being scrapped. Therefore, the position selection of the identification point is very important. In some embodiments, in order to reduce the influence of the Javanyl effect, the minimum distance between the identification point and the gold plating clamp point is less than or equal to 15 mm, such as 15 mm, 14.1 mm, 14.25 mm, 13.3 mm, 13.33 mm, etc. However, the minimum distance between the identification point and the gold plating clamp point is not the larger the better. In a specific application scenario, due to the layout requirements of high-density processes, the identification point of the to-be-processed board is set at a position too close to the gold plating clamp point, such as less than 11 mm, which is beneficial to space optimization, but significantly increases the risk of Javanyl effect between the identification point and the gold plated area in subsequent processes. Therefore, in some embodiments, the minimum distance between the identification point and the gold plating clamp point is generally set to be greater than 11 mm. The specific value can be determined according to the size of the circuit board and the equipment used in the gold plating process, etc., which is not limited here.

[0030] In a specific embodiment, as shown in Figure 2a the to-be-processed board 100 includes a substrate 10 and a circuit layer 20 arranged on the substrate 10. The circuit layer 20 is divided into a gold plating area 201 and a non-gold plating area 202 by an identification point 1. The circuit layer 20 further includes a gold plating clamp point 2. The minimum distance between the identification point 1 and the gold plating clamp point 2 is 13 mm.

[0031] S12: Increase solid copper at the edge of the gold plating clamp point corresponding to the non-gold plating area to form a solid copper area.

[0032] In order to minimize the risk of Javanyl effect, solid copper is added at the edge of the gold plating clamp point corresponding to the non-gold plating area through the outer circuit of the to-be-processed board to form a solid copper area meeting the size requirements, so that the Javanyl effect in the gold plating and etching process is concentrated on the solid copper area, thereby avoiding the identification point from being subjected to transition etching due to the potential difference. Specifically, the process such as pulse electroplating or chemical copper plating can be used to achieve this.

[0033] In some embodiments, in order to ensure that the Javan effect can be effectively guided to the predetermined area, while avoiding the real copper area being too large to affect the layout of the circuit or too small to play a sufficient protective role, the size of the real copper area is generally limited. The width of the real copper area is set to be greater than or equal to 1.8 mm, such as 1.8 mm, 1.81 mm, 1.84 mm, 1.9 mm, 1.95 mm, 2 mm, etc. The length ranges from 11.5 to 16.5 mm, such as 15.5 mm, 15.55 mm, 15.60 mm, 16 mm, 16.5 mm, etc. In actual application, the size of the real copper area can be flexibly adjusted within the limited range according to the specific design requirements and process conditions.

[0034] Specifically, as shown in Figure 2b The to-be-processed board piece 100 includes a substrate 10 and a circuit layer 20 arranged on the substrate 10. The circuit layer 20 is divided into a gold-plated area 201 and a non-gold-plated area 202 by an identification point 1. The non-gold-plated area 202 is provided with a gold-plated pinch point 2, and a real copper area 3 is added in the non-gold-plated area 202.

[0035] S13: First gold plating on part of the gold-plated area

[0036] Before the first gold plating, the real copper area of the to-be-processed board piece is covered and treated by a dry film process. Specifically, the dry film is uniformly covered and closely attached to the copper surface by a film pressing process in the real copper area. According to the gold plating requirements, the first gold plating is performed on part of the gold-plated area of the to-be-processed board piece. The gold plating process can be performed by electroplating soft gold technology, pulse electroplating, etc. The corresponding gold plating method can be used according to the actual application requirements, which is not limited here. Then the dry film in the real copper area is irradiated by ultraviolet light to cause a polymerization reaction to form a resist layer. In the subsequent developing process, the polymerized dry film is not dissolved by the developing solution due to its alkali resistance, thereby achieving protection of the real copper area.

[0037] As shown in Figure 2c The to-be-processed board piece 100 includes a substrate 10 and a circuit layer 20 arranged on the substrate 10. The circuit layer 20 is divided into a gold-plated area 201 and a non-gold-plated area 202 by an identification point 1. The non-gold-plated area 202 is provided with a gold-plated pinch point 2, and a real copper area 3 is added in the non-gold-plated area 202. The first gold-plated area 40 is formed by gold plating in the gold-plated area 201.

[0038] After the first gold plating, the dry film on the solid copper area needs to be removed. Specifically, a film-removing solution (usually a 4-6% sodium hydroxide solution, with a temperature controlled at 50-60 degrees Celsius) is used to swell the dry film and separate it from the copper surface of the solid copper area by spraying or immersion. After high-pressure water rinsing and drying, the film layer is completely removed, and the copper surface of the solid copper area is exposed, preparing for subsequent process steps.

[0039] S14: Second gold plating is performed on the gold-plated area after the first gold plating.

[0040] Before the second gold plating, the solid copper area is covered with a dry film. Then, according to the gold plating requirements, the un-plated area that existed after the first gold plating is supplemented with gold plating during the second gold plating of the gold-plated area of the processed board.

[0041] As shown in Figure 2d The processed board 100 includes a substrate 10 and a circuit layer 20 disposed on the substrate 10. The circuit layer 20 is divided into a gold-plated area 201 and a non-gold-plated area 202 by a recognition point 1. The gold-plated area 201 has a first gold-plated area 40, and the non-gold-plated area 202 has a solid copper area 3 and a gold-plated clip point 2. The solid copper area 3 is covered with a dry film 5, and the gold-plated area 201 is secondarily gold-plated to form a second gold-plated area 41.

[0042] To avoid the recognition point from being over-etched, the dry film on the solid copper area is subjected to an exposure offset process during the exposure process. The exposure offset needs to ensure that the dry film does not undergo a polymerization reaction to form a resist layer. For example, the exposure offset is 30-40 mm, so that the dry film is completely dissolved in the developing process to expose the copper surface of the solid copper area. After that, in the etching solution environment, the Javell effect caused by the potential difference between the recognition point and the gold-plated area acts on the nearest solid copper of the solid copper area, thereby protecting the integrity of the gold-plated recognition point.

[0043] In a specific application scenario, the solid copper area is covered with a dry film before the second gold plating. After the second gold plating of the gold-plated area of the processed board, the solid copper area is subjected to dry film covering and exposure offset processing. In the exposure process, a high-precision alignment system is used to offset the position of the solid copper area by 30 mm, ensuring that the ultraviolet light completely deviates from the dry film on the solid copper area, so that it cannot form a resist layer due to the absence of a polymerization reaction. In the subsequent developing process, the unexposed dry film is dissolved by the alkaline solution, resulting in complete exposure of the solid copper area. During the etching process, the Javell effect preferentially acts on the exposed solid copper area, effectively preventing the recognition point from being over-etched.

[0044] Through the above steps, the preparation method of the circuit board of the embodiment can effectively guide the Jaffee effect caused by the potential difference in the etching process to act on the solid copper area, ensure the integrity and reliable function of the identification point structure, and reduce the product scrap rate.

[0045] Referring to Figure 3 and Figures 4a-4h , Figure 3 is a flowchart of another embodiment of the preparation method of the circuit board provided by the present application, Figures 4a-4h is Figure 3 the corresponding structure diagram after each step of the preparation method.

[0046] S31: Prepare a to-be-processed board; wherein the to-be-processed board is marked with an identification point, and the to-be-processed board is divided into a gold-plated area and a non-gold-plated area by the identification point.

[0047] This step is the same as S11, and specific details are described with reference to the related description of S11.

[0048] In some embodiments, as shown in Figure 4a , the to-be-processed board 400 includes a substrate 41, and a circuit layer 40 is arranged on the substrate 41, wherein the circuit layer 40 is provided with an identification point 1, and the circuit layer 40 is divided into a gold-plated area 401 and a non-gold-plated area 402 by the identification point 1. In order to facilitate gold plating operation, the circuit layer 40 is further provided with a gold-plated clamping point 2.

[0049] S32: Increase solid copper at the edge of the gold-plated clamping point corresponding to the non-gold-plated area to form a solid copper area.

[0050] This step is the same as S12, and specific details are described with reference to the related description of S12.

[0051] In some embodiments, as shown in Figure 4b , the to-be-processed board 400 includes a substrate 41, and a circuit layer 40 is arranged on the substrate 41, wherein the circuit layer 40 is provided with an identification point 1, and the circuit layer 20 is divided into a gold-plated area 401 and a non-gold-plated area 402 by the identification point 1. The non-gold-plated area 402 is provided with a gold-plated clamping point 2, and the solid copper area 3 is formed by increasing solid copper in the non-gold-plated area 402.

[0052] S33: Cover the solid copper area with a first dry film.

[0053] To protect the solid copper areas from damage, a dry film is applied to the solid copper areas of the board to be treated. Specifically, a lamination process is used to evenly cover the solid copper surface with dry film material and form a tight bond with it.

[0054] like Figure 4c As shown, the board to be processed 400 includes a substrate 41 and a circuit layer 40 is provided on the substrate 41. The circuit layer 40 is provided with identification points 1, which divide the circuit layer 40 into a gold-plated area 401 and a non-gold-plated area 402. The non-gold-plated area 402 is provided with gold-plating clamps 2. There is a solid copper area 3 in the non-gold-plated area 402, and a dry film 5 is covered in the solid copper area.

[0055] S34: Perform a first gold plating on a portion of the gold-plated area.

[0056] This step is the same as S13; please refer to the relevant description of S13 for details.

[0057] like Figure 4d As shown, the board to be processed 400 includes a substrate 41, and a circuit layer 40 is provided on the substrate 41. In the region 402, the circuit layer 40 is provided with identification points 1. The circuit layer 40 is divided into a gold-plated region 401 and a non-gold-plated region 402 by the identification points 1. The non-gold-plated region 402 is provided with gold-plating clips 2. There is a solid copper region 3 in the non-gold-plated region. A dry film 5 is covered in the solid copper region 3. Gold is plated in the gold-plated region 401 to form the first gold-plated region 60.

[0058] S35: Etch and expose the workpiece after the first gold plating to form a pattern layer and remove the first dry film.

[0059] Subsequently, the dry film covering the solid copper area is subjected to ultraviolet irradiation treatment, causing a photopolymerization reaction to form a resist layer. In the subsequent alkaline development process, this polymerized dry film area remains chemically stable and does not dissolve, thus effectively masking the solid copper area. After the first gold plating, the dry film on the surface of the solid copper area needs to be removed. Specifically, a 4% to 6% sodium hydroxide solution is used as the stripping solution, and its temperature is maintained within the range of 50°C to 60°C. The dry film is fully swollen by spraying or immersion, thereby breaking its adhesion to the copper surface and achieving peeling. Following high-pressure water jet cleaning and drying, the residual film layer is thoroughly removed, exposing the copper surface of the solid copper area again. This provides a suitable surface condition for subsequent second gold plating or other processes, preparing the area for further processing.

[0060] like Figure 4eAs shown, the board to be processed 400 includes a substrate 41 and a circuit layer 40 is provided on the substrate 41. The circuit layer 40 is provided with an identification point 1, which divides the circuit layer 40 into a gold-plated area 401 and a non-gold-plated area 402. The gold-plated area 401 has a first gold-plated area 60, and the non-gold-plated area 402 is provided with a gold-plating clamp point 2.

[0061] S36: Cover the solid copper area of ​​the board to be processed after the first gold plating with a second dry film.

[0062] Before the second gold plating, a dry film is applied to the solid copper area. Specifically, this can be done by uniformly laminating the dry film onto the solid copper area using a laminating machine.

[0063] like Figure 4f As shown, the board to be processed 400 includes a substrate 41, and a circuit layer 40 is provided on the substrate 41. In the region 402, the circuit layer 40 is provided with identification points 1. The circuit layer 40 is divided into a gold-plated region 401 and a non-gold-plated region 402 by the identification points 1. The non-gold-plated region 402 is provided with gold-plating clips 2. There is a first gold-plated region 60 in the gold-plated region 401. There is a solid copper region 3 in the non-gold-plated region. A dry film 5 is covered in the solid copper region 3.

[0064] S37: Perform a second gold plating on the gold-plated area after the first gold plating.

[0065] This step is the same as S14; please refer to the relevant description of S14 for details.

[0066] In some embodiments, such as Figure 4g As shown, the board to be processed 400 includes a substrate 41, and a circuit layer 40 is provided on the substrate 41. In the region 402, the circuit layer 40 is provided with identification points 1. The circuit layer 40 is divided into a gold-plated region 401 and a non-gold-plated region 402 by the identification points 1. The non-gold-plated region 402 is provided with gold-plating clamps 2. There is a first gold-plated region 60 in the gold-plated region 401. There is a solid copper region 3 in the non-gold-plated region. A dry film 5 is covered in the solid copper region 3. Gold plating is performed in the gold-plated region 401 to form a second gold-plated region 61.

[0067] S38: Perform a windowing process on the second dry film to remove it.

[0068] In order to effectively prevent the identification point from being over-etched in the etching process, the dry film on the surface of the solid copper area is treated by exposure offset process. Specifically, in the exposure process, the bottom plate or optical system is controlled by the alignment system to produce a preset offset, for example, 30-40 mm, relative to the solid copper area, so as to ensure that the dry film on the area is not effectively irradiated by ultraviolet light, and thus the photopolymerization reaction does not occur. In the subsequent alkaline development process, the un-polymerized dry film is completely dissolved and removed, so that the copper surface of the solid copper area is fully exposed. In the subsequent etching process, the identification point and the gold-plated area in the etching liquid environment form an electrochemical potential difference with the above-mentioned exposed solid copper area, and the Javon effect generated is actively guided and concentrated on the solid copper area, so that the solid copper area is preferentially corroded as a sacrificial anode, thereby effectively protecting the structural integrity and functional reliability of the gold-plated identification point.

[0069] As shown in Figure 4h , the plate to be treated 400 includes a substrate 41, and a circuit layer 40 is arranged on the substrate 41. In the domain 402, the identification point 1 is arranged on the circuit layer 40, and the circuit layer 40 is divided into a gold-plated area 401 and a non-gold-plated area 402 by the identification point 1. The non-gold-plated area 402 is provided with a gold-plated pinch point 2. The first gold-plated area 60 is on the gold-plated area 401, and the solid copper area 3 is on the non-gold-plated area. The second gold-plated area 61 is formed by gold plating on the gold-plated area 401.

[0070] Through the above steps, the preparation method of the circuit board of the embodiment sets a solid copper area with a specific size between the gold-plated pinch point and the gold-plated identification point. The solid copper area is protected by the dry film during the first gold plating, and the dry film covering the solid copper area is treated by exposure offset during the second gold plating. The dry film in the area is effectively removed in the development process, so that the solid copper area is exposed. In the subsequent etching process, the Javon effect formed by the electrochemical potential difference is actively guided to the exposed solid copper area, so as to ensure the structural integrity and functional reliability of the identification point, and reduce the product scrap rate.

[0071] Please refer to Figure 5 , Figure 5 is a structural diagram of an embodiment of the circuit board of the present application.

[0072] As shown in Figure 5 , it includes a plate to be treated 1, and the plate to be treated 1 includes an identification point 4. The plate to be treated 1 is divided into a gold-plated area 5 and a non-gold-plated area 6 by the identification point 4. The gold-plated area includes a first gold-plated area 51 and a second gold-plated area 52. The non-gold-plated area 6 is provided with a gold-plated pinch point 3. The non-gold-plated area 6 has a solid copper area 2 corresponding to the edge of the gold-plated pinch point 3.

[0073] In the embodiment, the plate to be processed 1 includes the identification point 4 and the gold-plated clip point 3, and the identification point 4 divides the plate to be processed into the gold-plated area 5 and the non-gold-plated area 6, wherein the minimum distance between the identification point 4 and the gold-plated clip point 3 is not more than 15 mm, and the identification point 4 is damaged due to the Javelli effect caused by the potential difference between the gold-plated area 5 during the etching process after the second gold plating.

[0074] In the embodiment, the solid copper area 2 is arranged at the edge of the gold-plated clip point 3 of the non-gold-plated area, and the solid copper area 2 is formed by increasing the solid copper through the outer layer circuit, wherein the size of the solid copper area 2 is required to be greater than 1.8 mm in width and 11.5-16.5 mm in length, and the increased solid copper can be flexibly adjusted in size within the limited range according to the design requirements and process conditions, and then the dry film covering is performed on the solid copper area 2 and the first gold plating area 51 is plated, and the dry film of the solid copper area is removed through the film removal process before the second gold plating, so as to effectively protect the copper surface of the solid copper area 2 after the first gold plating and provide an alternative corrosion area for the Javelli effect occurring during the second gold plating.

[0075] In the embodiment, the dry film covering is performed on the solid copper area 2 and the second gold plating area 52 of the plate to be processed 1 is plated, the dry film is subjected to exposure offset treatment, the dry film is dissolved during development, and thus the solid copper of the solid copper area 2 is exposed, and finally the Javelli effect between the gold-plated area 5 and the identification point 4 during the etching process of the plate to be processed 1 acts on the solid copper area 2 to protect the identification point 4 from being excessively etched.

[0076] The beneficial effect of the embodiment is that the solid copper area meeting the size requirements is arranged at the edge of the corresponding gold-plated clip point of the non-gold-plated area, the Javelli effect of the connected non-gold-plated identification point near the gold-plated area during the second gold plating is effectively guided to act on the solid copper area, and thus the problems such as excessive etching or deformation of the identification point during the etching process are avoided, and the product rejection rate is reduced.

[0077] The above is only an embodiment of the application, and does not limit the patent scope of the application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the application.

Claims

1. A method for manufacturing a wiring board, characterized by, The preparation method of the circuit board comprises the following steps: preparing a to-be-processed board member, wherein the to-be-processed board member is marked with an identification point, and the to-be-processed board member is divided into a gold-plated region and a non-gold-plated region by taking the identification point as a boundary; adding solid copper at the edge of a gold-plated clamping point corresponding to the non-gold-plated region to form a solid copper region; firstly gold-plating a partial region of the gold-plated region; secondly gold-plating the gold-plated region after the first gold-plating.

2. The method for producing a circuit board according to claim 1, wherein The width of the solid copper region is greater than or equal to 1.8 mm, and the length ranges from 11.5 mm to 16.5 mm.

3. The method of manufacturing a circuit board according to claim 1 or 2, wherein The minimum distance from the identification point to the edge of the gold-plated clamping point is less than 15 mm.

4. The method for producing a circuit board according to any one of claims 1 to 3, characterized by, The step of adding solid copper at the edge of a gold-plated clamping point corresponding to the non-gold-plated region to form a solid copper region and firstly gold-plating a partial region of the gold-plated region comprises the following steps: adding the solid copper at the outer layer circuit of the to-be-processed board member to form the solid copper region.

5. The method of manufacturing a circuit board according to claim 4, wherein After the step of adding solid copper at the edge of a gold-plated clamping point corresponding to the non-gold-plated region to form a solid copper region and before the step of firstly gold-plating a partial region of the gold-plated region, the following step is further included: covering the solid copper region with a first dry film; after the step of firstly gold-plating a partial region of the gold-plated region, the following step is further included: performing etching exposure treatment on the to-be-processed board member after the first gold-plating to form a pattern layer and remove the first dry film.

6. The method of manufacturing a circuit board according to claim 5, wherein Before the step of secondly gold-plating the gold-plated region after the first gold-plating, the following step is further included: covering the solid copper region of the to-be-processed board member after the first gold-plating with a second dry film; the step of secondly gold-plating the gold-plated region after the first gold-plating further comprises the following step: performing windowing treatment on the second dry film to remove the second dry film.

7. The method of manufacturing a circuit board according to claim 6, wherein The step of performing windowing treatment on the second dry film to remove the second dry film comprises the following step: performing exposure offset treatment on the second dry film of the solid copper region.

8. The method of manufacturing a circuit board according to claim 1, wherein The step of secondly gold-plating the gold-plated region after the first gold-plating comprises the following step: gold-plating a non-gold-plated region in the gold-plated region.

9. The method of manufacturing a circuit board according to claim 1, wherein After the step of secondly gold-plating the gold-plated region after the first gold-plating, the following step is further included: removing the solid copper of the solid copper region during etching treatment of the to-be-processed board member.

10. A wiring board, characterized by The circuit board is prepared by the preparation method according to any one of claims 1 to 9.

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