Processing method of multilayer circuit board
By forming conductive and protective layers on multilayer circuit boards and reducing the diameter of residual hole through precise residual hole processing technology, the problems of complex wiring and low space utilization of multilayer circuit boards are solved, achieving a more reasonable wiring design and higher space utilization.
Patent Information
- Application Number
- CN202410960699.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-17
- Publication Date
- 2026-01-20
AI Technical Summary
When removing residual stubs from existing multilayer circuit boards, the drilling diameter is relatively large, which occupies a lot of space, resulting in complex wiring design and low space utilization.
After through-holes are fabricated on a multilayer circuit board, a conductive layer is formed and covered with a protective layer. The protective layer and part of the conductive layer of the non-conductive layer are removed through the residual hole, the diameter of the residual hole is reduced, and the remaining conductive layer is removed by an appropriate etching method.
It reduces the workload of wiring design, increases the number of vias, and improves the space utilization and signal transmission integrity of multilayer circuit boards.
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Figure CN121368087A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of circuit board processing, in particular to a processing method of a multilayer circuit board. BACKGROUND
[0002] With the continuous development of communication technology, the signal integrity requirement of electronic products is more and more strict. The multilayer circuit board is a core component for signal transmission in electronic products, and the via hole of the multilayer circuit board can realize the transmission of signals between layers, and the via hole has a greater impact on signal integrity.
[0003] The hole wall of the via hole of the multilayer circuit board is plated with a copper layer, and the copper layer is used for interlayer signal communication of the multilayer circuit board, and the copper layer between the layers which do not need to communicate is called a stub. The stub will cause adverse conditions such as reflection, scattering and delay of high-speed signal transmission, affect signal integrity, and needs to be drilled out. The current drilling precision is ±2mil, the first time the via hole is drilled, the diameter of the via hole is D1, after the via hole is plated with copper, the second time the via hole is drilled, at least a hole with a diameter of D1+8mil needs to be drilled to drill out the stub.
[0004] However, the hole diameter is large when the via hole is drilled for the second time on the multilayer circuit board, the hole occupies a large space of the multilayer circuit board, which will complicate the wiring design of the multilayer circuit board, increase the workload of the design, and reduce the number of holes, so that the space utilization of the multilayer circuit board is low. SUMMARY
[0005] In view of the above problems, the processing method of the multilayer circuit board provided in the embodiments of the present application can reduce the hole diameter for drilling out the stub, make the wiring of the multilayer circuit board more reasonable, reduce the workload of the wiring design, increase the number of holes, and improve the space utilization of the multilayer circuit board.
[0006] In order to achieve the above purpose, the embodiments of the present application provide the following technical solutions:
[0007] The processing method of the multilayer circuit board provided in the embodiments of the present application comprises:
[0008] A via hole is processed at a target position on the multilayer circuit board; wherein the diameter of the via hole is D1, and the offset of the via hole is ±e;
[0009] A conductive layer is formed on the hole wall of the via hole, and the thickness of the conductive layer is t;
[0010] A protective layer is formed on the surface of the conductive layer;
[0011] A stub hole is processed at the non-conductive layer of the target position to remove the protective layer and at least part of the conductive layer located in the non-conductive layer; wherein the diameter of the stub hole is D2, the offset of the stub hole is ±e, and D2≥D1+(4e-2t);
[0012] removing the conductive layer located in the non-conductive layer;
[0013] removing the protective layer.
[0014] In one possible implementation, when the offset directions of the stub hole and the through hole are opposite, D2≥D1+(2e-2t).
[0015] In one possible implementation, when the offset directions of the stub hole and the through hole are the same, D2≤D1+(2e-2t).
[0016] In one possible implementation, the offset e≤2 mil,
[0017] The thickness of the conductive layer is 1≤t≤D1 / 2 mil,
[0018] The diameter D2≥D1+6(mil).
[0019] In one possible implementation, the protective layer is a tin layer.
[0020] In one possible implementation, the thickness of the tin layer is 0.2 mil.
[0021] In one possible implementation, removing the protective layer comprises:
[0022] etching and removing the protective layer by using an alkaline solution.
[0023] In one possible implementation, the conductive layer is a copper layer.
[0024] In one possible implementation, drilling the through hole at the target position comprises:
[0025] drilling the through hole by using a drill bit with a diameter of D1;
[0026] and / or, drilling the stub hole in the non-conductive layer at the target position comprises:
[0027] drilling the stub hole by using a drill bit with a diameter of D2.
[0028] In one possible implementation, the processing method of the multilayer circuit board further comprises: plugging the through hole after removing the protective layer.
[0029] This application provides a method for processing a multilayer circuit board. The method first processes through-holes at target locations on the multilayer circuit board. The diameter of the through-hole is D1, and the offset is ±e. Next, a conductive layer is formed on the wall of the through-hole. This conductive layer is used for signal communication between multilayer circuit boards, and its thickness is t. Then, a protective layer is formed on the surface of the conductive layer to protect the surface of the multilayer circuit board and the conductive layer from damage. Next, a residual hole is processed in the non-conductive layer at the target location to remove the protective layer and at least part of the conductive layer, exposing the conductive layer in the non-conductive layer. The diameter of the residual hole is D2, and the offset is ±e, where D2 ≥ D1 + (4e - 2t). Then, the conductive layer in the non-conductive layer is removed. Finally, the protective layer is removed. This reduces the minimum diameter of the residual hole for drilling residual holes, making the wiring of the multilayer circuit board more rational, reducing the workload of wiring design, increasing the number of vias, and improving the space utilization of the multilayer circuit board. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a schematic diagram of a processing method for multilayer circuit boards in the prior art;
[0032] Figure 2 A flowchart illustrating the steps of a multilayer circuit board fabrication method provided in this application embodiment;
[0033] Figure 3 for Figure 2 A schematic diagram of the through-hole structure in the fabrication method of a multilayer circuit board;
[0034] Figure 4 for Figure 2 A schematic diagram of the conductive layer structure in the fabrication method of a multilayer circuit board;
[0035] Figure 5 for Figure 2 A schematic diagram of the protective layer structure in the fabrication method of multilayer circuit boards;
[0036] Figure 6 for Figure 2 A schematic diagram of the residual hole structure in the processing method of multilayer circuit boards;
[0037] Figure 7 for Figure 6 A top view of the structure of the remaining pile hole;
[0038] Figure 8 for Figure 2 A schematic diagram of the structure of the conductive layer after removing the non-conductive layer in the processing method of multilayer circuit boards.
[0039] Explanation of reference numerals in the attached figures:
[0040] 1-Copper layer;
[0041] 10 - Through hole; 20 - Conductive layer; 30 - Protective layer; 40 - Residual pile hole;
[0042] H1 - Non-conductive layer; H2 - Conductive layer;
[0043] N1 - Actual location; N2 - Target location; N3 - Residual pile hole location. Detailed Implementation
[0044] As described in the background section, in related technologies, through-holes in multilayer circuit boards enable signal transmission between different circuit boards. To avoid the negative effects of residual spikes on high-speed signal transmission, such as reflection, scattering, and delay, which would affect signal integrity, residual spikes must be removed.
[0045] For example, a multilayer circuit board has ten layers. The walls of the through holes in the multilayer circuit board are plated with copper. According to the design requirements, the first to the seventh layer need to be connected, while the eighth to the tenth layer have no circuit connection. The eighth to the tenth layer are not conductive. The copper layer between the eighth and tenth layers will interfere with the signal transmission between the first to the seventh layer, causing signal integrity problems.
[0046] Figure 1 This is a schematic diagram of a multilayer circuit board fabrication method in the prior art, with reference to... Figure 1 As shown, after lamination, a through-hole is drilled for the first time according to design requirements. The through-hole diameter is D1, and the drilling accuracy is ±e, meaning the positional deviation of the through-hole is ±e. Then, a copper layer 1 is electroplated onto the hole wall. Copper layer 1 is used for signal transmission between layers of the multilayer circuit board. Next, the copper layer located on the non-conductive layer needs to be removed, requiring re-drilling.
[0047] If there is no position deviation in the second drilling, the hole diameter required for drilling needs to be at least D1+2e to drill the copper layer 1 located in the non-conductive layer. In actual processing, the processing precision of the second drilling is also ±e, that is, the position deviation of the second drilling is also ±e. In order to ensure that the copper layer 1 located in the non-conductive layer is removed completely in all cases, the position of the first drilling and the position of the second drilling are both selected to be at the limit position, in other words, the offset direction of the first drilled hole is different from the offset direction of the second drilled hole, and the hole diameter required for drilling needs to be at least D1+2e+2e=D1+4e to remove the copper layer 1 located in the non-conductive layer. For example, if the processing precision of drilling is ±2 mil (1 mil is about 25.4 μm) and the hole diameter of the through hole is 20 mil, the hole diameter of the second drilling needs to be at least 28 mil to remove the copper layer located in the non-conductive layer.
[0048] The hole diameter of the residual stub is 4e larger than the hole diameter of the through hole, which increases the design workload, reduces the number of holes, and lowers the space utilization of the multi-layer circuit board.
[0049] Therefore, embodiments of the present application provide a processing method of a multi-layer circuit board. The processing method first processes a through hole at a target position on the multi-layer circuit board. The diameter of the through hole is D1, and the offset of the through hole is ±e. Then, a conductive layer is formed on the hole wall of the through hole. The conductive layer is used for signal communication between the multi-layer circuit boards, and the thickness of the conductive layer is t. Next, a protective layer is formed on the surface of the conductive layer. The protective layer is used to protect the surface of the multi-layer circuit board and the conductive layer from damage. Then, a residual stub hole is processed in the non-conductive layer at the target position to remove the protective layer and at least part of the conductive layer located in the non-conductive layer, so that the conductive layer located in the non-conductive layer is exposed. The diameter of the residual stub hole is D2, the offset of the residual stub hole is ±e, and D2≥D1+(4e-2t). Next, the conductive layer located in the non-conductive layer is removed. Finally, the protective layer is removed. In this way, the minimum hole diameter of the residual stub hole drilled to remove the residual stub is reduced, the wiring of the multi-layer circuit board is more reasonable, the workload of the wiring design is reduced, the number of holes is increased, and the space utilization of the multi-layer circuit board is improved.
[0050] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.
[0051] Embodiments of the present application provide a processing method of a multi-layer circuit board. The multi-layer circuit board is formed by sequentially stacking a plurality of inner layers and a plurality of prepreg layers.
[0052] When manufacturing a multi-layer circuit board, first, an inner layer board is manufactured, a layer of dry film is covered on the copper foil on the surface of the inner layer board, a photo mask designed with a circuit pattern is covered on the dry film, the area corresponding to the circuit pattern on the photo mask is transparent, and the other areas are black and opaque. Then, the inner layer board is sent into a ultraviolet irradiation machine, the ultraviolet irradiation machine emits ultraviolet rays to the inner layer board, because the area corresponding to the circuit pattern on the photo mask is transparent, the dry film under the area corresponding to the circuit pattern on the photo mask is solidified, and the dry film in other areas is not solidified. Next, a developing solution is applied to the inner layer board, the area of the dry film which is not solidified is exposed to the underlying copper, then the inner layer board is placed in an alkaline solution at a certain temperature, the exposed copper is etched away, and the inner layer board is placed in another solution tank, the photo mask and the dry film corresponding to the area above the circuit pattern are dissolved away, and the circuit pattern on the inner layer board is formed.
[0053] After the inner layer board is manufactured, the inner layer board is laminated with a prepreg according to the process requirements.
[0054] Figure 2 The step flow chart of the processing method of the multi-layer circuit board provided by the embodiment of the present application is shown in Figure 2 After the previous manufacturing process of the multi-layer circuit board is completed, the processing method of the multi-layer circuit board provided by the embodiment of the present application has the following specific steps:
[0055] Step S100, a via hole is processed at a target position on the multi-layer circuit board; wherein the diameter of the via hole is D1, and the offset of the via hole is ±e.
[0056] Figure 3 The structure schematic diagram of the via hole of the processing method of the multi-layer circuit board in Figure 2 The structure schematic diagram of the via hole of the processing method of the multi-layer circuit board in Figure 3 After the multi-layer circuit board is laminated, first, a via hole 10 is processed on the multi-layer circuit board, the via hole 10 is a hole designed for signal transmission between the inner layer boards of the multi-layer circuit board.
[0057] Generally, a plurality of via holes 10 need to be designed on the multi-layer circuit board, the positions of the via holes 10 are as far away from the sensitive elements or high-frequency circuits on the multi-layer circuit board as possible, so as to avoid signal interference and reduce the influence on signal transmission and ensure the stability of the circuit. At the same time, the layout of the via holes 10 should be as evenly distributed as possible to avoid too many via holes 10 gathering in some areas on the multi-layer circuit board, thereby increasing the risk of signal interference, so the via holes 10 are processed at the target positions N2 which are accurately designed and carefully laid out, to ensure the transmission of signals of the multi-layer circuit board and improve the reliability of the multi-layer circuit board.
[0058] For convenience of description, the target position N2 of the via hole 10 is shown in Figure 3In the figure, the board surface direction of the multilayer circuit board is the X direction, and the X arrow direction points to the right. The target position N2 and the actual position N1 are both the axis of the hole.
[0059] The diameter of the processed through hole 10 is D1. The through hole 10 has a processing deviation, and the offset of the through hole 10 is ±e. That is, taking the axis of the target position N2 as the axis, the radius of the through hole plus e is the radius of the cylinder, and the through hole 10 falls within the range of this cylinder, and the actual position N1 of the through hole 10 is within the range of the circle with the target position N2 as the axis and a diameter of D1+2e.
[0060] As an embodiment, the through hole 10 can be drilled at the target position N2, and a numerical control drilling machine, a manually operated single-axis drilling machine, or a laser drilling machine can be used. The manually operated single-axis drilling machine has low equipment requirements. The laser drilling machine can achieve fine hole processing and depth control.
[0061] Specifically, drilling can be performed on a numerical control drilling machine, and a drill bit with a diameter of D1 is used to drill the through hole 10. This drilling method has the advantages of high precision, high efficiency, and simple operation.
[0062] Step S200, a conductive layer is formed on the hole wall of the through hole, and the thickness of the conductive layer is t.
[0063] Figure 4 For Figure 2 The structure diagram of the conductive layer of the processing method of the multilayer circuit board in the figure, refer to Figure 4 After the through hole 10 is formed on the multilayer circuit board, a conductive layer 20 is then formed on the hole wall of the through hole 10. The conductive layer 20 has excellent conductivity, which ensures signal transmission between the layers of the multilayer circuit board.
[0064] The conductive layer 20 can have good adhesion, and the conductive layer 20 has good adhesion with the hole wall of the through hole 10, so as to ensure that it is not easy to fall off during long-term use and ensure signal transmission between the layers of the multilayer circuit board. In order to ensure the conductivity and corrosion resistance of the conductive layer 20, it is necessary to process a uniform and dense conductive layer 20.
[0065] For example, the conductive layer 20 can be made of materials such as tin, copper, gold, silver, etc. Gold and silver have strong oxidation resistance and corrosion resistance, which can protect the through hole 10 from environmental factors and improve the stability and life of the circuit board. Copper has good conductivity and is relatively low in price. Tin has good conductivity.
[0066] The conductive layer 20 has a certain thickness in order to ensure conductivity, and the thickness of the conductive layer 20 is t.
[0067] Based on performance, reliability and cost of each aspect of the comprehensive consideration, the conductive layer 20 formed on the hole wall of the via 10 can be set as a copper layer. Because copper has very high conductivity, the resistance of the conductive layer 20 is relatively low, so as to improve the quality of signal transmission between the layers of the multilayer circuit board and the overall performance of the circuit. Copper also has very high thermal conductivity. In high-power applications, heat can be conducted from the inner layer of the multilayer circuit board to other parts or heat sinks through the conductive layer 20, which is beneficial to improve the service life of the multilayer circuit board.
[0068] Moreover, the copper layer formed by using copper material is easy to manufacture and can be manufactured by electroplating and chemical deposition processes.
[0069] As an embodiment, the copper layer can be electroplated on the hole wall of the via 10. After the via 10 is cleaned, a thin layer of catalyst (such as palladium) is usually deposited on the hole wall of the via 10 by a chemical method. The activated hole wall of the via 10 is deposited with a thin layer of copper by chemical copper plating. Then the multilayer circuit board is immersed in an electroplating solution, and copper ions are deposited on the hole wall of the via 10 by electric current. In this way, a conductive layer 20 with high precision and high consistency can be made on the hole wall of the via 10.
[0070] As another embodiment, after the via 10 is cleaned, the copper layer is deposited on the hole wall of the via 10 by plasma-enhanced chemical reaction. This processing method is relatively simple and has high processing efficiency.
[0071] The thickness of the conductive layer 20 will affect the resistance of the conductive layer 20, thereby affecting the quality of signal transmission and the overall performance of the circuit. When the thickness of the conductive layer 20 is relatively thick, the mechanical strength of the via 10 can be enhanced to prevent the phenomenon of fracture under the action of mechanical stress. Moreover, when the thickness of the conductive layer 20 is too thick, more material is needed, which will increase the manufacturing cost. Therefore, the thickness of the conductive layer 20 can be set as 1≤t≤D1 / 2(mil).
[0072] Step S300, forming a protective layer on the surface of the conductive layer.
[0073] Figure 5 For Figure 2 the structure of the protective layer of the processing method of the multilayer circuit board in Figure 5 As shown in FIG. 8, after the conductive layer 20 is formed, a protective layer 30 is formed on the surface of the conductive layer 20. The protective layer 30 is used to prevent the surface of the multilayer circuit board from being corroded or damaged, and the surface of the conductive layer 20 is also prevented from being corroded or damaged.
[0074] As an embodiment, the protective layer 30 formed on the surface of the conductive layer 20 can be a tin layer. The tin layer can effectively prevent the surface of the conductive layer 20 of the multilayer circuit board from being oxidized, and ensure the reliability of the electrical connection. Moreover, tin has the characteristics of being resistant to acid but not alkali, and the tin layer can have a certain anti-alkaline solution corrosion effect, and can protect the surface of the multilayer circuit board and the conductive layer 20 from being corroded by alkaline solution.
[0075] If the thickness of the tin layer is too thick, a large amount of tin material needs to be used, which will increase the processing cost. If the thickness of the tin layer is too thin, a uniform tin layer cannot be formed on the conductive layer 20, so that the protective effect of the conductive layer 20 is lost. After comprehensive consideration, the thickness of the tin layer can be set to 0.2 mil.
[0076] In step S400, a stub hole is processed in the non-conductive layer at the target position, so as to remove the protective layer and at least part of the conductive layer in the non-conductive layer; wherein the diameter of the stub hole is D2, the offset of the stub hole is ±e, and D2≥D1+(4e-2t).
[0077] Figure 6 For Figure 2 the structure diagram of the stub hole of the processing method of the multilayer circuit board in Figure 7 the structure diagram of the stub hole of the processing method of the multilayer circuit board in Figure 6 . Referring to Figure 6 and Figure 7 , signal transmission is performed between the top layer and one of the layers of the multilayer circuit board, and these layers are called conductive layers H2, and the remaining layers have no signal transmission and are called non-conductive layers H1.
[0078] After the above processing procedure is completed, a stub hole 40 is processed in the non-conductive layer H1 at the target position N2, and the diameter of the stub hole 40 is D2. The processing equipment and clamps of the stub hole 40 and the via hole 10 are the same, and the offset of the stub hole is ±e. The stub hole position N3 is shown in the figure, the stub hole position N3 is offset to the right of the target position N2 by e, the actual position N1 of the via hole 10 is offset to the right of the target position N2 by e, and according to the processing method of the prior art, the diameter of the stub hole 40 is at least D1+2e+2e=D1+4e to remove the conductive layer 20 in the non-conductive layer H1.
[0079] In the embodiment of the present application, the conductive layer 20 is formed on the hole wall of the through hole 10, the protective layer 30 is formed on the surface of the conductive layer 20, the protective layer 30 and part of the conductive layer 20 located in the non-conductive layer H1 are drilled out by processing the residual stub hole 40, and the remaining part of the conductive layer 20 located in the non-conductive layer H1 is removed by other means. Therefore, the diameter D2 of the residual stub hole 40 can be set to at least D1+(4e-2t). That is, D2≥D1+(4e-2t), and the diameter D2 of the residual stub hole 40≥D1+(4e-2t) can be used to remove the protective layer 30 and at least part of the conductive layer 20 located in the non-conductive layer H1, and the diameter D2 of the residual stub hole 40 is reduced by 2t compared with the processing method of the prior art.
[0080] After the residual stub hole 40 with a diameter of D2≥D1+(4e-2t) is processed, the protective layer 30 located in the non-conductive layer H1 is completely removed, part of the conductive layer 20 located in the non-conductive layer H1 is removed, the remaining part of the conductive layer 20 located in the non-conductive layer H1 is completely exposed, and there is no protective layer 30 attached.
[0081] The non-conductive layer H1 at the target position N2 can be processed by drilling to drill the residual stub hole 40. The residual stub hole 40 can be drilled by using a numerical control drilling machine, a single-axis drilling machine operated manually, and a laser drilling machine.
[0082] Further, the drilling can be performed on a numerical control drilling machine, and a drill bit with a diameter of D2 is used to drill the residual stub hole 40. Similarly, the processing method of drilling has the advantages of high precision, high efficiency, and simple operation.
[0083] As an embodiment, when the processing offset e of the residual stub hole 40 is 0, the processing offset of the through hole 10 is e, or the processing offset of the residual stub hole 40 is e, and the processing offset of the through hole 10 is 0, when the offset directions of the residual stub hole 40 and the through hole 10 are opposite, the diameter of the residual stub hole 40 is set to D2≥D1+(2e-2t) to remove the protective layer 30 and at least part of the conductive layer 20 located in the non-conductive layer H1. After completing the subsequent processing procedure, the conductive layer 20 located in the non-conductive layer H1 can be removed. In this way, the minimum value of the diameter of the residual stub hole 40 is reduced by 2e, and the space utilization is further improved.
[0084] As another embodiment, the processing offset of the stub hole 40 is 0, the maximum processing offset of the via hole 10 is e, and the processing offset of the via hole 10 is generally less than e. Alternatively, the maximum processing offset of the stub hole 40 is e, the processing offset of the stub hole 40 is generally less than e, and the processing offset of the via hole 10 is 0. The diameter of the stub hole 40 is set to D2≤D1+(2e-2t) to remove the protective layer 30 and at least part of the conductive layer 20 in the non-conductive layer H1. After the subsequent processing procedure is completed, the conductive layer 20 in the non-conductive layer H1 can be removed. Moreover, the minimum value of the diameter D2 of the stub hole 40 can be set to D1, further improving the space utilization of the multilayer circuit board.
[0085] Since the processing offset is affected by the precision of the processing equipment, the precision of the fixture, and the material properties, and other factors, the processing offset e is different when using different equipment or fixtures for processing. According to the current processing level, the maximum processing offset e is 2 mil, and the processing offset e of the via hole 10 and the stub hole 40 is ≤2 mil. For example, the processing offset of the via hole 10 and the stub hole 40 can be ±1 mil or ±2 mil according to the use of different equipment or fixtures.
[0086] The processing offset of the via hole 10 and the stub hole 40 is e≤2 mil. As described above, the thickness of the conductive layer 20 is set to 1≤t≤D1 / 2(mil). Then, the larger the value of the processing offset e is, the larger the minimum value of the diameter D2 of the stub hole 40 must be set to be, so that all of the protective layer 30 and part of the conductive layer 20 in the non-conductive layer H1 can be drilled out. Therefore, the processing offset e takes the maximum value of 2 mil. However, the smaller the value of the thickness t of the conductive layer 20 is, the larger the minimum value of the diameter D2 of the stub hole 40 must be set to be, and the thickness t of the conductive layer 20 takes the minimum value of 1 mil. At this time, the minimum value of the diameter D2 of the stub hole 40 is set to D1+6(mil) to remove part of the conductive layer 20 in the non-conductive layer H1, that is, D2≥D1+6(mil), and a small part of the conductive layer 20 in the non-conductive layer H1 is removed by solution etching or other methods. In comparison with the processing method of the prior art, D1+8 mil must be used to remove part of the conductive layer 20 in the non-conductive layer H1. Therefore, the hole diameter of the stub hole 40 is reduced, and the space utilization of the multilayer circuit board is improved.
[0087] Step S500, removing the conductive layer in the non-conductive layer.
[0088] Figure 8 For Figure 2 the processing method of the multilayer circuit board in the structure diagram of removing the conductive layer in the non-conductive layer. Referring to Figure 8As shown, the remaining conductive layer 20 on the non-conductive layer H1 is exposed, and then the conductive layer 20 on the non-conductive layer H1 is removed. In this way, the remaining conductive layer 20 on the non-conductive layer H1 can be removed by combining the residual stub hole 40, so as to prevent the conductive layer 20 on the non-conductive layer H1 from causing reflection, scattering, delay and other adverse effects of high-speed signal transmission, and improve the integrity of signal transmission of the multilayer circuit board.
[0089] For example, the conductive layer 20 on the non-conductive layer H1 can be removed by chemical etching dissolution, laser etching, electrolytic method, plasma etching method, and mechanical grinding method. The most suitable method for removing the conductive layer 20 is selected by comprehensively considering the material of the conductive layer 20, processing precision, cost, processing efficiency, processing area, and environmental protection requirements.
[0090] In the case of using copper as the conductive layer 20, copper has the characteristics of being resistant to alkali but not resistant to acid, so an acidic solution can be used to etch away the copper layer. For example, the acidic solution can be a mixed solution of hydrochloric acid and hydrogen peroxide or ferric chloride.
[0091] After the residual stub hole 40 is processed on the multilayer circuit board, the protective layer 30 and at least part of the conductive layer 20 on the non-conductive layer H1 are removed, and the remaining conductive layer 20 on the non-conductive layer H1 can be etched away using an acidic solution. The remaining conductive layer 20 on the non-conductive layer H1 is removed by chemical etching, which has relatively low cost of equipment and materials and is suitable for mass production.
[0092] Step S600, remove the protective layer.
[0093] Finally, the protective layer 30 on the conductive layer and the protective layer 30 on other areas of the multilayer circuit board are removed by a specific method. Removing the protective layer 30 facilitates the subsequent processing flow of the multilayer circuit board.
[0094] The protective layer 30 can be removed by chemical etching or by heating with a specific instrument. The protective layer 30 is removed by a specific method without damaging the circuit lines on the multilayer circuit board.
[0095] The specific method for removing the protective layer 30 can be chemical etching, laser etching, hot air reworking, and mechanical grinding method. The material of the protective layer 30, processing precision, cost, processing efficiency, processing area, and environmental protection requirements are comprehensively considered to achieve the desired processing effect and cost benefit.
[0096] In the case of using tin as the protective layer 30, an alkaline solution can be used to remove the protective layer 30. For example, the alkaline solution can be a solution of copper chloride, ammonia, etc.
[0097] The protective layer 30 is removed by using an alkaline solution, so that the processing speed is faster, and the processing is suitable for large-area processing. In addition, the alkaline solution and the equipment cost are relatively low, and the processing cost is relatively low.
[0098] As an embodiment, the characteristics of tin and copper are used. The copper layer is electroplated on the hole wall of the via hole 10, and the surface of the copper layer is formed into a tin layer as the protective layer 30. After the processing of the residual stub hole 40, the tin layer and at least part of the copper layer on the non-conductive layer H1 are removed. The remaining copper layer on the non-conductive layer H1 can be removed by an acidic solution. The copper layer on the conductive layer H2 and other areas on the multilayer circuit board are covered with a tin layer, and the tin layer prevents damage to the acidic solution. Then, the tin layer on the conductive layer H2 and the tin layer on other areas of the multilayer circuit board are removed by using an alkaline solution. The copper layer on the conductive layer H2 and the copper layer on other areas of the multilayer circuit board are resistant to alkaline and will not be etched. This processing method is simple to operate, has low processing cost, and is suitable for mass processing.
[0099] The alkaline solution can remove the protective layer 30 and protect the conductive layer 20. For example, the tin layer can prevent the surface of the copper conductor from oxidizing. Copper is easily oxidized in the air to form copper oxide, which affects the reliability of electrical connection. The tin layer as a protective layer can prevent this oxidation phenomenon.
[0100] The via hole 10 is processed to form the conductive layer 20 on the via hole 10 for signal transmission between the layers of the multilayer circuit board. Then, the protective layer 30 is formed on the surface of the conductive layer 20. The residual stub hole 40 with a diameter of D2≥D1+(4e-2t) is drilled to remove the protective layer 30 on the non-conductive layer H1 and part of the conductive layer 20 on the non-conductive layer H1. The remaining part of the conductive layer 20 is removed, which can reduce the minimum diameter of the residual stub hole 40 by 2t. After the protective layer 30 is removed by a specific method, other processing procedures are completed. The reduction of the diameter of the residual stub hole 40 makes the wiring reasonable, reduces the workload of wiring design, increases the number of holes, and improves the space utilization of the multilayer circuit board. The diameter D2 of the residual stub hole 40 indirectly affects the number of via holes 10. Reducing the diameter can increase the number of via holes 10, so that more circuit lines can be designed on the multilayer circuit board, and the layout is more reasonable.
[0101] In addition, when processing the residual stub hole 40, the circuit lines beside the residual stub hole 40 are prevented from being damaged, and the precision of processing the residual stub hole 40 needs to be improved. After the diameter D2 of the residual stub hole 40 is reduced, lower-precision equipment can be used for processing, which can reduce the processing cost of the multilayer circuit board.
[0102] The reduction of the diameter D2 of the residual stub hole 40 can also prevent the mechanical strength of the multilayer circuit board from being reduced due to a larger hole diameter, which can cause damage to the multilayer circuit board during subsequent processing and use.
[0103] After the protective layer 30 is removed, the via hole 10 can be filled with a specific material to plug the via hole 10, to enhance the performance and reliability of the circuit board.
[0104] The plugged via hole 10 can prevent short circuit between the non-conductive layers H1 of the multi-layer circuit board, and can also protect the conductive layer 20 in the conductive layer H2 from being damaged or chemically changed, to improve the reliability of the multi-layer circuit board. In addition, the plugged via hole 10 can prevent the flux from remaining in the via hole 10 during soldering, so that the multi-layer circuit board can be kept clean and the subsequent soldering process can be prevented from being adversely affected. In addition, the plugged via hole 10 can also help maintain the flatness of the surface of the multi-layer circuit board, to improve the appearance quality of the multi-layer circuit board.
[0105] For example, common materials for plugging the via hole 10 include conductive glue, resin and the like. The processing method for plugging the via hole 10 with resin is to fill the via hole 10 with epoxy resin after the hole wall is formed into the conductive layer 20, and then to plate copper on the surface of the epoxy resin to realize the hole plugging. This method can ensure that the hole is conductive and the surface is free of indentations, and does not affect soldering.
[0106] After the via hole 10 is plugged, the multi-layer circuit board still needs to go through processes such as pattern etching, surface treatment, molding, electrical testing and appearance inspection, to ensure the integrity and functionality of the circuit board.
[0107] In the description of the present specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between embodiments can be referred to each other.
[0108] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0109] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A method of processing a multilayer circuit board, characterized by, The method comprises: forming a via hole at a target position on a multi-layer circuit board, wherein a diameter of the via hole is D1, and an offset of the via hole is ±e; forming a conductive layer on a hole wall of the via hole, wherein a thickness of the conductive layer is t; forming a protective layer on a surface of the conductive layer; forming a stub hole at the target position to remove the protective layer and at least part of the conductive layer located on a non-conductive layer, wherein a diameter of the stub hole is D2, an offset of the stub hole is ±e, and D2≥D1+(4e-2t); removing the conductive layer located on the non-conductive layer; removing the protective layer.
2. The multilayered circuit board processing method according to claim 1, wherein When offset directions of the stub hole and the via hole are opposite, D2≥D1+(2e-2t).
3. The multilayer circuit board processing method according to claim 1, wherein When offset directions of the stub hole and the via hole are the same, D2≤D1+(2e-2t).
4. The multilayer circuit board processing method according to any one of claims 1 to 3, characterized by, The offset e≤2 mil, The thickness of the conductive layer is 1≤t≤D1 / 2 mil, The diameter D2≥D1+6(mil).
5. The multilayer circuit board processing method according to any one of claims 1 to 3, characterized by, The protective layer is a tin layer.
6. The multilayered circuit board processing method according to claim 5, wherein The thickness of the tin layer is 0.2 mil.
7. The multilayer circuit board processing method according to claim 5, wherein The method of removing the protective layer comprises: etching and removing the protective layer by using an alkaline solution.
8. The multilayer circuit board processing method according to any one of claims 1 to 3, characterized by, The conductive layer is a copper layer.
9. The method of processing a multilayer circuit board according to any one of claims 1 to 3, characterized in that, The method of drilling the via hole at the target position comprises: drilling the via hole by using a drill bit with a diameter of D1; and / or, the method of drilling the stub hole at the target position on the non-conductive layer comprises: drilling the stub hole by using a drill bit with a diameter of D2.
10. The method of processing a multilayer circuit board according to any one of claims 1 to 3, characterized in that, After removing the protective layer, the method further comprises: plugging the via hole.