Semiconductor structure

Abstract

The invention discloses a semiconductor structure. The semiconductor structure includes a pad array. The bonding pad array comprises a plurality of bonding pads, a bonding pad boundary, a plurality of second branches and at least one first surrounding bonding pad. The pads are arranged in a plurality of rows. The bonding pad boundary is arranged outside all the bonding pads and comprises a plurality of first branches. The second branches and the first branches are alternately arranged. The at least one first peripheral bonding pad is located between the first branch and the bonding pads and located between two adjacent second branches, and the gravity center of the at least one first peripheral bonding pad and the gravity centers of the bonding pads arranged in the same row are not on the same line. Therefore, the peripheral bonding pads with the center of gravity shifted are arranged on the periphery of the bonding pad array, so that the possibly derived structural defects of the semiconductor device are improved.

Description

[0001] This application is a divisional application of the original application with the application number 202410396139.6 and the original filing date of April 2, 2024, and the entire contents of the original application are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to a semiconductor structure and a manufacturing method thereof, and in particular, to a semiconductor structure including a pad. BACKGROUND

[0003] With the trend of miniaturization of various electronic products, the design of dynamic random access memory (DRAM) cells must also meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, because it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the DRAM cell with only a planar gate structure under the current mainstream development trend. Generally, a DRAM cell with a recessed gate structure includes a transistor component and a charge storage device to receive voltage signals from bit lines and word lines. However, due to the limitations of process technology, the existing DRAM cell with a recessed gate structure still has many defects and needs to be further improved and effectively improve the performance and reliability of the related memory device. SUMMARY

[0004] One purpose of the present application is to provide a semiconductor structure that improves the structural defects that may be derived from the continuous improvement of the density of memory cells by arranging a center-of-gravity offset peripheral pad on at least one side of a pad array.

[0005] To achieve the above-mentioned purpose, one embodiment of the present application provides a semiconductor structure including a pad array. The pad array includes a plurality of pads, a pad boundary, a plurality of second branches, and at least one first peripheral pad. The pads are arranged along a first direction and a second direction, and are arranged in multiple rows in the first direction. The pad boundary is arranged outside all the pads and includes a plurality of first branches extending in the first direction. The second branches extend in the first direction and are alternately arranged with the first branches in the third direction. The at least one first peripheral pad is arranged between the first branches and the pads in the first direction, and is arranged between two adjacent second branches in the third direction, wherein the center of gravity of the at least one first peripheral pad and the center of gravity of the pads arranged in the same row in the first direction are not on the same line.

[0006] To achieve the above-mentioned object, another embodiment of the present application provides a semiconductor structure including a pad array. The pad array includes a plurality of pads, a pad border, and a plurality of second branches. The pads are arranged along a first direction and a second direction, and each of the pads has two opposite sides parallel to the first direction. The pad border is arranged outside all of the pads and includes a plurality of first branches extending along the first direction. The second branches extend along the first direction and are arranged alternately with the first branches along a third direction. At least one surrounding pad is located between the pad border and the pads, wherein the at least one surrounding pad has two opposite sides parallel to each other, and the two opposite sides of the at least one surrounding pad are not parallel to the two opposite sides of any of the pads.

[0007] To achieve the above-mentioned object, another embodiment of the present application provides another method for manufacturing a semiconductor structure, including the following steps. A chip is provided, and a plug array including a plurality of plugs is formed on the chip. A plurality of first parallel patterns extending along a first direction are defined on the chip. A plurality of second parallel patterns extending along a second direction are defined on the chip, and the second direction is different from the first direction. An end of at least one of the second parallel patterns is modified to define at least one modified pattern, wherein the end of the at least one modified pattern deviates from the first direction. A first patterning process is performed through the first parallel patterns, and a second patterning process is performed through the modified pattern and the second parallel patterns, so as to form a pad array including a plurality of pads and at least one surrounding pad on the plugs, and each of the pads is coincident with a corresponding plug below.

[0008] In general, the semiconductor structure and the method for manufacturing the same are characterized in that, before performing twice self-aligned reverse patterning processes, a modification step is performed to adjust the inclination angle and / or line width of an end of at least one pattern, so as to ensure that the end of a corresponding mask pattern formed after the modification step is coincident with a plug arranged below, and thus the center of gravity of a surrounding pad formed on at least one side of the pad array deviates from the center of gravity of an adjacent pad, or the side of the surrounding pad is not parallel to the side of the adjacent pad, thereby ensuring the coincidence between the surrounding pad and the corresponding plug, and improving the structural defects of the semiconductor structure caused by the continuous increase of the storage unit density. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate the principles of the embodiments. It will be appreciated that all the drawings are schematic and for purposes of illustration and convenience in drafting, the relative sizes and proportions of the elements have been modified. Identical symbols represent corresponding or analogous features in different embodiments.

[0010] Figures 1-2Fig. 1 is a schematic view of a semiconductor structure according to a first embodiment of the present application, wherein:

[0011] Figure 1 Fig. 2 is a schematic view of a top view of the semiconductor structure; and

[0012] Figure 2 Fig. 3 is a schematic view of a cross-section along the tangent D-D'. Figure 1 Fig. 4 is a schematic view of a cross-section along the tangent D-D'.

[0013] Figures 3-4 Fig. 5 is a schematic view of a semiconductor structure according to a second embodiment of the present application, wherein:

[0014] Figure 3 Fig. 6 is a schematic view of a top view of the semiconductor structure; and

[0015] Figure 4 Fig. 7 is a schematic view of a cross-section along the tangent D-D'. Figure 3 Fig. 8 is a schematic view of a cross-section along the tangent D-D'.

[0016] Figures 5-10 Fig. 9 is a schematic view of a method of manufacturing a semiconductor structure according to a preferred embodiment of the present application, wherein:

[0017] Figure 5 Fig. 10 is a schematic view of a flow chart of the method of manufacturing a semiconductor structure;

[0018] Figure 6 Fig. 11 is a schematic view after forming a parallel pattern;

[0019] Figure 7 Fig. 12 is a schematic view after modifying the parallel pattern;

[0020] Figure 8 Fig. 13 is a schematic view of a top view of forming a mask pattern according to the parallel pattern;

[0021] Figure 9 Fig. 14 is a schematic view of a top view of forming a mask pattern according to the modified pattern; and

[0022] Figure 10 Fig. 15 is another schematic view after modifying the parallel pattern.

[0023] Wherein, the reference numerals are explained as follows:

[0024] 10, 20 semiconductor structure

[0025] 100A storage area

[0026] 100B peripheral area

[0027] 102 insulating layer

[0028] 104 isolation structure

[0029] 110 pad array

[0030] 111 pad

[0031] 111a side edge

[0032] 113 pad border

[0033] 115 first peripheral pad, peripheral pad

[0034] 115a side edge

[0035] 117 first branch

[0036] 119 second branch

[0037] 121 first edge

[0038] 123 second edge

[0039] 125 second peripheral pad, peripheral pad

[0040] 125a side edge

[0041] 130 word line

[0042] 131 dielectric layer

[0043] 133 gate dielectric layer

[0044] 135 gate

[0045] 137 cap layer

[0046] 140 plug array

[0047] 141, 143 plug

[0048] 200 chip

[0049] 202 mask layer

[0050] 204 first parallel pattern

[0051] 206 second parallel pattern

[0052] 208, 210, 308, 310 modified pattern

[0053] 212 first opening

[0054] 214 silicon hard mask bottom antireflective coating

[0055] 216 second mask pattern

[0056] A, B, C center of gravity

[0057] D1 first direction

[0058] D2 second direction

[0059] D3 third direction

[0060] D4 fourth direction

[0061] L1 first length

[0062] L2 second length

[0063] L3, L4 extension length

[0064] L5 length

[0065] R1, R2, R3…Rn row

[0066] S1 first distance

[0067] S2 second distance

[0068] S3 third distance

[0069] S4 fourth distance

[0070] S5 fifth distance

[0071] S6 sixth distance

[0072] S7 seventh distance

[0073] S8 eighth distance

[0074] S9 ninth distance

[0075] S10 tenth distance

[0076] W1, W2 end line width

[0077] θ1, θ2 angle DETAILED DESCRIPTION

[0078] In order to enable the person skilled in the art to further understand the present application, the following preferred embodiments of the present application are listed, and the constitution content and the desired effect of the present application are described in detail with the aid of the accompanying drawings. It should be understood that the following embodiments can be replaced, reorganized, mixed to complete other embodiments without departing from the spirit of the present application.

[0079] Please refer to Figures 1-2 , which is a schematic diagram of the semiconductor structure 10 in the first embodiment of the present application. First, as shown in Figure 1As shown, the semiconductor structure 10 includes a pad array 110, which includes a plurality of pads 111, pad boundaries 113, first peripheral pads 115, a plurality of first branches 117, and a plurality of second branches 119. The pads 111 are arranged alternately along a first direction D1 and a second direction D2, which are intersecting but not perpendicular, and are arranged in multiple rows R1, R2…Rn along the first direction D1 to serve as storage node pads (SNpads) for semiconductor devices (not shown, such as dynamic random access memory devices). The pad boundaries 113 are located outside all the pads 111, including the first branches 117 extending along the first direction D1. The second branches 119 also extend along the first direction D1 and are alternately arranged with the first branches 117 along the third direction D3. It should be noted that at least one first peripheral pad 115 is located between a first branch 117 and a pad 111 along the first direction D1, and between two adjacent second branches 119 along the third direction D3. In this configuration, the centroid A of the pads 111 arranged in the same row R1, R2...Rn all fall on the same extension line parallel to the first direction D1, while the centroid B of at least one first surrounding pad 115 arranged in the same row of pads 111 does not fall on the same extension line. Under this configuration, as... Figure 2 As shown, the centers of gravity A / B of pad 111 and / or at least one first surrounding pad 115 can respectively correspond to the center of gravity of the plug 141 disposed below, ensuring the contact range between pad 111 and / or at least one first surrounding pad 115 and the corresponding plug 141. Thus, by providing a first surrounding pad 115 on one side of the pad array 110 whose center of gravity is offset from the center of gravity A of the adjacent row of pads 111, structural defects that may arise in the semiconductor structure 10 due to the continuous increase in memory cell density can be improved.

[0080] In detail, such as Figure 1As shown, the first branches 117 are sequentially arranged in the third direction D3, and the first surrounding pads 115 are respectively arranged between each first branch 117 and the corresponding pad 111, such that the first surrounding pads 115 are all located on one side of the pad array 110 and have the center of gravity B deviated from the extension line. Wherein, the center of gravity B of each first surrounding pad 115 has a first distance S1 and a second distance S1 respectively between two adjacent second branches 119 in the third direction D3, and the first distance S1 is less than the second distance S2, for example. While the center of gravity B of each first surrounding pad 115 has a third distance S3 and a fourth distance S4 respectively between one adjacent pad 111 and one first branch 117 in the first direction D1, and the third distance S3 is less than the fourth distance S4, for example. On the other hand, the center of gravity A of each pad 111 has a fifth distance S5 and a sixth distance S6 respectively between two adjacent pads 111 in the third direction D3, and the difference between the fifth distance S5 and the sixth distance S6 is less than the difference between the first distance S1 and the second distance S2, for example. While the center of gravity A of each pad 111 has a seventh distance S7 and an eighth distance S8 respectively between two adjacent pads 111 in the first direction D1, and the difference between the seventh distance S7 and the eighth distance S8 is less than the difference between the third distance S3 and the fourth distance S4, for example. In a preferred embodiment, the fifth distance S5 and the sixth distance S6 are the same as each other, and / or the seventh distance S7 and the eighth distance S8 are preferably the same as each other, i.e. the difference between the two is zero, but not limited thereto.

[0081] Further as shown Figure 1 As shown, the pad boundary 113 includes two first edges 121 arranged in the third direction D3, and two second edges 123 arranged in the fourth direction D4 perpendicular to the third direction D3. In an embodiment, each first edge 121 is directly connected to one end of each second edge 123 to form a whole rectangular frame structure and surround the pads 111 and the first surrounding pads 115, thereby achieving the effect of protecting the pads 111 and the first surrounding pads 115, but not limited thereto. Those skilled in the art should easily understand that in another embodiment, the pad boundary can also optionally include other edges to form a whole other suitable shape, thereby achieving a more optimized protection effect. Wherein, each first branch 117 is arranged on the first edge 121, for example, and has a first length L1 in the first direction D1, while each second branch 119 is arranged close to but not in contact with the first edge 121, and has a second length L2 in the first direction D1, and the first length L1 is less than the second length L2, for example, but not limited thereto.

[0082] The pad array 110 further includes a plurality of second surrounding pads 125 disposed between the second edges 123 of the pad boundary 113 and the pads 111 in the third direction D3. It is noted that the center of gravity C of each of the second surrounding pads 125 is also offset from the extension line of the center of gravity A of the adjacent row of pads 111. In which, the center of gravity C of each of the second surrounding pads 125 has a ninth distance S9 and a tenth distance S10 to the adjacent second edge 123 and pad 111 in the third direction D3, respectively, the ninth distance S9 is for example smaller than the tenth distance S10, and the ninth distance S9 is not equal to the aforementioned first distance S1, but not limited thereto. In this way, the center of gravity C of the second surrounding pads 125 can also correspond to the center of gravity of the plug 141 disposed below, as shown in Figure 2 Fig. 8, to ensure the contact range between the second surrounding pads 125 and the corresponding plug 141. In an embodiment, the maximum extension length L3 of each of the second surrounding pads 125 is for example different from the maximum extension length L4 of each of the first surrounding pads 115, and the maximum extension length L4 of the first surrounding pads 115 is preferably equal to the length L5 of each of the pads 111 in the first direction D1 or the second direction D2. It should be easily understood by those skilled in the art that the aforementioned first length L1, second length L2, maximum extension lengths L3, L4, and length L5 all refer to the average length or maximum length of each component of the pad array 110 in the first direction D1 or the second direction D2, but not limited thereto. The pad array 110 for example includes a low resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), and preferably includes tungsten, but not limited thereto.

[0083] As shown in Figure 1 and Figure 2 The semiconductor structure 10 further includes a substrate 100 and a plurality of word lines 130 disposed in the substrate 100. The aforementioned pad array 110 is for example disposed on the substrate 100, which for example includes a silicon substrate, a silicon-containing substrate (such as SiC, SiGe), or a silicon-on-insulator substrate or other suitable material, but not limited thereto. Moreover, the pads 111 of the pad array 110 are in principle disposed in a storage region (cell region) 100A of the substrate 100 with relatively high component integration, and the first branch 117, the second branch 119 and the like around the pad array 110 are in principle disposed in a periphery region (periphery region) 100B of the substrate 100 with relatively low component integration. In an embodiment, the periphery region 100B is for example disposed on at least one side of the storage region 100A, and preferably, from Figure 1The peripheral region 100B is, for example, disposed around the storage region 100A as viewed from the top view, but is not limited thereto. The word lines 130 are disposed in the substrate 100 in a manner of being separated from each other, and include, in detail, a dielectric layer 131, a gate dielectric layer 133, and a gate 135 which are sequentially stacked, and a cap layer 137 which covers the gate 135, as shown. Figure 2 The surface of the cap layer 137 can be flush with the top surface of the substrate 100, so that each of the word lines 130 serves as a buried word line (BWL) of the semiconductor device and is electrically isolated from components disposed on the substrate 100 by the insulating layer 102 disposed on the substrate 100. In an embodiment, the insulating layer 102 preferably has a composite layer structure, for example, an oxide-nitride-oxide (ONO) structure, but is not limited thereto.

[0084] As shown again Figure 2 The semiconductor structure 10 further includes a plug array 140 which is also disposed on the substrate 100, including a plurality of plugs 141, 143 which are disposed in the storage region 100A and the peripheral region 100B, respectively. Each of the plugs 141, 143 is disposed in the first direction D1 in an alternating manner with the plurality of isolation structures 104, so as to be electrically isolated from adjacent plugs 141, 143 by the isolation structures 104. In an embodiment, the plugs 141, 143 include, for example, epitaxial materials such as silicon (Si), silicon phosphorus (SiP), silicon germanium (SiGe), or germanium (Ge), or low-resistance metal materials such as aluminum, titanium, copper, or tungsten, but are not limited thereto. In a direction perpendicular to the substrate 100, each of the plugs 141 is disposed below the pads 111 or the first surrounding pads 115 and physically contacts the corresponding pads 111 or the first surrounding pads 115 above. In this way, the top of the plug 141 is electrically connected to the pad 111 or the first surrounding pad 115, and the bottom of the plug 141 extends into the substrate 100 and is electrically connected to a transistor component (not shown) disposed in the substrate 100, so as to serve as a storage node contact (SNC) of the semiconductor device and further electrically connect to a storage node (SN) which is disposed above the pad array 110 subsequently. On the other hand, each of the plugs 143 is disposed below the first branches 117 or the second branches 119 and physically contacts the corresponding first branches 117 or second branches 119 above. However, the bottom of the plug 143 is on the insulating layer 102 and does not contact the substrate 100, so as to serve as a dummy plug of the semiconductor device.

[0085] According to the semiconductor structure 10 of the first embodiment of the present application, by disposing the first surrounding pads 115 and / or the second surrounding pads 125 with the centers of gravity deviated from the center of gravity A of the adjacent one row of pads 111 around the pad array 110, for example, at least one side of the pad array 110, the centers of gravity B / C of the first surrounding pads 115 and / or the second surrounding pads 125 adjacent to the pad border 113 can correspond to the center of gravity of the plug 141 disposed below, so as to ensure the contact range between the first surrounding pads 115 and / or the second surrounding pads 125 and the corresponding plug 141. Accordingly, by disposing the first surrounding pads 115 and / or the second surrounding pads 125 with the centers of gravity deviated at least one side of the pad array 110, the structural defects of the semiconductor structure 10 due to the continuous increase of the storage cell density can be improved. Those skilled in the art of the present application should easily understand that the semiconductor structure 10 of the present embodiment can also be provided with various components, such as transistor components, bit line components and / or capacitor components, etc. in the storage region 100A according to the actual device requirements, so as to form a dynamic random access memory device and achieve good device performance.

[0086] Please refer to Figures 3-4 , which is a schematic diagram of the semiconductor structure 20 of the second embodiment of the present application. The semiconductor structure 20 of the present embodiment is generally the same as the semiconductor structure 10 of the foregoing embodiment, for example, both include the pad array 110, the word line 130 and the plug array 140, and the pad array 110 also includes the plurality of pads 111, the pad border 113, the plurality of first branches 117 and the plurality of second branches 119, and the same parts will not be described here.

[0087] As shown in Figures 3-4 , the main difference between the manufacturing method of the semiconductor structure 20 of the present embodiment and the foregoing first embodiment is that the pad array 110 further includes at least one surrounding pad 115 / 125, for example, between the first edge 121 or the second edge 123 of the pad border 113 and the pad 111. The at least one surrounding pad 115 / 125 has two opposite sides 115a / 125a parallel to each other, and each pad 111 has two opposite sides 111a parallel to the first direction D1 or the second direction D2, and the two opposite sides 115a / 125a of the at least one surrounding pad 115 / 125 are not parallel to the two opposite sides 111a of any pad 111 in the second direction D2. Under this arrangement, Figure 4As shown, at least one of the surrounding pads 115 / 125 can correspond to the underlying plug 141, respectively, to ensure the contact range between the at least one of the surrounding pads 115 / 125 and the corresponding plug 141. In this way, by providing the at least one of the surrounding pads 115 / 125 with side edges 115a that are not parallel to the side edges 111a of the adjacent pads 111 around the pad array 110, e.g. at least one side of the pad array 110, the structural defects of the semiconductor structure 10 due to the increasing density of the memory cells can be improved.

[0088] In detail, as shown in Figure 3 The semiconductor structure 10 comprises a plurality of surrounding pads 115 and / or a plurality of surrounding pads 125. The surrounding pads 115 are arranged between each of the first branches 117 and the corresponding pads 111, respectively. In this regard, the two opposite side edges 115a of each of the surrounding pads 115 are not parallel to the two opposite side edges 111a of the corresponding pads 111 in the second direction D2, and the included angle θ1 between the two opposite side edges 115a of the surrounding pads 115 and the two opposite side edges 111a of the pads 111 is not greater than 90 degrees, but not limited thereto. On the other hand, the surrounding pads 125 are arranged between the second edges 123 and the corresponding pads 111 in the third direction D3, respectively. In this regard, the two opposite side edges 125a of each of the surrounding pads 125 are also not parallel to the two opposite side edges 111a of the corresponding pads 111 in the second direction D2, and the included angle θ2 between the two opposite side edges 125a of the surrounding pads 125 and the two opposite side edges 111a of the pads 111 is not greater than 90 degrees, and the included angle θ2 is preferably different from the included angle θ1, but not limited thereto. In an embodiment, the surrounding pads 115 and the surrounding pads 125, for example, have different maximum extension lengths, respectively, wherein the maximum extension length L3 of the surrounding pads 125 is preferably greater than the maximum extension length L4 of the surrounding pads 115, or the length L5 of each of the pads 111 in the first direction D1 or the second direction D2, and the maximum extension length L4 of the surrounding pads 115 is also preferably greater than the length L5 of the pads 111, but not limited thereto.

[0089] According to the semiconductor structure 20 of the second embodiment of the present application, by means of the peripheral pads 115 / 125, which are arranged around the pad array 110, for example, at least one side of the pad array 110, and have side edges 115a / 125a which are not parallel to the side edges 111a of the pads 111, and / or have a maximum extension length which is greater than the length L5 of the pads 111, the arrangement positions of the peripheral pads 115 / 125 adjacent to the pad boundaries 113 can all be aligned with the underlying arranged plugs 141, so as to ensure the contact range between the peripheral pads 115 / 125 and the corresponding plugs 141. In this way, by means of the peripheral pads 115 / 125 arranged at at least one side of the pad array 110, the structural defects of the semiconductor structure 20 which may be caused by the continuous increase of the memory cell density can be improved, so that the subsequently further composed dynamic random access memory device can achieve good device performance.

[0090] In order to enable the person skilled in the art to which the semiconductor structure 10 / 20 of the present application belongs to easily understand the semiconductor structure 10 / 20 of the present application, the manufacturing method of the semiconductor structure 10 / 20 of the present application will be further described below.

[0091] Please refer to Figures 5-10 , which is a schematic diagram of the manufacturing method of the semiconductor structure 10 / 20 in the preferred embodiment of the present application, wherein, Figure 5 is a schematic diagram of the step flow of the manufacturing method of the semiconductor structure 10 / 20, Figures 6-10 is a schematic diagram of the manufacturing process of the semiconductor structure 10 / 20. First, please refer to Figure 5 and Figure 6 , a chip 200 is provided, and a plug array 140 is formed on the chip 200 (step S1), which includes a plurality of plugs 141.

[0092] Then, a mask layer 202 is formed on the chip 200, covering the plug array 110, and a parallel pattern is defined on the mask layer 202 (step S2), which includes a plurality of first parallel patterns 204 arranged along a first direction D1 and separated from each other, and a plurality of second parallel patterns 206 arranged along a second direction D2 and separated from each other. Wherein, each first parallel pattern 204 and each second parallel pattern 204, for example, respectively presents a strip shape, and the first parallel patterns 204 and the second parallel patterns 206 are interlaced with each other, as shown in Figure 6 .

[0093] As shown in Figure 5 and Figure 7As shown, a modification step is performed to modify at least one parallel pattern (step S3) to define at least one modified pattern 208 / 210. In detail, the modification step is, for example, adjusting the tilt angle of the end of at least one second parallel pattern 206 (step S31), for example, to make the end of at least one modified pattern 208 / 210 deviate from the second direction D2 by a deviation angle θ1 / θ2, for example, less than 90 degrees, but not limited thereto. Those skilled in the art in the field of the present disclosure should easily understand that, in an embodiment, the modification step can be performed on the end of any second parallel pattern 206 according to actual manufacturing needs, or alternatively, the modification step can be performed on the end of all second parallel patterns 206 simultaneously. For example, before defining at least one modified pattern 208 / 210, a comparison step can be performed in advance to select the second parallel pattern 206 to be modified by comparing the overlapping ratio of each second parallel pattern 206 with the underlying plug 141, and then performing the modification step on the selected second parallel pattern 206 to make the overlapping ratio of at least one modified pattern 208 / 210 with the underlying plug 141 greater than the overlapping ratio of the second parallel pattern 206 before modification with the underlying plug 141. Alternatively, in another embodiment, the modification step can be performed on the end of a portion of the second parallel patterns 206 to make the end thereof deviate from the second direction D2 and have a deviation angle θ1, and the modification step can be performed on the end of another portion of the second parallel patterns 206 to make the end thereof deviate from the second direction D2 and have a deviation angle θ2, as shown, but not limited thereto. Among them, the deviation angle θ2 is preferably not equal to the deviation angle θ1, so that the overlapping ratio of the modified patterns 208, 210 with the underlying plug 141 can be greater than the overlapping ratio of the second parallel patterns 206 before modification with the underlying plug 141. Figure 7

[0094] Then, as shown in Figure 5 and Figures 8-9 , a pad array is formed by the parallel pattern (step S4) to form a semiconductor structure 10, 20 as shown in Figure 1 or Figure 3 . In detail, a first patterning process is first performed by the first parallel pattern 204, for example, a first self-aligned reverse patterning (SARP) manufacturing process, to etch a plurality of first openings 212 in the form of a rectangular frame on the mask layer 202, as shown in Figure 8 ​As shown. Next, a mask structure (not shown) is formed on the mask layer 202, covering all the first openings 212. The mask structure, for example, has a composite structure including sequentially stacked organic underlayers (not shown), a silicon hard mask bottom anti-reflective coating 214, and a plurality of second mask patterns 216 in a rectangular frame shape formed by performing a second patterning process, such as a second self-aligned reverse patterning process, through a second parallel pattern 204 and at least one correction pattern 208 / 210. Figure 9 As shown. Then, a second etching process is performed using the second mask pattern 216. The rectangular frame pattern of the second mask pattern 216 is first sequentially transferred to the lower silicon hard mask bottom anti-reflective coating 214 and the organic underlayer, and then transferred to the lower mask layer 202, so that multiple second openings (not shown) in a rectangular frame shape are etched again on the mask layer 202. Subsequently, at least one more etching process is performed to transfer the pattern on the mask layer 202 to the conductive material layer (not shown) on the chip 200, thus forming a pattern on the conductive material. Figure 1 or Figure 3 The pad array 110 shown includes multiple pads 111 and at least one surrounding pad 115 / 125, which overlap the plug 141 below.

[0095] This operation completes the fabrication of the semiconductor structure 10 / 20 in the preferred embodiment of the present invention. According to the fabrication method of this embodiment, the pads 111 in the pad array 110 are fabricated by performing two self-aligned reverse patterning processes, and the surrounding pads 115 / 125 are fabricated by additionally performing the aforementioned correction step. Thus, by performing the correction step, the degree of overlap between the end of the second mask pattern 216 and the lower plug 141 is adjusted, so that the center of gravity of the formed surrounding pads 115 / 125 is offset from the center of gravity A of the adjacent pads 111, or the side edges of the surrounding pads 115 / 125 are not parallel to the side edges 111a of the adjacent pads 111, thereby ensuring the overlap rate between the surrounding pads 115 / 125 and the corresponding plugs 141. Accordingly, by forming the surrounding pads 115 / 125 on at least one side of the pad array 110, structural defects that may arise in the semiconductor structure 10 / 20 due to the continuous increase in memory cell density can be improved. Those skilled in the art to which this invention pertains should readily understand that the semiconductor structure 10 / 20 of this embodiment can also form various components, such as transistor components, bit line components, and / or capacitor components, within the storage region 100A according to actual device requirements, in order to subsequently form a dynamic random access memory device and achieve good device performance.

[0096] Furthermore, to meet actual product requirements, the method for fabricating the semiconductor device of the present invention may also have other forms and is not limited to those described above. For example, such as Figure 10In another embodiment, the modification step can also be used to adjust the line width of the end of at least one of the second parallel patterns 206 to form at least one modified pattern 308 / 310 with a relatively larger end line width W1 / W2, so that the overlap ratio of the at least one modified pattern 308 / 310 with the underlying plug 141 is greater than the overlap ratio of the second parallel pattern 206 before modification with the underlying plug 141. Similarly, the modification step of the present embodiment can be performed on the end of any one of the second parallel patterns 206, or simultaneously performed on the end of all the second parallel patterns 206, or selectively adjust the end line width of a portion of the second parallel patterns 206 to have a relatively larger end line width W1, while adjusting the end line width of another portion of the second parallel patterns 206 to have a relatively larger end line width W2, as shown in FIG. 3B, but not limited thereto. In the present embodiment, the end line width W2 is preferably not equal to the end line width W1, so that the overlap ratio of the modified patterns 308, 310 with the underlying plug 141 is greater than the overlap ratio of the second parallel pattern 206 before modification with the underlying plug 141. In other embodiments, the modification step can be used to simultaneously adjust the inclination angle and the end line width of at least one of the second parallel patterns 206 to further improve the overlap ratio of the modified pattern (not shown) before modification with the underlying plug 141. Thus, the surrounding pads 115 / 125 formed by performing the aforementioned modification step can also have a center of gravity deviated from the center of gravity A of the adjacent pads 111, or have a side edge not parallel to the side edge 111a of the adjacent pads 111, to ensure the overlap ratio between the surrounding pads 115 / 125 and the corresponding plug 141, thereby improving the structural defects of the semiconductor structure due to the continuous increase in the density of memory cells. Figure 10

[0097] In summary, the semiconductor structure and the method of manufacturing the same can be used to perform a modification step to adjust the inclination angle and / or the line width of at least one pattern before performing twice the self-aligned reverse patterning process, so that the end of the corresponding mask pattern formed thereby can be highly overlapped with the underlying plug, so that the center of gravity of the surrounding pads formed around the pad array can be deviated from the center of gravity of the adjacent pads, or the side edge of the surrounding pads can be not parallel to the side edge of the adjacent pads, thereby ensuring the overlap ratio between the surrounding pads and the corresponding plug, to improve the structural defects of the semiconductor structure due to the continuous increase in the density of memory cells. In this operation, the method of manufacturing the semiconductor structure of the present application can effectively avoid the structural defects of the surrounding pads around the pad array due to the continuous increase in the density of memory cells, so that the semiconductor structure of the present application can have an optimized structure and component reliability, and achieve excellent operational performance and efficiency.

[0098] ​The above merely provides the preferred embodiments of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the principles and technical scope of the present application shall fall into the scope of the present application.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a plurality of pads arranged along a first direction and a second direction, and arranged in a plurality of rows along the first direction, wherein the centers of gravity of the pads in a same row are located on a same center of gravity line; a plurality of branches arranged outside all the pads and extending along the first direction, the branches comprising a plurality of long branches and a plurality of short branches, the long branches and the short branches being arranged alternately along a third direction; and at least one surrounding pad located between the short branches and the pads along the first direction and between two adjacent long branches along the third direction, wherein the center of gravity of the at least one surrounding pad deviates from the center of gravity line of the row.

2. The semiconductor structure of claim 1, wherein, The at least one surrounding pad comprises at least one first surrounding pad, the center of gravity of the at least one first surrounding pad having a first distance and a second distance to two adjacent long branches along the third direction, the first distance being smaller than the second distance.

3. The semiconductor structure of claim 1, wherein, The at least one surrounding pad comprises at least one first surrounding pad, the center of gravity of the at least one first surrounding pad having a third distance and a fourth distance to one pad and one short branch along the first direction, the third distance being smaller than the fourth distance.

4. The semiconductor structure of claim 2, wherein, The center of gravity of each pad has a fifth distance and a sixth distance to two adjacent pads along the third direction, wherein the difference between the fifth distance and the sixth distance is smaller than the difference between the first distance and the second distance.

5. The semiconductor structure of claim 3, wherein, The center of gravity of each pad has a seventh distance and an eighth distance to two adjacent pads along the first direction, wherein the difference between the seventh distance and the eighth distance is smaller than the difference between the third distance and the fourth distance.

6. The semiconductor structure of claim 2, wherein, The semiconductor structure further comprises at least one second surrounding pad located between a pad boundary and the pads along the third direction, the pad boundary extending along a fourth direction perpendicular to the third direction, the center of gravity of the at least one second surrounding pad having a ninth distance to the pad boundary along the third direction, and the center of gravity of the at least one second surrounding pad having a tenth distance to one pad along the third direction, the ninth distance being smaller than the tenth distance.

7. The semiconductor structure of claim 6, wherein, The at least one first surrounding pad and the at least one second surrounding pad have different extension lengths.

8. The semiconductor structure of claim 6, wherein, The ninth distance is not equal to the first distance.

9. A semiconductor structure comprising: a plurality of pads arranged along a first direction and a second direction, and arranged in a plurality of rows along the first direction, wherein the centers of gravity of the pads in a same row are located on a same center of gravity line; and at least one surrounding pad located on one side of all the pads in the same row along the first direction, wherein the center of gravity of the at least one surrounding pad deviates from the center of gravity line of the row.

10. The semiconductor structure of claim 9, wherein, The semiconductor structure further comprises a pad boundary surrounding the plurality of pads, the at least one surrounding pad being located between the pad boundary and the pads, wherein the at least one surrounding pad has two opposite side edges parallel to each other, and the two opposite side edges of the at least one surrounding pad are not parallel to the two opposite side edges of any pad.

11. The semiconductor structure of claim 10, wherein, An angle between one of the two opposite sides of the at least one peripheral pad and one of the two opposite sides of the pad is not greater than 90 degrees.

12. The semiconductor structure of claim 10, wherein, The at least one peripheral pad comprises a plurality of the peripheral pads, at least two of the peripheral pads having different maximum extension lengths.

13. The semiconductor structure of claim 12, wherein, Angles between one of the two opposite sides of at least two of the peripheral pads and one of the two opposite sides of the pad are not equal.

14. The semiconductor structure of claim 9, wherein, A maximum extension length of the at least one peripheral pad is greater than a length of each of the pads in the first direction.

15. The semiconductor structure of claim 9, wherein, A plurality of branches are further included, disposed outside all of the pads, extending in the first direction, the branches comprising a plurality of long branches and a plurality of short branches, the long branches and the short branches being alternately arranged in a third direction; The at least one peripheral pad comprises at least one first peripheral pad, the at least one peripheral pad being positioned between the short branches and the pads in the first direction, and between two adjacent long branches in the third direction.

16. The semiconductor structure of claim 15, wherein, The at least one peripheral pad comprises at least one second peripheral pad, the at least one second peripheral pad being positioned between a pad boundary and the pads in the third direction.

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