Managing capacitors in semiconductor devices

Abstract

Systems, devices, and methods for managing capacitors in semiconductor devices are provided. In one aspect, a semiconductor device includes a capacitor and a semiconductor body corresponding to the capacitor. The semiconductor bodies each include a first end coupled to an end of a respective one of the capacitors. The semiconductor device includes a ring-shaped conductive structure including a pair of wire segments and a pair of end segments adjacent to ends of the pair of wire segments. A pair of wire segments is coupled to the second end of the semiconductor body. A pair of end sections is coupled to the control circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and manufacturing processes for semiconductor devices. BACKGROUND

[0002] Semiconductor memory devices can be classified as nonvolatile memory devices, such as flash memory devices, and volatile memory devices, such as dynamic random access memory (DRAM). Semiconductor memory devices can have different structures with different densities of memory cells and lines on a chip. A memory device typically includes a memory array of memory cells and a control circuit. The control circuit can facilitate operation of the memory array. SUMMARY

[0003] The present disclosure describes methods, devices, systems, and techniques for managing capacitor structures of control circuitry in three-dimensional (3D) semiconductor devices.

[0004] One aspect of the present disclosure features a semiconductor device including capacitors and semiconductor bodies corresponding to the capacitors. The semiconductor bodies each include a first end coupled to an end of a respective one of the capacitors. The semiconductor device includes a ring-shaped conductive structure including a pair of line segments and a pair of end segments contiguous with ends of the pair of line segments. The pair of line segments is coupled to second ends of the semiconductor bodies. The pair of end segments is coupled to control circuitry.

[0005] In some implementations, the semiconductor device includes a pair of conductive vias. First ends of the pair of conductive vias are coupled to the pair of end segments of the ring-shaped conductive structure. Second ends of the pair of conductive vias are coupled to a conductor. The conductor is coupled to the control circuitry.

[0006] In some implementations, the semiconductor device includes memory cells each including a transistor and a capacitor. The transistor includes a transistor body, a gate structure, a first terminal, and a second terminal on opposite ends of the transistor body. The first terminal of the transistor is coupled to the capacitor. The semiconductor device includes bit lines. Each bit line is coupled to a corresponding second terminal of the transistor. The semiconductor device includes individual conductive vias. A first conductive via of the individual conductive vias is coupled to a first end of a first bit line of the bit lines. A second conductive via of the individual conductive vias is coupled to a second end of a second bit line adjacent to the first bit line. The first end is opposite the second end.

[0007] In some implementations, the first end of the first bit line extends beyond the first end of the second bit line.

[0008] In some implementations, the capacitor, the semiconductor body, the ring-shaped conductive structure, and the pair of conductive vias are in a semiconductor structure. The semiconductor device further includes a control structure bonded with the semiconductor structure. The control structure includes the control circuit. The capacitor is coupled to the control circuit through the ring-shaped conductive structure, the pair of conductive vias, and the conductor.

[0009] In some implementations, the semiconductor structure includes one or more first conductive contacts isolated by a first dielectric material. The control structure includes one or more second conductive contacts isolated by a second dielectric material. The one or more first conductive contacts are in contact with the one or more second conductive contacts.

[0010] In some implementations, the semiconductor body includes doped polysilicon having a dopant concentration greater than 1E15 dopant atoms per cubic centimeter.

[0011] In some implementations, the dopant includes at least one of phosphorus (P), arsenic (As), boron (B), or gallium (Ga).

[0012] In some implementations, a resistance of one of the semiconductor bodies is in a range between 100 kilo-ohms and 500 kilo-ohms.

[0013] In some implementations, the pair of line segments of the ring-shaped conductive structure have uniform lengths.

[0014] In some implementations, a semiconductor device includes a first region and a second region. The first region includes the capacitor, the semiconductor body, and the ring-shaped conductive structure. Each of the second regions includes the memory cell and the bit line. The first region is centered in the second regions.

[0015] Another aspect of the disclosure features a semiconductor device including ring-shaped conductive structures each including a pair of line segments and a pair of end segments contiguous with ends of the pair of line segments. The semiconductor device includes pairs of conductive vias. A first end of each pair of conductive vias is coupled to the pair of end segments of a corresponding one of the ring-shaped conductive structures. The semiconductor device includes conductors each coupled to a second end of a corresponding pair of the pairs of conductive vias.

[0016] In some implementations, each line segment of the pair of line segments extends along a first direction, and the ring-shaped conductive structure is arranged along a second direction perpendicular to the first direction.

[0017] In some implementations, the semiconductor device includes capacitors and semiconductor bodies corresponding to the capacitors. Each semiconductor body includes a first end coupled to an end of a respective one of the capacitors and a second end coupled to the pair of wire segments of a corresponding one of the ring-shaped conductive structures.

[0018] In some implementations, the semiconductor bodies include doped polysilicon having a dopant concentration greater than 1E15 dopant atoms per cubic centimeter.

[0019] In some implementations, the dopant includes at least one of phosphorus (P), arsenic (As), boron (B), or gallium (Ga).

[0020] In some implementations, a resistance of one of the semiconductor bodies is in a range between 100 kilo-ohms and 500 kilo-ohms.

[0021] Another aspect of the disclosure features a method including forming capacitors and semiconductor bodies corresponding to the capacitors. Each of the semiconductor bodies includes a first end coupled to a respective one of the capacitors. The method includes forming ring-shaped conductive structures, each ring-shaped conductive structure including a pair of wire segments and a pair of end segments adjacent to ends of the pair of wire segments. The pair of wire segments is coupled to a second end of a corresponding one of the semiconductor bodies. The method includes forming pairs of conductive vias. Each pair of conductive vias is coupled to the pair of end segments of a corresponding one of the ring-shaped conductive structures.

[0022] In some implementations, forming the ring-shaped conductive structures includes: (i) forming a dielectric structure on a semiconductor substrate; (ii) depositing a spacer layer on sidewalls of the dielectric structure; (iii) removing the dielectric structure; and (iv) etching exposed portions of the semiconductor substrate.

[0023] In some implementations, the semiconductor bodies include doped polysilicon having a dopant concentration greater than 1E15 dopant atoms per cubic centimeter.

[0024] In some implementations, the dopant includes at least one of phosphorus (P), arsenic (As), boron (B), or gallium (Ga).

[0025] In some implementations, a resistance of one of the semiconductor bodies is in a range between 100 kilo-ohms and 500 kilo-ohms.

[0026] The details of one or more implementations of the subject matter of this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims. Attached Figure Description

[0027] The accompanying drawings, which are incorporated herein and form part of this disclosure, illustrate various aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0028] Figure 1 A cross-sectional view of an example semiconductor device is shown.

[0029] Figure 2A A plan view of an example semiconductor device is shown.

[0030] Figure 2B and Figure 2C It shows Figure 2A A schematic diagram of an example capacitor array for an example semiconductor device.

[0031] Figure 2D and Figure 2E It shows Figure 2A A schematic diagram of an example memory array of an example semiconductor device.

[0032] Figure 3A A schematic diagram of the equivalent circuit of the example capacitor array is shown.

[0033] Figure 3B A schematic diagram of the equivalent circuit of the example memory array is shown.

[0034] Figures 4A-4E A plan view of an additional embodiment of an example semiconductor device with different arrangements of a first region and a second region is shown.

[0035] Figures 5A-5F Top and cross-sectional views of an example semiconductor device are shown at various stages of an example process for forming an annular conductive structure and pairs of conductive vias.

[0036] Figure 6 A flowchart of an example process for forming a semiconductor device is shown.

[0037] Figure 7 A block diagram of the system is shown.

[0038] It should be understood that the various exemplary embodiments shown in the accompanying drawings are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0039] Complementary metal-oxide-semiconductor (CMOS) control circuits are commonly used with memory arrays to manage reading, writing, and other operations within the memory. The control circuits can include word line drivers, bit line drivers, row decoders, column decoders, and / or control logic, among others. Capacitors are commonly used in CMOS control circuits. In some cases, it can be difficult to create high capacitance or larger capacitors due to process complexities and design constraints in CMOS fabrication.

[0040] Embodiments of the present disclosure provide semiconductor devices and methods of forming such semiconductor devices. In some embodiments, a semiconductor device includes capacitors and semiconductor bodies corresponding to the capacitors. The semiconductor bodies each include a first end coupled to an end of a respective one of the capacitors. The semiconductor device includes a ring-shaped conductive structure including a pair of line segments and a pair of end segments contiguous with ends of the pair of line segments. The pair of line segments is coupled to second ends of the semiconductor bodies. The pair of end segments is coupled to a control circuit.

[0041] Embodiments of the present disclosure can provide one or more of the following technical advantages and / or benefits. By using a portion of a capacitor in a memory array to provide a capacitor to a CMOS circuit, existing resources can be effectively utilized, which helps to alleviate the need for additional steps in CMOS capacitor fabrication. Additionally, transforming two bit lines into a ring-shaped structure for a capacitor array can allow a pair of conductive vias to be connected at both ends of a single line segment of the ring-shaped structure. Such a configuration can also reduce the overall resistance of the circuit and alleviate potential risks of short circuits. Lower resistance in the CMOS control circuit can allow for faster operation, reduce power consumption, improve signal integrity, and / or improve thermal performance.

[0042] The technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices) or non-volatile memory (NVM) devices (e.g., NAND flash, NOR flash, resistive random access memory (RRAM), phase change memory (PCM) (e.g., phase change random access memory (PCRAM)), spin transfer torque (STT)-magnetic random access memory (MRAM), etc.). The technology can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating gate based memory devices. The technology can be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory types, such as SLC (single level cell) devices, MLC (multi-level cell) devices like 2-level cell devices, TLC (tri-level cell) devices, QLC (quad-level cell) devices, or PLC (penta-level cell) devices. Additionally or alternatively, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid state drives (SSD), embedded systems, etc.

[0043] Figure 1 A side view of a cross-section of an example 3D semiconductor device 100 is shown. The 3D semiconductor device 100 can be a 3D dynamic random access memory (DRAM). It should be understood that, Figure 1 For illustrative purposes only, can not necessarily reflect actual device structures (e.g., interconnects) in practice. In some implementations, the 3D semiconductor device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked above the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 can be joined at a bonding interface 106 between them.

[0044] As Figure 1 shown, the first semiconductor structure 102 can include a substrate 110, which can include silicon (e.g., single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The first semiconductor structure 102 can include peripheral circuitry 112 on and / or in the substrate 110. In some implementations, the peripheral circuitry 112 includes a plurality of transistors 114 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of the transistors 114) can also be formed on or in the substrate 110. In some examples, the peripheral circuitry 112 is formed using complementary metal-oxide-semiconductor (CMOS) technology, and the first semiconductor structure 102 can also be formed on a semiconductor die that can be referred to as a control die or CMOS die 102.

[0045] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 116 above the peripheral circuitry 112 for transmitting electrical signals to and from the peripheral circuitry 112. The interconnect layer 116 may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and via contacts. The interconnect layer 116 may also include one or more interlayer dielectric (ILD) layers, in which interconnects and via contacts may be formed. That is, the interconnect layer 116 may include interconnects and via contacts in multiple ILD layers. In some embodiments, the peripheral circuitry 112 is coupled to each other via interconnects in the interconnect layer 116. The interconnects in the interconnect layer 116 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may be formed of dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0046] like Figure 1 As shown, the first semiconductor structure 102 has a front side and a back side, and the first semiconductor structure 102 may further include a bonding layer 118 on the back side at the bonding interface 106 and above the interconnect layer 116 and the peripheral circuitry 112. The bonding layer 118 may include a plurality of bonding contacts 119 and a dielectric for electrically isolating the bonding contacts 119. The bonding contacts 119 may include a conductive material, such as Cu. The remaining region of the bonding layer 118 may be formed using a dielectric material such as silicon oxide. The bonding contacts 119 in the bonding layer 118 and the surrounding dielectric may be used for hybrid bonding. Similarly, as Figure 1 As shown, the second semiconductor structure 104 may also include a bonding layer 120 at the bonding interface 106 and above the bonding layer 118 of the first semiconductor structure 102. The bonding layer 120 may include a plurality of bonding contacts 121 and a dielectric material for electrically isolating the bonding contacts 121. The bonding contacts 121 may include a conductive material, such as Cu. The remaining region of the bonding layer 120 may be formed using a dielectric material, such as silicon oxide. The bonding contacts 121 in the bonding layer 120 and the surrounding dielectric material may be used for hybrid bonding. The bonding contacts 121 may contact the bonding contacts 119 at the bonding interface 106. In some embodiments, the bonding layer 120 includes a dielectric layer opposite a memory cell (e.g., a DRAM cell) 114, wherein bit lines 123 are located between the dielectric layer and the memory cell 124, such as... Figure 1 As shown in the diagram, the dielectric layer may include a bonding interface 106 having bonding contacts 121.

[0047] The second semiconductor structure 104 can be bonded on top of the first semiconductor structure 102 in a face-to-face manner at a bonding interface 106. In some embodiments, the bonding interface 106 is disposed between the bonding layers 120 and 118 as a result of a hybrid bonding (also referred to as a “metal / dielectric hybrid bonding”), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as a solder or an adhesive), and can achieve both metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, the bonding interface 106 is where the bonding layers 120 and 118 meet and bond. In some examples, the bonding interface 106 can be a layer with a certain thickness that includes a top surface of the bonding layer 118 of the first semiconductor structure 102 and a bottom surface of the bonding layer 120 of the second semiconductor structure 104.

[0048] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 122 that includes bit lines 123 above the bonding layer 120 to transport electrical signals. The interconnect layer 122 can include a plurality of interconnects, such as middle-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. In some embodiments, the interconnects in the interconnect layer 122 further include local interconnects, such as the bit lines 123 and word line contacts (not shown). The interconnect layer 122 can further include one or more ILD layers in which interconnect lines and via contacts can be formed. The interconnects in the interconnect layer 122 can include a conductive material including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can be formed of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0049] In some embodiments, the peripheral circuitry 112 includes a word line driver / row decoder that is coupled to word line contacts in the interconnect layer 122 through the bonding contacts 121 and 119 in the bonding layers 120 and 118 and the interconnect layer 116. In some embodiments, the peripheral circuitry 112 includes a bit line driver / column decoder that is coupled to the bit lines 123 and bit line contacts in the interconnect layer 122 through the bonding contacts 121 and 119 in the bonding layers 120 and 118 and the interconnect layer 116. In some embodiments, the bit lines 123 are metal bit lines, rather than semiconductor bit lines (e.g., doped silicon bit lines). For example, the bit lines 123 can include W, Co, Cu, Al, or any other suitable metal that has a higher conductivity than doped silicon. In some embodiments, the bit line contacts are ohmic contacts rather than Schottky contacts.

[0050] In some implementations, the bit lines 123 are made of a composite conductive material that can be based on a metal material (e.g., W, Co, Cu, Al) and a semiconductor material (e.g., Si). For example, the composite conductive material can include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide that has a higher conductivity than doped silicon.

[0051] In some implementations, the second semiconductor structure 104 includes a DRAM device in which memory cells are provided in the form of an array of DRAM cells 124 over the interconnect layer 122 and the bonding layer 120. That is, the interconnect layer 122 including the bit lines 123 can be disposed between the bonding layer 120 and the array of DRAM cells 124. The bit lines 123 in the interconnect layer 122 can be coupled to a string of DRAM cells 124. In some implementations, the second semiconductor structure 104 is formed on a semiconductor die and can be referred to as an array die 104.

[0052] In some implementations, a semiconductor device can include a plurality of array dies (e.g., the array die 104) and a CMOS die (e.g., the CMOS die 102). The plurality of array dies and the CMOS die can be stacked and bonded together. The CMOS die can be coupled to each of the plurality of array dies, respectively, and can drive each of the plurality of array dies, respectively, to operate in a similar manner as the semiconductor device. The semiconductor device can be any suitable device. In some examples, the semiconductor device includes at least a first wafer and a second wafer that are face-to-face bonded. The array dies can be disposed on the first wafer together with other array dies, and the CMOS die can be disposed on the second wafer together with other CMOS dies. The first wafer and the second wafer can be bonded together, and thus, the array dies on the first wafer can be bonded with corresponding CMOS dies on the second wafer. In some examples, the semiconductor device is a chip in which at least the array dies and the CMOS die are bonded together. In an example, the chip is cut from the wafers that are bonded together. In another example, the semiconductor device is a semiconductor package that includes one or more semiconductor chips assembled on a package substrate.

[0053] Each DRAM cell 124 may include a vertical transistor 126 and a capacitor 128 coupled to the vertical transistor 126. The DRAM cell 124 may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that the DRAM cell 124 may be any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 126 may be a MOSFET for switching the individual DRAM cells 124. In some embodiments, the vertical transistor 126 includes a vertically (in the Z direction) extending transistor body 130 (where an active region may form a channel) and a gate structure 136 contacting one side of the transistor body 130. In a single-gate vertical transistor, the transistor body 130 may have a cuboid or cylindrical shape, and the gate structure 136 may be adjacent to one side of the transistor body 130 in a plan view, for example, as shown in the figure. Figure 1 As shown. In some embodiments, the vertical transistor 126 has a structure including two or more gates, such as a dual-gate structure, a tri-gate structure, or a gate all-around (GAA) structure. In some embodiments, the gate structure 136 includes a gate electrode 134 and a gate dielectric 132 laterally located between the gate electrode 134 and the transistor body 130 in the bit line direction (e.g., in the Y direction). In some embodiments, the gate dielectric 132 is adjacent to one side of the transistor body 130, and the gate electrode 134 is adjacent to the gate dielectric 132.

[0054] like Figure 1 As shown, in some embodiments, the transistor body 130 has two ends in the vertical direction (Z direction). Figure 1and at least one end portion (e.g., the lower end portion) extends beyond the gate dielectric 132 into the ILD layer in the vertical direction (Z direction). In some embodiments, one end portion (e.g., the upper end portion) of the transistor body 130 is flush with a corresponding end portion (e.g., the upper end portion) of the gate dielectric 132. In some embodiments, both end portions (the upper end portion and the lower end portion) of the transistor body 130 extend beyond the gate electrode 134 into the ILD layer in the vertical direction (Z direction), respectively. That is, the transistor body 130 can have a vertical dimension (e.g., in the Z direction) that is greater than a vertical dimension (e.g., a depth) of the gate electrode 134, and neither the upper end portion nor the lower end portion of the transistor body 130 is flush with a corresponding end portion of the gate electrode 134. As a result, shorting between the bit line 123 and the word line / gate electrode 134 or between the word line / gate electrode 134 and the capacitor 128 can be avoided. The vertical transistor 126 can also include a source and a drain (both referred to as 138 because their positions can be interchangeable) disposed at the two end portions (the upper end portion and the lower end portion) of the transistor body 130 in the vertical direction (Z direction), respectively. The source can also be referred to as a first terminal 138a in the present disclosure. The drain can also be referred to as a second terminal 138b in the present disclosure. In some embodiments, one of the source and the drain 138 (e.g., at the upper end portion in Figure 1 is coupled to the capacitor 128, and the other one of the source and the drain 138 (e.g., at the lower end portion in Figure 1 is coupled to the bit line 123. That is, the vertical transistor 126 can have a first terminal in the positive Z direction and a second terminal opposite the first terminal in the negative Z direction, as shown in Figure 1

[0055] ​In some embodiments, the transistor body 130 includes a semiconductor material, such as single crystalline silicon, poly crystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the transistor body 130 can include single crystalline silicon. The source and drain 138 can be doped with N+ type dopants (e.g., phosphorus (P) or arsenic (As)) or P type dopants (e.g., boron (B) or gallium (Ga)) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source / drain 138 of the vertical transistor 126 and the bit line 123 as a bit line contact, or between the source / drain 138 of the vertical transistor 126 and the first electrode of the capacitor 128 as a capacitor contact 142 to reduce contact resistance. In some embodiments, the gate dielectric 132 includes a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to AI2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 134 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, poly silicon, silicide, or any combination thereof. In some embodiments, the gate electrode 134 includes multiple conductive layers, such as a W layer over a TiN layer. In one example, the gate structure 136 can be a "gate oxide / gate poly" gate, where the gate dielectric 132 includes silicon oxide and the gate electrode 134 includes doped poly silicon. In another example, the gate structure 136 can be HKMG, where the gate dielectric 132 includes a high-k dielectric and the gate electrode 134 includes a metal.

[0056] As described above, since the gate electrode 134 can be part of a word line or extend in a word line direction (e.g., the X direction) as a word line, the second semiconductor structure 104 of the 3D semiconductor device 100 can also include a plurality of word lines each extending in the word line direction. Each word line 134 can be coupled to a row of DRAM cells 124. That is, the bit lines 123 and the word lines 134 can extend in two perpendicular lateral directions, and the transistor body 130 of the vertical transistor 126 can extend in a vertical direction perpendicular to the two lateral directions in which the bit lines 123 and the word lines 134 extend. The word lines 134 are in contact with word line contacts (not shown). In some embodiments, the word lines 134 include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, poly silicon, silicide, or any combination thereof. In some embodiments, the word lines 134 include multiple conductive layers, such as a W layer over a TiN layer, as shown. Figure 1

[0057] In some embodiments, as Figure 1 ​As shown, the vertical transistor 126 extends vertically through and contacts the word line 134, and the source or drain 138 of the vertical transistor 126 contacts the bit line 123 (or contacts the bit line contact, if any) at its lower end. Therefore, due to the vertical arrangement of the vertical transistor 126, the word line 134 and the bit line 123 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 134 and the bit line 123. In some embodiments, the bit line 123 is vertically disposed between the bonding layer 120 and the word line 134, and the word line 134 is vertically disposed between the bit line 123 and the capacitor 128. The word line 134 can be coupled to the peripheral circuitry 112 in the first semiconductor structure 102 via word line contacts (not shown) in the interconnect layer 122, bonding contacts 121 and 119 in the bonding layers 120 and 118, and interconnects in the interconnect layer 116. Similarly, bit lines 123 in interconnect layer 122 can be coupled to peripheral circuits 112 in the first semiconductor structure 102 via bonding contacts 121 and 119 in bonding layers 120 and 118 and interconnects in interconnect layer 116.

[0058] In some implementations, the vertical transistors 126 can be arranged in a mirror-symmetric manner to increase the density of DRAM cells 124 in the bit-line direction (Y direction). For example... Figure 1 As shown, two adjacent vertical transistors 126 in the bit line direction are mirror-symmetrical with respect to the trench isolation 160. That is, the second semiconductor structure 104 may include a plurality of trench isolations 160, each trench isolation 160 extending parallel to the word line 134 in the word line direction (X direction) and disposed between the vertical gates 134 of two adjacent rows of vertical transistors 126. In some embodiments, rows of vertical transistors 126 separated by trench isolations 160 are mirror-symmetrical with respect to the trench isolations 160. The trench isolations 160 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. It should be understood that the trench isolations 160 may include air gaps, each laterally disposed between adjacent vertical gates 134. Air gaps can be formed due to the relatively small spacing of the vertical transistors 126 in the bit line direction (e.g., the Y direction). On the other hand, the relatively small dielectric constant of air in the air gap (e.g., about 1 / 4 of the dielectric constant of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the isolation effect between the vertical transistors 126 (and the rows of DRAM cells 124). Similarly, in some embodiments, air gaps are also formed laterally in the bit line direction between the word lines / gate electrodes 134, depending on the spacing of the word line / gate electrodes 134 in the bit line direction.

[0059] In some embodiments, instead of trench isolation 160 having an air gap between adjacent vertical gate electrodes 134 of adjacent rows of vertical transistors 126, a shielding conductive structure 170 (e.g., comprising a metal such as W) is disposed between adjacent transistor bodies 130 of adjacent rows of vertical transistors 126. The shielding conductive structure 170 may contact at least one of the adjacent transistor bodies 130 and may be coupled to a low voltage (e.g., a fixed negative voltage), which can reduce charge buildup in the memory cells 124, thereby mitigating the floating body effect in the memory cells 124. Furthermore, by applying a fixed low voltage to the shielding conductive structure 170 between the memory cells 124, the threshold voltage of the memory cells 124 can be easily adjusted, which can reduce overall manufacturing complexity and cost and improve the reliability of the memory cells 124. Additionally, the conductive structure 170 may be coupled out from the same side as the word line or from a side different from the word line. For example, the shielding conductive structure 170 may be coupled out from the back side of the second semiconductor structure 104. The shielding conductive structure 170 may also be referred to as a shielding conductive material. In this disclosure, trench isolation having such a shielded conductive structure 170 may also be referred to as trench isolation (TISO).

[0060] like Figure 1 As shown, in some embodiments, capacitor 128 includes a first electrode 144 above the source or drain 138 of vertical transistor 126 (e.g., the upper end of transistor body 130) and coupled to the source or drain 138 of vertical transistor 126 via capacitor contact 142. In some embodiments, capacitor contact 142 is an ohmic contact, such as a metal silicide contact, rather than a Schottky contact. For example, capacitor contact 142 may include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. Capacitor 128 may also include a capacitor dielectric above and in contact with the first electrode 144, and a second electrode above and in contact with the capacitor dielectric. That is, capacitor 128 may be a vertical capacitor, wherein the electrodes and capacitor dielectric are stacked vertically (in the Z direction), and the capacitor dielectric may be sandwiched between the electrodes. In some implementations, each first electrode is coupled to the source or drain 138 of a corresponding vertical transistor 126 in the same DRAM cell, while all second electrodes are coupled to a common plate 146 coupled to ground (e.g., common ground). The capacitor 128 may have a first end in the negative Z direction and a second end opposite the first end in the positive Z direction, as shown below. Figure 1 As shown. In some embodiments, the first terminal of capacitor 128 is coupled to the first terminal of vertical transistor 126 via an ohmic contact (e.g., capacitor contact 142 made of a metal silicide material). Figure 1As shown, the second semiconductor structure 104 may further include capacitor contacts 147 (e.g., conductors) in contact with the common plate 146 for directly coupling the capacitor 128 to the peripheral circuit 112 or ground. In some embodiments, the capacitor contacts 147 (e.g., conductors) extend in the Z direction from the dielectric layer of the bonding layer 120 to couple to a second end of the capacitor 128 via the common plate 146, such as... Figure 1 As shown. In some embodiments, the ILD layer forming capacitor 128 has the same dielectric material, such as silicon oxide, as the two ILD layers into which transistor body 130 extends.

[0061] It should be understood that the structure and configuration of capacitor 128 are not limited to Figure 1 Examples may include any suitable structure and configuration, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate capacitors. In some embodiments, the capacitor dielectric includes a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, capacitor 128 may be a ferroelectric capacitor for use in an FRAM cell, and the capacitor dielectric may be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, the electrodes include conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0062] like Figure 2A-2E As shown, the vertical transistor 126 extends vertically through and contacts the word line 134. The source or drain 138 of the vertical transistor 126 contacts the bit line 123 at its lower end, and the source or drain 138 of the vertical transistor 126 is coupled to the capacitor 128 at its upper end. That is, due to the vertical arrangement of the vertical transistor 126, the bit line 123 and the capacitor 128 can be arranged in different planes in the vertical direction and coupled to the opposite ends of the vertical transistor 126 of the DRAM cell 124 in the vertical direction. In some embodiments, the bit line 123 and the capacitor 128 are arranged on opposite sides of the vertical transistor 126 in the vertical direction. Compared to a DRAM cell where the bit line and capacitor are arranged on the same side of a planar transistor, this simplifies the wiring of the bit line 123 and reduces the coupling capacitance between the bit line 123 and the capacitor 128.

[0063] like Figure 2AAs shown, in some embodiments, the vertical transistor 126 is vertically disposed between the capacitor 128 and the bonding interface 106. That is, the vertical transistor 126 can be arranged closer to the peripheral circuitry 112 and the bonding interface 106 of the first semiconductor structure 102 than the capacitor 128. Since the bit line 123 and the capacitor 128 are coupled to opposite ends of the vertical transistor 126, the bit line 123 (as part of the interconnect layer 122) is vertically disposed between the vertical transistor 126 and the bonding interface 106. Therefore, the interconnect layer 122 including the bit line 123 can be arranged close to the bonding interface 106 to reduce interconnect wiring distance and complexity.

[0064] In some embodiments, the second semiconductor structure 104 further includes a substrate 148 disposed above the DRAM cell 124. The substrate 148 may be part of a carrier wafer. It should be understood that in some examples, the substrate 148 may not be included in the second semiconductor structure 104.

[0065] like Figures 2B-2C As shown, the second semiconductor structure 104 may further include a pad-out interconnect layer 150 above the substrate 148 and the DRAM cell 124. The pad-out interconnect layer 150 may include interconnects in one or more ILD layers, such as contact pads 154. The pad-out interconnect layer 150 and the interconnect layer 122 may be formed on opposite sides of the DRAM cell 124. A capacitor 128 may be vertically disposed between the vertical transistor 126 and the pad-out interconnect layer 150. In some embodiments, the interconnects in the pad-out interconnect layer 150 may transmit electrical signals between the 3D semiconductor device 100 and external circuitry, for example, for pad-out purposes.

[0066] In some embodiments, the second semiconductor structure 104 further includes one or more contacts 152 extending through a portion of the substrate 148 and the pad-out interconnect layer 150 to couple the pad-out interconnect layer 150 to the DRAM cell 124 and the interconnect layer 122. As a result, peripheral circuitry 112 can be coupled to the DRAM cell 124 via interconnect layers 116 and 122 and bonding layers 120 and 118, and peripheral circuitry 112 and the DRAM cell 124 can be coupled to external circuitry via the contacts 152 and the pad-out interconnect layer 150. The contact pads 154 and contacts 152 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, the contact pad 154 may include Al, and the contact 152 may include W. In some embodiments, the contact 152 includes a via surrounded by a dielectric spacer (e.g., having silicon oxide) to electrically isolate the via from the substrate 148. Depending on the thickness of the substrate 148, the contact 152 can be an ILV with a depth of submicron level (e.g., between 20 nm and 1 μm) or a TSV with a depth of micron level or tens of micron level (e.g., between 1 μm and 100 μm).

[0067] Although not shown, it should be understood that the pad leads of the 3D memory device are not limited to those from, for example... Figures 2D-2E The second semiconductor structure 104 shown has DRAM cells 124 and may be derived from a first semiconductor structure 102 having peripheral circuitry 112. Although not shown, it should be understood that the air gaps between word lines 134 and / or between transistor bodies 130 may be partially or completely filled with dielectric. Although not shown, it should be understood that arrays of more than one DRAM cell 124 may be stacked vertically to proportionally increase the number of DRAM cells 124.

[0068] In some implementations, instead of such Figure 2A As shown, substrate 148 is positioned above DRAM cell 124, and second semiconductor structure 104 includes a substrate disposed below DRAM cell 124. The substrate may be part of a carrier wafer. DRAM cell 124 may be formed in the front side of the substrate, and bit line 123 may be formed in the back side of the substrate. Bit line 123 may be electrically coupled to DRAM cell 124 (e.g., terminal 138 of vertical transistor 126) through the substrate.

[0069] Figure 2B A schematic diagram of the semiconductor device 100 is shown. Figure 1 A plan view of the semiconductor device 100 is shown. Figure 2A A schematic diagram of an example capacitor array 200 of a semiconductor device 100 is shown. Figures 4A-4EA schematic diagram of an example memory array 250 of the semiconductor device 100 is shown.

[0070] Referring Figure 2B , the semiconductor device 100 can include at least one first region 202 and a plurality of second regions 204. The first region 202 can include one or more capacitor cells 210 (e.g., as shown in Figure 2B ). The second regions 204 can include one or more memory blocks. Each memory block includes a plurality of memory cells (e.g., DRAM cells 124) and bit lines 123, as shown in Figure 1 . In some implementations, the first region 202 can be sandwiched by or centered in the second regions 204, as shown in Figure 1 . Additional implementations of the semiconductor device 100 having different arrangements of the first region 202 and the second regions 204 are also described below in the description of Figure 1 .

[0071] Figure 1 A schematic cross-sectional view of the capacitor array 200 in the first region 202 is shown. The capacitor array 200 includes one or more capacitor cells 210 and one or more ring-shaped conductive structures 220. Each capacitor cell 210 in the first region 202 includes a capacitor 206 and a semiconductor body 208. Each capacitor 206 corresponds to a respective semiconductor body 208. The capacitor 206 includes a first end 216 and a second end 218 opposite the first end 216 in a direction perpendicular to a surface of the substrate. In the example shown, the substrate (e.g., the substrate 110 or the substrate 148 as shown in Figure 1 ) extends along the Y direction, and the first end 216 and the second end 218 are positioned along the Z direction. The semiconductor body 208 includes a first end 212 and a second end 214 opposite the first end 212 along the Z direction. The first end 212 of the semiconductor body 208 is coupled to the first end 216 of the respective capacitor 206. In some implementations, the second end 218 of the capacitor 206 is connected to a ground plane 222. The ground plane 222 can be implemented as the common plate 146 in Figure 2C .

[0072] As described above, in some implementations, a portion of the capacitors in the memory array can be used to provide capacitors to CMOS circuits. Thus, the capacitor cells 210 can have substantially similar structures as the 1T1C DRAM cells 124 in Figure 2B . That is, the capacitors 206 in the first region 202 can have the same or substantially similar structures as the capacitors 128 in the second regions 204 as shown in Figure 1 . The semiconductor bodies 208 of the capacitor cells 210 in the first region 202 can have the same or substantially similar structures as the semiconductor bodies 128 of the capacitor cells 124 in Figure 2C .Figure 2C The transistor body 130 in the second region 204 shown has the same or substantially similar structure as the transistor body 130, except that the semiconductor body 208 may have a different doping level than the transistor body 130.

[0073] In some embodiments, the semiconductor body 208 has a doping level similar to that of the first terminal 130a and the second terminal 138b of the transistor 126. Therefore, the semiconductor body 208 can be used as a resistor in the capacitor array 200 in the first region 202, rather than as a transistor. In some embodiments, the resistance of one of the semiconductor bodies 208 can be in the range of 100 kΩ to 500 kΩ.

[0074] In some embodiments, the semiconductor body 208 comprises doped polycrystalline silicon with a dopant concentration greater than 1E15 dopant atoms per cubic centimeter. In some embodiments, the dopant comprises at least one of phosphorus (P), arsenic (As), boron (B), or gallium (Ga). In some embodiments, the dopant in the semiconductor body 208 may have the same conductivity type as the dopant in the transistor body 130. For example, both the transistor body 130 and the semiconductor body 208 may be N-type doped or P-type doped. In some embodiments, the dopant in the semiconductor body 208 may have a different conductivity type than the dopant in the transistor body 130.

[0075] like Figure 2B As shown, the annular conductive structure 220 can be formed to connect to the second end 214 of the semiconductor body 208. The annular conductive structure 220 includes a pair of line segments 224 and a pair of end segments 226 adjacent to the ends of the pair of line segments 224. Figure 1 In some embodiments, a pair of end segments 226 and a pair of line segments 224 can seamlessly form a single, monolithic ring structure. In some embodiments, each line segment in the pair of line segments 224 has a uniform, substantially similar, or identical length along the direction of the bit line (e.g., the Y direction). In some embodiments, the pair of line segments 224 are coupled to a second end 214 of the semiconductor body 208. Figure 1 The ring-shaped conductive structure 220 can be made of conductive materials including, but not limited to, W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, or any combination thereof. In some embodiments, the ring-shaped conductive structure 220 is made of a composite conductive material that may be based on a metallic material (e.g., W, Co, Cu, Al) and a semiconductor material (e.g., Si). For example, the composite conductive material may include metal silicides such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. In some embodiments, the ring-shaped conductive structure 220 may have a [missing information - likely a specific characteristic or feature]. Figure 1The bit line 123 in the semiconductor structure 100 is made of the same material as the bit line 123 in the semiconductor structure 200.

[0076] As shown in FIG. 2A, each line segment 224 of the ring-shaped conductive structure 220 extends in a first direction (e.g., the Y direction). Adjacent ring-shaped conductive structures 220 are arranged in a second direction (e.g., the X direction or the direction of the word line) that is perpendicular to the first direction. Adjacent ring-shaped conductive structures 220 can be separated by a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Figure 1 As shown in FIG. 2A, each line segment 224 of the ring-shaped conductive structure 220 extends in a first direction (e.g., the Y direction). Adjacent ring-shaped conductive structures 220 are arranged in a second direction (e.g., the X direction or the direction of the word line) that is perpendicular to the first direction. Adjacent ring-shaped conductive structures 220 can be separated by a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0077] Figure 2D As shown in FIG. 2A, each line segment 224 of the ring-shaped conductive structure 220 extends in a first direction (e.g., the Y direction). Adjacent ring-shaped conductive structures 220 are arranged in a second direction (e.g., the X direction or the direction of the word line) that is perpendicular to the first direction. Adjacent ring-shaped conductive structures 220 can be separated by a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0078] The second end 234 of the pair of conductive vias 230 is coupled to a conductor 238. The conductor 238 can be coupled to a control circuit, such as the peripheral circuit 112 in the first semiconductor structure 102. In some embodiments, the pair of conductive vias 230 and / or the conductor 238 are made of a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the pair of conductive vias 230 and / or the conductor 238 include multiple conductive layers, such as a W layer over a TiN layer.

[0079] In some embodiments, the capacitor 206, the semiconductor body 208, the ring-shaped conductive structure 220, and the pair of conductive vias 230 are in a semiconductor structure (e.g., the second semiconductor structure 104) as shown in FIG. 2B. In some embodiments, as shown in FIG. 2B, the semiconductor body 208 is a semiconductor body 208a in the second semiconductor structure 104. Figure 2E Figure 1 ​​As shown, the semiconductor device 100 also includes a control structure (e.g., the first semiconductor structure 102) bonded with a semiconductor structure (e.g., the second semiconductor structure 104). The control structure 102 includes control circuitry, such as the peripheral circuitry 112. In some embodiments, the capacitor 206 is coupled to the control circuitry by the ring-shaped conductive structure 220, the pair of conductive vias 230, and the conductor 238. Thus, the capacitor 206 in the second semiconductor structure 104 can be provided for the peripheral circuitry 112 in the first semiconductor structure 102. In some embodiments, the conductor 238 is located in the first semiconductor structure 102. In some embodiments, the conductor 238 is located in the second semiconductor structure 104. Although not shown, it should be appreciated that the control circuitry can also be located in the second semiconductor structure 104.

[0080] In some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded with direct bonding. In some embodiments, the direct bonding involves oxide bonding. The surfaces of the two semiconductor structures can be prepared by thoroughly cleaning the surfaces to remove any contaminants and oxides. An oxide layer can be grown or deposited on the surfaces of the first sides of the two semiconductor structures. In some examples, the oxide layer includes silicon dioxide (SiO2). The two semiconductor structures can then be aligned to have proper matching. The integrated semiconductor structure can be subjected to high-temperature annealing. During the annealing, the oxide layer can become porous, and the atoms at the interface can diffuse and rearrange, forming strong covalent bonds between the two semiconductor structures. After the annealing, the bonded semiconductor structures can be gradually cooled down. This allows strong bonds to be formed between the semiconductor materials. It should be appreciated that the direct bonding can involve any other suitable techniques, such as molecular or atomic bonding.

[0081] In some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded with hybrid bonding. The hybrid bonding can include a combination of metal-metal bonding and direct oxide bonding. In some embodiments, the second semiconductor structure 104 includes one or more first conductive contacts, such as the bonding contacts 121 Figure 1 ) isolated by a first dielectric material, such as the bonding layer 120. The control structure 102 includes one or more second conductive contacts, such as the bonding contacts 119 Figure 2D ) isolated by a second dielectric material, such as the bonding layer 118. The first conductive contacts can be in contact with the one or more second conductive contacts to form the hybrid bonding.

[0082] Figure 2E A schematic cross-sectional view of an example memory array 250 in the second region 204 is shown. Figure 1A schematic plan view of bit lines and individual conductive vias of the memory array 250 in the second region 204 is shown. The memory cells 124 in the memory array 250 can have the same or substantially similar configuration as the configuration shown in Figure 1 FIG. 1. For ease of description, when describing the structure of the memory array 250, reference will be made to Figure 2D , Figure 2E and Figure 2E .

[0083] The memory array 250 includes memory cells, e.g., DRAM cells 124. Each memory cell 124 includes a transistor 126 and a capacitor 128. The transistor 126 includes a transistor body 130, a gate structure 136, a first terminal 138a and a second terminal 138b on opposite ends of the transistor body 130 Figures 3A-3B . The first terminal 138a of the transistor 126 is coupled to the capacitor 128.

[0084] The memory array 250 also includes bit lines 123. Each bit line 123 is coupled to a corresponding second terminal 138b of a transistor 126, as shown in Figure 3A and Figure 3B . In some embodiments, the memory array 250 includes individual conductive vias 252. As shown in Figure 3A , a first conductive via 252a of the individual conductive vias 252 can be coupled to a first end 254 of a first bit line 123a of the bit lines 123. A second conductive via 252b of the individual conductive vias 252 can be coupled to a second end 256 of a second bit line 123b adjacent to the first bit line 252a. The first end 254 of the first bit line 123a is opposite the second end 256 of the second bit line 123b. That is, the individual conductive vias 252 are located on opposite ends of adjacent bit lines 123.

[0085] In some embodiments, the first end 254 of the first bit line 123a extends beyond the first end 254 of the second bit line 123b in a bit line direction (e.g., the Y direction). For example, as shown in Figures 2B-2C , the bit lines 123 can have an alternating pattern in which odd numbered lines (e.g., the first bit line 123a) are shifted up while even numbered lines (e.g., the second bit line 123b) are shifted down. This alternating configuration, together with the opposite individual conductive vias 252, can expand the process window for forming the individual conductive vias on the bit lines and improve yield by reducing the risk of shorting between adjacent bit lines 123. It is noted that each bit line 123 of the memory array 250 in the second region 204 can be coupled to one conductive via on one end, while each line segment 224 of the ring-shaped conductive structure 220 in the first region 202 can be coupled to two conductive vias at both ends. This ring-shaped configuration can help to reduce resistance, as described below inFigure 3B Further described in detail below.

[0086] Figure 3A A schematic diagram of an equivalent circuit of the capacitor array 200 is shown. Figure 3B A schematic diagram of an equivalent circuit of the memory array 250 is shown.

[0087] As noted above, the capacitor array 200 can include one or more capacitor cells 210. Each capacitor cell 210 includes a capacitor 206 and a resistor, such as a semiconductor body 208. Additionally, the ring-shaped conductive structure 220 can include a pair of line segments 224. Each line segment 224 can be coupled to one or more capacitor cells 210. In Figures 4A-4E In the present example shown, each line segment 224 is coupled to nine capacitor cells 210. In the equivalent circuit 300, each line segment 224 can be equivalent to eight resistor portions 308, with each resistor portion 308 between adjacent capacitor cells 210.

[0088] As noted above in Figures 2B-2C each line segment 224 abuts an end segment 226, and the end segment 226 is coupled to a pair of conductive vias 230. The pair of conductive vias 230 are further coupled to a conductor 238. Thus, the two ends of the line segment 224 (e.g., the first node 302 and the second node 304) are electrically connected and share the same electrical potential. Thus, the resistance of the present example of the capacitor array 200 can be equivalent to the combined resistance of two portions (e.g., the first portion 312 and the second portion 314 of the equivalent circuit 300) arranged in parallel. The first portion 312 of the equivalent circuit 300 can include the capacitor cells 210 and the resistor portions 308 between the first node 302 and the intermediate node 306, and the second portion 314 of the equivalent circuit 300 includes the capacitor cells 210 and the resistor portions 308 between the intermediate node 306 and the second node 304.

[0089] Conversely, for the equivalent circuit 350 of the memory array 250 as shown in Figure 1 only one end of the line segment 224 (e.g., the second node 304) is connected to an individual conductive via 252. Thus, the first node 302 and the second node 304 can have different electrical potentials. The resistance of the present example of the memory array 250 can thus be equivalent to the combined resistance of two portions (e.g., the first portion 312 and the second portion 314 of the equivalent circuit 350) arranged in series. Thus, the equivalent circuit 300 in Figure 2D may have a higher resistance than the equivalent circuit 350 in Figure 2EThe lower resistance in the equivalent circuit 350 in the CMOS control circuit (e.g., the peripheral circuit 112) can have several benefits, such as faster operation, reduced power consumption, improved signal integrity, and / or better thermal performance.

[0090] Figure 4A A plan view showing an additional embodiment of the semiconductor device 100 having a different arrangement of the first region 202 and the second region 204 is shown.

[0091] As described above, the semiconductor device 100 can include one or more first regions 202 and one or more second regions 204. Each first region 202 can include one or more capacitor cells 210 as described above in Figure 4B Figure 4D , Figure 4C and Figure 4E . The one or more first regions 202 and the one or more second regions 204 can be separated from each other by a gap structure 402. In some embodiments, the gap structure 402 can include a dielectric gap spacer (not shown) separating adjacent regions. The gap spacer can be made of a material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the gap structure 402 includes an inner conductive portion (not shown) surrounded by the dielectric gap spacer, e.g., including W, polysilicon, and / or TiN.

[0092] It should be appreciated that any of the first regions 202 can be divided into a plurality of capacitor blocks (not shown). The capacitor blocks can be separated from each other by a dielectric structure (e.g., a gap structure). Each capacitor block can include one or more capacitor cells 210. The plurality of capacitor blocks can vary in size, e.g., having different numbers of capacitor cells 210 in each capacitor block. Additionally or alternatively, the spacing between adjacent capacitor blocks within the same first region 202 can not be uniform.

[0093] As shown in Figures 5A-5F , Figure 5A and Figure 5B , in some embodiments, the second region 204 is at least partially surrounded by, centered in, or sandwiched in the first region 202. In some embodiments, the first region 202 is symmetric about the second region 204. In some embodiments, as shown in Figure 5C and Figure 5C ​As shown, the first region 202 is centered within the second region 204. The second region 204 may be symmetrical about the first region 202. In some cases, symmetry can promote uniformity of electrical characteristics, mitigate temperature variations in the semiconductor device 100, and provide better matching between resistors. Although not shown, it should be understood that the first region 202 and the second region 204 may have an asymmetrical arrangement or layout.

[0094] Figure 5D Top and cross-sectional views of a semiconductor device 100 are shown at various stages of an example process for forming the annular conductive structure 220 and the paired conductive vias 230. Each figure includes a plan view in the XY plane in schematic (a) and a cross-sectional view in the XZ plane in schematic (b). The X direction may be the direction of word lines. The Y direction may be the direction of bit lines. The Z direction may be a direction perpendicular to the substrate surface. For ease of description, both figures will be referenced when describing each figure.

[0095] like Figure 5E As shown, a hard mask layer 503 is deposited on a first side 501a of a substrate 502. The substrate 502 may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The hard mask layer 503 may be made of materials including silicon nitride, silicon oxide, or silicon carbide. In some embodiments, a memory array 250 and a capacitor array 200 are formed on a second side 501b of the substrate 502. In some embodiments, the hard mask layer 503 is formed on the first side 501a of the substrate 502 after the memory array 250 and capacitor array 200 are formed on the second side 501b of the substrate 502. This process may involve employing a carrier wafer (not shown) and a substrate thinning process. After the memory array 250 and capacitor array 200 are formed on the second side 501b of the substrate 502, the carrier wafer may be bonded to this side. After bonding, the combined structure is flipped to allow access to the first side 501a of the substrate 502 to form the hard mask layer 503.

[0096] like Figure 5E As shown, a patterned hard mask layer 503 is used to form a plurality of separate hard mask structures 504 arranged along the X direction. Each hard mask structure 504 may extend along the Y direction. Adjacent hard mask structures 504 are separated by trenches 506. The trenches 506 may be formed by a variety of processes, including but not limited to photolithography and / or etching. The etching process may involve one or more dry etching and / or wet etching techniques, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputtering etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), piranha solution (H2SO4 / H2O2), or any combination thereof.

[0097] As shown in Figure 5F , a spacer layer 508 is deposited into the trench 506. In some embodiments, the spacer layer 508 is formed on the sidewalls 510 of the hardmask structures 504. The spacer layer 508 can not completely fill the trench 506, leaving some space 506a remaining within the trench 506. The width 514 of the remaining space 506a at the bottom of the trench 506 can be less than the width 516 of the trench 506 between adjacent hardmask structures 504. In some embodiments, the spacer layer 508 is formed on four lateral sidewalls 510 of the hardmask structures 504, forming a ring shape, as shown in Figure 6 (a). Adjacent ring-shaped spacer layers 508 are arranged along the X direction and separated by the remaining space 506a of the trench 506. In some embodiments, one or more of a dry etch and / or a wet etch is performed after depositing the spacer layer 508 to remove a portion of the spacer layer 508, thereby exposing the top surface 512 of the hardmask structures 504.

[0098] The spacer layer 508 can be made of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. One or more thin film deposition techniques can be used to deposit the spacer layer 508, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or any combination thereof.

[0099] As shown in Figure 1 , the hardmask structures 504 are removed. The spacer layer 508 remains on the substrate 502, covering some portions of the substrate 502. Remaining portions 507 of the substrate 502 are exposed. The removal process can involve one or more dry etch and / or wet etch techniques, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputter etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), piranha solution (H2SO4 / H2O2), or any combination thereof. The etching process can be a selective etch such that the etchant only etches the hardmask structures 504 or has a higher etch rate for the hardmask structures 504 than for the spacer layer 508.

[0100] As shown in Figures 2D-2E , an etch is performed to etch the exposed portions 507 of the substrate 502 and form substrate trenches 518 in the substrate 502. The ring-shaped spacer layer 508 can be used as a mask in this process step for transferring the ring-shaped pattern into the substrate 502. Thus, the remaining portions of the substrate 502 can have a ring shape, which forms the ring-shaped conductive structures 220, as shown in Figure 3BThe schematic diagram (a) shows the substrate trench 518. After etching is completed, the spacer layer 508 can be subsequently removed. The substrate trench 518 can be formed by one or more dry etching and / or wet etching techniques, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputtering etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), piranha solution (H2SO4 / H2O2), or any combination thereof.

[0101] like Figures 2B-2C As shown, pairs of conductive vias 230 are formed on the end segments 226 of the annular conductive structure 220. The process of forming the pairs of conductive vias 230 may include forming a dielectric layer (not shown) on the annular conductive structure 220, followed by an etching process to form holes (not shown) on the dielectric layer. The holes may be filled with a conductive material to form the pairs of conductive vias 230.

[0102] Figure 3A A flowchart illustrating an example process for forming a semiconductor device 100 is shown. At step 602, a capacitor and a corresponding semiconductor body are formed. Each semiconductor body includes a first terminal coupled to a corresponding capacitor in the capacitor. The capacitor may be, for example... Figures 2B-2C , Figure 3A and Figure 2B Capacitor 128, or Figures 2B-2C and Figures 5E-5F The capacitor 206 in the example. The semiconductor body can be, for example... Figures 2B-2C and Figure 3A The semiconductor body 208 in the middle. The first end can be, for example... Figures 5E-5F The first end 212 of the semiconductor body 208 in the middle.

[0103] In step 604, a ring-shaped conductive structure is formed. Each ring-shaped conductive structure includes a pair of line segments and a pair of end segments adjacent to the ends of the pair of line segments. The pair of line segments are coupled to a second end of a corresponding semiconductor body in the semiconductor body. The ring-shaped conductive structure may be, for example... Figures 2B-2C and Figures 5E-5F The ring-shaped conductive structure 220 in the middle. A pair of line segments can be, for example... Figure 2B , Figures 2B-2C and Figure 5F Line segment 224 in the middle. A pair of end segments can be, for example... Figures 5B-5C and Figures 5C-5D A pair of end segments 226 in the semiconductor body. The second end of the semiconductor body can be, for example... Figure 5C The second end 214 of the semiconductor body 208 in the middle.

[0104] At step 606, pairs of conductive vias are formed. Each pair of conductive vias is coupled to a pair of end sections of a corresponding one of the ring-shaped conductive structures. The pairs of conductive vias can be, for example, the pairs of conductive vias 230 in Figure 5D and Figure 7 .

[0105] In some embodiments, forming the ring-shaped conductive structures includes (i) forming a dielectric structure on the semiconductor substrate; (ii) depositing a spacer layer on sidewalls of the dielectric structure; (iii) removing the dielectric structure; and (iv) etching exposed portions of the semiconductor substrate. The dielectric structure can be, for example, the hardmask structure 504 in Figure 7 . The spacer layer can be, for example, the spacer layer 508 in Figures 1-2A . The sidewalls of the dielectric structure can be, for example, the sidewalls 510 of the hardmask structure 504 in Figures 4A-4E . The exposed portions of the semiconductor substrate can be, for example, the exposed portions 507 of the semiconductor substrate 502 in Figures 2B-2C .

[0106] In some embodiments, the semiconductor bodies include doped polysilicon having a dopant concentration greater than 1E15 dopant atoms per cubic centimeter. In some embodiments, the dopant includes at least one of phosphorus (P), arsenic (As), boron (B), or gallium (Ga). In some embodiments, a resistance of one of the semiconductor bodies is in a range between 100 kilo-ohms and 500 kilo-ohms.

[0107] Figures 2D-2E A block diagram illustrating a system 700 having one or more semiconductor devices 100 (e.g., memory devices) in accordance with one or more embodiments of the present disclosure is shown. The system 700 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. As shown in Figures 5A-5F , the system 700 can include a host device 708 and a memory system 702 having one or more 3D memory devices 704 and a memory controller 706. The host device 708 can include a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), such as an application processor (AP). The host device 708 can be configured to send data to or receive data from the one or more 3D memory devices 704.

[0108] The 3D memory device 704 can be any 3D memory device disclosed herein, such as the 3D memory device 100 in Figure 7 and ​a 3D semiconductor device 100 in FIG. 1, or a portion of the 3D semiconductor device 100 (e.g., ​ a capacitor array 200 in FIG. 2, ​ a memory array 250 in FIG. 3), or ​ a structure in a middle of a manufacturing process of the 3D semiconductor device 100 in FIG. 4.

[0109] In some embodiments, the 3D memory device 704 includes NAND flash memory. A memory controller 706 (also referred to as a controller circuit) is coupled to the 3D memory device 704 and a host device 708. Consistent with embodiments of the present disclosure, the 3D memory device 704 can include a plurality of conductive interconnects through an overcoat layer, the plurality of conductive interconnects being in contact with a conductive pad in a conductive pad layer, and the memory controller 706 can be coupled to the 3D memory device 704 through at least one of the plurality of conductive interconnects. The memory controller 706 is configured to control the 3D memory device 704. For example, the memory controller 706 can be configured to operate the plurality of channel structures via word lines. The memory controller 706 can manage data stored in the 3D memory device 704 and communicate with the host device 708.

[0110] In some embodiments, the memory controller 706 is designed / configured for operation in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile telephones, etc. In some embodiments, the memory controller 706 is designed / configured for operation in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC) that is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 706 can be configured to control operations of the 3D memory device 704, such as read, erase, and program (or write) operations. The memory controller 706 can also be configured to manage various functions with respect to data stored or to be stored in the 3D memory device 704, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 706 is also configured to process error correction codes (ECCs) with respect to data read from or written to the 3D memory device 704. Any other suitable functions can also be performed by the memory controller 706, such as formatting the 3D memory device 704.

[0111] The memory controller 706 can communicate with external devices (e.g., the host device 708) according to a particular communication protocol. For example, the memory controller 706 can communicate with external devices through at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0112] The memory controller 706 and the one or more 3D memory devices 704 can be integrated into various types of memory devices, e.g., included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 702 can be implemented and packaged into different types of end electronic products. In one example as shown, the memory controller 706 and a single 3D memory device 704 can be integrated into a memory card 702. The memory card 702 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCMicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. ​

[0113] Embodiments of the subject matter and the actions and operations described in this disclosure can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or in combinations of one or more thereof. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, e.g., one or more modules of computer program instructions encoded on a computer program carrier for execution by, or to control the operation of, data processing apparatus. The carrier can be a tangible non-transitory computer storage medium. Alternatively or additionally, the carrier can be a propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more thereof, or a part thereof. The computer storage medium is not a propagated signal.

[0114] ​It should be noted that reference to“one embodiment”,“an embodiment”,“example embodiments”,“some embodiments”,“some implementations”,“one implementation”,“implementations”,“example implementations”, etc., in this disclosure indicates that a described embodiment can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that

[0115] Generally, terminology can be understood at least in part from usage in context. For example, the term“one or more” as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in the singular or can be used to describe combinations of features, structures or characteristics. Similarly, terms such as“a”,“an”, or“the” again, can be understood to express a singular usage or to

[0116] It should be readily understood that the terms“on”,“over”, and“above”, in the present disclosure, are to be interpreted in the broadest relative terms consistent with the context. That is,“on” not only means“directly on” something, but also includes the meaning of“on” something with intervening features or layers therebetween. Additionally,“over” or“above” not only means“over” or“above” something, but also can include the meaning of“over” or“above” something without intervening features or layers therebetween (i.e., directly on something).

[0117] Furthermore, to facilitate description, spatially relative terms— such as“beneath”,“below”,“lower”,“on”,“over”, and the like— can be used herein for describing an element’s or feature’s relationship to another element(s) or feature(s) as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0118] As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and thus, unless otherwise specified, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the top surface, and thus, the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Further, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0119] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer has a top side and a bottom side, where the bottom side of the layer is relatively close to a substrate and the top side is relatively far from the substrate. A layer can extend over an entire underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any set of lateral planes between and at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, where it can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect accesses (VIA) are formed) and one or more dielectric layers.

[0120] As used herein, the term "nominal / nominally" refers to a desired or target value of a characteristic or parameter of a component or process step, and a range of values above and / or below the desired value, set during the design phase of a product or process. As used herein, a range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" denotes a value of a given quantity that can vary based on a particular technology node associated with a subject semiconductor device. Based on a particular technology node, the term "about" can denote a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0121] In the present disclosure, the term "horizontal / horizontally / lateral / laterally" denotes nominally parallel to a lateral surface of a substrate, and the term "vertical" or "vertically" denotes nominally perpendicular to a lateral surface of a substrate.

[0122] As used herein, the term“3D memory” refers to a three-dimensional (3D) semiconductor device having strings of vertically oriented memory cell transistors 126 (referred to herein as“memory strings,” such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0123] The present disclosure provides many different embodiments or examples of implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are in no way intended to be limiting. For example, in the following description, a first feature over or on a second feature can include embodiments in which the first and second features are directly in contact and / or there can be an additional feature or features between the first and second features. Additionally, the present disclosure can repeat reference numerals and / or letters in the figures and / or the specification. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various implementations and / or configurations discussed.

[0124] The foregoing description of specific implementations and / or embodiments has been presented for the purposes of simplicity and clarity. It is not intended to be an exhaustive list of variations or modifications of or to specific implementations and / or embodiments. The description has been presented only as illustrative and not limiting; it will be apparent to those skilled in the art that other variations and / or modifications that are apparent to those of ordinary skill in the art can be made within the scope of the disclosed implementations and / or embodiments. Moreover, variations and / or modifications to such implementations and / or embodiments can be made which do not depart from the spirit and scope of the claimed subject matter.

[0125] While the present disclosure contains many specific implementations and / or embodiments, these should not be construed as limiting the scope of the claims, but as merely providing instructions of features which can be specific to particular implementations of the application. Certain features that are described in the context of separate implementations can also be implemented in combination. Conversely, various features that are described in the context of a single implementation can also be implemented or practiced separately or in any suitable subcombination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claim can be directed to a subcombination or variation of a subcombination.

[0126] Similarly, while operations are illustrated in the drawings and recited in the claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing can be advantageous. Moreover, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated in a single software product or packaged into multiple software products.

[0127] Particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, acts recited in the claims can occur in a different order and still achieve the desired results. As one example, the processes illustrated in the figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In some instances, multitasking and parallel processing can be advantageous.

[0128] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising: capacitors and semiconductor bodies corresponding to the capacitors, each of the semiconductor bodies comprising a first end coupled to an end of a respective one of the capacitors; and a ring-shaped conductive structure comprising a pair of line segments and a pair of end segments contiguous with ends of the pair of line segments, the pair of line segments coupled to second ends of the semiconductor bodies, the pair of end segments coupled to a control circuit.

2. The semiconductor device of claim 1, further comprising a pair of conductive vias, first ends of the pair of conductive vias coupled to the pair of end segments of the ring-shaped conductive structure, second ends of the pair of conductive vias coupled to a conductor, the conductor coupled to the control circuit.

3. The semiconductor device of claim 1 or 2, further comprising: memory cells, each memory cell comprising a transistor and a capacitor, the transistor comprising a transistor body, a gate structure, a first terminal and a second terminal on opposite ends of the transistor body, the first terminal of the transistor coupled to the capacitor; bit lines, each bit line coupled to a corresponding second terminal of the transistor; and individual conductive vias, a first one of the individual conductive vias coupled to a first end of a first one of the bit lines, a second one of the individual conductive vias coupled to a second end of a second one of the bit lines adjacent to the first one of the bit lines, and the first end opposite the second end.

4. The semiconductor device according to claim 2, wherein the capacitors, the semiconductor bodies, the ring-shaped conductive structure, and the pair of conductive vias in a semiconductor structure, wherein the semiconductor device further comprises a control structure bonded with the semiconductor structure, the control structure comprising the control circuit, and wherein the capacitors are coupled to the control circuit through the ring-shaped conductive structure, the pair of conductive vias, and the conductor.

5. The semiconductor device according to any one of Claims 1 to 4, wherein the semiconductor bodies comprise doped polysilicon having a dopant concentration greater than 1E15 dopant atoms per cubic centimeter.

6. The semiconductor device according to claim 5, wherein the dopant comprises at least one of phosphorous (P), arsenic (As), boron (B), or gallium (Ga).

7. The semiconductor device according to any one of Claims 1 to 6, wherein a resistance of one of the semiconductor bodies is in a range between 100 kilo-ohms and 500 kilo-ohms.

8. The semiconductor device according to any one of Claims 1 to 7, wherein the pair of line segments of the ring-shaped conductive structure have a uniform length.

9. The semiconductor device according to claim 3, wherein the semiconductor device comprises a first region comprising the capacitors, the semiconductor bodies, and the ring-shaped conductive structure, and second regions each comprising the memory cells and the bit lines, and wherein the first region is centered in the second regions.

10. A semiconductor device comprising: ring-shaped conductive structures, each ring-shaped conductive structure comprising a pair of line segments and a pair of end segments contiguous with ends of the pair of line segments; pairs of conductive vias, first ends of each pair of conductive vias coupled to the pair of end segments of a corresponding one of the ring-shaped conductive structures; and conductors, each conductor coupled to second ends of a corresponding one of the pairs of conductive vias.

11. The semiconductor device according to claim 10, wherein Each of the pair of line segments extends in a first direction, and the annular conductive structure is arranged in a second direction perpendicular to the first direction.

12. The semiconductor device of claim 10 or 11, further comprising: capacitors and semiconductor bodies corresponding to the capacitors, each of the semiconductor bodies comprising a first end coupled to an end of a respective one of the capacitors and a second end coupled to the pair of line segments of a corresponding one of the annular conductive structures.

13. The semiconductor device according to claim 12, wherein The semiconductor bodies comprise doped polysilicon having a dopant concentration greater than 1E15 dopant atoms per cubic centimeter.

14. The semiconductor device according to claim 13, wherein The dopant comprises at least one of phosphorus (P), arsenic (As), boron (B), or gallium (Ga).

15. The semiconductor device according to any one of Claims 12 to 14, wherein One of the semiconductor bodies has a resistance in a range between 100 kilo-ohms and 500 kilo-ohms.

16. A method comprising: forming capacitors and semiconductor bodies corresponding to the capacitors, each of the semiconductor bodies comprising a first end coupled to a respective one of the capacitors; forming annular conductive structures, each annular conductive structure comprising a pair of line segments and a pair of end segments contiguous with ends of the pair of line segments, the pair of line segments coupled to a second end of a corresponding one of the semiconductor bodies; and forming pairs of conductive vias, each pair of conductive vias coupled to the pair of end segments of a corresponding one of the annular conductive structures.

17. The method of claim 16, wherein, Forming the annular conductive structures comprises: forming a dielectric structure on a semiconductor substrate; depositing a spacer layer on sidewalls of the dielectric structure; removing the dielectric structure; and etching exposed portions of the semiconductor substrate.

18. The method of claim 16 or 17, wherein, The semiconductor bodies comprise doped polysilicon having a dopant concentration greater than 1E15 dopant atoms per cubic centimeter.

19. The method of claim 18, wherein, The dopant comprises at least one of phosphorus (P), arsenic (As), boron (B), or gallium (Ga).

20. The method of any one of claims 16-19, wherein, One of the semiconductor bodies has a resistance in a range between 100 kilo-ohms and 500 kilo-ohms.

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