Manufacturing method of doped microcrystalline silicon layer, heterojunction solar cell and preparation method of heterojunction solar cell

Abstract

The invention provides a manufacturing method of a doped microcrystalline silicon layer, a heterojunction solar cell and a preparation method of the heterojunction solar cell. The manufacturing method of the doped microcrystalline silicon layer comprises the following steps: firstly, providing PECVD (Plasma Enhanced Chemical Vapor Deposition) equipment, and placing a silicon wafer in a reaction cavity of the PECVD Then the pressure of the reaction cavity is adjusted to be first deposition pressure, a PECVD doping process is carried out in the reaction cavity so as to deposit a microcrystalline silicon seed layer on the silicon wafer, and the first deposition pressure ranges from 1 mbar to 2.9 mbar; finally, the pressure of the reaction cavity is adjusted to be second deposition pressure, the PECVD doping process is carried out in the reaction cavity so as to deposit a microcrystalline silicon main layer on the microcrystalline silicon seed layer, and the second deposition pressure ranges from 3 mbar to 10 mbar. According to the invention, the quality of the doped microcrystalline silicon layer can be improved, the stability of the heterojunction solar cell is improved, and the dark attenuation of the heterojunction solar cell is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of photovoltaic manufacturing, in particular to a preparation method of a doped microcrystalline silicon layer, a heterojunction solar cell and a preparation method thereof. BACKGROUND

[0002] Thin film / crystalline silicon heterojunction solar cells (hereinafter referred to as heterojunction solar cells, also known as HIT or HJT or SHJ solar cells) belong to the third generation of high-efficiency solar cell technology, which combines the advantages of crystalline silicon and silicon thin film, has high conversion efficiency, low temperature coefficient and other characteristics, and will gradually replace PERC (Passivated Emitter and Rear Cell) cells and become the mainstream of photovoltaic cells.

[0003] Compared with the traditional amorphous silicon thin film with completely disordered amorphous structure, the microcrystalline silicon thin film has the characteristics of both crystalline silicon and amorphous silicon, has better light transmittance, lower defect density, higher doping efficiency and higher conductivity. After the heterojunction cell adopts double-sided microcrystalline silicon doped layer instead of amorphous silicon, the photoelectric conversion efficiency of the heterojunction cell is greatly improved.

[0004] At present, microcrystalline silicon thin film is usually formed by plasma enhanced chemical vapor deposition (PECVD) process, which generates columnar grains under harsh conditions of high pressure, high power and high hydrogen. However, due to the discontinuity of columnar grains, microcrystalline silicon is prone to form pores and defect states during thin film deposition, which is prone to be invaded by oxygen in air or water vapor, resulting in degradation of film performance and reduction of photoelectric conversion efficiency of the heterojunction cell.

[0005] How to solve the stability of microcrystalline silicon thin film is the key to improve the stability of heterojunction cell. Experimental research shows that growing microcrystalline silicon under a single deposition pressure is not conducive to forming a uniform and dense high-quality microcrystalline silicon thin film, and is not conducive to further improving the stability of the microcrystalline silicon thin film.

[0006] Therefore, how to provide a preparation method of a doped microcrystalline silicon layer, a heterojunction solar cell and a preparation method thereof to improve the quality of the doped microcrystalline silicon layer, improve the stability of the heterojunction solar cell and reduce the dark decay of the heterojunction solar cell has become a technical problem to be solved in the industry. SUMMARY

[0007] In view of the above problems of the prior art, the present application provides a preparation method of a doped microcrystalline silicon layer, comprising the following steps:

[0008] (a00), providing a PECVD device, and placing a silicon wafer in a reaction chamber of the PECVD device;

[0009] (a01) adjusting the pressure of the reaction chamber to a first deposition pressure, in which a doped PECVD process is performed to deposit a microcrystalline silicon seed layer on the silicon wafer, wherein the first deposition pressure ranges from 1 to 2.9 mbar; and

[0010] (a02) adjusting the pressure of the reaction chamber to a second deposition pressure, in which the doped PECVD process is performed to deposit a microcrystalline silicon main layer on the microcrystalline silicon seed layer, wherein the second deposition pressure ranges from 3 to 10 mbar.

[0011] In an embodiment, the deposition pressure in step (a02) increases in steps, with each step being 5-10 s, and the deposition pressure increases by 0.1-1 mbar in each step, and a microcrystalline silicon main layer with a thickness of 1-3 nm is deposited in each step.

[0012] In an embodiment, the deposition pressure in step (a02) increases in steps, with the pressure increasing in a total of 6 steps, each step being 10 s, and the corresponding pressure of each step being 3 mbar, 3.15 mbar, 3.3 mbar, 3.45 mbar, 3.6 mbar, and 3.75 mbar, respectively, and a microcrystalline silicon main layer with a thickness of 2 nm is deposited in each step, and the total thickness of the microcrystalline silicon main layer deposited in step (a02) is 12 nm.

[0013] In an embodiment, the first deposition pressure in step (a01) is 2.7 mbar.

[0014] In an embodiment, the doped PECVD process for depositing the microcrystalline silicon seed layer in step (a01) is performed for 10-30 s, and the thickness of the microcrystalline silicon seed layer ranges from 0.5 to 5 nm.

[0015] In an embodiment, the doped PECVD process for depositing the microcrystalline silicon main layer in step (a02) is performed for 50-150 s, and the thickness of the microcrystalline silicon main layer ranges from 10 to 40 nm.

[0016] In an embodiment, the doped PECVD process in steps (a01) and (a02) includes an N-type deposition process, the process gas of the N-type deposition process includes SiH4, H2, and PH3, and further includes CO2 or N2O, the radio frequency (RF) power is 2000 W-10000 W, the gas volume ratio of PH3 to SiH4 is 1%-10%, and the gas volume ratio of CO2 (N2O) to SiH4 is 0%-100%.

[0017] In an embodiment, the doping deposition process in steps (a01) and (a02) comprises a P-type deposition process, the process gas of the P-type deposition process comprises SiH4, H2 and B2H6, the radio frequency (RF) power is 2000-10000 W, and the gas volume ratio of B2H6 to SiH4 is 0.1%-10%.

[0018] The application further provides a heterojunction solar cell, which comprises a single crystal silicon wafer, a first intrinsic amorphous silicon layer, an N-type microcrystalline silicon layer, a first transparent conductive film layer and a first electrode are sequentially formed on the front surface of the single crystal silicon wafer, a second intrinsic amorphous silicon layer, a P-type microcrystalline silicon layer, a second transparent conductive film layer and a second electrode are sequentially formed on the back surface of the single crystal silicon wafer; the N-type microcrystalline silicon layer is formed by the above-mentioned method for forming a doped microcrystalline silicon layer, and / or the P-type microcrystalline silicon layer is formed by the above-mentioned method for forming a doped microcrystalline silicon layer.

[0019] In an embodiment, the thickness of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer is 2-10 nm, the thickness of the N-type microcrystalline silicon layer and the P-type microcrystalline silicon layer is 10.5-45 nm, and the thickness of the first transparent conductive film layer and the second transparent conductive film layer is 10-100 nm.

[0020] The application further provides a method for manufacturing a heterojunction solar cell, which comprises the following steps:

[0021] (a10), providing a single crystal silicon wafer and performing a texturing cleaning on the single crystal silicon wafer;

[0022] (a11), forming a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front and back surfaces of the single crystal silicon wafer by an intrinsic PECVD process;

[0023] (a12), forming an N-type microcrystalline silicon layer on the first intrinsic amorphous silicon layer on the front surface of the single crystal silicon wafer by the above-mentioned method for forming a doped microcrystalline silicon layer;

[0024] (a13), forming a P-type microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back surface of the single crystal silicon wafer by the above-mentioned method for forming a doped microcrystalline silicon layer;

[0025] (a14), forming a first transparent conductive film layer and a second transparent conductive film layer on the N-type microcrystalline silicon layer and the P-type microcrystalline silicon layer, respectively; and

[0026] (a15), forming a first electrode and a second electrode on the first transparent conductive film and the second transparent conductive film, respectively.

[0027] Compared with the single deposition pressure in the prior art, the method for manufacturing the doped microcrystalline silicon layer of the present application first provides a PECVD device, places a silicon wafer in a reaction chamber of the PECVD device, then adjusts the pressure of the reaction chamber to a first deposition pressure, and performs a doped PECVD process in the first deposition pressure to deposit a microcrystalline silicon seed layer on the silicon wafer, wherein the first deposition pressure ranges from 1 to 2.9 mbar, and finally adjusts the pressure of the reaction chamber to a second deposition pressure, and performs the doped PECVD process in the second deposition pressure to deposit a microcrystalline silicon main layer on the microcrystalline silicon seed layer, wherein the second deposition pressure ranges from 3 to 10 mbar. The present application can improve the quality of the doped microcrystalline silicon layer, improve the stability of the heterojunction solar cell, and reduce the dark decay of the heterojunction solar cell. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above features and advantages of the present application will be better understood by reading the detailed description of the embodiments of the present application in conjunction with the following drawings, in which the same or similar components are denoted by the same or similar reference numerals. The components are not necessarily drawn to scale, and components having similar or identical properties or features can have the same or similar reference numerals.

[0029] Figure 1 The present application is a method for manufacturing a doped microcrystalline silicon layer.

[0030] Figure 2 The present application is a heterojunction solar cell.

[0031] Figure 3 The present application is a method for manufacturing a heterojunction solar cell.

[0032] Figure 4 The present application is a method for manufacturing a heterojunction solar cell. Figure 2 The present application is a heterojunction solar cell. DETAILED DESCRIPTION

[0033] The embodiments of the present application will be described in detail by specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure. Although the description of the present application will be introduced in conjunction with the preferred embodiments, this does not mean that the features of the present application are limited to the embodiments. On the contrary, the purpose of introducing the present application in conjunction with the embodiments is to cover other options or modifications that can be extended based on the claims of the present application. In order to provide a deep understanding of the present application, many specific details will be included in the following description. The present application can also be implemented without using these details. In addition, in order to avoid confusion or obscure the focus of the present application, some specific details will be omitted in the description.

[0034] In the description of the present application, it is necessary to point out that unless otherwise explicitly specified and limited, the terms "mount", "connect", "connection" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0035] In addition, "upper", "lower", "left", "right", "top", "bottom", "horizontal", "vertical" used in the following description should be understood as the orientation shown in the section and the related drawings. The relative terms are only for the convenience of description, and do not mean that the device described should be manufactured or operated in a particular orientation, so it should not be understood as a limitation on the present application.

[0036] It can be understood that although the terms "first", "second", "third" and the like are used herein to describe various components, regions, layers and / or parts, these components, regions, layers and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, regions, layers and / or parts. Therefore, the first component, region, layer and / or part discussed below can be referred to as the second component, region, layer and / or part without departing from some embodiments of the present application. The microcrystalline silicon layer in the P-type microcrystalline silicon layer and the N-type microcrystalline silicon layer described in the present application includes amorphous silicon layer, microcrystalline silicon layer and mixture layer of amorphous silicon and microcrystalline silicon in any ratio. The dark decay described in the present application refers to the phenomenon that the conversion efficiency of a solar cell decays over time.

[0037] Referring to Figure 1 , which is a flowchart of an embodiment of a method for manufacturing a doped microcrystalline silicon layer of the present application. As Figure 1 shown, the method S10 for manufacturing the doped microcrystalline silicon layer first performs step S100 of providing a PECVD device and placing a silicon wafer in the reaction chamber of the PECVD device.

[0038] Then continue step S110, adjust the pressure of the reaction chamber to a first deposition pressure, and perform a doped PECVD process in it to deposit a microcrystalline silicon seed layer on the silicon wafer, wherein the first deposition pressure ranges from 1 to 2.9 mbar. The doped PECVD process for depositing the microcrystalline silicon seed layer in step S110 is performed for 10-30 seconds, and the thickness of the microcrystalline silicon seed layer ranges from 0.5 to 5 nm. In a more specific embodiment, the first deposition pressure in step S110 can be 2.7 mbar. The low deposition pressure in step S110 for preparing the microcrystalline silicon seed layer helps to remove the layer of weakly bonded silicon hydrogen atoms, and promotes the formation of more dense and stable microcrystalline nuclei.

[0039] The doping PECVD process in step S110 includes an N-type deposition process, the process gas of the N-type deposition process includes SiH4, H2 and PH3, and further includes CO2 or N2O, the RF power is 2000-10000 W, the gas volume ratio of PH3 to SiH4 is 1%-10%, and the gas volume ratio of CO2 (N2O) to SiH4 is 0%-100%.

[0040] The doping deposition process in step S110 can further include a P-type deposition process, the process gas of the P-type deposition process includes SiH4, H2 and B2H6, the RF power is 2000-10000 W, the gas volume ratio of B2H6 to SiH4 is 0.1%-10%.

[0041] Then, step S120 is continued, the pressure of the reaction chamber is adjusted to a second deposition pressure, and the doping PECVD process is performed in the second deposition pressure to deposit a microcrystalline silicon main layer on the microcrystalline silicon seed layer, wherein the second deposition pressure ranges from 3 to 10 mbar. The deposition pressure in the doping PECVD process in step S120 increases in steps, with each step being 5-10 s, the deposition pressure increases by 0.1-1 mbar in each step, and a microcrystalline silicon main layer with a thickness of 1-3 nm is deposited in each step. The thickness of the microcrystalline silicon main layer ranges from 10 to 40 nm, and the doping PECVD process for depositing the microcrystalline silicon main layer in step S120 is performed for 50-150 s. The deposition in step S120 adopts a high-pressure process, the plasma density increases, the mean free path decreases, the electron temperature decreases, and the particle bombardment weakens, which is beneficial to the growth of crystal grains and the reduction of defect state density; the pressure gradient helps to optimize the continuity of the microcrystalline structure, avoid defects and stress generated in the growth of microcrystalline, and thus improve the stability of microcrystalline silicon.

[0042] In a more specific embodiment, the deposition pressure in the doping PECVD process in step S120 increases in steps, with a total of 6 steps, each step being 10 s, the corresponding pressures of each step being 3 mbar, 3.15 mbar, 3.3 mbar, 3.45 mbar, 3.6 mbar and 3.75 mbar respectively, and a microcrystalline silicon main layer with a thickness of 2 nm is deposited in each step, and the total thickness of the microcrystalline silicon main layer deposited in step S120 is 12 nm.

[0043] The doping PECVD process in step S120 includes an N-type deposition process, the process gas of the N-type deposition process includes SiH4, H2 and PH3, and further includes CO2 or N2O, the RF power is 2000-10000 W, the gas volume ratio of PH3 to SiH4 is 1%-10%, and the gas volume ratio of CO2 (N2O) to SiH4 is 0%-100%.

[0044] The doping deposition process in step S120 can also include a P-type deposition process, the process gas of which includes SiH4, H2 and B2H6, the RF power is 2000W-10000W, and the gas volume ratio of B2H6 to SiH4 is 0.1%-10%.

[0045] Referring to Figure 2 which is a schematic diagram of the composition structure of the heterojunction solar cell of the present application. As shown in Figure 2 , the heterojunction solar cell includes a single crystal silicon wafer 20, the front surface of which is sequentially formed with a first intrinsic amorphous silicon layer 21, an N-type microcrystalline silicon layer 23, a first transparent conductive film layer 25 and a first electrode 27, and the back surface of which is sequentially formed with a second intrinsic amorphous silicon layer 22, a P-type microcrystalline silicon layer 24, a second transparent conductive film layer 26 and a second electrode 28; the N-type microcrystalline silicon layer 23 is formed by the method for forming a doped microcrystalline silicon layer shown in Figure 1 , and / or the P-type microcrystalline silicon layer 24 is formed by the method for forming a doped microcrystalline silicon layer shown in Figure 1 .

[0046] The single crystal silicon wafer 20 can be an N-type single crystal silicon wafer with a resistivity of 0.5-3Ω.cm, a thickness of 100-130 microns (μm) and a size of 125mm×125mm, 156mm×156mm, 166mm×166mm, 210mm×210mm or 182mm×210mm, etc., which are the common or future general sizes. The front and back surfaces of the single crystal silicon wafer 20 can be formed with a pyramidal-like texture by an alkaline solution such as sodium hydroxide or potassium hydroxide.

[0047] The thickness of the first intrinsic amorphous silicon layer 21 and the second intrinsic amorphous silicon layer 22 is in the range of 2-10nm, the thickness of the N-type microcrystalline silicon layer 23 is in the range of 10.5-45nm, the thickness of the P-type microcrystalline silicon layer 24 is in the range of 10.5-45nm, and the thickness of the first transparent conductive film layer 25 and the second transparent conductive film layer 26 is in the range of 10-100nm. The first electrode 27 and the second electrode 28 can be formed by an electroplating process or a screen printing process.

[0048] Referring to Figure 3 which is a flowchart of the method for forming the heterojunction solar cell of the present application. As shown in Figure 3As shown, the method 30 for manufacturing the heterojunction solar cell of the present application first proceeds with step S300 of providing a single crystal silicon wafer and performing a texturing cleaning thereon. In the present embodiment, the single crystal silicon wafer in step S300 is an N-type single crystal silicon wafer, which can be subjected to a damage-removing layer and a pyramidal-like texturing by an alkali etching solution (e.g. a mixture of sodium hydroxide solution or potassium hydroxide solution, isopropyl alcohol and Na2SiO3).

[0049] Next, step S310 is continued to form a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front and back surfaces of the single crystal silicon wafer respectively by an intrinsic PECVD process. In step S310, the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer can be formed on the front and back surfaces of the N-type single crystal silicon wafer respectively by an intrinsic PECVD process performed in the same PECVD reaction chamber, or can be formed on the front and back surfaces of the N-type single crystal silicon wafer respectively by an intrinsic PECVD process performed in different PECVD reaction chambers. The thickness of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer ranges from 2 nm to 10 nm, and the process gas of the intrinsic PECVD process can be silane or a mixture of silane and hydrogen.

[0050] Next, step S320 is continued to form an N-type microcrystalline silicon layer on the first intrinsic amorphous silicon layer on the front surface of the single crystal silicon wafer by a method for manufacturing a doped microcrystalline silicon layer as shown. Figure 1 The method for manufacturing a doped microcrystalline silicon layer in step S320 forms an N-type microcrystalline silicon layer on the first intrinsic amorphous silicon layer on the front surface of the single crystal silicon wafer. The thickness of the N-type microcrystalline silicon layer in step S320 ranges from 10.5 nm to 45 nm.

[0051] Next, step S330 is continued to form a P-type microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back surface of the single crystal silicon wafer by a method for manufacturing a doped microcrystalline silicon layer as shown. Figure 1 The method for manufacturing a doped microcrystalline silicon layer in step S330 forms a P-type microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back surface of the single crystal silicon wafer. The thickness of the P-type microcrystalline silicon layer in step S330 ranges from 10.5 nm to 45 nm.

[0052] Next, step S340 is continued to form a first transparent conductive film layer and a second transparent conductive film layer on the N-type microcrystalline silicon layer and the P-type microcrystalline silicon layer respectively. In the present embodiment, the first transparent conductive film layer and the second transparent conductive film layer are formed by a PVD process, and the thickness of the first transparent conductive film layer and the second transparent conductive film layer ranges from 10 nm to 100 nm. The material of the first transparent conductive film layer and the second transparent conductive film layer is selected from one or more of tin-doped indium oxide, tungsten-doped indium oxide, cerium-doped indium oxide and aluminum-doped zinc oxide.

[0053] Next, step S350 is continued to form a first electrode and a second electrode on the first transparent conductive film and the second transparent conductive film respectively. The first electrode and the second electrode in step S350 can be formed by an electroplating process or a screen printing process.

[0054] Figure 4 For Figure 2 The heterojunction solar cell of the present application and prior art heterojunction solar cell conversion efficiency attenuation comparison chart. As Figure 4 shown, the conversion efficiency of the prior art heterojunction solar cell is attenuated by 0.106%, 0.128%, and 0.187% after 7 days, 14 days, and 28 days, respectively, and the conversion efficiency of the heterojunction solar cell of the present application is attenuated by 0.073%, 0.099%, and 0.112% after 7 days, 14 days, and 28 days, respectively, and the dark decay of the heterojunction solar cell of the present application is significantly reduced.

[0055] In summary, first, a PECVD device is provided, and a silicon wafer is placed in a reaction chamber of the PECVD device; then the pressure of the reaction chamber is adjusted to a first deposition pressure, and a doped PECVD process is performed therein to deposit a microcrystalline silicon seed layer on the silicon wafer, wherein the first deposition pressure ranges from 1 to 2.9 mbar; finally, the pressure of the reaction chamber is adjusted to a second deposition pressure, and the doped PECVD process is performed therein to deposit a microcrystalline silicon main layer on the microcrystalline silicon seed layer, wherein the second deposition pressure ranges from 3 to 10 mbar. The present application can improve the quality of the doped microcrystalline silicon layer, improve the stability of the heterojunction solar cell, and reduce the dark decay of the heterojunction solar cell.

[0056] The foregoing description of the present disclosure has been provided for the purposes of enabling any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. The above-described embodiments are provided as illustrative examples of the present application, and various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and the scope of protection of the present application is not limited by the above-described embodiments but should be accorded the maximum scope consistent with the innovative features disclosed herein.

Claims

1. A method for fabricating a doped microcrystalline silicon layer, characterized in that, The method comprises the following steps: (a00), providing a PECVD device, and placing a silicon wafer in a reaction chamber of the PECVD device; (a01), adjusting a pressure of the reaction chamber to a first deposition pressure, and performing a doped PECVD process in the first deposition pressure to deposit a microcrystalline silicon seed layer on the silicon wafer, wherein the first deposition pressure ranges from 1 mbar to 2.9 mbar; and (a02), adjusting the pressure of the reaction chamber to a second deposition pressure, and performing the doped PECVD process in the second deposition pressure to deposit a microcrystalline silicon main layer on the microcrystalline silicon seed layer, wherein the second deposition pressure ranges from 3 mbar to 10 mbar.

2. The method of claim 1, wherein the step of forming the doped microcrystalline silicon layer is performed by a plasma enhanced chemical vapor deposition method. The deposition pressure in the doped PECVD process in step (a02) increases in steps, with each step being 5-10 s, the deposition pressure increases by 0.1-1 mbar in each step, and a microcrystalline silicon main layer with a thickness of 1-3 nm is deposited in each step.

3. The method of claim 2, wherein the step of forming the doped microcrystalline silicon layer is performed by a plasma enhanced chemical vapor deposition method. The deposition pressure in the doped PECVD process in step (a02) increases in steps, with a total of 6 steps, each step being 10 s, the corresponding pressure of each step being 3 mbar, 3.15 mbar, 3.3 mbar, 3.45 mbar, 3.6 mbar, and 3.75 mbar, respectively, a microcrystalline silicon main layer with a thickness of 2 nm is deposited in each step, and the total thickness of the microcrystalline silicon main layer deposited in step (a02) is 12 nm.

4. The method of claim 1, wherein the microcrystalline silicon layer is doped with phosphorus. The first deposition pressure in step (a01) is 2.7 mbar, the doped PECVD process for depositing the microcrystalline silicon seed layer is performed for 10-30 s, and the thickness of the microcrystalline silicon seed layer ranges from 0.5 nm to 5 nm.

5. The method of claim 1, wherein the microcrystalline silicon layer is doped with phosphorous. The doped PECVD process for depositing the microcrystalline silicon main layer in step (a02) is performed for 50-150 s, and the thickness of the microcrystalline silicon main layer ranges from 10 nm to 40 nm.

6. The method of claim 1, wherein the microcrystalline silicon layer is doped with phosphorous. The doped PECVD process in steps (a01) and (a02) includes an N-type deposition process, the process gas of the N-type deposition process includes SiH4, H2, and PH3, and further includes CO2 or N2O, the radio frequency (RF) power is 2000 W-10000 W, the gas volume ratio of PH3 to SiH4 is 1%-10%, and the gas volume ratio of CO2 (N2O) to SiH4 is 0%-100%.

7. The method of claim 1, wherein the microcrystalline silicon layer is doped with phosphorous. The doped PECVD process in steps (a01) and (a02) includes a P-type deposition process, the process gas of the P-type deposition process includes SiH4, H2, and B2H6, the radio frequency (RF) power is 2000 W-10000 W, the gas volume ratio of B2H6 to SiH4 is 0.1%-10%.

8. A heterojunction solar cell, comprising a single crystal silicon wafer, a first intrinsic amorphous silicon layer, an N-type microcrystalline silicon layer, a first transparent conductive film layer and a first electrode are sequentially formed on the front side of the single crystal silicon wafer, a second intrinsic amorphous silicon layer, a P-type microcrystalline silicon layer, a second transparent conductive film layer and a second electrode are sequentially formed on the back side of the single crystal silicon wafer; the N-type microcrystalline silicon layer is formed by the method for forming a doped microcrystalline silicon layer according to any one of claims 1 to 6, and / or the P-type microcrystalline silicon layer is formed by the method for forming a doped microcrystalline silicon layer according to any one of claims 1 to 5, 7.

9. The heterojunction solar cell according to claim 8, characterized in that, The thickness of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer is 2-10 nm, the thickness of the N-type microcrystalline silicon layer and the P-type microcrystalline silicon layer is 10.5-45 nm, and the thickness of the first transparent conductive film layer and the second transparent conductive film layer is 10-100 nm.

10. A method for fabricating a heterojunction solar cell, characterized in that, It comprises the following steps: (a10), providing a single crystal silicon wafer and performing a texturing cleaning; (a11), forming a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front and back sides of the single crystal silicon wafer by an intrinsic PECVD process; (a12), forming an N-type microcrystalline silicon layer on the first intrinsic amorphous silicon layer on the front side of the single crystal silicon wafer by the method for forming a doped microcrystalline silicon layer according to any one of claims 1 to 6; (a13), forming a P-type microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back side of the single crystal silicon wafer by the method for forming a doped microcrystalline silicon layer according to any one of claims 1 to 5, 7; (a14), forming a first transparent conductive film layer and a second transparent conductive film layer on the N-type microcrystalline silicon layer and the P-type microcrystalline silicon layer, respectively; and (a15), forming a first electrode and a second electrode on the first transparent conductive film and the second transparent conductive film, respectively.

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