Current-carrying detection method of circuit board and electronic equipment

Abstract

The invention discloses a current-carrying detection method of a circuit board and electronic equipment, and relates to the technical field of circuit board current-carrying, and the method comprises the steps: obtaining the position and current-carrying data of each through hole in a to-be-detected circuit board; determining a copper sheet overlapping area of the to-be-tested circuit board according to the position of each layer of copper sheet board of the to-be-tested circuit board; according to the position of each through hole and the copper sheet overlapping area, at least one effective through hole group is determined, each effective through hole group comprises multiple effective through holes, and the multiple effective through holes are all located in the copper sheet overlapping area; the distance between any effective through hole in the effective through hole group and at least one effective through hole in the effective through hole group is smaller than or equal to a preset effective distance; determining current-carrying data corresponding to each effective through hole group according to the current-carrying data of each effective through hole included in each effective through hole group; and carrying out current-carrying detection on the to-be-detected circuit board according to the current-carrying data corresponding to the at least one effective through hole group to obtain a current-carrying detection result.

Description

Technical Field

[0001] This application relates to the field of circuit board current carrying technology, and in particular to a method for detecting the current carrying capacity of circuit boards and an electronic device. Background Technology

[0002] With the widespread application of electrification technology in industries such as industry, communications, transportation, and consumer electronics, the design complexity and performance requirements of printed circuit boards (PCBs), as the core carrier of electronic devices, are increasing. In multilayer PCB structures, different conductive copper layers are electrically connected through vias. When current signals need to be transmitted through these vias for interlayer connections, insufficient current-carrying capacity of the vias can easily lead to excessive localized temperature rise, copper foil melting, or even complete board failure. Therefore, how to effectively and accurately assess the current-carrying capacity of vias on circuit boards has become an urgent problem to be solved. Summary of the Invention

[0003] This application provides a current-carrying detection method and electronic device for circuit boards, in order to at least solve the problem of how to effectively and accurately evaluate the current-carrying capacity of vias on circuit boards.

[0004] This application provides a current-carrying detection method for a circuit board, including: Acquire the location and current carrying capacity of each via on the circuit board under test; Based on the positions of each copper layer of the circuit board under test, the overlapping area of ​​the copper layers of the circuit board under test is determined. Based on the location of each via and the copper overlap area, at least one effective via group is determined. Each effective via group includes multiple effective vias, all of which are located in the copper overlap area. The distance between any effective via in the effective via group and at least one effective via in the effective via group is less than or equal to a preset effective distance. Based on the current carrying data of each effective via included in each effective via group, determine the current carrying data corresponding to each effective via group; Based on the current carrying data corresponding to the at least one effective via group, the circuit board under test is subjected to current carrying capacity detection to obtain current carrying capacity detection results. The current carrying capacity detection results are used to indicate whether the current carrying capacity of the at least one effective via group reaches the preset current carrying capacity threshold corresponding to the effective via group. The preset current carrying capacity threshold is set according to the position of the at least one effective via group in the copper overlap area.

[0005] This application also provides a current-carrying detection device for a circuit board, comprising: The acquisition module is used to acquire the location and current carrying data of each via on the circuit board under test. The processing module is used to determine the copper overlap area of ​​the circuit board under test based on the position of each copper layer of the circuit board under test. The processing module is further configured to determine at least one effective via group based on the position of each via and the copper overlap area, wherein each effective via group includes multiple effective vias, all of which are located in the copper overlap area, and the distance between any effective via in the effective via group and at least one effective via in the effective via group is less than or equal to a preset effective distance. The processing module is further configured to determine the current carrying data corresponding to each effective via group based on the current carrying data of each effective via included in each effective via group; The processing module is further configured to perform current carrying capacity detection on the circuit board under test based on the current carrying capacity data corresponding to the at least one effective via group, and obtain a current carrying capacity detection result. The current carrying capacity detection result is used to indicate whether the current carrying capacity of the at least one effective via group reaches the preset current carrying capacity threshold corresponding to the effective via group. The preset current carrying capacity threshold is set according to the position of the at least one effective via group in the copper overlap area.

[0006] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the current detection method of any of the above-described circuit boards.

[0007] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the current-carrying detection method of any of the above-described circuit boards.

[0008] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the current-carrying detection method for any of the above-described circuit boards.

[0009] This application obtains the location and current-carrying data of each via on the circuit board under test; determines the copper overlap area of ​​the circuit board under test based on the location of each copper layer; determines at least one effective via group based on the location of each via and the copper overlap area, each effective via group including multiple effective vias located in the copper overlap area, the distance between any effective via and at least one effective via in the effective via group being less than or equal to a preset effective distance; determines the current-carrying data corresponding to each effective via group based on the current-carrying data of each effective via included in each effective via group; and performs current-carrying detection on the circuit board under test based on the current-carrying data corresponding to at least one effective via group to obtain the current-carrying detection result, which is used to indicate whether the current-carrying capacity of at least one effective via group reaches the preset current-carrying threshold corresponding to the effective via group, the preset current-carrying threshold being set according to the location of at least one effective via group in the copper overlap area. In this solution, for multiple vias on the circuit board under test, the vias located in the overlapping areas of each copper layer are divided into at least one effective via group according to a certain distance threshold. This allows the current carrying capacity of some closely spaced effective vias to be equivalent to the current carrying capacity of a via group, thus enabling rapid detection and reflecting the current carrying capacity of the entire circuit board. This method allows for rapid and accurate current carrying capacity testing of the entire circuit board, simplifies the current carrying capacity testing operation steps, improves testing efficiency, effectively avoids problems such as thermal failure caused by insufficient number of vias or insufficient current carrying capacity, and ensures the normal operation of the circuit board. Attached Figure Description

[0010] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A simulation diagram illustrating a current-carrying detection method for a circuit board provided in an embodiment of this application; Figure 2 The flowchart of a current-carrying detection method for a circuit board provided in this application embodiment Figure 1 ; Figure 3 A schematic diagram of a circuit board under test provided in an embodiment of this application. Figure 1 ; Figure 4 The flowchart of a current-carrying detection method for a circuit board provided in this application embodiment Figure 2 ; Figure 5 A schematic diagram of a circuit board under test provided in an embodiment of this application. Figure 2 ; Figure 6 A structural diagram of a circuit board current detection device provided in an embodiment of this application; Figure 7 This is a structural diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0013] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0014] It should be noted that in the embodiments of this application, the words "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0015] With the widespread application of electrification technology in industries such as industry, communications, transportation, and consumer electronics, the design complexity and performance requirements of PCBs, as the core carriers of electronic devices, are increasing, especially in high-power, high-frequency applications such as server power systems, electric vehicle control units, 5G base stations, and data center equipment. In these applications, PCBs not only need to achieve precise signal transmission but also bear significant operating currents. Therefore, the current-carrying capacity design of PCBs has become one of the key factors affecting product reliability and safety.

[0016] In multilayer PCB structures, different conductive layers are electrically connected vias, which often become bottlenecks in the current path. Because the cross-sectional area of ​​vias is typically smaller than the trace width and their copper plating thickness is limited, their current-carrying capacity is much lower than that of a planar trace of the same width. When multiple high-current signals need to be connected between layers through multiple vias, insufficient via quantity or inadequate current-carrying capacity of individual vias can lead to increased local resistance, significant Joule heating, and excessive temperature rise. This not only accelerates material aging and reduces insulation performance, but in severe cases, it can also cause copper plating to burn out, vias to break, and even short circuits or fires. Therefore, assessing the current-carrying capacity of vias during the design phase is a crucial step in preventing thermal failure and ensuring reliable system operation.

[0017] Current Electronic Design Automation (EDA) tools (such as CadenceAllegro, Mentor Xpedition, and Altium Designer) possess powerful analysis capabilities. By setting network properties, they can automatically calculate the total current of a specified network and perform preliminary current-carrying capacity verification based on the number and specifications of vias. Some advanced software also supports integration with signal integrity / power integrity (SI / PI) simulation tools to perform DC-DC drop analysis, visually displaying current density distribution and hotspot areas, helping engineers identify potential overcurrent risks.

[0018] However, current simulations based on EDA tools primarily focus on the temperature of a region, using different colors or shades to distinguish different temperatures. They do not provide a direct visual indication of whether the number of vias is sufficient. Figure 1 As shown, the middle area is deeper, while the circled areas on the left and right are shallower. It can be assumed that the temperature in the middle area is higher than that in the two end areas. It is also impossible to accurately locate which area has insufficient vias, which makes it impossible to quickly and accurately detect the current carrying capacity of vias in various areas of the PCB, wasting design time and affecting development efficiency.

[0019] In summary, to solve all or part of the above-mentioned technical problems, this application provides a current-carrying detection method and electronic device for a circuit board, which acquires the position and current-carrying data of each via on the circuit board under test; determines the copper overlap area of ​​the circuit board under test based on the position of each copper layer of the circuit board under test; determines at least one effective via group based on the position of each via and the copper overlap area, wherein each effective via group includes multiple effective vias, all of which are located in the copper overlap area, and the distance between any effective via in the effective via group and at least one effective via in the effective via group is less than or equal to a preset effective distance; determines the current-carrying data corresponding to each effective via group based on the current-carrying data of each effective via included in each effective via group; and performs current-carrying detection on the circuit board under test based on the current-carrying data corresponding to at least one effective via group to obtain a current-carrying detection result, which is used to indicate whether the current-carrying capacity of at least one effective via group reaches a preset current-carrying threshold corresponding to the effective via group, wherein the preset current-carrying threshold is set according to the position of at least one effective via group in the copper overlap area. In this solution, for multiple vias on the circuit board under test, the vias located in the overlapping areas of each copper layer are divided into at least one effective via group according to a certain distance threshold. This allows the current carrying capacity of some closely spaced effective vias to be equivalent to the current carrying capacity of a via group, thus enabling rapid detection and reflecting the current carrying capacity of the entire circuit board. This method allows for rapid and accurate current carrying capacity testing of the entire circuit board, simplifies the current carrying capacity testing operation steps, improves testing efficiency, effectively avoids problems such as thermal failure caused by insufficient number of vias or insufficient current carrying capacity, and ensures the normal operation of the circuit board.

[0020] To implement the circuit board current detection method provided in the embodiments of this application, an EDA plugin can be designed, such as a Skill app suitable for Allegro. This plugin can be configured on an electronic device to implement the following steps.

[0021] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] like Figure 2 As shown, Figure 2 A flowchart of a current-carrying detection method for a circuit board provided in an embodiment of this application is shown. The method may include the following steps: 201. Obtain the location and current carrying capacity of each via on the circuit board under test.

[0023] In this embodiment, the circuit board under test can be a PCB board, and there can be many through holes on the circuit board under test. Typically, multiple conventional holes and multiple through holes can be set on the PCB board. Conventional holes can include mounting holes, positioning holes, etc., which are mainly used for mechanical fixation, heat dissipation or non-electrical functions and usually do not participate in circuit signal transmission. Through holes are specially designed conductive channels in the PCB, which are used to connect the copper traces of different conductive layers (such as top layer, inner layer, bottom layer) to form a complete electrical path. The core function of through holes is the vertical transmission of signals or current.

[0024] Understandably, the circuit board under test (PCB) may include a multi-layer copper foil structure, and the via is a hole that needs to pass through this multi-layer copper foil structure. In a multi-layer PCB, a via acts as a "bridge" for signal or current transmission between different layers. For example, a signal may be routed from the top layer through a via to an inner layer, and then transmitted to the bottom layer through another via.

[0025] In some embodiments, the PCB board may include a conductive layer, an insulating layer, a cover layer, etc.

[0026] The circuit board under test (TBD) may include many vias, each of which can transmit current through traces. The location and current carrying capacity of each via can be obtained. The location of the via is its specific position on the TBD, which can be directly determined from the physical structure of the TBD. The current carrying capacity is the amount of current that the via can support, which can be data that is set in advance when designing the TBD.

[0027] 202. Determine the overlapping area of ​​the copper layers of the circuit board under test based on the position of each copper layer.

[0028] In this embodiment, the circuit board under test can be a multi-layer structure, with each layer consisting of copper foil. The copper foil layers can overlap each other. When overlapping, the copper foil layers can completely overlap or only partially overlap. Therefore, the copper foil overlapping area of ​​the circuit board under test can be determined. This copper foil overlapping area can be the area where all copper foil layers overlap. In other words, the number of copper foil layers covered by the copper foil overlapping area is the total number of layers of the circuit board under test. Since the position of each copper foil layer of the circuit board under test is fixed after the circuit board under test is designed, the copper foil overlapping area of ​​the circuit board under test can be determined directly by the position of each copper foil layer.

[0029] For example, such as Figure 3As shown, the circuit board under test includes three copper foil layers. Copper foil 1 and copper foil 2 have an overlapping area A, copper foil 1 and copper foil 3 have an overlapping area B, and copper foil 2 and copper foil 3 have an overlapping area C. By comparison, it can be seen that the overlapping parts between overlapping areas A, B, and C are all overlapping areas A. That is to say, only overlapping area A is the area covered by copper foil 1, copper foil 2, and copper foil 3. Therefore, overlapping area A can be identified as the copper foil overlapping area of ​​the circuit board under test.

[0030] 203. Based on the location of each via and the overlapping area of ​​the copper foil, determine at least one effective via group.

[0031] In this embodiment of the application, after determining the copper overlap area, each via can be screened according to the position of each via and the copper overlap area to determine at least one effective via group. Each effective via group can include multiple effective vias, all of which are located in the copper overlap area, and the distance between any effective via in the effective via group and at least one effective via in the effective via group is less than or equal to a preset effective distance.

[0032] In other words, when screening vias, all vias located in the copper overlap area can be identified first. Then, for these vias located in the copper overlap area, the spacing between each pair of vias can be calculated. If the spacing between two vias is less than or equal to the preset effective spacing, then these two vias can be considered as effective vias. Then, at least one effective via group can be determined based on the positions of all effective vias. Each effective via group includes at least two effective vias. For any effective via group, the spacing between each of the effective vias included in the group and at least one effective via in the group is less than or equal to the preset effective spacing, while the spacing between each of the effective vias and other vias not belonging to the group is greater than the preset effective spacing.

[0033] Understandably, all vias on the circuit board under test are divided into valid vias and invalid vias. Valid vias must meet the following two conditions: they are located in the copper overlap area, and the distance between them and at least one valid via is less than or equal to a preset valid distance; invalid vias are not located in the copper overlap area, and / or, the distance between them and any other via is greater than the preset valid distance. For each valid via, those with a distance less than or equal to the preset valid distance can then be grouped into a valid via group, thus forming at least one valid via group.

[0034] In some embodiments, the preset effective spacing can be a pre-set fixed distance threshold. This preset effective spacing can be set based on experience, custom settings, or actual needs. Generally, the preset effective spacing is less than or equal to 50 mils (mil). A mil is a unit of length representing one-thousandth of an inch, commonly used in engineering, science, and manufacturing fields, such as measuring the thickness of metal sheets, films, and coatings, or representing the diameter of wires or threads. 1 mil = 0.0254 millimeters (mm) = 0.001 inches (inch) = 25.4 micrometers (μm).

[0035] 204. Based on the current-carrying data of each effective through-hole included in each effective through-hole group, determine the current-carrying data corresponding to each effective through-hole group.

[0036] In this embodiment of the application, since each effective via group includes multiple effective vias, and each effective via is provided with current-carrying data, the current-carrying data corresponding to each effective via group can be determined based on the current-carrying data of each effective via included in each effective via group.

[0037] It should be noted that since one of the criteria for determining the effective vias in an effective via group is the spacing between the effective vias, it can be assumed that the effective vias in an effective via group are relatively close to each other. Therefore, the current carrying capacity of all the effective vias in an effective via group can be equivalent to the current carrying capacity of the entire effective via group.

[0038] 205. Based on the current carrying data corresponding to at least one effective via group, perform current carrying detection on the circuit board under test and obtain the current carrying detection results.

[0039] In this embodiment, after determining the current-carrying data corresponding to each effective via group, the current-carrying capacity of the circuit board under test can be detected. Since the effective vias in the effective via groups are vias that simultaneously connect to each copper plate and can form via clusters, while the vias not in the effective via groups are either not connected to each copper plate or are separate vias that are far away from other vias, these vias not in the effective via groups do not have a significant impact on the current-carrying capacity of the entire circuit board under test, so they do not need to be detected. Only the current-carrying capacity of each effective via group can be detected. In other words, the current-carrying capacity of each effective via group can be detected, and the current-carrying capacity detection result of each effective via group is the current-carrying capacity detection result of the entire circuit board under test.

[0040] It should be noted that the current carrying capacity detection result can be used to indicate whether the current carrying capacity of at least one effective via group reaches the preset current carrying threshold corresponding to the effective via group. The preset current carrying threshold can be set separately for each effective via group, and the preset current carrying thresholds corresponding to each effective via group can be different. Specifically, the preset current carrying threshold can be set according to the position of at least one effective via group in the copper overlap area.

[0041] In some embodiments, since the entire circuit board under test may need to carry the transmission of various current signals, the current carrying requirements corresponding to each current output terminal are different. Therefore, a preset current carrying threshold can be set in advance according to the location on the circuit board under test. The specific value of the preset current carrying threshold can be determined based on historical experience, or based on the actual current network requirements, or based on the attribute information of the devices and copper on the circuit board.

[0042] It should be noted that the preset current carrying threshold can be understood as the amount of current that each area on the circuit board under test needs to carry, that is, the amount of current that the vias in this area need to support. Therefore, the current carrying data of each effective via group can be compared with the preset current carrying threshold. If the current carrying data of an effective via group exceeds the preset current carrying threshold, it means that the current carrying capacity of the area corresponding to the effective via group on the circuit board under test meets the requirements. If the current carrying data of an effective via group does not reach the preset current carrying threshold, it means that the current carrying capacity of the area corresponding to the effective via group on the circuit board under test does not meet the requirements. In this case, it is necessary to continue drilling in this area to improve the current carrying capacity of this area by constructing more effective vias in this area.

[0043] In this embodiment, the preset current carrying threshold for each area on the circuit board under test can be determined based on the copper properties and device properties of the circuit board under test.

[0044] It should be noted that determining the preset current carrying threshold is a key step in PCB design to ensure electrical performance and reliability. It can be determined by combining design requirements, device specifications, simulation analysis, and empirical criteria.

[0045] In some embodiments, device attribute information is a crucial basis for judgment. For the circuit board under test to operate normally, the preset current carrying threshold must at least meet the requirements of each device on the circuit board under test. For example, for power supply devices (such as LDOs, DC-DC converters, and power chips), the datasheet can be consulted to clarify the output current capability (such as "Max Output Current"). Assuming that the LDO datasheet indicates a maximum output current of 1A, the expected current of its power supply network (such as VCC) must be ≤1A, with a 20%-30% margin (such as a design of 0.8A). In addition, for load devices (such as MCUs, sensors, and LEDs), the total power consumption of all loads can be calculated and converted into a current value. Assuming that the MCU's operating current is 50mA and each of the three LEDs' operating current is 20mA, then the total operating current is 110mA, and therefore the corresponding network current is at least 110mA.

[0046] In some embodiments, copper properties are also a crucial criterion for judgment. The thicker the copper and the wider the line width, the stronger the current carrying capacity and the greater the current it can carry. For example, a 1oz copper thickness (35μm) and a 10mil wide trace can carry approximately 1A of current at 25°C; if the line width is increased to 20mil or a 2oz copper thickness is used, then it can carry 2A of current.

[0047] In some embodiments, simulation can also be used to determine whether the voltage drop under network current is within a safe range. This can be done through DC drop analysis using EDA tools (such as Altium Designer's PDN Analyzer or Cadence Sigrity); or through thermal analysis to check whether the temperature rise of high-current paths (such as power input) is within a safe range.

[0048] In some embodiments, the entire circuit board design industry has also proposed some general standards, such as IPC-2221, which provides a current carrying capacity table for different copper thicknesses and line widths; and IPC-2152, which is an updated standard that more accurately considers ambient temperature and heat dissipation conditions.

[0049] In this embodiment, for multiple vias on the circuit board under test, the vias located in the overlapping areas of each copper layer are divided into at least one effective via group according to a certain distance threshold. This allows the current carrying capacity of some close-range effective vias to be equivalent to the current carrying capacity of a via group, thus enabling rapid detection and reflecting the current carrying capacity of the entire circuit board. This allows for rapid and accurate current carrying capacity detection of the entire circuit board, simplifies the operation steps of current carrying capacity detection, improves detection efficiency, effectively avoids problems such as thermal failure caused by insufficient number of vias or insufficient current carrying capacity, and ensures the normal operation of the circuit board.

[0050] like Figure 4 As shown, Figure 4 Another flowchart of a current-carrying detection method for a circuit board provided in an embodiment of this application, the method may include the following steps: 401. Obtain the position of each through hole on the circuit board under test.

[0051] In this embodiment, the description of step 401 is the same as the detailed description of step 201 in the above embodiments, and will not be repeated in this embodiment.

[0052] 402. Obtain the via type of each via on the circuit board under test.

[0053] In this embodiment of the application, a plurality of through holes are provided on the circuit board under test. These through holes can include various types, such as signal holes, power holes, high-speed holes, low-speed holes, etc. Different through hole types can correspond to different current carrying data. Therefore, in order to determine the current carrying data of each through hole, the through hole type of each through hole can be determined first.

[0054] 403. Based on the via type of each via, determine the current carrying data corresponding to each via and via type.

[0055] In this embodiment of the application, after determining the via type of each via, the current carrying data corresponding to the via type can be determined according to the correspondence between the via type and the current carrying data.

[0056] It should be noted that the correspondence between the via type and the current carrying data can be a pre-set correspondence based on experience.

[0057] 404. Set up a planar coordinate system for the circuit board under test.

[0058] In the embodiments of this application, when setting up a planar coordinate system, any position on the circuit board under test can be used as the origin, and any vertical direction can be used as the x-axis and y-axis to establish the planar coordinate system.

[0059] In some embodiments, a planar coordinate system can be established with the center of any layer of copper foil on the circuit board under test as the origin and the boundary directions of any regularly shaped copper foil as the coordinate axes. For example... Figure 5 As shown, the circuit board under test includes two copper layers, where copper layer 1 is a regular rectangle and copper layer 2 is an irregular shape. A planar coordinate system can be established with the center point of copper layer 1 as the origin, the long side of copper layer 1 as the x-axis, and the wide side of copper layer 1 as the y-axis.

[0060] In some embodiments, a planar coordinate system can be established with any vertex of the circuit board under test as the origin, the horizontal direction as the x-axis, and the vertical direction as the y-axis; or a planar coordinate system can be established based on ensuring that the entire circuit board under test is located in the first quadrant of the coordinate system; or various ways of setting the planar coordinate system can be included, which are not specifically limited in the embodiments of this application.

[0061] 405. Based on the plane coordinate system, determine the coordinate range corresponding to each layer of copper foil on the circuit board to be tested.

[0062] In this embodiment of the application, after constructing a planar coordinate system, each layer of copper foil on the circuit board under test can be mapped to the planar coordinate system. In this way, the coordinate range corresponding to each layer of copper foil in the planar coordinate system can be determined. This coordinate range is the set of coordinates of all boundaries of each layer of copper foil.

[0063] In some embodiments, if the copper sheet is a regular shape, such as Figure 5 If the copper sheet is 1, then the coordinate range of this copper sheet can be the range from the minimum to the maximum value of the x-coordinate corresponding to the longer side, and the range from the minimum to the maximum value of the y-coordinate corresponding to the wider side. If the copper sheet is irregularly shaped, such as... Figure 5 If we consider copper sheet 2 in the diagram, then the coordinate range of this copper sheet is the coordinate range corresponding to each boundary.

[0064] 406. Determine the overlapping area of ​​the copper foil of the circuit board under test based on the coordinate range corresponding to each layer of copper foil.

[0065] In this embodiment of the application, after determining the coordinate range corresponding to each layer of copper foil, the coordinate range corresponding to each layer of copper foil can be compared to determine the coordinate range that overlaps. The area on the circuit board under test indicated by the coordinate range is the copper foil overlap area.

[0066] In some embodiments, since the copper overlap area is the area where all copper layers overlap, during the comparison of the coordinate ranges corresponding to each copper layer, the coordinate ranges corresponding to any two copper layers can be compared sequentially. That is, the copper overlap area of ​​the circuit board under test is determined based on the coordinate ranges corresponding to each copper layer. Specifically, this may include: determining the first overlap area based on the coordinate ranges of the first and second copper layers; determining the second overlap area based on the coordinate ranges of the first and third copper layers; repeating the above steps until the coordinate ranges of all copper layers are traversed to obtain the copper overlap area of ​​the circuit board under test.

[0067] It should be noted that the first copper sheet, the second copper sheet, and the third copper sheet can be any layer of the copper sheet of the circuit board under test, and are not limited to adjacent layers.

[0068] It should be noted that when the circuit board under test has only two copper layers, the overlapping area can be obtained by directly comparing the coordinate ranges of the two copper layers. When there are three copper layers, the coordinate ranges of any two copper layers can be compared first, and then the overlapping area of ​​the coordinate ranges of these two copper layers can be compared with the coordinate range of the other copper layer to obtain the overlapping area. When there are more copper layers, the overlapping area can be compared with the coordinate ranges of the other copper layers until the coordinate ranges of all copper layers have been compared, and then the final overlapping area can be obtained.

[0069] For example, such as Figure 3 As shown, the circuit board under test comprises three copper layers. Figure 3 This can be considered a cross-sectional view of the circuit board under test. Figure 3 Each copper layer can represent a range of x-coordinate values, while the y-coordinate ranges of all three copper layers are identical. Therefore, only the x-coordinate ranges need to be compared. First, the coordinate ranges of copper layer 1 and copper layer 2 are compared to obtain the overlapping region A. Then, the coordinate range of overlapping region A is compared with that of copper layer 3. It can be observed that copper layer 3 completely covers overlapping region A. This means that the overlap between overlapping region A and the coordinate range of copper layer 3 is also overlapping region A. Therefore, overlapping region A can be defined as the copper overlap region of the circuit board under test. Figure 5 As shown, the overlapping area of ​​copper sheets 1 and 2 is the shaded area in the figure.

[0070] In this embodiment of the application, in order to determine the copper overlap area of ​​the circuit board under test, the coordinate range of each copper layer mapped to the coordinate system can be compared sequentially to obtain the area where each copper layer overlaps. This ensures that the final copper overlap area is the area covered by all copper layers and that no copper overlap area is missed, thus ensuring the accuracy of subsequent effective via determination and current carrying detection.

[0071] 407. Based on the location of each via and the copper overlap area, determine at least one via located in the copper overlap area.

[0072] In this application, since the copper overlap area is the area covered by each copper sheet, only the through holes located in the copper overlap area can connect the copper sheets of each layer. Therefore, in order to screen out the effective through holes, at least one through hole located in the copper overlap area can be identified first.

[0073] In some embodiments, since a planar coordinate system has been constructed, each via of the circuit board under test can also be mapped to this planar coordinate system to obtain the position coordinates of each via. Then, the position coordinates of each via are compared with the coordinate range of the copper overlap area to detect whether the position coordinates of each via are within the coordinate range of the copper overlap area. If the position coordinates of a via are within the coordinate range of the copper overlap area, then the via can be considered to be located in the copper overlap area; if the position coordinates of a via are not within the coordinate range of the copper overlap area, then the via can be considered not to be located in the copper overlap area.

[0074] 408. For a first through hole in at least one through hole, determine the distance between the first through hole and the second through hole.

[0075] In this embodiment of the application, when determining the spacing between each via located in the copper overlap area, in order to determine all the valid vias, the spacing can be calculated for any pair of vias. That is, for any one of the at least one vias, the spacing between it and the other vias is calculated. The first via is any one of the at least one vias, and the second via is any other via in the at least one vias except the first via. The number of the second vias is not limited.

[0076] 409. If the spacing is less than or equal to the preset effective spacing, then both the first through hole and the second through hole are confirmed as effective through holes.

[0077] In this embodiment of the application, assuming that the distance between the first through hole and the second through hole is less than or equal to the preset effective distance, then the first through hole and the second through hole can both be considered as effective through holes, and the first through hole and the second through hole are in a group of effective through holes.

[0078] It should be noted that for the first through hole, the distance between it and multiple through holes can be compared. As long as the distance between any through hole and the first through hole is less than or equal to the preset effective distance, the through hole and the first through hole are considered to be effective through holes. If there is another through hole and the distance between it and the first through hole is also less than or equal to the preset effective distance, then the other through hole can also be considered to be a effective through hole.

[0079] Conversely, if the distance between the first through hole and all other through holes is greater than the preset effective distance, it means that the first through hole is far away from other through holes in the copper overlap area. In this case, the first through hole can be considered not to be a valid through hole, and no further processing will be performed on the first through hole.

[0080] 410. Repeat the above steps to traverse each through hole and obtain at least one effective through hole group.

[0081] In this embodiment of the application, the above steps are repeated to traverse each via. That is, for each via in the copper overlap area, the spacing is compared with all other vias, and all effective vias in the copper overlap area are determined. Then, these effective vias can be divided to obtain at least one group of effective vias.

[0082] It should be noted that since an effective via is defined as the distance between two vias being less than or equal to a preset effective distance, each group of effective vias includes at least two effective vias. In addition, for each effective via in a group of effective vias, the distance between it and at least one other effective via is less than or equal to the preset effective distance, while the distance between it and other vias outside the group of effective vias is greater than the preset effective distance.

[0083] In some embodiments, the following situations may occur when dividing the effective via group: Case 1: When traversing the spacing between valid vias, the spacing between each valid via and the previous valid via is less than or equal to the preset valid spacing, resulting in all valid vias being located in a group of valid vias.

[0084] For example, there are 5 vias in the copper overlapping area, where the distance between via 1 and via 2 is less than the preset effective distance, the distance between via 1 and via 3 is less than the preset effective distance, the distance between via 2 and via 4 is equal to the preset effective distance, and the distance between via 4 and via 5 is equal to the preset effective distance. Thus, it can be concluded that all 5 vias are effective vias and are located in a group of effective vias.

[0085] Scenario 2: When traversing the spacing between valid vias, the spacing between some vias is less than or equal to the preset valid spacing, and the spacing between other vias is also less than or equal to the preset valid spacing, but the spacing between these two groups of vias is greater than the preset valid spacing. In this case, these two groups of vias will form two groups of valid vias.

[0086] For example, there are 5 vias in the copper overlapping area, where the distance between via 1 and via 2 is less than the preset effective distance, the distance between via 1 and via 3 is less than the preset effective distance, and the distance between via 4 and via 5 is equal to the preset effective distance; however, the distances between via 1 and via 4, between via 1 and via 5, between via 2 and via 4, between via 2 and via 5, between via 3 and via 4, and between via 3 and via 5 are all greater than the preset effective distance. It can be seen that via 1, via 2, and via 3 belong to one effective via group, and via 4 and via 5 belong to another effective via group.

[0087] For example, such as Figure 5 As shown, the black dots represent the vias, and the gray diagonal lines represent the copper overlap area. The two vias in area e are not located in the copper overlap area, so even if the distance between these two vias is less than the preset effective distance, these two vias in area e are not valid vias. In addition, although via d is located in the copper overlap area, the distance between via d and all other vias is greater than the preset effective distance, so via d is also not a valid via.

[0088] like Figure 5 As shown, for each through hole in regions a, b, and c, it can be seen that the distance between two through holes in region a is less than the preset effective distance, therefore both through holes in region a are effective through holes. Furthermore, the distances between these two through holes and each other through hole are greater than the preset effective distance, so the two through holes in region a can be classified as a group of effective through holes. Similarly, in region b, among the three through holes, there are pairs of through holes with distances less than the preset effective distance, therefore all three through holes in region b are effective through holes, and the distances between these three through holes and each other through hole are greater than the preset effective distance, so the three through holes in region b can be classified as a group of effective through holes. Likewise, in region c, among the four through holes, there are pairs of through holes with distances less than the preset effective distance, therefore all four through holes in region c are effective through holes, and the distances between these four through holes and each other through hole are greater than the preset effective distance, so the four through holes in region c can be classified as a group of effective through holes. Therefore, it can be seen that… Figure 5 The circuit board under test shown has three effective via groups, which include two, three, and four effective vias, respectively.

[0089] In some embodiments, the number of specific effective via groups is not limited and can be at least one.

[0090] In some embodiments, when determining valid vias and valid via groups, all valid vias can be determined first, and then valid via groups can be divided according to the spacing between the valid vias. Alternatively, when determining valid vias based on the spacing between pairs of vias, valid via groups can be directly divided according to the spacing. For example, if the spacing between via 1 and via 2 is less than a preset effective spacing, then both via 1 and via 2 can be identified as valid vias, and via 1 and via 2 are in one valid via group. If the spacing between via 1 and via 3 is also less than the preset effective spacing, then via 3 can be considered as a valid via, and is in one valid via group along with via 1 and via 2. In other words, as long as the spacing between two vias is less than or equal to the preset effective spacing, both vias are considered as valid vias and belong to one valid via group. This process is repeated to iterate through and detect the spacing between all vias, continuously expanding at least one valid via group.

[0091] In this embodiment of the application, when determining the effective via group, vias located in the copper overlap area can be screened first. Then, for these vias, the distance between each via is detected sequentially and compared with the preset effective spacing, thereby determining all vias located in the copper overlap area. Furthermore, the effective via group can be divided based on the distance between each via, and the vias that are closer together can be integrated into an effective via group for unified calculation, which improves the comprehensiveness of current carrying capacity detection and also reduces the calculation workload of current carrying capacity detection.

[0092] 411. Sum the current-carrying data of each effective through-hole included in each effective through-hole group to obtain the current-carrying data corresponding to each effective through-hole group.

[0093] In the embodiments of this application, after determining at least one effective via group, the current carrying data of the effective via group can be determined. Since each effective via group includes multiple effective vias, the current carrying data of each effective via located in the effective via group can be summed, and the sum of the current carrying data can be determined as the current carrying data of the entire effective via group.

[0094] 412. Based on the position of at least one effective via group in the copper overlap area, determine the preset current carrying threshold corresponding to each effective via group.

[0095] In this embodiment, since the related attribute information of devices, copper, current network and other components in different areas of the circuit board under test may be different, the current carrying capacity requirements of different areas of the circuit board under test are also different. Therefore, when performing current carrying capacity testing on the circuit board under test, different areas of the circuit board under test can be tested separately. After determining at least one effective via group, the current carrying capacity requirements of each effective via group in the copper overlap area can be tested. Therefore, the current carrying capacity requirements corresponding to the positions of each effective via group in the copper overlap area can be determined first, that is, the preset current carrying capacity threshold corresponding to the positions of each effective via group in the copper overlap area can be determined.

[0096] In some embodiments, the preset current carrying threshold may be a current carrying threshold pre-set according to each area on the circuit board under test.

[0097] 413. Compare the current-carrying data of each effective via group with the preset current-carrying threshold corresponding to each effective via group to obtain the comparison result.

[0098] In this embodiment of the application, after determining the preset current carrying threshold corresponding to each effective via group, the current carrying data corresponding to each effective via group can be compared with the preset current carrying threshold. The current carrying data can be understood as the actual current size that the effective via group can support, while the preset current carrying threshold can be understood as the current size that the location area where the effective via group is located needs to carry. Therefore, by comparing the current carrying data corresponding to each effective via group with the preset current carrying threshold, the comparison result can indicate whether the current effective via group can meet the current carrying requirements.

[0099] 414. If the comparison result indicates that the current carrying capacity of the first effective via group is greater than or equal to the preset current carrying capacity threshold corresponding to the first effective via group, then the current carrying capacity detection result is determined to be that the current carrying capacity of the copper overlapping area corresponding to the first effective via group in the circuit board under test reaches the preset current carrying capacity threshold.

[0100] In this embodiment, the current carrying data of each effective via group is compared with the corresponding preset current carrying threshold. If the current carrying data of a certain effective via group is greater than or equal to the preset current carrying threshold corresponding to the first effective via group, it indicates that the first effective via group can meet the current carrying capacity requirement of the corresponding location area on the circuit board under test. Therefore, it can be determined that the current carrying capacity of the copper overlapping area corresponding to the first effective via group on the circuit board under test reaches the preset current carrying threshold.

[0101] 415. If the comparison result indicates that the current carrying capacity of the first effective via group is less than the preset current carrying capacity corresponding to the first effective via group, then the current carrying capacity detection result is determined to be that the current carrying capacity of the copper overlapping area corresponding to the first effective via group in the circuit board under test has not reached the preset current carrying capacity.

[0102] In this embodiment, the current carrying data of each effective via group is compared with the corresponding preset current carrying threshold. If the current carrying data of the first effective via group is less than the preset current carrying threshold corresponding to the first effective via group, it indicates that the first effective via group cannot meet the current carrying capacity requirement of the corresponding location area on the circuit board under test. Therefore, it can be determined that the current carrying capacity of the copper overlapping area corresponding to the first effective via group on the circuit board under test has not reached the preset current carrying threshold.

[0103] In this embodiment of the application, when performing current carrying capacity testing on the circuit board under test, since the current carrying capacity requirements of different areas on the circuit board under test may be different, the current carrying capacity data of each effective via group and the corresponding preset current carrying capacity threshold can be tested. This allows the current carrying capacity test results to more comprehensively and accurately show the current carrying capacity of each area on the circuit board under test, thereby improving the effectiveness and accuracy of the current carrying capacity test results.

[0104] 416. Based on the location information of the copper overlap area on the circuit board under test, map the copper overlap area to the corresponding position in the auxiliary layer of the circuit board under test.

[0105] In this embodiment, to more clearly and intuitively display the copper overlap area, effective vias, effective via groups, and current carrying capacity test results of the circuit board under test (PCB), an auxiliary layer can be set for the PCB. This auxiliary layer can be understood as a virtual layer, and its area can be the maximum area of ​​the entire PCB, meaning it covers all locations on the PCB. In other words, the auxiliary layer is the union of all copper layers included in the PCB. After determining the copper overlap area, it can be mapped to the corresponding position in the auxiliary layer of the PCB. That is, the copper overlap area can be displayed at the corresponding position in the auxiliary layer.

[0106] 417. Based on the position of each valid via in at least one valid via group, map each valid via in at least one valid via group to a corresponding position in the auxiliary layer of the circuit board under test.

[0107] In this embodiment, after determining at least one effective via group, each effective via in the at least one effective via group can be mapped to a corresponding position in the auxiliary layer of the circuit board under test. This way, only the copper overlap area and all effective vias located within that copper overlap area can be displayed in the auxiliary layer, and at least one effective via group derived from these effective vias can be delineated, while non-effective vias are not displayed.

[0108] 418. Output the current carrying capacity detection results in the auxiliary layer of the circuit board under test.

[0109] In this embodiment, since the current carrying capacity detection result can be used to indicate whether the current carrying capacity of each effective via group has reached the preset current carrying capacity threshold corresponding to the effective via group, the current carrying capacity detection result can be directly output in the auxiliary layer.

[0110] In some embodiments, the current carrying capacity detection result is output in the auxiliary layer of the circuit board under test. Specifically, this may include: if the current carrying capacity detection result indicates that the current carrying capacity of the second effective via group in the circuit board under test reaches a preset current carrying capacity threshold, the second effective via group is marked by a first identifier; if the current carrying capacity detection result indicates that the current carrying capacity of the second effective via group in the circuit board under test does not reach the preset current carrying capacity threshold, the second effective via group is marked by a second identifier; the first identifier and the second identifier have different display formats.

[0111] It should be noted that effective via groups whose current carrying capacity reaches the corresponding preset current carrying threshold and effective via groups whose current carrying capacity does not reach the corresponding preset current carrying threshold can be marked with different display forms.

[0112] In some embodiments, the identifier can be in the form of annotations, i.e., annotating "current carrying capacity meets requirements" for valid via groups whose current carrying capacity reaches the preset current carrying threshold, and annotating "current carrying capacity does not meet requirements" for valid via groups whose current carrying capacity does not reach the preset current carrying threshold, with the annotation content customizable; the identifier can also be in the form of colors, i.e., valid via groups whose current carrying capacity reaches the preset current carrying threshold are highlighted in green, and valid via groups whose current carrying capacity does not reach the preset current carrying threshold are highlighted in red, with the colors customizable; the identifier can also be in the form of bolding, i.e., valid via groups whose current carrying capacity reaches the preset current carrying threshold are bolded, and valid via groups whose current carrying capacity does not reach the preset current carrying threshold are not bolded, with the specific bolded objects customizable; of course, it can also include identifiers in various other display forms, as long as they can distinguish between valid via groups that meet and do not meet the current carrying capacity requirements.

[0113] In this embodiment, an auxiliary layer is constructed for the circuit board under test. The copper overlap area, effective vias, effective via groups, and current carrying capacity test results can all be mapped onto this auxiliary layer for a clearer and more intuitive display. This allows the auxiliary layer to be output to the staff, enabling them to intuitively understand whether the current carrying capacity of the vias meets the requirements, thus facilitating timely processing by the staff.

[0114] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0115] like Figure 6 As shown, embodiments of this application also provide a current-carrying detection device for a circuit board, which may include: The acquisition module 601 is used to acquire the position and current carrying data of each through hole on the circuit board under test. The processing module 602 is used to determine the copper overlap area of ​​the circuit board under test based on the position of each copper layer of the circuit board under test. The processing module 602 is further configured to determine at least one effective via group based on the position of each via and the copper overlap area, wherein each effective via group includes multiple effective vias, all of which are located in the copper overlap area, and the distance between any effective via in the effective via group and at least one effective via in the effective via group is less than or equal to a preset effective distance. The processing module 602 is further configured to determine the current carrying data corresponding to each effective via group based on the current carrying data of each effective via included in each effective via group; The processing module 602 is further configured to perform current carrying capacity detection on the circuit board under test based on the current carrying capacity data corresponding to at least one effective via group, and obtain the current carrying capacity detection result. The current carrying capacity detection result is used to indicate whether the current carrying capacity of at least one effective via group reaches the preset current carrying capacity threshold corresponding to the effective via group. The preset current carrying capacity threshold is set according to the position of at least one effective via group in the copper overlap area.

[0116] In some embodiments, the processing module 602 is specifically used to set a planar coordinate system for the circuit board under test; The processing module 602 is specifically used to determine the coordinate range corresponding to each layer of copper foil of the circuit board under test according to the planar coordinate system. The processing module 602 is specifically used to determine the overlapping area of ​​the copper foil of the circuit board under test based on the coordinate range corresponding to each layer of copper foil.

[0117] In some embodiments, the processing module 602 is specifically used to determine a first overlapping region based on the coordinate range of the first copper sheet and the coordinate range of the second copper sheet; The processing module 602 is specifically used to determine the second overlapping area based on the coordinate range of the first overlapping area and the third copper plate; The processing module 602 is specifically used to loop the above steps until the coordinate range of all copper plates is traversed to obtain the copper overlap area of ​​the circuit board under test.

[0118] In some embodiments, the processing module 602 is specifically configured to determine at least one via located in the copper overlap area based on the location of each via and the copper overlap area. Processing module 602 is specifically used to determine the distance between the first through hole and the second through hole for the first through hole in at least one through hole, wherein the first through hole is any one of the at least one through holes, and the second through hole is any other through hole other than the first through hole; The processing module 602 is specifically used to confirm both the first through hole and the second through hole as valid through holes if the spacing is less than or equal to the preset effective spacing. The processing module 602 is specifically used to loop the above steps, traverse each through hole, and obtain at least one effective through hole group. The distance between each effective through hole in the effective through hole group and the through hole outside the effective through hole group is greater than the preset effective spacing.

[0119] In some embodiments, the processing module 602 is specifically used to sum the current-carrying data of each effective via included in each effective via group to obtain the current-carrying data corresponding to each effective via group.

[0120] In some embodiments, the processing module 602 is specifically used to determine a preset current carrying threshold corresponding to each effective via group based on the position of at least one effective via group in the copper overlap area. The processing module 602 is specifically used to compare the current-carrying data of each effective via group with the preset current-carrying threshold corresponding to each effective via group to obtain the comparison result; The processing module 602 is specifically used to determine that the current carrying capacity of the copper overlapping area corresponding to the first effective via group in the circuit board under test reaches the preset current carrying threshold if the comparison result indicates that the current carrying data of the first effective via group is greater than or equal to the preset current carrying threshold corresponding to the first effective via group. The processing module 602 is specifically used to determine that the current carrying capacity of the copper overlapping area corresponding to the first effective via group in the circuit board under test has not reached the preset current carrying threshold if the comparison result indicates that the current carrying data of the first effective via group is less than the preset current carrying threshold corresponding to the first effective via group.

[0121] In some embodiments, the acquisition module 601 is specifically used to acquire the via type of each via on the circuit board under test; The processing module 602 is specifically used to determine the current-carrying data corresponding to each through hole and through hole type based on the through hole type of each through hole.

[0122] In some embodiments, the processing module 602 is further configured to map the copper overlap region to a corresponding position in the auxiliary layer of the circuit board under test according to the position information of the copper overlap region on the circuit board under test. The processing module 602 is further configured to map each effective via in at least one effective via group to a corresponding position in the auxiliary layer of the circuit board under test, based on the position of each effective via in at least one effective via group. The processing module 602 is also used to output the current carrying detection result in the auxiliary layer of the circuit board under test.

[0123] In some embodiments, the processing module 602 is specifically used to mark the second effective via group by a first identifier when the current carrying capacity of the second effective via group in the circuit board under test is indicated by the current carrying detection result to reach a preset current carrying threshold. The processing module 602 is specifically used to mark the second effective via group by means of a second identifier when the current carrying capacity of the second effective via group in the circuit board under test is not indicated by the current carrying capacity detection result to the preset current carrying capacity threshold; the display forms of the first identifier and the second identifier are different.

[0124] In the embodiments of this application, the description of the features corresponding to the current carrying capacity detection device of the circuit board can be found in the relevant description of the embodiment corresponding to the current carrying capacity detection method of the circuit board, and will not be repeated here.

[0125] like Figure 7 As shown, embodiments of this application also provide an electronic device, including a memory 701 and a processor 702. The memory 701 stores a computer program, and the processor 702 is configured to run the computer program to perform the steps in any of the above embodiments of the current-carrying detection method for a circuit board.

[0126] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the current-carrying detection method for circuit boards when running.

[0127] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0128] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the current-carrying detection method for circuit boards.

[0129] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above embodiments of the current-carrying detection method for circuit boards.

[0130] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0131] The foregoing has provided a detailed description of the process monitoring of a storage system provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for detecting the current carrying capacity of a circuit board, characterized in that, The method includes: Acquire the location and current carrying capacity of each via on the circuit board under test; Based on the positions of each copper layer of the circuit board under test, the overlapping area of ​​the copper layers of the circuit board under test is determined. Based on the location of each via and the copper overlap area, at least one effective via group is determined. Each effective via group includes multiple effective vias, all of which are located in the copper overlap area. The distance between any effective via in the effective via group and at least one effective via in the effective via group is less than or equal to a preset effective distance. Based on the current carrying data of each effective via included in each effective via group, determine the current carrying data corresponding to each effective via group; Based on the current carrying data corresponding to the at least one effective via group, the circuit board under test is subjected to current carrying capacity detection to obtain current carrying capacity detection results. The current carrying capacity detection results are used to indicate whether the current carrying capacity of the at least one effective via group reaches the preset current carrying capacity threshold corresponding to the effective via group. The preset current carrying capacity threshold is set according to the position of the at least one effective via group in the copper overlap area.

2. The method according to claim 1, characterized in that, The step of determining the copper overlap area of ​​the circuit board under test based on the positions of each copper layer includes: A planar coordinate system is set for the circuit board under test; Based on the plane coordinate system, determine the coordinate range corresponding to each copper layer of the circuit board under test; The overlapping area of ​​the copper foil on the circuit board under test is determined based on the coordinate range corresponding to each layer of copper foil.

3. The method according to claim 2, characterized in that, The step of determining the copper overlap area of ​​the circuit board under test based on the coordinate range corresponding to each copper layer includes: The first overlapping area is determined based on the coordinate range of the first copper sheet and the coordinate range of the second copper sheet. The second overlapping area is determined based on the coordinate range of the first overlapping area and the third copper plate; Repeat the above steps until the coordinate range of all copper sheets is traversed to obtain the copper overlap area of ​​the circuit board under test.

4. The method according to claim 1, characterized in that, The step of determining at least one effective via group based on the location of each via and the overlapping area of ​​the copper foil includes: Based on the location of each through hole and the copper overlap area, at least one through hole located in the copper overlap area is determined; For the first through hole in the at least one through hole, determine the distance between the first through hole and the second through hole, wherein the first through hole is any one of the at least one through holes, and the second through hole is any other through hole other than the first through hole; If the spacing is less than or equal to the preset effective spacing, then both the first through hole and the second through hole are confirmed as effective through holes; Repeat the above steps to traverse each through hole and obtain at least one effective through hole group. The distance between each effective through hole in the effective through hole group and the through hole outside the effective through hole group is greater than the preset effective spacing.

5. The method according to claim 1, characterized in that, The step of determining the current-carrying data corresponding to each effective via group based on the current-carrying data of each effective via group includes: The current-carrying data of each effective through-hole included in each effective through-hole group are summed to obtain the current-carrying data corresponding to each effective through-hole group.

6. The method according to claim 1, characterized in that, The step of performing current carrying capacity detection on the circuit board under test based on the current carrying capacity data corresponding to the at least one group of effective vias, and obtaining the current carrying capacity detection result, includes: Based on the positions of the at least one group of effective vias in the copper overlap area, a preset current carrying threshold corresponding to each group of effective vias is determined. The current-carrying data of each effective via group is compared with the preset current-carrying threshold corresponding to each effective via group to obtain the comparison result; If the comparison result indicates that the current carrying data of the first effective via group is greater than or equal to the preset current carrying threshold corresponding to the first effective via group, then the current carrying detection result is determined to be that the current carrying capacity of the copper overlapping area corresponding to the first effective via group in the circuit board under test reaches the preset current carrying threshold. If the comparison result indicates that the current carrying capacity of the first effective via group is less than the preset current carrying capacity threshold corresponding to the first effective via group, then the current carrying capacity detection result is determined to be that the current carrying capacity of the copper overlap area corresponding to the first effective via group in the circuit board under test has not reached the preset current carrying capacity threshold.

7. The method according to claim 1, characterized in that, The acquisition of current-carrying data for each via on the circuit board under test includes: Obtain the via type of each via on the circuit board under test; Based on the via type of each via, determine the current-carrying data corresponding to each via type.

8. The method according to claim 1, characterized in that, The method further includes: Based on the position information of the copper overlap area on the circuit board under test, the copper overlap area is mapped to the corresponding position in the auxiliary layer of the circuit board under test; Based on the position of each effective via in the at least one effective via group, each effective via in the at least one effective via group is mapped to a corresponding position in the auxiliary layer of the circuit board under test; The current-carrying detection result is output in the auxiliary layer of the circuit board under test.

9. The method according to claim 8, characterized in that, The step of outputting the current-carrying detection result in the auxiliary layer of the circuit board under test includes: If the current carrying capacity of the second effective via group in the circuit board under test reaches the preset current carrying threshold, the second effective via group is marked by the first identifier. If the current carrying capacity of the second effective via group in the circuit board under test does not reach the preset current carrying threshold, the second effective via group is marked by a second identifier; the first identifier and the second identifier are displayed in different ways.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the current-carrying detection method for a circuit board as described in any one of claims 1 to 9 when executing the computer program.

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