A shielded layer loop impedance and bridging impedance test calibration device

Abstract

This invention relates to the field of shielding layer impedance testing, specifically to a shielding layer loop impedance and lap impedance testing and calibration device. The shielding layer loop impedance testing and calibration device includes: a top solder mask layer, a top copper foil layer, a dielectric layer, a bottom copper foil layer, and a bottom solder mask layer. The top and bottom copper foil layers are connected by multiple vias, forming a parallel structure. Multiple surface-mount resistors are respectively installed in the impedance setting areas on the left and right sides of the calibration device. The top and bottom copper foil layers have a semi-circular segmented structure and are connected by solder on the surface-mount resistors. The shielding layer loop impedance consists of the copper foil layer impedance, the solder impedance, and the surface-mount resistor impedance. First, the copper foil layer impedance is calculated, then the solder impedance is obtained. Based on the target loop impedance and the corresponding loop current, the surface-mount resistor impedance is determined, and finally, the accurate impedance reading is obtained. This invention is applicable to shielding layer impedance testing.

Description

Technical Field

[0001] This invention relates to the field of shielding layer impedance testing, and more specifically to a device for testing and calibrating shielding layer loop impedance and lap impedance. Background Technology

[0002] In large electronic and electrical equipment such as aircraft and new energy vehicles, the communication bus serves as the primary carrier of information exchange, ensuring the reliability and integrity of transmitted signals. However, unpredictable lightning strikes and high-intensity radiation fields pose challenges to the quality of bus signal transmission. To address such complex electromagnetic interference, the bus shielding layer is double-grounded in specific areas of the equipment. A dedicated connector links both ends of the shielding layer to the equipment's structural ground, forming a shielding loop. Under good grounding conditions, the instantaneous high current induced on the shielding layer can be diverted to the structural ground, preventing it from interfering with the transmitted signals. The reliability of grounding primarily depends on the shielding layer's own resistance.

[0003] Wear and tear on the shielding layer can cause its resistance to become too high, severely reducing its shielding effectiveness. Additionally, poor connection of the dedicated plug can increase its termination resistance, also affecting shielding performance.

[0004] The shielding loop impedance testing system is a key device for testing the integrity and reliability of the low-impedance loop formed between the cable shielding layer and the equipment structure ground. Its testing accuracy directly affects the testing and judgment criteria for the cable harness shielding loop impedance. Therefore, a high-precision loop impedance and lap impedance testing and calibration device is needed. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a device for testing and calibrating the loop impedance and lap impedance of the shielding layer, thereby achieving accurate testing and calibration of the loop impedance and lap impedance of the shielding layer.

[0006] The present invention achieves the above objectives by adopting the following technical solution: The present invention provides a shielding layer loop impedance testing and calibration device, comprising:

[0007] The device consists of a top solder mask layer 1, a top copper foil layer 2, a dielectric layer 3, a bottom copper foil layer 4, and a bottom solder mask layer 5. The top copper foil layer 2 and the bottom copper foil layer 4 are connected by multiple vias 6 and form a parallel structure. Multiple chip resistors 7 are set in the impedance setting areas on the left and right sides of the calibration device. The top copper foil layer 2 and the bottom copper foil layer 4 are semi-circularly divided and connected by solder on the chip resistors. The loop impedance of the shielding layer consists of the copper foil layer impedance, the soldering impedance, and the chip impedance. During testing and calibration, the copper foil layer impedance, the soldering impedance, and the chip impedance are calculated separately, and finally the impedance value of the calibration device is calculated.

[0008] Furthermore, the impedance of the copper foil layer The calculation method is as follows:

[0009] ;

[0010] In the formula, Indicates the resistivity of copper foil. This indicates the thickness of the top copper foil layer 2 and the bottom copper foil layer 4. , These represent the outer diameter and inner diameter of the calibration device, respectively.

[0011] Furthermore, the method for obtaining the welding impedance is as follows: no chip resistor is placed on one side of the calibration device, and a 0Ω resistor is used for welding on the other side. Then, a micro-ohmmeter is used to clamp the test pad 8 on the calibration device, and multiple welding measurements are taken to obtain the average value. , This refers to welding resistance;

[0012] Furthermore, the surface mount impedance is determined based on the target loop impedance and the corresponding loop current. , The calculation method is as follows:

[0013] ;

[0014] In the formula, Indicates the target loop impedance;

[0015] Remove the 0Ω resistor, then use a micro-ohmmeter test clip to clamp the test pad 8 and read the impedance reading. Finally, the calibration device accurately measured the impedance value. .

[0016] The present invention also provides a shielding layer overlap impedance testing and calibration device, comprising: a top solder mask layer 1, a top copper foil layer 2, a dielectric layer 3, a bottom copper foil layer 4, and a bottom solder mask layer 5. The top copper foil layer 2 and the bottom copper foil layer 4 are connected by multiple vias 6 and form a parallel structure. The top copper foil layer 2 and the bottom copper foil layer 4 are fan-shaped segmented structures, and are segmented according to the overlap impedance series values. Surface mount resistors 7 are provided at the segmentation points. Some or all of the surface mount resistors are selected and soldered in different segmented areas. During testing and calibration, the impedance value of the fan-shaped area is read by a micro-ohmmeter test clip.

[0017] Furthermore, during testing and calibration, the impedance value of the sector region is read using the micro-ohmmeter test clip, specifically including:

[0018] During testing and calibration, after each pair of sector areas is soldered with chip resistors, a micro-ohmmeter is used to clamp the test pads 8 at both ends of the two sector divisions and measure and read the corresponding precise lap impedance value Zn. For the last division chip resistor measurement, the chip resistors at the adjacent divisions need to be removed before measurement, and then soldered back after the measurement is completed.

[0019] The beneficial effects of this invention are as follows:

[0020] The shielding layer loop impedance and lap impedance testing and calibration device proposed in this invention can provide a reliable carrier for the traceability of the shielding layer loop impedance testing system, verify the entire measurement system, and is the basic core tool to ensure the reliability of the shielding layer loop impedance and lap impedance measurement results.

[0021] This invention covers a wide range of loop impedances and lap impedances, and both loop and lap impedances can be flexibly set. The cost is significantly reduced compared to other fixed calibration components. This device features a ring-shaped PCB structure, eliminating the influence of lead resistance and taking into account copper foil and solder impedance values, resulting in high accuracy. The device's size can be flexibly set according to actual needs, making it easy to carry. Attached Figure Description

[0022] Figure 1 This is a structural diagram of a shielding layer loop impedance testing and calibration device provided by the present invention;

[0023] Figure 2 This is a structural diagram of a shielding layer overlap impedance testing and calibration device provided by the present invention;

[0024] Figure 3 This is a top view of a PCB for a shielding layer overlap impedance testing and calibration device provided by the present invention.

[0025] Figure 4 This is a circuit diagram of a shielding layer overlap impedance testing and calibration device with segmented regions provided by the present invention.

[0026] In the attached diagram, 1 represents the top solder mask layer, 2 represents the top copper foil layer, 3 represents the dielectric layer, 4 represents the bottom copper foil layer, 5 represents the bottom solder mask layer, 6 represents a via, 7 represents a chip resistor, and 8 represents a test pad. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0028] This invention provides a shielding layer loop impedance testing and calibration device, such as... Figure 1 As shown, it specifically includes:

[0029] The device comprises a top solder mask layer 1, a top copper foil layer 2, a dielectric layer 3, a bottom copper foil layer 4, and a bottom solder mask layer 5. The top copper foil layer 2 and the bottom copper foil layer 4 are connected by multiple vias 6, forming a parallel structure. Multiple surface-mount resistors 7 are respectively installed in the impedance setting areas on the left and right sides of the calibration device. The top copper foil layer 2 and the bottom copper foil layer 4 have a semi-circular segmented structure and are connected by solder on the surface-mount resistors. The loop impedance of the shielding layer consists of the copper foil layer impedance, the solder impedance, and the surface-mount impedance.

[0030] copper foil layer impedance The calculation method is as follows:

[0031] ;

[0032] In the formula, Indicates the resistivity of copper foil. This indicates the thickness of the top copper foil layer 2 and the bottom copper foil layer 4. , These represent the outer diameter and inner diameter of the calibration device, respectively.

[0033] The method for obtaining the soldering impedance is as follows: No chip resistor is placed on one side of the calibration device, and a 0Ω resistor is soldered on the other side. Then, a micro-ohmmeter is used to clamp the test pad 8 on the calibration device. Multiple soldering measurements are taken, and the average value is recorded. , This refers to welding resistance;

[0034] The surface mount impedance is determined based on the target loop impedance and the corresponding loop current. , The calculation method is as follows:

[0035] ;

[0036] In the formula, Indicates the target loop impedance;

[0037] Remove the 0Ω resistor, then use a micro-ohmmeter test clip to clamp the test pad 8 and read the impedance reading. Finally, the calibration device accurately measured the impedance value. .

[0038] Specifically, the present invention is illustrated by an example of a shielding layer loop impedance testing and calibration device (1mΩ-4Ω).

[0039] The main structure of the device is a four-layer PCB consisting of a top solder mask layer, a top copper foil layer, a dielectric layer, a bottom copper foil layer, and a bottom solder mask layer. The top and bottom solder mask layers protect the copper foil from oxidation and corrosion, and improve the PCB's insulation performance. The thickness T of the top and bottom copper foil layers... h The copper foil should be at least 4.5 oz and 157.5 μm in diameter, and its resistivity ρ should not exceed a certain value at 20°C. The dielectric layer is made of fiberglass board (FR4). The outer diameter of the device is D1=140mm and the inner diameter is D2=60mm. The top and bottom copper foil layers are connected by a large number of vias to form a parallel structure to reduce loop impedance.

[0040] The top and bottom copper foil layers have a semi-circular segmented structure, connected by high-precision surface-mount resistors. To reduce solder connection impedance and flexibly configure loop impedance, five high-precision surface-mount resistors are installed on each of the left and right sides of the front of the device. The loop impedance of this device consists of three parts: copper foil layer impedance, soldering impedance, and surface-mount resistor impedance. The impedance value of the semi-circular copper foil layer in this embodiment is... Method for obtaining welding impedance value: Do not attach a resistor to one side of the impedance setting area, and use a 0Ω resistor to weld the other side of the 0Ω resistance area. Then, use a micro-ohmmeter clamp to hold the test pad, perform multiple welds, and take the average value. It is generally around 0.2mΩ. The impedance value is selected according to different calibration values.

[0041] If the standard value of this calibration device is set to 10mΩ, then a surface-mount resistor should be placed on the right side of the PCB front. =8mΩ. If a resistor with this impedance value is unavailable, it can be obtained by connecting multiple resistors in parallel. Remove the 0Ω resistor area, then use a micro-ohmmeter to clamp the left pad on the front of the PCB and read the accurate reading. Then, a 0Ω surface mount resistor was soldered to the left side to complete the fabrication of the 10mΩ calibration device, which has a precise impedance value. .

[0042] When the loop impedance of the shielding layer is detected to be greater than the specified value, the cause of the loop impedance exceeding the standard specification needs to be investigated. Excessive loop impedance is caused by excessive lap impedance at a certain point, such as shielding layer aging or poor plug contact. It is necessary to calibrate the lap impedance test of the testing device. Therefore, this invention also provides a shielding layer lap impedance test calibration device to achieve accurate testing of the lap impedance of the wire harness shielding layer.

[0043] like Figure 2 As shown, the shielding layer overlap impedance testing and calibration device provided by this invention consists of a series of high-precision surface mount resistors and a PCB board. The main PCB board structure includes a top solder mask layer, a top copper foil layer, a dielectric layer, a bottom copper foil layer, and a bottom solder mask layer. The top and bottom copper foil layers are connected by numerous vias to form a parallel structure, thereby reducing loop impedance. The top and bottom copper foil layers have a fan-shaped segmented structure and are connected by high-precision surface mount resistors with solder, allowing for flexible setting of overlap impedance.

[0044] like Figure 3 As shown, this device incorporates high-precision surface-mount resistors at the copper foil layer divisions. The circuit diagram for the divided area is shown below. Figure 4As shown in Table 1, resistors R1-R4 are 1mΩ, R5-R7 are 3mΩ, R8-R10 are 20mΩ, R11-R13 are 100mΩ, R14-R16 are 500mΩ, R17-R19 are 1Ω, R20 is 500mΩ, R21 is 2Ω, R22 is 1Ω, and R23 is 2Ω. Different segmented areas can have some or all of the surface mount resistors soldered, resulting in different lap resistance values ​​Z1-Z8 as shown in Table 1, meeting the calibration requirements for lap impedance spanning 0.25mΩ to 2Ω. After soldering surface mount resistors to each pair of sector areas, a micro-ohmmeter is used to clamp the test pads at both ends of the two sector divisions, and the corresponding precise lap impedance value Zn is measured and read. For the final chip resistor measurement at the split point, the chip resistors at the adjacent split points need to be removed before measurement. After measurement, they should be soldered back. This will give you the shielding layer overlap impedance test and calibration device with a loop impedance of 4Ω.

[0045] Table 1. Overlap resistance values ​​for different specifications

[0046]

[0047] In summary, this invention provides a reliable carrier for the traceability of measurement values ​​in the shielding layer loop impedance testing system, verifies the entire measurement system, and is a fundamental core tool for ensuring the reliability of the measurement results of shielding layer loop impedance and lap impedance.

[0048] This invention covers typical loop impedances of 0.5mΩ to 4Ω and overlap impedances of 0.25mΩ to 4Ω, and both loop and overlap impedances can be flexibly set. The cost is significantly reduced compared to other fixed calibration components. This device features a ring-shaped PCB structure, eliminating the influence of lead resistance and taking into account copper foil and solder resistance values, resulting in high accuracy. The device size can be flexibly set according to actual needs, making it easy to carry.

[0049] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A device for testing and calibrating the loop impedance of a shielding layer, characterized in that, include: The top solder mask layer (1), the top copper foil layer (2), the dielectric layer (3), the bottom copper foil layer (4) and the bottom solder mask layer (5) are connected by multiple vias (6) to form a parallel structure. Multiple chip resistors (7) are set in the impedance setting areas on the left and right sides of the calibration device. The top copper foil layer (2) and the bottom copper foil layer (4) are semi-circularly divided and connected by soldering through the chip resistors. The loop impedance of the shielding layer consists of the copper foil layer impedance, the soldering impedance and the chip impedance. During the test and calibration, the copper foil layer impedance, the soldering impedance and the chip impedance are calculated respectively, and finally the impedance value of the calibration device is calculated.

2. The shielding layer loop impedance testing and calibration device according to claim 1, characterized in that, copper foil layer impedance The calculation method is as follows: ； In the formula, Indicates the resistivity of copper foil. This indicates the thickness of the top copper foil layer (2) and the bottom copper foil layer (4). , These represent the outer diameter and inner diameter of the calibration device, respectively.

3. The shielding layer loop impedance testing and calibration device according to claim 2, characterized in that, The method for obtaining the welding impedance is as follows: no chip resistor is set on one side of the calibration device, and a 0Ω resistor is used for welding on the other side. Then, the test pad (8) on the calibration device is clamped with a micro-ohmmeter test clamp, and the average value is taken after multiple welding measurements. , This is the welding resistance.

4. The shielding layer loop impedance testing and calibration device according to claim 3, characterized in that, The surface mount impedance is determined based on the target loop impedance and the corresponding loop current. , The calculation method is as follows: ； In the formula, Indicates the target loop impedance; Remove the 0Ω resistor, then use a microohmmeter test clip to clamp the test pad (8) and read the impedance reading. Finally, the calibration device accurately measured the impedance value. .

5. A device for testing and calibrating the lap impedance of a shielding layer, characterized in that, include: The top solder mask layer (1), the top copper foil layer (2), the dielectric layer (3), the bottom copper foil layer (4) and the bottom solder mask layer (5) are connected by multiple vias (6) to form a parallel structure. The top copper foil layer (2) and the bottom copper foil layer (4) are fan-shaped segmented structures, and the fan-shaped segmentation is carried out according to the overlap impedance value. The segmentation is provided with chip resistors (7). Some or all of the chip resistors are selected and soldered in different segmented areas. During testing and calibration, the impedance value of the fan-shaped area is read by the micro ohmmeter test clip.

6. The shielding layer overlap impedance testing and calibration device according to claim 5, characterized in that, During testing and calibration, the impedance value of the sector region is read using the micro-ohmmeter test clip, specifically including: During testing and calibration, after the two sector areas are soldered with chip resistors, the test pads (8) at both ends of the two sector divisions are clamped with a micro ohmmeter test clamp to measure and read the corresponding precise lap impedance value Zn. For the last division chip resistor measurement, the chip resistors at the adjacent divisions need to be removed before measurement. After the measurement is completed, they can be soldered back.

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