A high-speed detector chip and NPO module

Abstract

The application discloses a high-speed detector chip and an NPO module. The high-speed detector chip comprises a chip main body, a multi-channel optical port, a TIA radio frequency output pad area, a TIA direct current pad area and a TIA flip area. The multi-channel optical port is located at the edge of one wide side of the chip main body; the TIA radio frequency output pad area is located at the edge of two long sides of the chip main body, and two long sides are distributed with two; the TIA direct current pad area is located at the edge of the two long sides and the edge of the other wide side of the chip main body, and four TIA flip areas are distributed in pairs on the chip main body between the TIA radio frequency output pad area and the TIA direct current pad area. The high-speed detector chip is applied to the NPO module. The application has the advantages that the NPO module can be completely compatible with the OIF standard size through the ingenious layout design, and can be upgraded to support the 32-channel version.

Description

Technical Field

[0001] This invention relates to the fields of high-speed optical communication and optical chip technology, especially photodetector technology, optical access networks, and AI optical networks, specifically a high-speed detector chip and an NPO module. Background Technology

[0002] The basic principle of optical fiber communication is to load electrical signals containing information such as voice, images, video, and text ("1", "0", "1", "0") onto light waves through an optical modulator and transmit them. Then, the signals are transmitted through ultra-low loss optical fibers, and the high-speed optical signals are demodulated into electrical signals by a photodetector. Finally, the signals are recovered through digital signal processing and other processes.

[0003] One advantage of fiber optic communication is its low transmission loss, enabling transoceanic communication, while a single 5G wireless communication base station can cover a cell of approximately several hundred meters. Another advantage is its enormous information capacity. Optical carrier frequencies range from 184 to 238 THz, while wireless communication frequencies are typically between 10 kHz and 300 GHz. According to Shannon's formula, higher carrier frequencies extend the upper limit of available bandwidth, thus providing greater channel capacity.

[0004] With the development of 4G and 5G technologies, fiber optic communication technology has been widely applied in telecommunications, data centers, and other fields. Pluggable transceiver modules are commonly used for bidirectional full-duplex communication. Furthermore, as people's data demands grow, the technology is continuously evolving towards 800G and 1.6T.

[0005] With the widespread adoption of generative AI models, artificial intelligence, the Internet of Things, and cloud computing, reducing the high energy consumption of data nodes in data centers, supercomputing centers, and AI clusters has always been a key driver for the development of optical communication technology towards high integration, low power consumption, high density, and low cost. Among these technologies, CPO (Co-packaged optics) is a crucial alternative to traditional pluggable optical modules, proposed in recent years. Co-packaged optics differs significantly from traditional pluggable modules. Traditional pluggable modules require insertion into the switch panel, and the radio frequency (RF) signal must travel a long path to reach the switch chip. Co-packaged optics directly integrates the optical engine with the switch motherboard, greatly reducing the RF path. Therefore, co-packaged optics not only has low power consumption but also high integration, and is not limited by traditional switch panel interfaces. The disadvantage of CPO technology is that it is inconvenient to maintain and replace, unlike pluggable modules which can be directly replaced. For this reason, NPO (Near-packaged optics) has emerged. NPO modules connect to the socket on the switch motherboard via an LGA interface, similar to a pluggable CPU in a computer. It retains the advantage of pluggable optical modules that can be replaced and repaired, and the power consumption has been greatly reduced.

[0006] The Optical Internetworking Forum (OIF) has released the technical specification protocol for the 3.2T Co-Packaging 3.2T Module-01.0, which defines the NPO module's parameters, including electrical interfaces and mechanical dimensions. Figure 2 The diagram shows the outline of the NPO module, whose detailed structural dimensions are disclosed in the OIF protocol. The module is only about 30.1mm long and 17.5mm wide, sufficient to accommodate the chip. However, given current technological capabilities, achieving both high integration and single-channel speed while meeting the OIF standard size requirements presents a significant challenge.

[0007] An NPO module consists of a standard mechanical housing and a pigtail. It's a transceiver integrated design, typically containing a 16-channel transmitter and a 16-channel receiver, accessed via a multi-channel fiber optic interface. The receiver's core components are a high-speed photodetector (PD) and a transimpedance amplifier (TIA). The photodetector, usually with extremely high bandwidth, converts the high-speed optical signal (up to hundreds of Gbps) emitted by the optical modulator into a photocurrent containing AC information. The high-bandwidth transimpedance amplifier then amplifies the photocurrent and converts it into a high-speed voltage signal for transmission. The bottom of the NPO module has a dense array of pins, connecting to the switch motherboard via an LGA interface. NPO modules are very small. Traditional optical chips are pluggable modules, requiring wire bonding between chips and incorporating numerous capacitors, resistors, and other electronic components, making them difficult to integrate into NPOs.

[0008] Patent authorization number CN221883957U discloses an extended solution, which uses discrete chips to compactly accommodate four 8-channel receivers and four 8-channel transmitters by lengthening the standard optical engine housing. However, its module housing size is not standard, which greatly affects interoperability between different manufacturers. Summary of the Invention

[0009] The technical problem to be solved by this invention is that the size of NPO modules is very limited, and traditional 32-channel receiver chips cannot be installed due to chip size and mounting methods. The purpose of this invention is to propose a high-speed detector chip.

[0010] The technical solution adopted is as follows:

[0011] A high-speed detector chip includes a chip body, which is rectangular in shape.

[0012] The multi-channel optical port is located on the edge of a wide side of the chip body;

[0013] The TIA RF output pad area is located at the edges of the two long sides of the chip body, and there are two pads on each of the two long sides.

[0014] The TIA DC pad area is located at the edge of the two long sides and the edge of the other wide side of the chip body. The TIA DC pad area and the TIA RF output pad area are alternately distributed at the edges of the two long sides, and the TIA DC pad area on the edge of the other wide side is located at the center of the edge.

[0015] The four TIA flip-chip regions are arranged in pairs on the chip body between the TIA RF output pad area and the TIA DC pad area; the long side of the TIA flip-chip region is parallel to the long side of the chip body.

[0016] The TIA RF interfaces of the two TIA flip-chip areas closest to one long edge of the chip body both face the TIA RF output pad area, and the TIA RF interfaces are aligned with the TIA RF output pad area; the TIA RF interfaces of the other two TIA flip-chip areas both face the TIA RF output pad area on the other long edge of the chip body, and the TIA RF interfaces are also aligned with the TIA RF output pad area.

[0017] A further optimization of the technical solution of this invention involves four TIA flip-chip regions arranged in a 2×2 matrix on the chip body between the TIA RF output pad area and the TIA DC pad area. This 2×2 matrix arrangement ensures that the distances between the TIA RF interface and the TIA RF output pad area are equal, helping to reduce latency differences between different channels. Furthermore, the 2×2 matrix arrangement only requires routing one column of lines along the longer side; the other column can be obtained by rotating 180 degrees and translating.

[0018] A further optimization of the technical solution of this invention involves a chip body with dimensions of 5mm × 9mm. The dimensions of the chip body must strictly meet the size limitations of NPO modules. The technical solution proposed in this invention can achieve a size of 5mm × 9mm, satisfying the requirements of practical NPO modules.

[0019] A further optimization of the technical solution of this invention involves a multi-channel optical port comprising a 16-channel or 32-channel edge coupler coupled to an optical fiber array, allowing the light output from the optical fiber array to enter the detector chip. This invention's technical solution is based on a 16-channel design using existing mature TIA chips. With future technological advancements, TIA chips are expected to expand to an 8-channel design. This invention's technical solution can still be expanded to 32 channels, and the size, especially the width, will not increase accordingly, thus still meeting the application requirements of NPO modules.

[0020] A further optimization of the technical solution of the present invention is that the TIA RF output pad area includes the differential output pins of each TIA channel, distributed as GSSG pads. GSSG pad represents a ground-signal-signal-ground pad. The use of differential output in the TIA output pad area can provide better anti-interference capability.

[0021] A further optimization of the technical solution of the present invention is that the TIA DC pad area includes multiple pads for power, control, communication, and detection pins. The technical solution of the present invention, in a compact space, does not sacrifice some chip functions to save area, but rather includes the complete functionality of the receiver chip, thus possessing practicality.

[0022] In a further optimized version of the technical solution of this invention, both the TIA DC pad and the TIA RF pad are electrically connected to the packaging substrate via wire bonding. The mature wire bonding method results in a simple packaging structure, mature technology, and low cost.

[0023] A further optimization of the technical solution of this invention involves flip-chip bonding of the TIA flip-chip region to the transimpedance amplifier chip (TIA); the TIA mounted in the flip-chip region has 4 or 8 channels. The link between the PD and the TIA is highly sensitive to parasitic parameters. The TIA is directly connected to the detector of this invention via flip-chip bonding, resulting in better RF transmission performance.

[0024] A further preferred embodiment of the technical solution of this invention is that the channel rate of the high-speed detector chip is 100G, 200G, or 400G, and the modulation format is PAM4, PAM6, or PAM8. This invention can also be extended to higher rates and higher modulation formats in the future, which will help improve the overall transmission rate.

[0025] The second objective of this invention is to propose an NPO module that employs the aforementioned high-speed detector chip.

[0026] The advantages of this invention compared to the prior art are as follows:

[0027] 1. The high-speed detector chip of the present invention, through ingenious layout design, can achieve full compatibility with OIF standard size NPO modules, and can also be upgraded to support a 32-channel version; this provides a solution for subsequent 6.4T NPO modules and 12.8T NPO, and is more economical and mature than other technical routes such as hybrid bonding, heterogeneous integration, and wafer-level packaging.

[0028] 2. The high-speed detector chip of the present invention is installed in the NPO module, and its length direction is consistent with the length direction of the NPO module, its width direction is consistent with the width direction of the NPO module, and its size is less than 5mm×9mm.

[0029] 3. The high-speed detector chip of the present invention integrates 16 channels of detectors in a single chip, and only two chips are needed to achieve a standard module size layout of 32 channels; it can be easily expanded to 64 channels while maintaining a length of about 5mm, and is still compatible with the standard module size. Attached Figure Description

[0030] Figure 1 This is a structural layout diagram of the high-speed detector chip of the present invention;

[0031] Figure 2 This is the outline of a known NPO module;

[0032] Figure 3 This is a schematic diagram showing the layout of the two high-speed detector chips within the NPO module.

[0033] Figure 4 yes Figure 3 Enlarged view of point A in the image;

[0034] Among them, 1-chip body, 2-multi-channel optical port, 3-TIA RF output pad area, 4-TIA DC pad area, 5-TIA flip-chip area, 6-TIA RF interface. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the following description is provided in conjunction with the appendix. Figures 1-4 The present invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0036] This embodiment illustrates an application scenario for a high-speed detector chip in the field of optical fiber communication.

[0037] This embodiment proposes a high-speed detector chip for NPO modules, such as... Figure 3 and Figure 4 As shown, using two high-speed detector chips side-by-side in this embodiment can meet the compact layout requirements of the NPO module. Since the output direction of the NPO module's pigtail is already determined, the optical port extension direction of the optical chip should be consistent with it. This explains the position and direction described in this embodiment.

[0038] Taking a single-channel rate of 200Gbps and a total of 32 channels as an example, this embodiment proposes a high-speed detector chip for a 6.4T NPO module, including a chip body 1, a multi-channel optical port 2, a TIA RF output pad area 3, a TIA DC pad area 4, and a TIA flip-chip area 5. Figure 1 As shown.

[0039] The chip body 1 is rectangular in shape, and its size design conforms to the size requirements of the NPO module defined in the technical specification protocol related to the 3.2T CPO optical engine released by the OIF (Optical Internetworking Forum).

[0040] like Figure 1 As shown, the two long sides of chip body 1 are defined as follows: Figure 1 The left and right sides of the chip body 1 shown are where it is placed; the two wide sides of the chip body 1 are... Figure 1 The chip body 1 shown is placed at the top and bottom edges.

[0041] like Figure 1 As shown, the multi-channel optical port 2 is located at the lower edge of the chip body 1 and is used to receive the light emitted from the optical fiber.

[0042] TIA RF output pad area 3 is located on the left and right edges of the chip body 1, with two linearly distributed on the left edge and two linearly distributed on the right edge.

[0043] like Figure 1 As shown, in this embodiment, a chip body 1 is equipped with four TIAs, which are located in the flip-chip region 5. In this embodiment, four flip-chip bonded TIAs are required. The high-speed electrical signals output by the TIAs cannot directly reach the packaging substrate. Instead, they must first be led out to the edge of the chip body 1 and then reach the packaging substrate through wire bonding.

[0044] TIA DC pad area 4 is located on the left edge, right edge and top edge of chip body 1. The three TIA DC pad areas 4 and two TIA RF output pad areas 3 are alternately distributed on the left edge. The three TIA DC pad areas 4 and TIA RF output pad areas 3 are alternately distributed on the right edge. The one TIA DC pad area 4 on the top edge is located at the center of the top edge of chip body 1.

[0045] TIA DC pad area 4 includes power, control, communication, and monitoring pins. Similarly, these TIA pins cannot directly reach the packaging substrate. Instead, they must first be led out to the edge of the chip body 1 and then reach the packaging substrate through wire bonding.

[0046] TIA flip-chip regions 5: The four TIA flip-chip regions 5 are arranged in a 2×2 matrix array, with the long side of the TIA flip-chip region 5 parallel to the long side of the chip body 1.

[0047] TIA flip-chip region 5 contains flip-chip pads that are flip-chip bonded to TIA flip-chips. The two TIA RF interfaces 6 in the left column of TIA flip-chip region 5 should be oriented closer to the left TIA RF output pad area 3; the two TIA RF interfaces 6 in the right column of TIA flip-chip region 5 should be oriented closer to the right TIA RF output pad area 3.

[0048] A single TIA has four sides. One side is the RF output, and the parallel side is the photocurrent input pin, which connects to the active output pin of the waveguide detector. The other two sides are the power, control, communication, and monitoring pins of the TIA. Defining the direction of the TIA RF interface 6 determines the TIA's mounting orientation.

[0049] like Figure 1 As shown, the unlabeled areas include metal wiring, various waveguides, and the active area of ​​waveguide detectors. Referring to this embodiment, those skilled in the art can easily set it up according to its layout design rules.

[0050] like Figure 1 As shown, in this embodiment, the size of the chip body 1 is less than 5mm × 9mm, wherein the width is less than 5mm and the length is less than 9mm.

[0051] like Figure 4 As shown, in this embodiment, the chip body 1 is placed in the NPO module with the following orientation: its width direction is consistent with the width direction of the NPO module, the total width of the two chip bodies 1 is 10mm, and the total width of the NPO module is W=17.5mm. Approximately 7.5mm of space is left in the width direction of the NPO module to accommodate necessary electronic components. Its length direction is consistent with the length direction of the NPO module, the total length of the NPO module is L=30.10mm, and 21.1mm of space is left in the length direction to accommodate necessary fiber optic components, optical transmitter chips, and other components.

[0052] In this embodiment, the chip body 1 includes a 16-channel high-speed germanium-silicon waveguide detector, with 4 channels per group, for a total of 4 groups. The channel spacing in each group is conventionally set to 750μm. The 16-channel high-speed germanium-silicon waveguide detector is located in... Figure 1 The unlabeled area on the chip body 1 shown.

[0053] Optionally, the channel spacing of each group can be set to a smaller value, such as 500 μm. While setting the channel spacing of each group to a smaller value is beneficial for further shortening the length of the chip body 1, the corresponding channel crosstalk level will increase, which is detrimental to signal transmission.

[0054] In this embodiment, the multi-channel optical port 2 is a 16-channel edge coupler. The edge coupler can match the fiber mode field and can be efficiently coupled with the fiber array, so that the light output from the fiber array enters the detector chip.

[0055] Optionally, the multi-channel optical port 2 can be configured as a 16-channel grating coupler. The grating coupler can vertically receive light from the fiber array.

[0056] In this embodiment, the TIA RF output pad area 3 includes TIA RF output pads. The TIA RF output is a differential output. The differential output of a single channel is distributed as GSSG (ground-signal-signal-ground), with GND (ground) on both sides and signal in the middle. There are a total of 4 channels, with the channel spacing set to 750μm. All RF output PADs (pads) are arranged in a straight line.

[0057] Optionally, the channel spacing can be set to a smaller value, such as 500 μm. While setting the channel spacing to a smaller value is beneficial for further shortening the length of the chip body 1, the corresponding channel crosstalk level will increase, which is detrimental to signal transmission.

[0058] In this embodiment, the TIA DC pad area 4 includes pads for various power, control, communication, and detection pins arranged in a straight line. It can be easily set up according to the specific model of TIA selected, based on the distribution of the 7 TIA DC pad areas 4 in this embodiment.

[0059] In this embodiment, the pads of the TIA RF output pad region 3 and the pads of the TIA DC pad region 4 are electrically connected to the package substrate by wire bonding.

[0060] In this embodiment, the TIA flip-chip region 5 can be flip-chip soldered to the TIA. The TIA flip-chip region 5 includes flip-chip soldering pads that correspond one-to-one with the pin definitions of the TIA and are in the same position. These flip-chip soldering pads can be flip-chip soldered to the bumps of the flip-chip version of the TIA without any gold wire connection, resulting in better electrical performance.

[0061] In this embodiment, the TIA RF interface 6 is located close to the TIA RF output pad area 3, resulting in greater electrical interconnection distance and better RF performance.

[0062] Optionally, the TIA flip-chip region 5 is selected to mount a 4-channel TIA with a channel spacing of 750 micrometers.

[0063] Optionally, the dimensions of the aforementioned 4-channel TIA with a channel spacing of 750 micrometers are less than 3.5 mm in length and less than 1.5 mm in width.

[0064] Optionally, the TIA channel spacing selected in the TIA flip region 5 can be smaller, such as 500 micrometers. Although setting the channel spacing to be smaller is beneficial to further shorten the length of the chip body 1, the corresponding channel crosstalk level will increase, which is detrimental to signal transmission.

[0065] This embodiment only uses a 6.4T NPO module implemented with a single-channel rate of 200Gbps and a total of 32 channels as an example. The single-channel rate can also be 100G, 200G, 400G, etc., and the modulation format can be any of PAM4, PAM6, PAM8, etc. The total number of channels is not limited to 32 channels and can also be any other number of channels. Any layout idea that adopts this scheme without any inventive effort is within the protection scope of this invention.

[0066] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-speed detector chip, characterized in that, The high-speed detector chip is an integrated chip, including the chip body (1), which is rectangular in shape. The multi-channel optical port (2) is located on the edge of a wide side of the chip body (1); The TIA RF output pad area (3) is located at the edges of the two long sides of the chip body (1), and there are two pads on each of the two long sides. The TIA DC pad area (4) is located at the edge of the two long sides and the edge of the other wide side of the chip body (1). The TIA DC pad area (4) and the TIA RF output pad area (3) at the edges of the two long sides are alternately distributed. The TIA DC pad area (4) on the edge of the other wide side is located at the center of the edge. TIA flip-chip area (5), four TIA flip-chip areas (5) are arranged in pairs on the chip body (1) between the TIA RF output pad area (3) and the TIA DC pad area (4); wherein, the long side of the TIA flip-chip area (5) is parallel to the long side of the chip body (1); The TIA RF interfaces (6) of the two TIA flip-chip regions (5) near one long edge of the chip body (1) are all facing the TIA RF output pad area (3), and the TIA RF interfaces (6) are aligned with the TIA RF output pad area (3); the TIA RF interfaces (6) of the other two TIA flip-chip regions (5) are all facing the TIA RF output pad area (3) on the other long edge of the chip body (1), and the TIA RF interfaces (6) are also aligned with the TIA RF output pad area (3).

2. The high-speed detector chip according to claim 1, characterized in that, Four TIA flip-chip regions (5) are distributed in a 2×2 matrix on the chip body (1) between the TIA RF output pad region (3) and the TIA DC pad region (4).

3. The high-speed detector chip according to claim 1, characterized in that, The chip body (1) has a size of 5mm×9mm.

4. The high-speed detector chip according to claim 1, characterized in that, The multi-channel optical port (2) includes a 16-channel or 32-channel edge coupler that couples with the fiber array so that the light output from the fiber array enters the detector chip.

5. The high-speed detector chip according to claim 1, characterized in that, The TIA RF output pad area (3) includes the differential output pins of each channel of the transimpedance amplifier chip TIA, which are distributed as GSSG pads.

6. The high-speed detector chip according to claim 1, characterized in that, The TIA DC pad area (4) includes a variety of pads for power, control, communication and detection pins.

7. The high-speed detector chip according to claim 5 or 6, characterized in that, Both the TIA DC pads and the TIA RF pads are electrically connected to the package substrate via wire bonding.

8. The high-speed detector chip according to claim 1, characterized in that, The TIA flip-chip area (5) is flip-chip soldered to the transimpedance amplifier chip TIA; the TIA flip-chip area (5) is a 4-channel or 8-channel TIA.

9. The high-speed detector chip according to claim 1, characterized in that, The high-speed detector chip has a channel rate of 100G, 200G or 400G, and a modulation format of PAM4, PAM6 or PAM8.

10. An NPO module, characterized in that, The high-speed detector chip described in any one of claims 1-9 is used.

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