Array substrate, display substrate, array substrate preparation method and related equipment

Abstract

The invention provides an array substrate, a display substrate, an array substrate preparation method and related equipment, the array substrate comprises a substrate, a plurality of grid lines and a plurality of data lines, the grid lines and the data lines are arranged on the substrate in a transverse and longitudinal crossing mode, and the data lines comprise the first data lines and the second data lines. The load of the first data line is smaller than that of the second data line; and the driving circuit comprises a plurality of switch units and a data driving unit. The plurality of switch units comprise a first switch unit and a second switch unit, the first data line is electrically connected with the data driving unit through the first switch unit, and the second data line is electrically connected with the data driving unit through the second switch unit. The area of the orthographic projection of the first switch unit on the substrate is smaller than the area of the orthographic projection of the second switch unit on the substrate, so that the voltage jump value of the first data line is smaller than or equal to the voltage jump value of the second data line, and the display uniformity of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panels, and in particular to an array substrate, a display substrate, an array substrate preparation method and related equipment. BACKGROUND

[0002] With the rapid development of display technology, in order to meet the needs of different scenes, unlike traditional rectangular display panels, special-shaped display panels with special shapes have emerged. For example, electronic rearview mirrors in vehicles or special-shaped central control screens. However, the special-shaped display panel has the problem of uneven display, which seriously affects the display effect. SUMMARY

[0003] Therefore, the purpose of the present application is to provide an array substrate, a display substrate, an array substrate preparation method and related equipment to solve the problem of uneven display of special-shaped display panels.

[0004] To achieve the above purpose, the first aspect of the present application provides an array substrate, comprising:

[0005] a substrate, and a plurality of gate lines and a plurality of data lines arranged transversely and longitudinally on the substrate, wherein the plurality of data lines comprises a first data line and a second data line, and the load of the first data line is less than the load of the second data line;

[0006] a driving circuit on the substrate, comprising a plurality of switching units and a data driving unit; the plurality of switching units comprises a first switching unit and a second switching unit; the first data line is electrically connected to the data driving unit through the first switching unit, and the second data line is electrically connected to the data driving unit through the second switching unit; the area of the orthographic projection of the first switching unit on the substrate is less than the area of the orthographic projection of the second switching unit on the substrate, so that the voltage jump value of the first data line is less than or equal to the voltage jump value of the second data line.

[0007] Optionally, the first switching unit comprises a first thin film transistor, and the second switching unit comprises a second thin film transistor, wherein the width-to-length ratio of the channel region of the first thin film transistor is less than the width-to-length ratio of the channel region of the second thin film transistor.

[0008] Optionally, the source of the first thin film transistor is electrically connected to the first data line, the drain of the first thin film transistor is electrically connected to the data driving unit, and the width-to-length ratio of the channel region of the first thin film transistor is positively correlated with the load of the first data line.

[0009] Optionally, the first switching unit and the second switching unit are multiplexers.

[0010] The second aspect of the present application further provides a display substrate comprising the array substrate as described in the first aspect.

[0011] The third aspect of the present application further provides a preparation method of an array substrate, applied to the array substrate as described in the first aspect, and the method comprises:

[0012] determining an area of the second switch unit, a load of the first data line and a load of the second data line; and calculating the area of the first switch unit according to the area of the second switch unit, the load of the second data line and the load of the first data line.

[0013] Optionally, the first switch unit comprises a first thin film transistor, and the second switch unit comprises a second thin film transistor; and the calculating the area of the first switch unit according to the area of the second switch unit, the load of the second data line and the load of the first data line comprises:

[0014] determining a width-length ratio of a channel region of the second thin film transistor according to the area of the second switch unit;

[0015] calculating a voltage jump value of the second data line according to the width-length ratio of the channel region of the second thin film transistor and the load of the second data line;

[0016] calculating a width-length ratio of a channel region of the first thin film transistor according to the voltage jump value of the second data line and the load of the first data line;

[0017] determining the area of the first switch unit according to the width-length ratio of the channel region of the first thin film transistor.

[0018] Optionally, the calculating the voltage jump value of the second data line according to the width-length ratio of the channel region of the second thin film transistor and the load of the second data line comprises:

[0019] determining a gate-source coupling capacitance of the second thin film transistor according to the width-length ratio of the channel region of the second thin film transistor;

[0020] calculating the voltage jump value of the second data line according to the gate-source coupling capacitance and the load of the second data line.

[0021] Optionally, the number of the first data lines is multiple; and the calculating the area of the first switch unit according to the area of the second switch unit, the load of the second data line and the load of the first data line comprises:

[0022] determining a width-length ratio of a channel region of the second thin film transistor according to the area of the second switch unit;

[0023] calculating a voltage jump value of the second data line according to a width-length ratio of a channel region of the second thin film transistor and a load of the second data line;

[0024] taking a first data line with the smallest load among all the first data lines as a third data line, and taking a first thin film transistor electrically connected with the third data line as a third thin film transistor, calculating a width-length ratio of a channel region of the third thin film transistor according to the voltage jump value of the second data line and a load of the third data line;

[0025] determining a unit width-length ratio change amount according to the load of the second data line, the load of the third data line, the width-length ratio of the channel region of the second thin film transistor and the width-length ratio of the channel region of the third thin film transistor;

[0026] for each of the first data lines other than the third data line,

[0027] determining a width-length ratio of a channel region of a first thin film transistor electrically connected with the first data line according to the width-length ratio of the channel region of the third thin film transistor, the unit width-length ratio change amount, the load of the third data line and the load of the first data line; or

[0028] determining a width-length ratio of a channel region of a first thin film transistor electrically connected with the first data line according to the width-length ratio of the channel region of the second thin film transistor, the unit width-length ratio change amount, the load of the second data line and the load of the first data line;

[0029] determining an area of the first switch unit according to the width-length ratio of the channel region of the first thin film transistor.

[0030] Optionally, the determining the unit width-length ratio change amount according to the load of the second data line, the load of the third data line, the width-length ratio of the channel region of the second thin film transistor and the width-length ratio of the channel region of the third thin film transistor comprises:

[0031] determining a first difference value between the width-length ratio of the channel region of the second thin film transistor and the width-length ratio of the channel region of the third thin film transistor;

[0032] determining a second difference value between the load of the second data line and the load of the third data line;

[0033] taking a ratio of the first difference value to the second difference value as the unit width-length ratio change amount.

[0034] Optionally, the method further comprises:

[0035] determining a first ratio between the load of the first data line and the load of the third data line;

[0036] multiplying the first ratio and the unit width-length ratio variation to obtain a target width-length ratio increment;

[0037] adding the width-length ratio of the channel region of the third thin film transistor and the target width-length ratio increment to obtain the width-length ratio of the channel region of the first thin film transistor.

[0038] Optionally, the method further comprises:

[0039] determining a second ratio between the load of the second data line and the load of the first data line;

[0040] multiplying the second ratio and the unit width-length ratio variation to obtain a target width-length ratio increment;

[0041] subtracting the width-length ratio of the channel region of the second thin film transistor and the target width-length ratio increment to obtain the width-length ratio of the channel region of the first thin film transistor.

[0042] A fourth aspect of the present application provides a preparation device of an array substrate, applied to the array substrate of the first aspect, and the device comprises:

[0043] a determining module configured to determine the area of the second switch unit, the load of the first data line and the load of the second data line;

[0044] a calculating module configured to calculate the area of the first switch unit according to the area of the second switch unit, the load of the second data line and the load of the first data line.

[0045] A fifth aspect of the present application provides an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method of the third aspect.

[0046] The sixth aspect of the present application provides a non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of the third aspect above.

[0047] The seventh aspect of the present application provides a computer program product comprising computer program instructions for causing a computer to perform the method of the third aspect above when the computer program instructions are run on the computer.

[0048] As can be seen from the above, the array substrate, display substrate, array substrate preparation method and related equipment provided by the present application, the array substrate comprises: a substrate, and a plurality of gate lines and a plurality of data lines arranged transversely and longitudinally on the substrate, the plurality of data lines comprising a first data line and a second data line, the lengths of the first data line and the second data line are inconsistent, the number of pixel units mounted by the first data line and the second data line is inconsistent, the load of the first data line is smaller than the load of the second data line, thereby causing the voltage jump value of the first data line to be greater than the voltage jump value of the second data line, and the pixel unit driven by the first data line displays abnormally. The array substrate further comprises a driving circuit, and the driving circuit comprises a plurality of switching units and a data driving unit. The plurality of switching units comprise a first switching unit and a second switching unit, the first data line is electrically connected to the data driving unit through the first switching unit, and the second data line is electrically connected to the data driving unit through the second switching unit. The pixel unit driven by the second data line is a critical pixel unit in the display panel, and the display effect of the pixel unit is normal, while the pixel unit driven by the first data line is an abnormal pixel unit in the display panel, and the display effect is abnormal. In the present application, the area of the orthographic projection of the first switching unit on the substrate is smaller than the area of the orthographic projection of the second switching unit on the substrate, so that the voltage jump value of the first data line is smaller than or equal to the voltage jump value of the second data line. Compared with the orthographic projection area of the second switching unit on the substrate, reducing the orthographic projection area of the first switching unit on the substrate can reduce the voltage jump value of the first data line, so as to reduce the difference between the voltage jump value of the first data line and the voltage jump value of the second data line, achieve the purpose of adjusting the display effect of the pixel unit corresponding to the first data line, and further improve the display uniformity of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the present application or related art, the following will briefly introduce the drawings needed to be used in the embodiments or related art description. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0050] Figure 1 FIG. 1 is a structural schematic diagram of an array substrate in a rectangular liquid crystal display screen according to an embodiment of the present application;

[0051] Figure 2 FIG. 2 is a driving circuit timing diagram and a data line voltage schematic diagram of the array substrate according to the embodiment of the present application;

[0052] Figure 3 FIG. 3 is a structural schematic diagram of an array substrate in a special-shaped liquid crystal display screen according to an embodiment of the present application;

[0053] Figure 4A FIG. 4 is a driving circuit timing diagram and a data line voltage schematic diagram of a non-special-shaped region of the array substrate according to the embodiment of the present application;

[0054] Figure 4B FIG. 5 is a driving circuit timing diagram and a data line voltage schematic diagram of a special-shaped region of the array substrate according to the embodiment of the present application;

[0055] Figure 5 FIG. 6 is a structural schematic diagram of an array substrate in a special-shaped liquid crystal display screen according to another embodiment of the present application;

[0056] Figure 6A FIG. 7 is a driving circuit timing diagram and a data line voltage schematic diagram of a non-special-shaped region of the array substrate according to the another embodiment of the present application;

[0057] Figure 6B FIG. 8 is a driving circuit timing diagram and a data line voltage schematic diagram of a special-shaped region of the array substrate according to the another embodiment of the present application;

[0058] Figure 7 FIG. 9 is a structural schematic diagram of a first switch unit according to an embodiment of the present application;

[0059] Figure 8 FIG. 10 is a flow schematic diagram of a preparation method of the array substrate according to the embodiment of the present application;

[0060] Figure 9 FIG. 11 is a pixel equivalent circuit schematic diagram in the array substrate according to the embodiment of the present application;

[0061] Figure 10 FIG. 12 is a flow schematic diagram of a calculation method of an area of the first switch unit according to the embodiment of the present application;

[0062] Figure 11 FIG. 13 is a structural schematic diagram of a preparation device of the array substrate according to the embodiment of the present application;

[0063] Figure 12 FIG. 14 is a hardware structural schematic diagram of an electronic device according to the embodiment of the present application. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and in conjunction with specific embodiments.

[0065] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the common meanings understood by those with ordinary skills in the art to which the present application belongs. The terms "first", "second" and similar terms used in the embodiments of the present application do not represent any order, number or importance, but are only used to distinguish different components. The terms "include", "contain" and similar terms mean that the components or objects before the terms encompass the components or objects listed after the terms and their equivalents, and do not exclude other components or objects. The terms "connect" or "connected" and similar terms do not mean physical or mechanical connection, but can include electrical connection, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like only represent relative positional relationships, which can change accordingly when the absolute positions of the described objects change.

[0066] Figure 1 The structure of the array substrate in the rectangular liquid crystal display screen in the present application is shown, and in the Figure 1 , a plurality of gate lines 102 (G1, G2, …, G n ) and a plurality of data lines 103 (Date1, Date2, …, Date n ) arranged in a horizontal and vertical manner define a plurality of pixel units. The plurality of gate lines 102 are arranged in a first direction, and the plurality of data lines 103 are arranged in a second direction. Each data line 103 has the same length and the same number of pixel units mounted thereon, i.e., each data line 103 has the same load. Correspondingly, a driving circuit 104 is included below the display area, which is responsible for providing signals to the data lines 103 to charge the pixel electrodes in the pixel units. The driving circuit 104 includes a plurality of switch units 105, and the driving circuit 104 forms an electrical connection with each data line 103 through each switch unit 104. Each switch unit 105 has the same area.

[0067] Figure 2 The driving circuit timing diagram and the data line voltage diagram of the array substrate in the Figure 1 are shown. In the Figure 2 , 11 represents the driving circuit timing diagram of the nth gate line Gate n , 12 represents the driving circuit timing diagram of the nth data line Date n , and specifically includes the driving circuit timing diagram of the red sub-pixel Figure 12-1 , the driving circuit timing diagram of the green sub-pixel Figure 12-2 , and the driving circuit timing diagram of the blue sub-pixel Figure 12-313 represents the data line voltage Date under positive voltage n+ Figure 14 represents the data line voltage Date under negative voltage n- Figure 15 represents the common voltage COM n When the driving control signal is high, each sub-switching unit in the switching unit of the driving circuit sequentially drives each sub-pixel according to the driving signal of the nth data line Date n After data writing is completed, at the moment when each sub-switching unit is closed, i.e. from high to low, due to the coupling effect between circuits, the data line voltage Date n+ and Date n- will generate fluctuations accordingly. Since Figure 1 the load of each data line is balanced, the data line voltage Date n+ and Date n- in 13 and 14 fluctuate the same and the fluctuation is small.

[0068] Figure 3 The structure schematic diagram of the array substrate in the special-shaped liquid crystal display screen of the present application is shown. As shown in Figure 3 , the array substrate is a special-shaped array substrate, and there is a special-shaped region A (such as the upper right corner and the lower left corner in Figure 3 ). In the special-shaped region A, the length of the data line 103 is obviously smaller than that of the data line 103 in the central region of the array substrate, which leads to the problem of uneven load of the data line 103 in the same array substrate. The area of each switching unit 105 in the driving circuit 104 is the same, i.e. the driving capacity of each switching unit 105 is the same, but due to the different loads of each data line 103, it will affect the display effect of the corresponding pixel region, leading to the problem of display abnormality in the special-shaped region A in Figure 3 , such as bias brightening or flickering.

[0069] Figure 4A and Figure 4B The driving circuit timing diagram and the schematic diagram of the data line voltage of the array substrate of Figure 3 are shown. Figure 4A The driving circuit timing diagram and the schematic diagram of the data line voltage of the central region (non-special-shaped region) of the array substrate of Figure 3 are shown, Figure 4B The driving circuit timing diagram and the schematic diagram of the data line voltage of the special-shaped region of the array substrate of Figure 3 are shown. It can be obviously seen that Figure 4A , at the moment when each sub-switching unit is closed, the data line voltage Date n+ and Date n- in 13 and 14 fluctuate little. Figure 4BIn the middle, at the moment when each sub-switching unit is closed, the data line voltage Date n+ and Date n- fluctuates greatly, resulting in the display of the irregular area A appearing to be biased and bright or flickering.

[0070] Therefore, the present application proposes an array substrate, by adjusting the area of each switching unit in the driving circuit, to solve the problem of display abnormality caused by uneven load of each data line in the array substrate. The embodiments of the present application are described in detail below in combination with the drawings.

[0071] Figure 5 The present application shows a schematic diagram of the array substrate in the irregular liquid crystal display screen, which comprises:

[0072] a substrate 101, and a plurality of gate lines 102 and a plurality of data lines 103 arranged in a cross manner on the substrate 101, wherein the plurality of data lines 103 comprises a first data line 1031 and a second data line 1032, and the load of the first data line 1031 is less than that of the second data line 1032.

[0073] a driving circuit 104 located on the substrate 101, comprising a plurality of switching units 105 and a data driving unit 106; the plurality of switching units 105 comprises a first switching unit 1051 and a second switching unit 1052; the first data line 1031 is electrically connected to the data driving unit 106 through the first switching unit 1051, and the second data line 1032 is electrically connected to the data driving unit 106 through the second switching unit 1052; the area of the orthographic projection of the first switching unit 1051 on the substrate 101 is less than that of the second switching unit 1052 on the substrate 101, so that the voltage jump value of the first data line 1031 is less than or equal to that of the second data line 1032.

[0074] Specifically, on the substrate 101, a plurality of gate lines 102 and a plurality of data lines 103 are arranged to form a plurality of pixel units. Each pixel unit includes a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit. Each sub-pixel unit further includes a thin film transistor T1, the gate of T1 is electrically connected with the gate line, the drain of T1 is electrically connected with the data line, and the source of T1 is electrically connected with the sub-pixel. Under the control of the gate, the data line of the drain charges and discharges the sub-pixel connected with the source through T1. The array substrate in the embodiment is a special-shaped array substrate, the number of pixel units mounted by each data line is different, the data line with the largest number of pixel units mounted is taken as the second data line 1032, and the data line with the number of pixel units mounted less than the second data line 1032 is taken as the first data line 1031. The load of the first data line 1031 is less than the load of the second data line 1032.

[0075] The array substrate of the embodiment further includes a driving circuit 104, the driving circuit 104 includes a plurality of switch units 105 and a data driving unit 106. Each data line 103 is electrically connected with the data driving unit 106 through the switch unit 105. Exemplarily, the switch unit 105 can be a multiplexer (MUX), and the multiplexer includes a plurality of thin film transistors. For example, each MUX includes three thin film transistors, which are TFT-R, TFT-G and TFT-B respectively. The gate of each thin film transistor is connected with a corresponding clock signal line, and under the control of the clock signal input from the clock signal line, the thin film transistor transmits the data signal input from the data driving unit to the corresponding data line. The clock signal corresponding to TFT-R is MUXR, the clock signal corresponding to TFT-G is MUXG, and the clock signal corresponding to TFT-B is MUXB. The source of each thin film transistor is connected with each sub-pixel unit in the pixel unit, such as TFT-R connected with the red sub-pixel, TFT-G connected with the green sub-pixel, and TFT-B connected with the blue sub-pixel.

[0076] The first data line 1031 is electrically connected with the first switch unit 1051, and the second data line 1032 is electrically connected with the second switch unit 1052. The area of the orthographic projection of the first switch unit 1051 on the substrate 101 is less than the area of the orthographic projection of the second switch unit 1052 on the substrate 101. For example, Figure 5As shown, the second data line 1032 includes all data lines electrically connected to the second switching unit 1052. That is, the second data line 1032 includes all data lines electrically connected to the 8th, 9th, and 10th switching units. All other data lines besides the second data line 1032 are first data lines 1031. The second switching units 1052 (the 8th, 9th, and 10th switching units) have the same area projected onto the substrate 101.

[0077] like Figure 4A It can be seen that in the non-irregular region of the array substrate ( Figure 3 In the central area of ​​the display panel, at the instant each second switch unit 1052 is turned off, the data line voltage Date... n+ and Date n- The fluctuations are relatively small. The data line contained in the non-irregular area is the second data line 1032, because the Date of the second data line 1032... n+ and Date n- The fluctuation is small, meaning the voltage jump value of the second data line 1032 is small. Therefore, using the voltage jump value of the second data line 1032 as a reference, the voltage jump value of the first data line 1031 is adjusted. When the voltage jump value of the first data line 1031 is less than or equal to the voltage jump value of the second data line 1032, it is considered that the display abnormality problem of the pixel unit corresponding to the first data line 1031 can be effectively eliminated. Figure 4B In the process, when the gate voltage of the thin-film transistor in the first switching unit 1051 drops from a high level to a low level, the change in gate voltage is coupled to the data line by the gate-source coupling capacitance generated by the thin-film transistor in the first switching unit 1051, causing a voltage jump to the pixel unit, and the irregular region in the array substrate ( Figure 3 The irregularly shaped display area A) pixel unit of the display panel has a display abnormality problem.

[0078] Furthermore, with Figure 3 The areas of the orthographic projections of each switching unit 105 on the substrate 101 are different. Figure 5 By reducing the area of ​​the orthogonal projection of the first switching unit 1051 onto the substrate 101, the structural size of each thin-film transistor (TFT-R, TFT-G, and TFT-B) in the first switching unit 1051 is reduced, thereby reducing the capacitance value of the gate-source coupling capacitor in each thin-film transistor. This makes the voltage jump value coupled to the first data line 1031 less than or equal to the voltage jump value of the second data line 1032, thereby improving the display uniformity of the irregularly shaped display panel.

[0079] Figure 6A and Figure 6B It shows Figure 5The timing diagram of the driving circuit and the schematic diagram of the data line voltage of the array substrate are shown. Figure 6A for Figure 5 The timing diagram of the driving circuit and the schematic diagram of the data line voltage in the central region of the array substrate are shown. Figure 6B for Figure 5 The timing diagram of the driving circuit and the schematic diagram of the data line voltages for the irregularly shaped region A of the array substrate are shown. It can be clearly seen that... Figure 6A In the middle, at the instant that each thin-film transistor (TFT-R, TFT-G, and TFT-B) is turned off, the data line voltage Date in 13 and 14... n+ and Date n- The fluctuations are relatively small. Figure 6B In the process, when the area of ​​the first switching unit 1051 projected onto the substrate 101 is reduced, at the instant that each thin-film transistor (TFT-R, TFT-G, and TFT-B) is turned off, the data line voltage Date in 3 and 14... n+ and Date n- The fluctuations have decreased significantly (compared to) Figure 4B In comparison, this solved the problem of bias-induced brightness or flickering in the irregular area A.

[0080] The following specific embodiments describe how to reduce the structural size of each thin-film transistor in the first switching unit so that the voltage jump value of the first data line is less than or equal to the voltage jump value of the second data line.

[0081] In some embodiments, the first switching unit includes a first thin-film transistor, and the second switching unit includes a second thin-film transistor, wherein the aspect ratio of the channel region of the first thin-film transistor is smaller than the aspect ratio of the channel region of the second thin-film transistor.

[0082] Specifically, the thin-film transistor in the first switching unit 1051 is the first thin-film transistor 1071, and the thin-film transistor in the second switching unit 1052 is the second thin-film transistor 1072. When adjusting the structural dimensions of the first thin-film transistor 1071, the width-to-length ratio W / L of the channel region of the second thin-film transistor 1072 is used as a reference, and the width-to-length ratio W / L of the channel region of the first thin-film transistor 1071 is reduced. Typically, to obtain a higher on-state current of the thin-film transistor, the length L is generally chosen to be the minimum spacing that ensures no short circuit occurs between the source and drain metal layers at the same process level; therefore, the length L is a fixed value. In this embodiment, the length L remains constant, and the width-to-length ratio W / L is reduced by decreasing the width W. Reducing the width-to-length ratio W / L can lower the capacitance value of the gate-source coupling capacitor in the first thin-film transistor 1071, thereby reducing the voltage jump value of the data line, solving the problem of bias-induced brightness or flickering in irregularly shaped areas, and improving the uniformity of the display panel's display effect.

[0083] In Figure 5 In the array substrate shown in the figure, the load of the first data line 1031 is smaller than the load of the second data line 1032, but the loads of different first data lines 1031 are not completely the same, and correspondingly, the width-length ratios of the channel regions of the first thin film transistors 1071 connected with different first data lines 1031 are not the same, which will be explained below through specific embodiments.

[0084] In some embodiments, the source of the first thin film transistor is electrically connected with the first data line, the drain of the first thin film transistor is electrically connected with the data driving unit, and the width-length ratio of the channel region of the first thin film transistor is positively correlated with the load of the first data line.

[0085] Figure 7 The structure schematic diagram of the first switch unit is shown. In the first switch unit 1051, three first thin film transistors 1071 are included, the source 1071-1 of each first thin film transistor 1071 is electrically connected with the first data line 1031, the drain 1071-2 of the first thin film transistor 1071 is electrically connected with the data driving unit 106, and the gate 1071-3 of the first thin film transistor 1071 is connected with the clock signal line 111. The width-length ratio of the channel region of the first thin film transistor 1071 is positively correlated with the load of the first data line 1031, the greater the load, the greater the width-length ratio of the channel region, and the smaller the load, the smaller the width-length ratio of the channel region. As shown in the figure, Figure 5 As shown in the figure, the area of the second switch unit 1052 corresponding to the second data line 1032 is the largest, and correspondingly, the width-length ratio of the channel region of the thin film transistor in the second switch unit 1052 is also the largest. Extending from the second data line 1032 to both sides, as the load of the first data line 1031 gradually decreases, the area of the corresponding first switch unit 1051 also gradually decreases, and correspondingly, the width-length ratio of the channel region of the thin film transistor in the first switch unit 1051 also gradually decreases. According to the load of the first data line 1031, the width-length ratio of the channel region of the thin film transistor in the first switch unit 1051 is determined, so as to achieve the effect of regulating the driving capability of different first switch units 1051, reduce the voltage jump value of the first data line 1013, and thus achieve the effect of improving the display uniformity of the special-shaped display panel.

[0086] Figure 8 A preparation method of an array substrate is shown, which is applied to the array substrate as described in any one of the preceding embodiments, and the method comprises the following steps:

[0087] Step 802, determining the area of the second switch unit, the load of the first data line, and the load of the second data line.

[0088] Specifically, in the special-shaped display panel, the critical position of the abnormal display region is determined according to the display effect in the special-shaped display panel. For example, in theFigure 5 In the embodiment, the critical position of the abnormal display area is between the display area corresponding to the junction of the 7th switch unit and the 8th switch unit, and the display area corresponding to the junction of the 10th switch unit and the 11th switch unit. The simulation model is constructed by simulating the display panel, and the area of the second switch unit 1052 and the load of each data line 103 are determined by the simulation model.

[0089] In step 804, the area of the first switch unit is calculated according to the area of the second switch unit, the load of the second data line and the load of the first data line.

[0090] After the area of the second switch unit 1052 and the load of each data line are determined, the area of the first switch unit 1051 can be further determined. The area of the switch unit 105 is positively correlated with the load of the corresponding data line 103, that is, the greater the load, the greater the area of the switch unit. Further, the ratio of the load of the first data line 1031 to the load of the second data line 1032 is calculated based on the area of the second switch unit 1052, and the area of the first switch unit 1051 can be determined according to the ratio and the area of the second switch unit 1052.

[0091] Through the method of the embodiment, the area of each first switch unit can be determined based on the second switch unit, so as to achieve the effect of regulating the driving capability of different first switch units, reduce the voltage jump value of the first data line of the abnormal display area, and thus improve the display uniformity of the special-shaped display panel.

[0092] In some embodiments, the first switch unit includes a first thin film transistor, and the second switch unit includes a second thin film transistor; and the calculation of the area of the first switch unit according to the area of the second switch unit, the load of the second data line and the load of the first data line includes:

[0093] The width-length ratio of the channel region of the second thin film transistor is determined according to the area of the second switch unit; the voltage jump value of the second data line is calculated according to the width-length ratio of the channel region of the second thin film transistor and the load of the second data line; the width-length ratio of the channel region of the first thin film transistor is calculated according to the voltage jump value of the second data line and the load of the first data line; and the area of the first switch unit is determined according to the width-length ratio of the channel region of the first thin film transistor.

[0094] Specifically, when the width-length ratio of the channel region of the thin film transistor changes, the area of the switching unit changes accordingly. The width-length ratio of the channel region of the thin film transistor and the area of the switching unit have a certain correspondence, and when the area of the switching unit is determined, the width-length ratio of the channel region of the thin film transistor can be further determined according to the simulation model. When the width-length ratio of the channel region of the thin film transistor is determined, the structure of the thin film transistor is determined. The thin film transistor includes a source, a gate and a drain, and after the structure of the thin film transistor is determined, the capacitance value of the gate-source coupling capacitor between the gate and the source can be calculated. Correspondingly, after the area of the second switching unit 1052 is determined, the width-length ratio of the channel region of the second thin film transistor 1072 and the capacitance value of the gate-source coupling capacitor in the second thin film transistor 1072 can be determined.

[0095] Figure 9 A schematic diagram of a pixel equivalent circuit in an array substrate is shown. The pixel unit includes a third thin film transistor 108, a storage capacitor 109 (denoted as C st ) and a liquid crystal capacitor 110 (denoted as C lc ), the source 108-1 of the third thin film transistor 108 is connected with the liquid crystal capacitor 110, the drain 108-2 of the third thin film transistor 108 is connected with the data line 103, and the gate 108-3 of the third thin film transistor 108 is connected with the gate line 102. The first gate-source coupling capacitor 108-4 (denoted as C gs-1 ) is formed between the gate 108-3 and the source 108-1 of the third thin film transistor 108. The switching unit 105 includes a thin film transistor 107 (the first thin film transistor 1071 or the second thin film transistor 1072), the source 107-1 of the thin film transistor 107 is connected with the first data line 1031, the gate 107-3 of the thin film transistor 107 is connected with the clock signal line 111, and the drain 107-2 of the thin film transistor 107 is electrically connected with the data driving unit 106. The second gate-source coupling capacitor 107-4 (denoted as C gs-2 ) is formed between the gate 107-3 and the source 107-1 of the thin film transistor 107. At the moment when the gate signal of the third thin film transistor 108 or the thin film transistor 107 is turned off, due to the voltage division effect of the first gate-source coupling capacitor 108-4 or the second gate-source coupling capacitor 107-4, the voltage V p of the data line 103 will jump, and the voltage jump value of V p is ΔV p .

[0096] At the moment when the third thin film transistor 108 is turned off, according to the principle of charge conservation, it can be obtained that:

[0097] (V p Gate -V com )*(C lc +Cst )+(V p Gate -V gh )*C gs-1 =(V′) p Gate -V com )*(C lc +C st )+(V′ p Gate -V gl )*C gs-1 Equation (1)

[0098] From equation (1), we can obtain the jump value ΔV generated by the first data line voltage. p Gate :

[0099] ΔV p Gate =(ΔV) g * C gs-1 ) / (C gs-1 +C lc +C st Equation (2)

[0100] Where, ΔV g =V gh –V gl V p Gate V before the third thin-film transistor 108 is turned off p , V′ p Gate V after the third thin-film transistor 108 is turned off p V com For common voltage, V gh V is the gate voltage (high level) before the thin-film transistor is turned off. gl This is the gate voltage (low level) after the thin-film transistor is turned off.

[0101] At the instant the thin-film transistor 107 is turned off, according to the principle of charge conservation, we can obtain:

[0102] V p MUX *C AA +(V p MUX -V gh )*C gs-2 =V′ p MUX *C AA +(V′ pMUX -V gl )*C gs-2 Equation (3),

[0103] From equation (3), the jump value of the first data line voltage is ΔV p MUX :

[0104] ΔV p MUX = (Δ Vg * C gs-2 ) / (C gs-2 + C AA ) equation (4)

[0105] Wherein, ΔV g = V gh – V gl , V p MUX is V p of the thin film transistor 107 before being turned off, V′ pMUX is V p of the thin film transistor 107 after being turned off, and C AA is the capacitance of the data line 103.

[0106] When the loads of the data lines are different, the C AA of the data lines are different, and from equation (4), the different C AA of the data lines leads to different ΔV p MUX .

[0107] Further, the calculation of the voltage jump value of the second data line according to the width-length ratio of the channel region of the second thin film transistor and the load of the second data line comprises:

[0108] determining the gate-source coupling capacitance of the second thin film transistor according to the width-length ratio of the channel region of the second thin film transistor, and calculating the voltage jump value of the second data line according to the gate-source coupling capacitance and the load of the second data line.

[0109] From the foregoing, the capacitance value C gs-2 of the second gate-source coupling capacitance 107-4 can be determined through the width-length ratio of the channel region of the thin film transistor 107, the capacitance C AA of the data line 103 can be determined according to the load of the data line 103, and the jump value ΔV p MUX of the data line voltage can be obtained by substituting equation (4). Correspondingly, when the thin film transistor 107 is the second thin film transistor 1072, the capacitance value C gs-2 of the second gate-source coupling capacitance 107-4 can be determined according to the width-length ratio of the channel region of the second thin film transistor 1072, and the capacitance CAA The voltage jump value AV of the second data line 1032 can be calculated by formula (4) p MUX According to the voltage jump value AV of the second data line 1032 p MUX And the load of the first data line 1031, the width-length ratio of the channel region of the first thin film transistor 1071 is calculated by the simulation model, and the area of the first switch unit 1051 is determined.

[0110] In addition to calculating the area of each first switch unit according to the method of the foregoing embodiments, the area of each first switch unit can also be calculated by the method of the following embodiments.

[0111] In some embodiments, the number of the first data lines is multiple; Figure 10 A flowchart of the calculation method of the area of the first switch unit is shown, as shown in Figure 10 According to the area of the second switch unit, the load of the second data line, and the load of the first data line, the area of the first switch unit is calculated, including the following steps:

[0112] Step 1002, determining the width-length ratio of the channel region of the second thin film transistor according to the area of the second switch unit.

[0113] When the area of the second switch unit 1052 is determined, the width-length ratio of the channel region of the second thin film transistor 1072 can be further determined according to the simulation model.

[0114] Step 1004, calculating the voltage jump value of the second data line according to the width-length ratio of the channel region of the second thin film transistor and the load of the second data line.

[0115] As known from the foregoing embodiments, the capacitance value Cgs of the second gate-source coupling capacitor 107-4 can be determined by the width-length ratio of the channel region of the second thin film transistor 1072 gs-2 The capacitance C of the second data line 1032 can be determined according to the load of the second data line 1032 AA The voltage jump value AV of the second data line can be obtained by formula (4) p MUX .

[0116] Step 1006, taking the first data line with the minimum load among all the first data lines as a third data line, taking the first thin film transistor electrically connected with the third data line as a third thin film transistor, and calculating the width-length ratio of the channel region of the third thin film transistor according to the voltage jump value of the second data line and the load of the third data line.

[0117] The data line with the smallest load among all the first data lines is designated as the third data line, and the first thin-film transistor electrically connected to the third data line is designated as the third thin-film transistor. For example, as... Figure 5 As shown, the third data line includes the data line corresponding to the first switching unit. Based on the simulation model, the voltage jump value ΔV of the second data line 1032... p MUX Based on the load of the third data line, the aspect ratio of the channel region of the third thin-film transistor can be calculated.

[0118] Step 1008: Determine the unit width-to-length ratio change based on the load of the second data line, the load of the third data line, the width-to-length ratio of the channel region of the second thin-film transistor, and the width-to-length ratio of the channel region of the third thin-film transistor.

[0119] Furthermore, step 1008 includes:

[0120] A first difference is determined between the width-to-length ratio of the channel region of the second thin-film transistor and the width-to-length ratio of the channel region of the third thin-film transistor; a second difference is determined between the load of the second data line and the load of the third data line; the ratio of the first difference to the second difference is used as the unit width-to-length ratio change.

[0121] Unit width-to-length ratio change ΔMUX Size Determined by the following formula (5):

[0122] ΔMUX Size =(MUX SizeCV -MUX Sizemin ) / (C AACV -C AAmin Equation (5)

[0123] Among them, MUX SizeCV MUX represents the aspect ratio of the channel region of the second thin-film transistor 1072. Sizemin This represents the aspect ratio of the channel region of the third thin-film transistor, (MUX) SizeCV -MUX Sizemin ) indicates the first difference. C AACV This indicates the capacitor of the second data line 1032, through C. AACV Indicates the load of the second data line 1032, C AAmin This indicates the capacitance of the third data line, via C. AAmin Indicates the load of the third data line, (C AACV -C AAmin The first difference is represented by ΔMUX, which is the ratio of the first difference to the second difference. Size .

[0124] When the unit width-length ratio variation ΔMUX Size Then, the width-length ratio of the channel region of any one of the first thin film transistors can be determined, which includes two methods, described by steps 10010a and 10010b respectively.

[0125] For each of the other first data lines except the third data line,

[0126] Step 10010a, according to the width-length ratio of the channel region of the third thin film transistor, the unit width-length ratio variation, the load of the third data line and the load of the first data line, determines the width-length ratio of the channel region of the first thin film transistor electrically connected with the first data line.

[0127] Further, step 10010a includes:

[0128] determining a first ratio between the load of the first data line and the load of the third data line;

[0129] taking the product of the first ratio and the unit width-length ratio variation as a target width-length ratio increment;

[0130] taking the sum of the width-length ratio of the channel region of the third thin film transistor and the target width-length ratio increment as the width-length ratio of the channel region of the first thin film transistor.

[0131] Specifically, a first ratio between the load of the first data line 1031 and the load of the third data line is determined, and when the load is represented by capacitance, a first ratio between the capacitance of the first data line 1031 and the capacitance of the third data line is determined. The product of the first ratio and the unit width-length ratio variation is taken as a target width-length ratio increment. When calculating the width-length ratio of the channel region of the first thin film transistor, since the width-length ratio of the channel region of the third thin film transistor is the minimum value of the channel region width-length ratio, the target width-length ratio increment is added to the width-length ratio of the channel region of the third thin film transistor, and the target width-length ratio increment is taken as a compensation value to obtain the width-length ratio of the channel region of the first thin film transistor.

[0132] Alternatively, step 10010b, according to the width-length ratio of the channel region of the second thin film transistor, the unit width-length ratio variation, the load of the second data line and the load of the first data line, determines the width-length ratio of the channel region of the first thin film transistor electrically connected with the first data line.

[0133] Further, step 10010b includes:

[0134] determining a second ratio between the load of the second data line and the load of the first data line;

[0135] The product of the second ratio and the unit width-length ratio change amount is taken as a target width-length ratio increment.

[0136] The difference between the width-length ratio of the channel region of the second thin film transistor and the target width-length ratio increment is taken as the width-length ratio of the channel region of the first thin film transistor.

[0137] Specifically, a second ratio between the load of the second data line 1032 and the load of the third data line is determined, that is, a second ratio between the capacitance of the second data line 1032 and the capacitance of the third data line is determined. The product of the second ratio and the unit width-length ratio change amount is taken as a target width-length ratio increment. When calculating the width-length ratio of the channel region of the first thin film transistor, the width-length ratio of the channel region of the second thin film transistor is the maximum width-length ratio of the channel region, and the target width-length ratio increment is reduced on the basis of the width-length ratio of the channel region of the second thin film transistor, that is, the difference between the width-length ratio of the channel region of the second thin film transistor and the target width-length ratio increment is taken as the width-length ratio of the channel region of the first thin film transistor.

[0138] Step 10012: determining the area of the first switch unit according to the width-length ratio of the channel region of the first thin film transistor.

[0139] After the width-length ratio of the channel region of the first thin film transistor 1071 is determined, the area of the first switch unit 1051 can be determined according to the simulation model.

[0140] Through the method of the embodiment, after the unit width-length ratio change amount is determined, the area of each first switch unit can be determined according to the width-length ratio of the channel region of the third thin film transistor and the load of the third data line, or according to the width-length ratio of the channel region of the second thin film transistor and the load of the second data line, so as to achieve the purpose of flexibly and quickly determining the area of the first switch unit.

[0141] It should be noted that the method of the embodiment of the present application can be executed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scenario and completed by multiple devices in cooperation. In this distributed scenario, one of the multiple devices can only execute one or more steps in the method of the embodiment of the present application, and the multiple devices can interact with each other to complete the method.

[0142] It is to be understood that the foregoing description is directed to embodiments of the application. Various embodiments are described herein, including the best mode of the inventors. It will be apparent, however, to those skilled in the art having the benefit of this disclosure, that variations and / or modifications of these embodiments can be made without departing from the spirit and scope of the application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0143] Based on the same inventive concept, the application further provides a preparation device of an array substrate corresponding to the method of any of the above embodiments.

[0144] With reference to Figure 11 , the preparation device of the array substrate comprises:

[0145] A determination module 1102 is configured to determine an area of the second switch unit, a load of the first data line, and a load of the second data line.

[0146] A calculation module 1104 is configured to calculate the area of the first switch unit according to the area of the second switch unit, the load of the second data line, and the load of the first data line.

[0147] In some embodiments, the first switch unit comprises a first thin film transistor, and the second switch unit comprises a second thin film transistor; the calculation module 1104 is further configured to determine a width-length ratio of a channel region of the second thin film transistor according to the area of the second switch unit; calculate a voltage jump value of the second data line according to the width-length ratio of the channel region of the second thin film transistor and the load of the second data line; calculate a width-length ratio of a channel region of the first thin film transistor according to the voltage jump value of the second data line and the load of the first data line; and determine the area of the first switch unit according to the width-length ratio of the channel region of the first thin film transistor.

[0148] In some embodiments, the calculation module 1104 is further configured to determine a gate-source coupling capacitance of the second thin film transistor according to the width-length ratio of the channel region of the second thin film transistor; and calculate a voltage jump value of the second data line according to the gate-source coupling capacitance and the load of the second data line.

[0149] In some embodiments, the number of the first data lines is multiple; the computing module 1104 is further configured to determine a width-length ratio of a channel region of the second thin film transistor according to an area of the second switch unit; calculate a voltage jump value of the second data line according to the width-length ratio of the channel region of the second thin film transistor and a load of the second data line; take a first data line with the smallest load among all the first data lines as a third data line, take a first thin film transistor electrically connected with the third data line as a third thin film transistor, and calculate a width-length ratio of a channel region of the third thin film transistor according to the voltage jump value of the second data line and the load of the third data line; determine a unit width-length ratio change amount according to the load of the second data line, the load of the third data line, the width-length ratio of the channel region of the second thin film transistor and the width-length ratio of the channel region of the third thin film transistor; for each first data line other than the third data line, determine the width-length ratio of the channel region of the first thin film transistor electrically connected with the first data line according to the width-length ratio of the channel region of the third thin film transistor, the unit width-length ratio change amount, the load of the third data line and the load of the first data line; or, determine the width-length ratio of the channel region of the first thin film transistor electrically connected with the first data line according to the width-length ratio of the channel region of the second thin film transistor, the unit width-length ratio change amount, the load of the second data line and the load of the first data line; and determine the area of the first switch unit according to the width-length ratio of the channel region of the first thin film transistor.

[0150] In some embodiments, the computing module 1104 is further configured to determine a first difference value between the width-length ratio of the channel region of the second thin film transistor and the width-length ratio of the channel region of the third thin film transistor; determine a second difference value between the load of the second data line and the load of the third data line; and take a ratio of the first difference value to the second difference value as the unit width-length ratio change amount.

[0151] In some embodiments, the computing module 1104 is further configured to determine a first ratio value between the load of the first data line and the load of the third data line; take a product of the first ratio value and the unit width-length ratio change amount as a target width-length ratio increment; and take a sum of the width-length ratio of the channel region of the third thin film transistor and the target width-length ratio increment as the width-length ratio of the channel region of the first thin film transistor.

[0152] In some embodiments, the computing module 1104 is further configured to determine a second ratio between the load of the second data line and the load of the first data line; take a product of the second ratio and the unit width-length ratio variation as a target width-length ratio increment; and take a difference between the width-length ratio of the channel region of the second thin film transistor and the target width-length ratio increment as the width-length ratio of the channel region of the first thin film transistor.

[0153] For the convenience of description, the above apparatus is described in various modules in terms of functions. Of course, the functions of the modules can be implemented in one or more software and / or hardware in the implementation of the present application.

[0154] The apparatus of the above embodiments is used to implement the corresponding determination module in any of the preceding embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be described here.

[0155] Based on the same inventive concept, the present application also provides an electronic device corresponding to the method of any of the above embodiments, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the determination module of any of the above embodiments when executing the program, and is configured to determine the area of the second switch unit, the load of the first data line, and the load of the second data line.

[0156] A computing module is configured to calculate the area of the first switch unit according to the area of the second switch unit, the load of the second data line, and the load of the first data line.

[0157] Figure 12 A more specific hardware structure of an electronic device provided by the present embodiment is shown, which can include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 for communication within the device.

[0158] The processor 1010 can be implemented in the form of a general-purpose CPU (Central Processing Unit), a microprocessor, an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits, etc., for executing related programs to implement the technical solutions provided by the present embodiment.

[0159] The memory 1020 can be implemented in the form of a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, etc. The memory 1020 can store an operating system and other application programs, and when the technical solutions provided by the embodiments of the present specification are implemented by software or firmware, the related program codes are stored in the memory 1020 and are called and executed by the processor 1010.

[0160] The input / output interface 1030 is configured to connect an input / output module to realize information input and output. The input / output module can be configured as a component in the device (not shown in the figure) or can be externally connected to the device to provide corresponding functions. The input device can include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device can include a display, a speaker, a vibrator, an indicator light, etc.

[0161] The communication interface 1040 is configured to connect a communication module (not shown in the figure) to realize the communication interaction between the device and other devices. The communication module can realize communication through a wired manner (such as USB, network cable, etc.) or through a wireless manner (such as mobile network, WIFI, Bluetooth, etc.).

[0162] The bus 1050 includes a channel for transmitting information between various components (such as the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040) of the device.

[0163] It should be noted that although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040, and the bus 1050, in the specific implementation process, the device can also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above device can also only contain the components necessary to implement the embodiments of the present specification, and does not have to contain all the components shown in the figure.

[0164] The electronic device of the above embodiment is used to implement the preparation method of the array substrate in any of the preceding embodiments, and has the beneficial effects of the corresponding method embodiments, which are not described here.

[0165] Based on the same inventive concept, the present application also provides a non-transitory computer readable storage medium storing computer instructions for causing the computer to execute the preparation method of the array substrate as described in any of the above embodiments.

[0166] The computer readable medium of the embodiments can include permanent and non-permanent, removable and non-removable media, which can be implemented by any method or technology to store information. The information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device.

[0167] The storage medium of the above embodiments stores computer instructions for causing the computer to perform the preparation method of the array substrate as described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which are not repeated here.

[0168] Based on the same concept, corresponding to the method of any of the above embodiments, the present application also provides a computer program product comprising computer program instructions, which, when executed on a computer, cause the computer to perform the method as described in any of the above embodiments, with the beneficial effects of the corresponding method embodiments, which are not repeated here.

[0169] Those skilled in the art should understand that the above discussion of any of the embodiments is only exemplary and is not intended to imply that the scope of the present application (including claims) is limited to these examples; the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of the different aspects of the embodiments of the present application as described above. In order to be brief, they are not provided in detail.

[0170] Additionally, to simplify the description and discussion, and so as not to obscure the embodiments of the application being presented, the well-known functions or constructions of integrated circuit (IC) chips and other components can or can not be shown in the figures and will be omitted as not to unnecessarily obscure the embodiments of the application being presented. Moreover, the devices can be shown in block diagram form in order to avoid obscuring the embodiments of the application, and this also acknowledges the fact that the details in regard to the implementation of the block diagram devices are highly dependent on the platform within which the embodiments of the application are to be implemented (i.e., these details should be well within the purview of one of ordinary skill in the art). Where specific details are set forth in order to describe an illustrative embodiment of the application, it will be apparent to one of ordinary skill in the art that the embodiments of the application can be practiced without, or with variation of, these specific details. Thus, the description is to be considered as illustrative only and not restrictive in nature.

[0171] While the application has been described in connection with specific embodiments thereof, it will be understood that many modifications, substitutions and changes will be apparent to those of ordinary skill in the art once they have the benefit of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) can use the embodiments discussed.

[0172] It is intended that the embodiments of the application encompass all such substitutions, modifications and variations as fall within the scope of the appended claims. Accordingly, any omission, modification, equivalent replacement, improvement, etc. made in the spirit and principle of the embodiments of the application should be included in the scope of protection of the application.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate substrate, and a plurality of gate lines and a plurality of data lines arranged in a cross manner on the substrate substrate, the plurality of data lines comprising a first data line and a second data line, the load of the first data line being less than the load of the second data line; a driving circuit on the substrate substrate, comprising a plurality of switching units and a data driving unit; the plurality of switching units comprising a first switching unit and a second switching unit; the first data line is electrically connected with the data driving unit through the first switching unit, and the second data line is electrically connected with the data driving unit through the second switching unit; the area of the orthographic projection of the first switching unit on the substrate substrate is less than the area of the orthographic projection of the second switching unit on the substrate substrate, so that the voltage jump value of the first data line is less than or equal to the voltage jump value of the second data line.

2. The array substrate of claim 1, wherein, The first switching unit comprises a first thin film transistor, and the second switching unit comprises a second thin film transistor, wherein the width-length ratio of the channel region of the first thin film transistor is less than the width-length ratio of the channel region of the second thin film transistor.

3. The array substrate of claim 2, wherein, The source of the first thin film transistor is electrically connected with the first data line, the drain of the first thin film transistor is electrically connected with the data driving unit, and the width-length ratio of the channel region of the first thin film transistor is positively correlated with the load of the first data line.

4. The array substrate according to any one of claims 1 to 3, wherein, The first switching unit and the second switching unit are multiplexers.

5. A display substrate, characterized by, The array substrate as claimed in any one of claims 1-4.

6. A method for manufacturing an array substrate, applied to the array substrate according to any one of claims 1 to 4, characterized in that, The method comprises: determining the area of the second switching unit, the load of the first data line and the load of the second data line; calculating the area of the first switching unit according to the area of the second switching unit, the load of the second data line and the load of the first data line.

7. The method of claim 6, wherein, The first switching unit comprises a first thin film transistor, and the second switching unit comprises a second thin film transistor; the calculation of the area of the first switching unit according to the area of the second switching unit, the load of the second data line and the load of the first data line comprises: determining the width-length ratio of the channel region of the second thin film transistor according to the area of the second switching unit; calculating the voltage jump value of the second data line according to the width-length ratio of the channel region of the second thin film transistor and the load of the second data line; calculating the width-length ratio of the channel region of the first thin film transistor according to the voltage jump value of the second data line and the load of the first data line; determining the area of the first switching unit according to the width-length ratio of the channel region of the first thin film transistor.

8. The method of claim 7, wherein, The calculation of the voltage jump value of the second data line according to the width-length ratio of the channel region of the second thin film transistor and the load of the second data line comprises: determining the gate-source coupling capacitance of the second thin film transistor according to the width-length ratio of the channel region of the second thin film transistor; calculating the voltage jump value of the second data line according to the gate-source coupling capacitance and the load of the second data line.

9. The method of claim 6, wherein, The number of the first data lines is multiple; the area of the first switch unit is calculated according to the area of the second switch unit, the load of the second data line and the load of the first data line, comprising: determining the width-length ratio of the channel region of the second thin film transistor according to the area of the second switch unit; calculating the voltage jump value of the second data line according to the width-length ratio of the channel region of the second thin film transistor and the load of the second data line; taking the first data line with the minimum load among all the first data lines as the third data line, taking the first thin film transistor electrically connected with the third data line as the third thin film transistor, and calculating the width-length ratio of the channel region of the third thin film transistor according to the voltage jump value of the second data line and the load of the third data line; determining the unit width-length ratio variation according to the load of the second data line, the load of the third data line, the width-length ratio of the channel region of the second thin film transistor and the width-length ratio of the channel region of the third thin film transistor; for each first data line other than the third data line, determining the width-length ratio of the channel region of the first thin film transistor electrically connected with the first data line according to the width-length ratio of the channel region of the third thin film transistor, the unit width-length ratio variation, the load of the third data line and the load of the first data line; or determining the width-length ratio of the channel region of the first thin film transistor electrically connected with the first data line according to the width-length ratio of the channel region of the second thin film transistor, the unit width-length ratio variation, the load of the second data line and the load of the first data line; determining the area of the first switch unit according to the width-length ratio of the channel region of the first thin film transistor.

10. The method of claim 9, wherein, The determination of the unit width-length ratio variation according to the load of the second data line, the load of the third data line, the width-length ratio of the channel region of the second thin film transistor and the width-length ratio of the channel region of the third thin film transistor, comprising: determining a first difference value between the width-length ratio of the channel region of the second thin film transistor and the width-length ratio of the channel region of the third thin film transistor; determining a second difference value between the load of the second data line and the load of the third data line; taking the ratio of the first difference value to the second difference value as the unit width-length ratio variation.

11. The method of claim 9, wherein, The determination of the width-length ratio of the channel region of the first thin film transistor electrically connected with the first data line according to the width-length ratio of the channel region of the third thin film transistor, the unit width-length ratio variation, the load of the third data line and the load of the first data line, comprising: determining a first ratio value between the load of the first data line and the load of the third data line; taking the product of the first ratio value and the unit width-length ratio variation as a target width-length ratio increment; taking the sum of the width-length ratio of the channel region of the third thin film transistor and the target width-length ratio increment as the width-length ratio of the channel region of the first thin film transistor.

12. The method of claim 9, wherein, The method comprises: determining a second ratio between the load of the second data line and the load of the first data line; multiplying the second ratio by the unit width-length ratio variation to obtain a target width-length ratio increment; determining a width-length ratio of a channel region of the first thin film transistor by subtracting the target width-length ratio increment from the width-length ratio of the channel region of the second thin film transistor.

13. An apparatus for manufacturing an array substrate, applied to the array substrate according to any one of claims 1 to 4, characterized in that, The device comprises: a determining module configured to determine an area of the second switch unit, a load of the first data line, and a load of the second data line; a calculating module configured to calculate the area of the first switch unit according to the area of the second switch unit, the load of the second data line, and the load of the first data line.

14. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor implements the method of any one of claims 6 to 12 when executing the program.

15. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to make the computer execute the method of any one of claims 6 to 12.

16. A computer program product comprising computer program instructions, characterised in that, The computer program instructions, when running on the computer, make the computer execute the method of any one of claims 6 to 12.

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