High-frequency high-PSRR LDO circuit based on current sampling feedback
The LDO circuit with current sampling feedback structure solves the problem of poor PSRR performance of traditional LDOs in the high-frequency range, and achieves improved high-frequency PSRR and enhanced circuit stability.
Patent Information
- Application Number
- CN202511647961.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-11
- Publication Date
- 2026-01-23
AI Technical Summary
Traditional LDO circuits have poor power supply rejection ratio (PSRR) performance at high frequencies. Existing technologies for improvement are complex, have large areas, high power consumption, and are difficult to compensate for frequency.
A current sampling feedback structure is adopted, which forms a series negative feedback structure through a circuit composed of first and second transconductance operational amplifiers, IV conversion circuit, power transistor and mirror power transistor, thereby improving the high-frequency PSRR.
It significantly improves high-frequency PSRR performance, reduces circuit area and power consumption, increases loop bandwidth, and improves circuit stability.
Smart Images
Figure CN121387005A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and in particular to a high-frequency high-PSRR LDO circuit based on current sampling feedback. BACKGROUND
[0002] With the continuous improvement of chip working frequency under advanced process and the increasing sensitivity requirement of digital-analog hybrid circuit to power supply noise, the power supply rejection ratio (PSRR) performance of low-dropout linear regulator (LDO) at high frequency becomes crucial. A low-dropout linear regulator with wideband high power supply rejection ratio, low power consumption and small area becomes a key module in designing high-precision analog circuits and is widely used after a switching power supply to filter out high-frequency noise and provide a voltage almost independent of input voltage and load fluctuation for the subsequent load.
[0003] The basic structure of a traditional LDO includes an error amplifier, a feedback network and a power tube. The LDO amplifies the difference between the feedback voltage and the reference voltage through the error amplifier, dynamically adjusts the gate voltage of the power tube, controls the conduction degree of the power tube, and thus keeps the output voltage stable. However, the PSRR of the LDO with the traditional structure is limited by the loop bandwidth of the error amplifier, which will drop to the lowest point when the frequency reaches the loop unity gain bandwidth, resulting in poor PSRR performance of the LDO at high frequency. The prior art usually adopts technologies such as extended loop bandwidth, feedforward ripple elimination and series low-pass filter to improve this drawback.
[0004] In the prior art, the extended loop bandwidth technology usually uses a wideband amplifier to improve the high-frequency PSRR, but this technology has the problems of difficult frequency compensation and easy loop instability; the feedforward ripple elimination technology suppresses the generation of ripples by feeding the power supply ripples to the gate of the power tube through an adder, but the high-frequency PSRR is limited by the bandwidth of the adder, the improvement range is limited, and the circuit complexity is high and the power consumption is large; the series low-pass filter technology occupies a large chip area and introduces additional chip pins in order to achieve low cutoff frequency filtering. SUMMARY
[0005] The present application aims to provide a high-frequency high-PSRR LDO circuit based on current sampling feedback, which uses a current sampling feedback structure to increase the PSRR of the LDO at high frequency, to solve the problems of complex circuit structure, large area, high power consumption and limited improvement of high-frequency PSRR in the prior art.
[0006] To achieve the above-mentioned purpose, the present application adopts the following technical solutions: A high-frequency high-PSRR LDO circuit based on current sampling feedback, comprising a first transconductance operational amplifier, a second transconductance operational amplifier, an I-V conversion circuit, a power tube, a mirror power tube, a sampling resistor RS, a resistor feedback network and a load end. The output end of the first transconductance operational amplifier is connected to the I-V conversion circuit, the first transconductance operational amplifier comprises two input ends, the first input end is connected to a reference voltage VREF, and the second input end is connected to a feedback voltage, so as to amplify the difference between the reference voltage VREF and the feedback voltage and output a current; The output end of the second transconductance operational amplifier is connected to the I-V conversion circuit, the second transconductance operational amplifier comprises two input ends, the first input end is connected to the first end of the sampling resistor RS, and the second input end is connected to the second end of the sampling resistor RS, so as to amplify the voltage difference between the two ends of the sampling resistor RS and output a current; The output end of the I-V conversion circuit is connected to the power tube and the mirror power tube, so as to convert the current output by the first transconductance operational amplifier and the second transconductance operational amplifier into a voltage signal, to control the conduction degree of the power tube and the mirror power tube; The power tube is connected to the output end of the I-V conversion circuit and the load end; The mirror power tube is connected to the sampling resistor RS, for proportionally sampling the output current of the power tube; The sampling resistor RS is used for converting the output current proportionally sampled by the mirror power tube into a voltage, and inputting the voltage into the two input ends of the second transconductance operational amplifier; The resistor feedback network is used for feeding back the feedback voltage obtained by resistively dividing the output voltage VOUT to the second input end of the first transconductance operational amplifier; The load end is connected to the power tube, for filtering the noise of the output voltage VOUT.
[0007] As a further scheme of the present application, the first transconductance operational amplifier comprises a PMOS tube MP9, a PMOS tube MP10 and a PMOS tube MP11; The source level of the PMOS tube MP9 is connected to a power supply voltage VDD, the drain of the PMOS tube MP9 is connected to the source level of the PMOS tube MP10 and the source level of the PMOS tube MP11, the gate of the PMOS tube MP9 is connected to the gate of the PMOS tube MP1, the gate of the PMOS tube MP2, the gate of the PMOS tube MP3, the gate of the PMOS tube MP4 and the gate of the PMOS tube MP12; the gate of the PMOS tube MP10 is connected to a reference voltage VREF, the drain of the PMOS tube MP10 is connected to the source level of the NMOS tube MN7 and the drain of the NMOS tube MN9; the gate of the PMOS tube MP11 is connected to the second end of the feedback resistor RF1 and the first end of the feedback resistor RF2, and the drain of the PMOS tube MP11 is connected to the source level of the NMOS tube MN8 and the drain of the NMOS tube MN10.
[0008] As a further scheme of the present application: the second transconductance operational amplifier comprises NMOS tube MN1, NMOS tube MN2, NMOS tube MN3, NMOS tube MN4, NMOS tube MN5, PMOS tube MP1, PMOS tube MP2, PMOS tube MP3, PMOS tube MP4, bias current source Ibias, resistance R1, capacitor C1; The gate of the NMOS tube MN1 is connected to the first end of the sampling resistance RS, the drain of the NMOS tube MN1 is connected to the drain of the PMOS tube MP3, the source of the NMOS tube MN1 is connected to the first end of the resistance R1 and the first end of the capacitor C1 and the drain of the NMOS tube MN4; the gate of the NMOS tube MN2 is connected to the second end of the sampling resistance RS, the drain of the NMOS tube MN2 is connected to the drain of the PMOS tube MP4, the source of the NMOS tube MN2 is connected to the second end of the resistance R1 and the second end of the capacitor C1 and the drain of the NMOS tube MN5; the gate of the NMOS tube MN4 is connected to the gate of the NMOS tube MN5 and the gate of the NMOS tube MN3 and the gate of the NMOS tube MN6, the source of the NMOS tube MN4 is connected to the source of the NMOS tube MN5 and grounded; the source of the NMOS tube MN3 is grounded, the drain of the NMOS tube MN3 is connected to the drain of the PMOS tube MP2; the gate of the PMOS tube MP3 is connected to the gate of the PMOS tube MP4 and the gate of the PMOS tube MP1 and the gate of the PMOS tube MP2 and the gate of the PMOS tube MP9 and the gate of the PMOS tube MP12, the source of the PMOS tube MP3 is connected to the power supply VDD; the source of the PMOS tube MP1 is connected to the source of the PMOS tube MP2 and the power supply voltage VDD, the drain of the PMOS tube MP1 is connected to the first end of the bias current source Ibias; the second end of the bias current source Ibias is grounded; the source of the PMOS tube MP4 is connected to the power supply VDD.
[0009] As a further scheme of the present application: the I-V conversion circuit comprises NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, resistance R2, PMOS tube MP5, PMOS tube MP6, PMOS tube MP8; The drain of the NMOS tube MN6 is connected with the gate of the PMOS tube MP5, the drain of the PMOS tube MP5 and the gate of the PMOS tube MP6 and the gate of the PMOS tube MP8, the source of the NMOS tube MN6 is grounded; the gate of the NMOS tube MN7 is connected with the gate of the NMOS tube MN8 and the first end of the resistor R2, the drain of the NMOS tube MN7 is connected with the second end of the resistor R2 and the gate of the NMOS tube MN9 and the gate of the NMOS tube MN10; the drain of the NMOS tube MN8 is connected with the drain of the PMOS tube MP8 and the gate of the NMOS tube MN11; the source of the NMOS tube MN9 is connected with the source of the NMOS tube MN10 and grounded; the source of the PMOS tube MP6 is connected with the drain of the NMOS tube MN1; the source of the PMOS tube MP8 is connected with the drain of the NMOS tube MN2; the source of the PMOS tube MP5 is connected with the power voltage VDD.
[0010] As a further scheme of the application: the power tube is the PMOS tube MP14; the mirror power tube is the PMOS tube MP13; the gate of the power tube PMOS tube MP14 is connected with the gate of the mirror power tube PMOS tube MP13 and the drain of the NMOS tube MN11 and the drain of the PMOS tube MP12, the source of the power tube PMOS tube MP14 is connected with the first end of the sampling resistor RS and the power voltage VDD, the drain of the power tube PMOS tube MP14 is connected with the drain of the mirror power tube PMOS tube MP13 and the second end of the resistor R3 and the first end of the resistor R4 and the first end of the feedback resistor RF1 and the first end of the resistor Resr and the first end of the load resistor RL and outputs the voltage VOUT; the first end of the resistor R3 is connected with the gate and the drain of the PMOS tube MP7; the source of the PMOS tube MP7 is connected with the source of the PMOS tube MP12 and the power voltage VDD; the second end of the resistor R4 is connected with the first end of the capacitor C2; the second end of the capacitor C2 is grounded; the source of the NMOS tube MN11 is grounded; the source of the mirror power tube PMOS tube MP13 is connected with the second end of the sampling resistor RS.
[0011] As a further scheme of the application: the feedback resistor network comprises the feedback resistor RF1 and the feedback resistor RF2; the load end comprises the resistor Resr, the load capacitor CL and the load resistor RL; the first end of the feedback resistor RF1 is connected with the first end of the resistor Resr and the first end of the load resistor RL, the second end of the feedback resistor RF1 is connected with the first end of the feedback resistor RF2 and the gate of the PMOS tube MP11; the second end of the feedback resistor RF2 is grounded; the second end of the resistor Resr is connected with the first end of the load capacitor CL; the second end of the load capacitor CL is grounded; the second end of the load resistor is grounded.
[0012] Compared with the prior art, the present application has the beneficial effects of: 1、In the present application, by current sampling feedback, the sampling voltage across the sampling resistor RS is fed back to the gate of the power tube after being amplified by the second transconductance operational amplifier, forming a series negative feedback structure, which improves the equivalent impedance from the power supply to the output, thereby significantly improving the high-frequency PSRR. 2、In the present application, the current sampling feedback is embedded in the voltage feedback network, which can increase the loop bandwidth, reduce the difficulty of frequency compensation, and improve the stability of the circuit. BRIEF DESCRIPTION OF DRAWINGS
[0013] Figure 1 FIG. 1 is a structural schematic diagram of a high-frequency high-PSRR LDO circuit based on current sampling feedback according to the present application. Figure 2 FIG. 2 is a circuit diagram of a high-frequency high-PSRR LDO circuit based on current sampling feedback according to the present application. Figure 3 FIG. 3 is a PSRR simulation waveform diagram of a high-frequency high-PSRR LDO circuit based on current sampling feedback according to the present application.
[0014] REFERENCE NUMERALS 1, first transconductance operational amplifier; 2, I-V conversion circuit; 3, power tube; 4, second transconductance operational amplifier; 5, mirror power tube; 6, sampling resistor RS; 7, feedback resistor network; 8, load end. DETAILED DESCRIPTION
[0015] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all. EMBODIMENT
[0016] Please refer to Figure 1 , Figure 1A structure schematic diagram of a high-frequency high-PSRR LDO circuit based on current sampling feedback is provided in the present application. In the embodiment of the present application, a high-frequency high-PSRR LDO circuit based on current sampling feedback comprises a first transconductance operational amplifier 1, an I-V conversion circuit 2, a power tube 3, a second transconductance operational amplifier 4, a mirror power tube 5, a sampling resistor RS (labeled as 6), a resistor feedback network 7, and a load end 8. The output end of the first transconductance operational amplifier 1 is connected to the I-V conversion circuit 2. The first transconductance operational amplifier 1 comprises two input ends, a first input end connected to a reference voltage VREF and a second input end connected to a feedback voltage, for amplifying the difference between the reference voltage VREF and the feedback voltage and outputting a current. The output end of the second transconductance operational amplifier 4 is connected to the I-V conversion circuit 2. The second transconductance operational amplifier 4 comprises two input ends, a first input end connected to a first end of the sampling resistor RS (labeled as 6) and a second input end connected to a second end of the sampling resistor RS (labeled as 6), for amplifying the voltage difference between the two ends of the sampling resistor RS (labeled as 6) and outputting a current. The output end of the I-V conversion circuit 2 is connected to the power tube 3 and the mirror power tube 5, for converting the currents outputted by the first transconductance operational amplifier 1 and the second transconductance operational amplifier 4 into voltage signals to control the conduction degree of the power tube 3 and the mirror power tube 5. The power tube 3 is connected to the output end of the I-V conversion circuit 2 and the load end 8. The mirror power tube 5 is connected to the sampling resistor RS (labeled as 6), for proportionally sampling the output current of the power tube 3. The sampling resistor RS (labeled as 6) is used to convert the output current proportionally sampled by the mirror power tube 5 into a voltage and input the voltage to the two input ends of the second transconductance operational amplifier 4. The resistor feedback network 7 is used to feed back the feedback voltage obtained by resistively dividing the output voltage VOUT to the second input end of the first transconductance operational amplifier 1. The load end 8 is connected to the power tube 3, for filtering the noise of the output voltage VOUT.
[0017] Please refer to Figure 2 , Figure 2A circuit diagram of the high-frequency high-PSRR LDO circuit based on current sampling feedback according to the application. In the embodiment of the application, the first transconductance operational amplifier 1 comprises a PMOS tube MP9, a PMOS tube MP10 and a PMOS tube MP11. The source of the PMOS tube MP9 is connected to a power supply voltage VDD, the drain of the PMOS tube MP9 is connected to the source of the PMOS tube MP10 and the source of the PMOS tube MP11, the gate of the PMOS tube MP9 is connected to the gate of the PMOS tube MP1, the gate of the PMOS tube MP2, the gate of the PMOS tube MP3, the gate of the PMOS tube MP4 and the gate of the PMOS tube MP12; the gate of the PMOS tube MP10 is connected to a reference voltage VREF, the drain of the PMOS tube MP10 is connected to the source of an NMOS tube MN7 and the drain of an NMOS tube MN9; the gate of the PMOS tube MP11 is connected to the second end of a feedback resistor RF1 and the first end of a feedback resistor RF2, the drain of the PMOS tube MP11 is connected to the source of an NMOS tube MN8 and the drain of an NMOS tube MN10.
[0018] Preferably, the width-length ratio of the PMOS tube MP10 is equal to the width-length ratio of the PMOS tube MP11.
[0019] As Figure 2As shown, in the present example, the second transconductance operational amplifier comprises NMOS transistor MN1, NMOS transistor MN2, NMOS transistor MN3, NMOS transistor MN4, NMOS transistor MN5, PMOS transistor MP1, PMOS transistor MP2, PMOS transistor MP3, PMOS transistor MP4, bias current source Ibias, resistor R1, capacitor C1. The gate of the NMOS transistor MN1 is connected to the first end of the sampling resistor RS, the drain of the NMOS transistor MN1 is connected to the drain of the PMOS transistor MP3, the source of the NMOS transistor MN1 is connected to the first end of the resistor R1 and the first end of the capacitor C1 and the drain of the NMOS transistor MN4; the gate of the NMOS transistor MN2 is connected to the second end of the sampling resistor RS, the drain of the NMOS transistor MN2 is connected to the drain of the PMOS transistor MP4, the source of the NMOS transistor MN2 is connected to the second end of the resistor R1 and the second end of the capacitor C1 and the drain of the NMOS transistor MN5; the gate of the NMOS transistor MN4 is connected to the gate of the NMOS transistor MN5 and the gate of the NMOS transistor MN3 and the gate of the NMOS transistor MN6, the source of the NMOS transistor MN4 is connected to the source of the NMOS transistor MN5 and grounded; the source of the NMOS transistor MN3 is grounded, the drain of the NMOS transistor MN3 is connected to the drain of the PMOS transistor MP2; the gate of the PMOS transistor MP3 is connected to the gate of the PMOS transistor MP4 and the gate of the PMOS transistor MP1 and the gate of the PMOS transistor MP2 and the gate of the PMOS transistor MP9 and the gate of the PMOS transistor MP12, the source of the PMOS transistor MP3 is connected to the power supply VDD; the source of the PMOS transistor MP1 is connected to the source of the PMOS transistor MP2 and the power supply voltage VDD, the drain of the PMOS transistor MP1 is connected to the first end of the bias current source Ibias; the second end of the bias current source Ibias is grounded; the source of the PMOS transistor MP4 is connected to the power supply VDD.
[0020] Preferably, the width-length ratio of the NMOS transistor MN1 is equal to the width-length ratio of the NMOS transistor MN2, and the transconductance of the NMOS transistor MN1 is the same as the transconductance of the NMOS transistor MN2.
[0021] Preferably, the current flowing through the NMOS transistor MN4 and the NMOS transistor MN5 is half of the current flowing through the PMOS transistor MP3 and the PMOS transistor MP4.
[0022] The resistor R1 and capacitor C1 modulate the transconductance of NMOS transistors MN1 and MN2. At low frequencies, capacitor C1 acts as an open circuit, and the resistor R1 at the source level of NMOS transistors MN1 and MN2 attenuates the equivalent transconductance of NMOS transistors MN1 and MN2. At high frequencies, capacitor C1 acts as a short circuit, causing the equivalent transconductance of NMOS transistors MN1 and MN2 to gradually increase back to their initial transconductance. By using resistors R1 and C1, at low frequencies, the voltage negative feedback loop of the first transconductance op-amp dominates, maintaining high PSRR performance at low frequencies. At high frequencies, as the gain of the voltage negative feedback loop gradually decreases and the PSRR gradually deteriorates, the current series negative feedback of the second transconductance op-amp plays an important role, improving the PSRR performance at high frequencies.
[0023] The equivalent transconductance gm_eff of NMOS transistor MN1 is expressed as:
[0024] Where gm_eff_low frequency is the equivalent transconductance of NMOS transistor MN1 at low frequency, gm_eff_high frequency is the equivalent transconductance of NMOS transistor MN1 at high frequency, R1 is the resistance value of resistor R1, and gm is the transconductance of NMOS transistor MN1.
[0025] like Figure 2 As shown, in this embodiment of the invention, the IV conversion circuit includes NMOS transistors MN6, MN7, MN8, MN9, and MN10, resistor R2, PMOS transistors MP5, MP6, and MP8. The drain of NMOS transistor MN6 is connected to the gate of PMOS transistor MP5, the drain of PMOS transistor MP5, the gate of PMOS transistor MP6, and the gate of PMOS transistor MP8; the source of NMOS transistor MN6 is grounded. The gate of NMOS transistor MN7 is connected to the gate of NMOS transistor MN8 and the first terminal of resistor R2; the drain of NMOS transistor MN7 is connected to the second terminal of resistor R2 and the gates of NMOS transistor MN9 and NMOS transistor MN10. The drain of NMOS transistor MN8 is connected to the drain of PMOS transistor MP8 and the gate of NMOS transistor MN11. The source of NMOS transistor MN9 is connected to the source of NMOS transistor MN10 and grounded. The source of PMOS transistor MP6 is connected to the drain of NMOS transistor MN1. The source of PMOS transistor MP8 is connected to the drain of NMOS transistor MN2. The source of PMOS transistor MP5 is connected to the power supply voltage VDD.
[0026] Preferably, the width-to-length ratio of PMOS transistors MP3 and MP4 is more than 4 times that of PMOS transistor MP5, and PMOS transistor MP5 is an inverted ratio transistor.
[0027] like Figure 2 As shown, in this embodiment of the invention, the power transistor is a PMOS transistor MP14; the mirror power transistor is a PMOS transistor MP13; the gate of the power transistor MP14 is connected to the gate of the mirror power transistor MP13, the drain of the NMOS transistor MN11, and the drain of the PMOS transistor MP12; the source of the power transistor MP14 is connected to the first terminal of the sampling resistor RS and connected to the power supply voltage VDD; the drain of the power transistor MP14 is connected to the drain of the mirror power transistor MP13, the second terminal of the resistor R3, and the resistor R The first terminal of resistor R4 is connected to the first terminal of feedback resistor RF1, the first terminal of resistor Resr, and the first terminal of load resistor RL, and outputs voltage VOUT; the first terminal of resistor R3 is connected to the gate and drain of PMOS transistor MP7; the source of PMOS transistor MP7 is connected to the source of PMOS transistor MP12 and connected to power supply voltage VDD; the second terminal of resistor R4 is connected to the first terminal of capacitor C2; the second terminal of capacitor C2 is grounded; the source of NMOS transistor MN11 is grounded; the source of mirror power transistor PMOS transistor MP13 is connected to the second terminal of sampling resistor RS.
[0028] Preferably, resistors R4 and C2 generate a zero with a frequency of 1 / R4C2 for frequency compensation.
[0029] Preferably, the aspect ratio of the power transistor PMOS MP14 is 20 times that of the mirror power transistor PMOS MP13.
[0030] Preferably, the resistance value of the sampling resistor RS is 50 ohms to 100 ohms.
[0031] like Figure 2 As shown in the example of this invention, the feedback resistor network includes feedback resistor RF1 and feedback resistor RF2; the load terminal includes resistor Resr, load capacitor CL, and load resistor RL. The first terminal of feedback resistor RF1 is connected to the first terminal of resistor Resr and the first terminal of load resistor RL; the second terminal of feedback resistor RF1 is connected to the first terminal of feedback resistor RF2 and the gate of PMOS transistor MP11; the second terminal of feedback resistor RF2 is grounded; the second terminal of resistor Resr is connected to the first terminal of load capacitor CL; the second terminal of load capacitor CL is grounded; and the second terminal of load resistor RF1 is grounded.
[0032] The ratio of the resistance values of the feedback resistors RF1 and RF2 determines the value of the output voltage VOUT, VOUT=VREF(1+RF1 / RF2), and the values of the feedback resistors RF1 and RF2 affect the noise of the output voltage VOUT and the static power consumption of the entire circuit.
[0033] The working principle of the example of the present application is that, at high frequencies, the fluctuation of the output current of the power tube caused by the fluctuation of the input power supply voltage VDD is amplified by current sampling feedback, and is fed into the gate of the power tube to form a current series negative feedback structure, thereby increasing the equivalent impedance from the input power supply voltage VDD to the output terminal to improve the PSRR performance of the LDO at high frequencies. At low frequencies, the equivalent impedance of the second transconductance operational amplifier is attenuated due to the effect of the resistor R1, and does not have a great impact on the PSRR at low frequencies.
[0034] Please refer to Figure 3 , Figure 3 Fig. 1 is a PSRR simulation waveform diagram of the LDO circuit based on current sampling feedback high-frequency high-PSRR according to the present application. The upper half of the figure is the PSRR waveform diagram of the LDO without current sampling feedback, and the lower half of the figure is the PSRR waveform diagram of the LDO circuit based on current sampling feedback high-frequency high-PSRR according to the present application. The horizontal coordinate is frequency (unit: Hz), and the vertical coordinate is voltage (unit: dB). The PSRR of the LDO without current sampling feedback drops sharply to-31.0535 dB at high frequencies, and the LDO based on current sampling feedback high-frequency high-PSRR according to the present application is enhanced to-83.0344 dB at the same frequency of 165.9 KHz, which is improved by 51.9809 dB. It can be seen that the example of the present application can significantly improve the PSRR performance of the LDO at high frequencies.
[0035] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. A high-frequency, high-PSRR LDO circuit based on current sampling feedback, characterized in that: It includes a first transconductance operational amplifier, a second transconductance operational amplifier, an IV conversion circuit, a power transistor, a mirror power transistor, a sampling resistor RS, a resistor feedback network, and a load terminal; The output terminal of the first transconductance operational amplifier is connected to the IV conversion circuit. The first transconductance operational amplifier includes two input terminals. The first input terminal is connected to the reference voltage VREF, and the second input terminal is connected to the feedback voltage. It is used to amplify the difference between the reference voltage VREF and the feedback voltage and output current. The output terminal of the second transconductance operational amplifier is connected to the IV conversion circuit. The second transconductance operational amplifier includes two input terminals. The first input terminal is connected to the first terminal of the sampling resistor RS, and the second input terminal is connected to the second terminal of the sampling resistor RS. It is used to amplify the voltage difference across the sampling resistor RS and output current. The output of the IV conversion circuit is connected to the power transistor and the mirror power transistor, and is used to convert the current output by the first transconductance operational amplifier and the second transconductance operational amplifier into a voltage signal to control the conduction degree of the power transistor and the mirror power transistor. The power transistor is connected to the output terminal of the IV conversion circuit and the load terminal; The mirror power transistor is connected to the sampling resistor RS to sample the output current of the power transistor in a proportional manner. The sampling resistor RS is used to convert the output current sampled proportionally by the mirror power transistor into voltage, and input it to the two input terminals of the second transconductance operational amplifier; The resistor feedback network is used to feed back the feedback voltage after the output voltage VOUT is divided by resistors to the second input terminal of the first transconductance operational amplifier. The load terminal is connected to the power transistor to filter out noise from the output voltage VOUT.
2. The high-frequency, high-PSRR LDO circuit based on current sampling feedback according to claim 1, characterized in that: The first transconductance operational amplifier includes PMOS transistors MP9, MP10, and MP11; The source of PMOS transistor MP9 is connected to the power supply voltage VDD; the drain of PMOS transistor MP9 is connected to the source of PMOS transistor MP10 and the source of PMOS transistor MP11; the gate of PMOS transistor MP9 is connected to the gate of PMOS transistor MP1, the gate of PMOS transistor MP2, the gate of PMOS transistor MP3, the gate of PMOS transistor MP4, and the gate of PMOS transistor MP12; the gate of PMOS transistor M10 is connected to the reference voltage VREF; the drain of PMOS transistor MP10 is connected to the source of NMOS transistor MN7 and the drain of NMOS transistor MN9; the gate of PMOS transistor MP11 is connected to the second terminal of feedback resistor RF1 and the first terminal of feedback resistor RF2; the drain of PMOS transistor MP11 is connected to the source of NMOS transistor MN8 and the drain of NMOS transistor MN10.
3. The high-frequency, high-PSRR LDO circuit based on current sampling feedback according to claim 1, characterized in that: The second transconductance operational amplifier includes NMOS transistors MN1, MN2, MN3, MN4, and MN5, PMOS transistors MP1, MP2, MP3, and MP4, a bias current source Ibias, a resistor R1, and a capacitor C1. The gate of NMOS transistor MN1 is connected to the first terminal of the sampling resistor RS; the drain of NMOS transistor MN1 is connected to the drain of PMOS transistor MP3; the source of NMOS transistor MN1 is connected to the first terminal of resistor R1, the first terminal of capacitor C1, and the drain of NMOS transistor MN4. The gate of NMOS transistor MN2 is connected to the second terminal of the sampling resistor RS; the drain of NMOS transistor MN2 is connected to the drain of PMOS transistor MP4; the source of NMOS transistor MN2 is connected to the second terminal of resistor R1, the second terminal of capacitor C1, and the drain of NMOS transistor MN5. The gate of NMOS transistor MN4 is connected to the gate of NMOS transistor MN5, the gate of NMOS transistor MN3, and the gate of NMOS transistor MN6; the source of NMOS transistor MN4 is connected to N... The source of MOS transistor MN5 is grounded; the source of NMOS transistor MN3 is grounded, and the drain of NMOS transistor MN3 is connected to the drain of PMOS transistor MP2; the gate of PMOS transistor MP3 is connected to the gates of PMOS transistor MP4, PMOS transistor MP1, PMOS transistor MP2, PMOS transistor MP9, and PMOS transistor MP12; the source of PMOS transistor MP3 is connected to the power supply VDD; the source of PMOS transistor MP1 is connected to the source of PMOS transistor MP2 and connected to the power supply VDD; the drain of PMOS transistor MP1 is connected to the first terminal of the bias current source Ibias; the second terminal of the bias current source Ibias is grounded; the source of PMOS transistor MP4 is connected to the power supply VDD.
4. The high-frequency, high-PSRR LDO circuit based on current sampling feedback according to claim 1, characterized in that: The IV conversion circuit includes NMOS transistors MN6, MN7, MN8, MN9, and MN10, resistor R2, PMOS transistors MP5, MP6, and MP8; The drain of NMOS transistor MN6 is connected to the gate of PMOS transistor MP5, the drain of PMOS transistor MP5, the gate of PMOS transistor MP6, and the gate of PMOS transistor MP8; the source of NMOS transistor MN6 is grounded. The gate of NMOS transistor MN7 is connected to the gate of NMOS transistor MN8 and the first terminal of resistor R2; the drain of NMOS transistor MN7 is connected to the second terminal of resistor R2 and the gates of NMOS transistor MN9 and NMOS transistor MN10. The drain of NMOS transistor MN8 is connected to the drain of PMOS transistor MP8 and the gate of NMOS transistor MN11. The source of NMOS transistor MN9 is connected to the source of NMOS transistor MN10 and grounded. The source of PMOS transistor MP6 is connected to the drain of NMOS transistor MN1. The source of PMOS transistor MP8 is connected to the drain of NMOS transistor MN2. The source of PMOS transistor MP5 is connected to the power supply voltage VDD.
5. The high-frequency, high-PSRR LDO circuit based on current sampling feedback according to claim 1, characterized in that: The mirror power transistor is PMOS transistor MP13; the gate of the power transistor MP14 is connected to the gate of the mirror power transistor MP13, the drain of NMOS transistor MN11, and the drain of PMOS transistor MP12; the source of the power transistor MP14 is connected to the first terminal of the sampling resistor RS and the power supply voltage VDD; the drain of the power transistor MP14 is connected to the drain of the mirror power transistor MP13, the second terminal of resistor R3, the first terminal of resistor R4, the first terminal of feedback resistor RF1, the first terminal of resistor Resr, and the first terminal of load resistor RL, and outputs voltage VOUT; the first terminal of resistor R3 is connected to the gate and drain of PMOS transistor MP7; the source of PMOS transistor MP7 is connected to the source of PMOS transistor MP12 and the power supply voltage VDD; the second terminal of resistor R4 is connected to the first terminal of capacitor C2; the second terminal of capacitor C2 is grounded; the source of NMOS transistor MN11 is grounded; the source of the mirror power transistor MP13 is connected to the second terminal of the sampling resistor RS.
6. The high-frequency, high-PSRR LDO circuit based on current sampling feedback according to claim 1, characterized in that: The feedback resistor network includes feedback resistor RF1 and feedback resistor RF2; the load terminal includes resistor Resr, load capacitor CL, and load resistor RL. The first end of the feedback resistor RF1 is connected to the first end of the resistor Resr and the first end of the load resistor RL; the second end of the feedback resistor RF1 is connected to the first end of the feedback resistor RF2 and the gate of the PMOS transistor MP11; the second end of the feedback resistor RF2 is grounded; the second end of the resistor Resr is connected to the first end of the load capacitor CL; the second end of the load capacitor CL is grounded; and the second end of the load resistor is grounded.