Trimming band-gap reference voltage source circuit and band-gap reference voltage source

Abstract

The invention discloses a trimmable band-gap reference voltage source circuit and a band-gap reference voltage source, relates to the technical field of band-gap reference circuits in analog circuits, and aims to offset non-linear current generated by a non-linear temperature drift term in base-emitter voltage of a bipolar transistor so as to obtain temperature secondary irrelevant current. The reference voltage is converted into the reference voltage which is secondarily irrelevant to the temperature through the resistor, the temperature coefficient of the reference voltage is effectively reduced, the reference voltage of a finished chip can be finely adjusted by introducing the trimming resistor, and the reference voltage error caused by element deviation in the chip production and manufacturing process is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog circuit, in particular to a tunable bandgap reference voltage source circuit.

[0002] The present application also relates to a tunable bandgap reference voltage source. BACKGROUND

[0003] The bandgap reference source has the characteristics of low temperature coefficient and high precision, and is widely used in ADC, DAC, LDO and other analog circuits. In the ADC and DAC circuit, the bandgap reference voltage source provides a reference voltage independent of temperature, power voltage and process angle for the system. By comparing the reference voltage with the input signal of the system, a discrete level with digital code can be obtained. In the LDO system, the bandgap reference circuit is combined with the error amplifier and the power tube to realize the voltage stabilizing function together. In addition, the bandgap reference source is also widely used in amplifier, driving circuit and other analog circuit systems to provide accurate and stable bias current or voltage for the system. With the continuous progress of process level, analog integrated circuits have been rapidly developed, and higher requirements have been put forward for various systems, which puts forward higher requirements for the precision and output consistency of the bandgap reference circuit in the chip.

[0004] Prior art scheme: The band gap reference voltage source circuit comprises a band gap reference voltage source circuit, wherein the ratio of the emitting junction area of PNP type bipolar transistors Q1 and Q2 is N:1, the base and the collector of the bipolar transistors are connected to GND, and the emitter is connected to resistor R2 and the inverting input terminal of operational amplifier OP1, respectively; one end of resistor R1 is connected to GND, the other end is connected to R2, and the non-inverting input terminal of operational amplifier OP1; the two ends of resistor R3 are connected to GND and the inverting input terminal of operational amplifier OP1, respectively; the source terminals of PMOS transistors M1, M2 and M3 are connected to power supply voltage VDD, the gate terminals are commonly connected to the output terminal of operational amplifier OP1, the drain terminal of PMOS transistor M1 is connected to the non-inverting input terminal of operational amplifier OP1, the drain terminal of PMOS transistor M2 is connected to the inverting input terminal of operational amplifier OP1, and the drain terminal of PMOS transistor M3 is connected to resistor R4; and the substrates of all the PMOS transistors in the circuit are connected to power supply voltage VDD. The circuit realizes voltage clamping through operational amplifier OP1, and clamps the voltage at the connection position of resistor R1 and R2 and the voltage at the connection position of bipolar transistor Q2 and resistor R3 to the same potential. By utilizing the characteristic that the base-emitter voltage of bipolar transistor Q2 is negatively correlated with temperature, a current with a negative temperature coefficient is generated on resistor R1. Due to the difference in current density between bipolar transistors Q1 and Q2, there is a voltage difference between the base-emitter voltages of the two bipolar transistors, which is positively correlated with temperature, and resistor R2 is used to convert the voltage difference into a current with a positive temperature coefficient. The current with a negative temperature coefficient and the current with a positive temperature coefficient are added together to obtain a current with a zero temperature coefficient, which is copied to the branch of resistor R4 through the current mirror composed of PMOS transistors M1 and M3, and resistor R4 is used to convert the current into a reference voltage with a zero temperature coefficient.

[0005] Defects of prior art solutions: Although the band gap reference voltage source reduces the temperature coefficient of the reference voltage to a certain extent, the circuit only compensates for the linear part of the temperature coefficient of the base-emitter voltage of the bipolar transistor, and there is still a high-order temperature drift term in the circuit due to the complex functional relationship between the base-emitter voltage of the bipolar transistor and temperature. Each processing step in the actual chip production and manufacturing process is uncertain, which causes unpredictable deviations between components, and the deviations will cause deviations of the reference voltage. Summary of the application

[0006] The application aims at solving the above problems, and provides a tunable band gap reference voltage source circuit and a band gap reference voltage source. By adding a high-order temperature compensation circuit, the non-linear temperature drift term of the base-emitter voltage of the bipolar transistor is compensated to reduce the temperature coefficient of the reference voltage. Meanwhile, a resistor tuning circuit is introduced to finely tune the reference voltage of the finished chip, thereby reducing the reference voltage error caused by the component deviation in the chip production and manufacturing process.

[0007] The technical scheme adopted by the present application is as follows: The adjustable bandgap reference voltage source circuit comprises a start-up and bias circuit, a bandgap reference circuit, a high-order temperature compensation circuit and a resistance trimming circuit. The start-up and bias circuit is electrically connected with the bandgap reference circuit and is used for providing a bias current. The bandgap reference circuit is used for outputting a reference voltage. The high-order temperature compensation circuit is electrically connected with the bandgap reference circuit and is used for offsetting a non-linear current generated by a non-linear temperature drift term in the reference voltage. The resistance trimming circuit is electrically connected with the high-order temperature compensation circuit and is used for trimming the compensated reference voltage.

[0008] Further, the start-up and bias circuit comprises PMOS transistors M1, M2, M3 and NMOS transistors M4, M5, M6 and M7. The gate end of M1 is connected with an enable signal EN, the drain end of M1 is connected with the drain end of M2, the gate end of M3 and M4 and the drain end of M6, the gate end of M2 is connected with the drain end of M5, the drain end of M3 is connected with the drain end of M4 and the gate end of M5, the gate end of M6 is connected with the enable signal EN, the source end of M6 is connected with the drain end of M7, and the gate end of M7 is connected with a power supply voltage VDD.

[0009] Further, a secondary operational amplifier is electrically connected between the bandgap reference circuit and the start-up and bias circuit, and the secondary operational amplifier comprises PMOS transistors MA1, MA2, MA5, MA7 and NMOS transistors MA3, MA4, MA6 and a capacitor Cc. The source end of MA1 is connected with the source end of MA2 and the drain end of MA5, the drain end of MA1 is connected with the drain end of MA3, the gate ends of MA1 and MA2 are connected with the bandgap reference circuit respectively, the drain end of MA2 is connected with the drain end of MA4, the gate end of MA3 is connected with the drain end of itself and the gate end of MA4, the drain end of MA4 is connected with the capacitor Cc and the gate end of MA6, the drain end of MA6 is connected with the drain end of MA7 and the capacitor Cc, the gate end of M2 is connected with the gate ends of MA5 and MA7, and the drain end of MA6 is an output end of the secondary operational amplifier.

[0010] Further, the bandgap reference circuit comprises PMOS transistors M8 and M9, resistors R1, R2 and R3 and bipolar transistors Q1 and Q2. Wherein, the drain of M8 is connected to R1 and R2 respectively; the drain of M9 is connected to R3 and the emitter of Q2; the base and collector of Q1 and the base and collector of Q2 are all connected to GND; one end of R2 is connected to R1, and the other end of R2 is connected to the emitter of Q1; one end of R3 is connected to GND, and the other end of R3 is connected to the emitter of Q2; The gate of M2 of the start-up and bias circuit is connected to the gates of M8 and M9, the gate of MA1 is connected to the emitter of Q2; the gate of MA2 is connected to R2, and the output of the second operational amplifier is connected to the gates of M8 and M9.

[0011] Further, the high-order temperature compensation circuit comprises PMOS transistor M10, bipolar transistor Q3, and resistors R4 and R5. Wherein, the drain of M10 is connected to the emitter of Q3; the two ends of R4 are connected to the drains of M8 and M10; the two ends of R5 are connected to the drains of M9 and M10 respectively, and the gate of M2 is connected to the gate of M10; the base and collector of Q3 are both connected to GND.

[0012] Further, the resistance trimming circuit comprises PMOS transistor M11, multiplexer MUX1, demultiplexer DEMUX1, trimming resistors Rtr1, Rtr2, Rtr3, Rtr4, Rtr5, Rtr6, and R6. Wherein, one end of Rtr1 is connected to GND, the other end of Rtr1 is connected to Rtr2 and Rtr3 in series, and Rtr3 is connected to R6; one end of Rtr4 is connected to R6, and the other end of Rtr4 is connected to Rtr5 and Rtr6 in series; the drain of M11 is connected to Rtr6, and the gate of M2 is connected to the gate of M11; the input of DEMUX1 is connected to GND, and the output is connected to the nodes between Rtr1, Rtr2, Rtr3, and R6; the input of MUX1 is connected to the nodes between R6, Rtr4, Rtr5, Rtr6, and the drain of M11, and the output of MUX1 is the reference voltage VREF.

[0013] Further, the source of the PMOS transistor except MA1 and MA2 in the second operational amplifier is connected to the power supply voltage VDD; the substrate of the PMOS transistor is connected to the power supply voltage VDD; the source of the NMOS transistor except M6 in the start-up and bias circuit is connected to GND; and the substrate of the NMOS transistor is connected to GND.

[0014] Further, the high-order temperature compensation circuit is used to offset the nonlinear current generated by the nonlinear temperature drift term in the base-emitter voltage of the bipolar transistor, obtain a temperature quadratic non-correlation current, and convert the temperature quadratic non-correlation current into a temperature quadratic non-correlation reference voltage through a resistor.

[0015] The application further provides a tunable bandgap reference voltage source comprising the bandgap reference voltage source circuit.

[0016] In summary, due to the adoption of the above technical solutions, the application has the following beneficial effects: The application offsets the nonlinear current generated by the nonlinear temperature drift term in the base-emitter voltage of the bipolar transistor to obtain a temperature quadratic non-correlation current, and converts the temperature quadratic non-correlation current into a temperature quadratic non-correlation reference voltage through a resistor, thereby effectively reducing the temperature coefficient of the reference voltage. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 It is a bandgap reference voltage source circuit diagram of the prior art; Figure 2 It is a principle block diagram of a tunable bandgap reference voltage source circuit of the application; Figure 3 It is a bandgap reference voltage source circuit diagram provided by the application; Figure 4 It is a temperature characteristic curve of the reference voltage of the prior art bandgap reference voltage source circuit under a 1.8V power supply voltage; Figure 5 It is a temperature characteristic curve of the reference voltage of the bandgap reference voltage source circuit provided by the application under a 1.8V power supply voltage; Figure 6 It is a power supply rejection ratio curve of the bandgap reference voltage source circuit provided by the application under TT, FF and SS process angles; Figure 7 It is a lowest working voltage simulation curve of the bandgap reference voltage source circuit provided by the application under TT, FF and SS process angles. DETAILED DESCRIPTION

[0018] The application will be described in further detail below with reference to the drawings.

[0019] In order to make the purpose, technical solutions and advantages of the application clearer, the application will be further described below with reference to the drawings and examples. It should be understood that the specific examples described herein are only used to explain the application and do not limit the application.

[0020] Embodiment The embodiment provides a trimmable bandgap reference voltage source circuit, which specifically comprises a start-up and bias circuit, an operational amplifier circuit, a bandgap reference circuit, a high-order temperature compensation circuit and a circuit trimming circuit, as shown in Figure 2 and Figure 3 . The start-up and bias circuit comprises PMOS transistors M1, M2, M3 and NMOS transistors M4, M5, M6, M7; the secondary operational amplifier comprises PMOS transistors MA1, MA2, MA5, MA7 and NMOS transistors MA3, MA4, MA6 and a capacitor Cc; the bandgap reference circuit comprises PMOS transistors M8, M9 and resistors R1, R2, R3 and bipolar transistors Q1, Q2; the high-order temperature compensation circuit comprises a PMOS transistor M10 and a bipolar transistor Q3 and resistors R4, R5; and the resistor trimming circuit comprises a PMOS transistor M11, a multiplexer MUX1, a demultiplexer DEMUX1 and trimming resistors Rtr1, Rtr2, Rtr3, Rtr4, Rtr5, Rtr6 and R6, specifically: The gate end of the PMOS transistor M1 in the start-up and bias circuit is controlled by an enable signal EN, the drain end of M1 is connected to the drain end of the PMOS transistor M2, the gate end of the PMOS transistor M3 and the NMOS transistor M4 and the drain end of the NMOS transistor M6 controlled by the enable signal EN; the gate end of the PMOS transistor M2 is connected to the drain end of the NMOS transistor M5 and the gate end of the PMOS transistors MA5, MA7, M8, M9, M10, M11; the drain end of the PMOS transistor M3 is connected to the drain end of the NMOS transistor M4 and the gate end of the NMOS transistor M5; the gate end of the NMOS transistor M6 is controlled by the enable signal EN, and the source end is connected to the drain end of the NMOS transistor M7; and the gate end of the NMOS transistor M7 is connected to a power supply voltage VDD.

[0021] In the operational amplifier circuit, the source end of the PMOS transistor MA1 is connected to the source end of the PMOS transistor MA2 and the drain end of the PMOS transistor MA5, the drain end of MA1 is connected to the drain end of the NMOS transistor MA3, and the gate end of MA1 is connected to the emitter of the bipolar transistor Q2; the gate end of the PMOS transistor MA2 is connected to the resistor R2, and the drain end is connected to the drain end of the NMOS transistor MA4; the gate end of the NMOS transistor MA3 is connected to the drain end of itself and the gate end of the NMOS transistor MA4; the drain end of the NMOS transistor MA4 is connected to the capacitor Cc and the gate end of the NMOS transistor MA6; the drain end of the NMOS transistor MA6 is connected to the drain end of the PMOS transistor MA7 and the capacitor Cc; and the drain end of the NMOS transistor MA6 is the output of the secondary operational amplifier, which is connected to the gate end of the PMOS transistors M8, M9.

[0022] The drain end of the PMOS transistor M8 in the bandgap reference circuit is connected with resistors R1 and R2; the drain end of the PMOS transistor M9 is connected with resistor R3 and the emitter of the bipolar transistor Q2; the base and the collector of the bipolar transistor Q1 are connected to GND, and the base and the collector of the bipolar transistor Q2 are also connected to GND; one end of the resistor R2 is connected with the resistor R1, and the other end is connected with the emitter of the bipolar transistor Q1; one end of the resistor R3 is connected with GND, and the other end is connected with the emitter of the bipolar transistor Q2.

[0023] The emitter of the bipolar transistor Q3 is connected with the drain end of the PMOS transistor M10 in the high-order temperature compensation circuit; one end of the resistor R4 is connected with the drain end of the PMOS transistor M8, and the other end is connected with the drain end of the PMOS transistor M10; one end of the resistor R5 is connected with the drain end of the PMOS transistor M9, and the other end is connected with the drain end of the PMOS transistor M10; the base and the collector of the bipolar transistor Q3 are connected to GND.

[0024] The PMOS transistor M11, the multiplexer MUX1, the demultiplexer DEMUX1, the trimming resistors Rtr1-Rtr6 and the resistor R6 in the circuit trimming circuit form a trimming circuit, wherein one end of the trimming resistor Rtr1 is connected to GND, the other end is connected with the trimming resistors Rtr2 and Rtr3 in series, and the trimming resistor Rtr3 is connected to the resistor R6; one end of the trimming resistor Rtr4 is connected to the resistor R6, and the other end is connected with the trimming resistors Rtr5 and Rtr6 in series; the drain end of the PMOS transistor M11 is connected with the trimming resistor Rtr6; the input end of the demultiplexer DEMUX1 is connected to GND, and the output end is connected with nodes a, b and c; the input end of the multiplexer MUX1 is connected with nodes d, e, f and g, and the output end is the reference voltage VREF. Except for the PMOS transistors MA1 and MA2, the source ends of the remaining PMOS transistors are connected to the power supply voltage VDD; the substrates of all the PMOS transistors are connected to the power supply voltage VDD; except for the NMOS transistor M6, the source ends of the remaining NMOS transistors are connected to GND; the substrates of all the NMOS transistors are connected to GND.

[0025] The embodiment also provides an operation principle of the adjustable bandgap reference voltage source circuit, which is specifically as follows: In the CMOS bandgap reference source, the collector current of the bipolar transistor has the following relationship with the base-emitter voltage : (1) In the formula, the base-emitter voltage is , and the saturation current of the bipolar transistor is , so that the temperature coefficient of the base-emitter voltage is:(2) where b is a proportional coefficient, m=-1.5, =1.12eV, k is the Boltzmann constant; when =750mV, temperature T=300K, the temperature coefficient of the base-emitter voltage of the bipolar transistor is about -1.5mV / K, i.e. the base-emitter voltage of the bipolar transistor has a negative temperature coefficient.

[0026] Suppose two bipolar transistors work at different collector currents, and their emitter area ratio is N:1, then the temperature coefficient of the base-emitter voltage difference between the two bipolar transistors is as follows: (3) i.e. the base-emitter voltage difference between the two bipolar transistors has a positive temperature coefficient, and the coefficient is only related to the emitter area ratio, the negative temperature coefficient voltage and the positive temperature coefficient voltage are converted into currents respectively, and the zero temperature coefficient current is obtained by adding the currents according to certain weights, and the zero temperature coefficient reference voltage is obtained by converting the zero temperature coefficient current into voltage by using a resistor in the output stage.

[0027] However, the base-emitter voltage of the bipolar transistor is not linear with the temperature, and the relationship between the base-emitter voltage and the temperature is as follows: (4) where , are the PN junction voltage and the emission junction voltage respectively when the temperature is 0K, T is the absolute temperature, is the reference temperature, is a temperature-independent but process-dependent constant, and the value is about 4; when the current flowing through the bipolar transistor is proportional to the temperature, =1; when the current flowing through the bipolar transistor is independent of the temperature, =0.

[0028] If the positive temperature coefficient is fixed, the temperature compensation of the base-emitter voltage is only first-order, and the temperature coefficient of the generated reference voltage is still not ideal. The present application compensates the nonlinear temperature drift term in the reference voltage by introducing a high-order temperature compensation circuit, and adds a trimming resistor in the output stage, and the reference voltage is trimmed by adjusting the size of the resistor, so as to reduce the temperature coefficient of the reference voltage and improve the system accuracy.

[0029] As Figure 3As shown, the input terminals of the high-gain operational amplifier are connected to the drain terminals of PMOS transistors M8 and M9, respectively. When the system is working normally, due to the clamping function of the operational amplifier, the drain voltages of PMOS transistors M8 and M9 are equal. Assume the emitter junction area ratio of bipolar transistors Q1 and Q2 is N:1, and the base-emitter voltages are respectively... and If resistors R1 and R3 have the same resistance, then the current flowing through resistor R1 is... and the current flowing through resistor R2 As shown in the following formula: *(5) (6) Due to the base-emitter voltage of a bipolar transistor A negative temperature coefficient current has a higher-order temperature drift term. With positive temperature coefficient current After addition, the total current still exhibits a nonlinear temperature drift term; adding resistors R4 and R5 and bipolar transistor Q3, assuming that the resistances of R4 and R5 are equal, and that the nonlinear component of the bipolar transistor's base-emitter voltage is... This allows the nonlinear components of the currents flowing through resistors R4 and R5 to be canceled out by the currents flowing through resistors R1 and R3, resulting in a temperature-independent second-order current, thus compensating for the nonlinear temperature drift term. The current flowing through bipolar transistor Q2 is proportional to temperature, i.e., for... In other words, =1; The current flowing through bipolar transistor Q3 is independent of temperature, that is, for the base-emitter voltage of bipolar transistor Q3... In other words, =0; therefore, the base-emitter voltages of bipolar transistors Q2 and Q3 are as follows: (7) (8) Nonlinear component in the base-emitter voltage of a bipolar transistor for and The difference is expressed by the following formula: (9) Current flowing through resistor R4 As shown in the following formula: (10) Current , and After addition, the temperature quadratic non-correlated current can be obtained, which is copied through the current mirror, converted into the temperature quadratic non-correlated reference voltage in the output stage through the resistance R6 and the trimming resistances Rtr1~Rtr6, as follows: (11) The ratio of the resistances R1 and R2 is adjusted to eliminate the temperature first order term in the reference voltage, i.e. (12) The ratio of the resistances R1 and R4 is adjusted to eliminate the high order temperature drift term in the reference voltage, i.e. (13) The reference voltage at this time can be expressed as: (14) In the formula, The resistances provided for the trimming resistances Rtr1~Rtr6; since the input of the demultiplexer DEMUX1 is connected to GND, when the trimming code controls the demultiplexer DEMUX1 to open, the corresponding node in the nodes a, b, c will be connected to GND, and the corresponding resistance will be short-circuited, so that the total resistance in the output stage is reduced, thereby reducing the reference voltage ; when the trimming code controls the multiplexer MUX1 to open, the multiplexer MUX1 can select the voltage of the nodes d, e, f, g as the reference voltage , i.e. by increasing the total resistance in the output stage, the increase of the reference voltage is realized.

[0030] Verification example The circuit provided by the present application is simulated and verified under the 1.8V power supply voltage.

[0031] As Figure 1 shown in the prior art band gap reference voltage source circuit, as Figure 4 and Figure 5 shown, the reference voltage of the circuit of the present application after high order temperature compensation is less affected by temperature change, as Figure 6 and Figure 7 shown, the circuit of the present application can have a higher power supply rejection ratio under different process angles, and is not sensitive to power supply noise; since the system adopts the current summation method to generate the reference voltage, the circuit can work in a lower power supply voltage.

[0032] The principles and implementation manners of the present application are described by using specific examples in the present application, and the above examples are only used for helping to understand the method of the present application and its core idea. It should be pointed out that, for ordinary skilled in the art, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. An adjustable bandgap reference voltage source circuit, characterized in that, The bandgap reference voltage source includes a startup and bias circuit, a bandgap reference circuit, a high-order temperature compensation circuit, and a resistor adjustment circuit. The startup and bias circuit is electrically connected to the bandgap reference circuit to provide bias current; The bandgap reference circuit is used to output a reference voltage; The high-order temperature compensation circuit is electrically connected to the bandgap reference circuit and is used to cancel the nonlinear current generated by the nonlinear temperature drift term in the reference voltage. The resistor adjustment circuit is electrically connected to the high-order temperature compensation circuit and is used to adjust the compensated reference voltage.

2. The adjustable bandgap reference voltage source circuit according to claim 1, characterized in that, The startup and bias circuit includes PMOS transistors M1, M2, and M3 and NMOS transistors M4, M5, M6, and M7; Specifically, the gate of M1 is connected to the enable signal EN, the drain of M1 is connected to the drain of M2, the gates of M3 and M4, and the drain of M6 is connected to the enable signal EN; the gate of M2 is connected to the drain of M5; the drain of M3 is connected to the drain of M4 and the gate of M5; the gate of M6 is connected to the enable signal EN, the source of M6 is connected to the drain of M7; and the gate of M7 is connected to the power supply voltage VDD.

3. The adjustable bandgap reference voltage source circuit according to claim 2, characterized in that, A two-stage operational amplifier is electrically connected between the bandgap reference circuit and the startup and bias circuit. The two-stage operational amplifier includes PMOS transistors MA1, MA2, MA5, MA7, NMOS transistors MA3, MA4, MA6, and capacitor Cc. In this configuration, the source terminal of MA1 is connected to the source terminal of MA2 and the drain terminal of MA5; the drain terminal of MA1 is connected to the drain terminal of MA3; the gate terminals of MA1 and MA2 are respectively connected to the bandgap reference circuit; the drain terminal of MA2 is connected to the drain terminal of MA4; the gate terminal of MA3 is connected to its own drain terminal and the gate terminal of MA4; the drain terminal of MA4 is connected to capacitor Cc and the gate terminal of MA6; the drain terminal of MA6 is connected to the drain terminal of MA7 and capacitor Cc; the gate terminal of M2 is connected to the gate terminals of MA5 and MA7; and the drain terminal of MA6 is the output terminal of the second-stage operational amplifier.

4. The adjustable bandgap reference voltage source circuit according to claim 3, characterized in that, The bandgap reference circuit includes PMOS transistors M8 and M9, resistors R1, R2, and R3, and bipolar transistors Q1 and Q2. In this configuration, the drain of M8 is connected to R1 and R2 respectively; the drain of M9 is connected to R3 and the emitter of Q2; the base and collector of Q1 and the base and collector of Q2 are both connected to GND; one end of R2 is connected to resistor R1, and the other end of R2 is connected to the emitter of Q1; one end of R3 is connected to GND, and the other end of R3 is connected to the emitter of bipolar transistor Q2. The gate terminal of M2 in the startup and bias circuit is connected to the gate terminals of M8 and M9, and the gate terminal of MA1 is connected to the emitter of Q2; the gate terminal of MA2 is connected to resistor R2, and the output terminal of the second-stage operational amplifier is connected to the gate terminals of M8 and M9.

5. The adjustable bandgap reference voltage source circuit according to claim 4, characterized in that, The high-order temperature compensation circuit includes a PMOS transistor M10, a bipolar transistor Q3, and resistors R4 and R5. Among them, the drain of M10 is connected to the emitter of Q3; the two ends of R4 are connected to the drains of M8 and M10; the two ends of R5 are connected to the drains of M9 and M10 respectively; the gate of M2 is connected to the gate of M10; the base and collector of Q3 are both connected to GND.

6. The adjustable bandgap reference voltage source circuit according to claim 4, characterized in that, The resistor adjustment circuit includes a PMOS transistor M11, a multiplexer MUX1, a multiplexer DEMUX1, and adjustment resistors Rtr1, Rtr2, Rtr3, Rtr4, Rtr5, Rtr6, and R6. In this circuit, one end of Rtr1 is connected to GND, and the other end of Rtr1 is connected in series with Rtr2 and Rtr3, with Rtr3 connected to R6; one end of Rtr4 is connected to resistor R6, and the other end of Rtr4 is connected in series with Rtr5 and Rtr6; the drain of M11 is connected to Rtr6, and the gate of M2 is connected to the gate of M11; the input of the multiplexer DEMUX1 is connected to GND, and the output is connected to the nodes between each pair of Rtr1, Rtr2, Rtr3 and R6; the input of the multiplexer MUX1 is connected to the nodes between each pair of R6, Rtr4, Rtr5, Rtr6 and the drain of M11, and the output of the multiplexer MUX1 is the reference voltage VREF.

7. The adjustable bandgap reference voltage source circuit according to claim 6, characterized in that, Except for MA1 and MA2 in the second-stage operational amplifier, the source terminals of all PMOS transistors are connected to the power supply voltage VDD; the substrates of all PMOS transistors are connected to the power supply voltage VDD; except for M6 in the startup and bias circuit, the source terminals of all NMOS transistors are connected to GND; the substrates of all NMOS transistors are connected to GND.

8. An adjustable bandgap reference voltage source circuit according to any one of claims 2 to 7, characterized in that, The high-order temperature compensation circuit is used to cancel the nonlinear current generated by the nonlinear temperature drift term in the base-emitter voltage of the bipolar transistor, obtain the temperature-second uncorrelated current, and convert the obtained temperature-second uncorrelated current into a temperature-second uncorrelated reference voltage through a resistor.

9. An adjustable bandgap reference voltage source, characterized in that, Includes the bandgap reference voltage source circuit as described in any one of claims 1 to 7.

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