A CPU power consumption optimization method and device based on instruction prediction

Abstract

This application discloses a CPU power consumption optimization method and apparatus based on instruction prediction. During the CPU instruction fetch stage, the instruction characteristics of the first instruction to be executed and the instruction characteristics of the second instruction pre-fetched from the same cache line are simultaneously acquired. Then, based on a preset instruction-resource mapping table and combining the instruction characteristics of the first and second instructions, at least one target resource module that the CPU pipeline needs to call in the following several cycles is predicted. Finally, all pipeline modules in the CPU except the target resource module are shut down, leaving only the target resource module in the working state. This application, by accurately acquiring the characteristics of current and subsequent instructions and predicting target resource modules, only shuts down unnecessary pipeline modules, avoiding continuous power consumption by idle units within the pipeline, and significantly improving power utilization efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method and apparatus for optimizing CPU power consumption based on instruction prediction. Background Technology

[0002] Current microcontroller units (MCUs) primarily employ global sleep mode or peripheral clock gating strategies for power management. Global sleep mode controls power consumption by reducing the overall CPU operating state or suspending some core functions, suitable for idle or low-load scenarios. Peripheral clock gating strategies reduce dynamic power consumption when peripherals are idle by cutting off the clock signals of unused peripherals in the system-on-chip (SoC). Additionally, some solutions use simple rule-based management methods, such as permanently shutting down unused hardware modules for a preset time period, to further reduce power consumption.

[0003] However, existing technologies still have significant limitations and cannot meet the needs of refined power management. Current solutions mostly focus on system-level or peripheral-level power control, failing to dynamically manage internal pipeline resources based on real-time CPU instruction execution demands. This results in these units generating "idle power consumption" even when idle, leading to energy waste. Secondly, there is a trade-off between prediction accuracy and adaptability. While complex prediction models (such as neural network models) can improve the accuracy of resource demand predictions, they incur high hardware overhead and runtime latency, resulting in significant power management errors. Summary of the Invention

[0004] To address the aforementioned issues, this application provides a CPU power consumption optimization method and device based on instruction prediction.

[0005] The embodiments of this application disclose the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a CPU power consumption optimization method based on instruction prediction, the method comprising:

[0007] During the instruction fetching phase of CPU execution, the instruction characteristics of the first instruction to be executed are obtained, and the instruction characteristics of the second instruction in the same cache line are read in advance from the instruction cache; the second instruction is the instruction to be executed after the first instruction is executed.

[0008] Based on the instruction-resource mapping table, and according to the instruction characteristics of the first instruction and the instruction characteristics of the second instruction, at least one target resource module to be called by the CPU pipeline within a certain number of cycles is predicted; the instruction-resource mapping table is used to indicate the correspondence between instruction characteristics and resource modules.

[0009] Control the shutdown of all resource modules in the CPU except for the at least one target resource module.

[0010] In one possible implementation, predicting at least one target resource module to be called by the CPU pipeline within a plurality of cycles based on the instruction characteristics of the first instruction and the instruction characteristics of the second instruction includes:

[0011] Based on the instruction characteristics of the first instruction and the historical execution record of the first instruction, predict at least one target resource module to be called by the CPU pipeline when executing the first instruction; the historical execution record includes the jump pattern of the program counter for the instruction;

[0012] Based on the instruction characteristics of the second instruction and the historical execution record of the second instruction, predict at least one target resource module to be called by the CPU pipeline when executing the second instruction.

[0013] In one possible implementation, based on the instruction characteristics and historical execution records, at least one target resource module to be called by the CPU pipeline during instruction execution is predicted, including:

[0014] The instruction and resource mapping table is queried, and the resource module that the instruction directly depends on is determined as the target resource module based on the instruction characteristics of the instruction; the instruction is either the first instruction or the second instruction.

[0015] Based on the jump patterns of the branch instructions executed in the past by the program counter, the target address of the branch instruction is predicted, and the instruction corresponding to the target address is prefetched from the instruction cache. The resource module required for the prefetched instruction is then determined as the target resource module.

[0016] In one possible implementation, the method further includes:

[0017] After completing the instruction execution of one CPU cycle, the second instruction is used as the new first instruction, the next instruction in the same cache line of the second instruction is read as the new second instruction, the instruction characteristics of the new first instruction and the new second instruction are re-acquired, and the new target resource module is predicted.

[0018] If the new target resource module includes a closed resource module, a wake-up signal is generated to control the closed resource module to resume normal operation.

[0019] In one possible implementation, the instruction features include at least an opcode and an operand type;

[0020] After obtaining the instruction features of the first instruction and the instruction features of the second instruction, the method further includes:

[0021] The opcodes of the first instruction and the second instruction are encoded using 8-bit binary encoding, and the operand types of the first instruction and the second instruction are encoded using 4-bit binary encoding.

[0022] In one possible implementation, shutting down other resource modules in the control CPU besides the at least one target resource module includes:

[0023] If it is necessary to reduce the dynamic power consumption of the other resource modules, the clock signal of the other resource modules can be cut off through the clock gating circuit;

[0024] If it is necessary to reduce the static power consumption of the other resource modules, the power supply to the other resource modules can be cut off through the power gating circuit.

[0025] In one possible implementation, the method further includes:

[0026] If a target resource module prediction error is detected, the control signal for the target resource module with the prediction error is immediately withdrawn, and the clock signal and power supply of the target resource module with the prediction error are restored.

[0027] Secondly, embodiments of this application disclose a CPU power consumption optimization device based on instruction prediction, the device comprising:

[0028] The fetch module is used to obtain the instruction characteristics of the first instruction to be executed during the instruction fetching phase of CPU execution, and to pre-read the instruction characteristics of the second instruction in the same cache line from the instruction cache; the second instruction is the instruction to be executed after the first instruction is executed;

[0029] The prediction module is used to predict at least one target resource module to be called by the CPU pipeline within a certain number of cycles, based on the instruction and resource mapping table and according to the instruction characteristics of the first instruction and the second instruction; the instruction and resource mapping table is used to indicate the correspondence between instruction characteristics and resource modules.

[0030] The control module is used to control the shutdown of other resource modules in the CPU besides the at least one target resource module.

[0031] In one possible implementation, the prediction module is specifically used to predict, based on the instruction characteristics of the first instruction and the historical execution record of the first instruction, at least one target resource module to be called by the CPU pipeline when executing the first instruction; the historical execution record includes the jump pattern of the program counter for the instruction; and based on the instruction characteristics of the second instruction and the historical execution record of the second instruction, to predict, at least one target resource module to be called by the CPU pipeline when executing the second instruction.

[0032] In one possible implementation, the prediction module is specifically used to query the instruction-resource mapping table, determine the resource module that the instruction directly depends on as the target resource module based on the instruction characteristics of the instruction; the instruction is the first instruction or the second instruction; combine the jump pattern of the branch instruction when the program counter executes the branch instruction in the past, predict the target address of the branch instruction, prefetch the instruction corresponding to the target address from the instruction cache, and determine the resource module required for the prefetched instruction as the target resource module.

[0033] In one possible implementation, the acquisition module is further configured to, after completing the instruction execution of one CPU cycle, take the second instruction as a new first instruction, read the next instruction in the same cache line of the second instruction as a new second instruction, reacquire the instruction characteristics of the new first instruction and the new second instruction, and predict a new target resource module; if the new target resource module includes a closed resource module, generate a wake-up signal to control the closed resource module to resume normal operation.

[0034] In one possible implementation, the instruction features include at least an opcode and an operand type;

[0035] The acquisition module is further configured to use 8-bit binary encoding for the opcode of the first instruction and the opcode of the second instruction, and to use 4-bit binary encoding for the operand type of the first instruction and the operand type of the second instruction.

[0036] In one possible implementation, the control module is specifically used to cut off the clock signal of the other resource modules through a clock gating circuit if it is necessary to reduce the dynamic power consumption of the other resource modules; and to cut off the power supply of the other resource modules through a power gating circuit if it is necessary to reduce the static power consumption of the other resource modules.

[0037] In one possible implementation, the control module is further configured to, if a prediction error of the target resource module is detected, immediately cancel the control signal to the target resource module with the prediction error, and restore the clock signal and power supply to the target resource module with the prediction error.

[0038] Thirdly, embodiments of this application disclose a control device, including a processor and a memory, wherein the memory is used to store programs, instructions or code, and the processor is used to execute the programs, instructions or code in the memory to perform the CPU power consumption optimization method based on instruction prediction as described in any of the first aspects.

[0039] Fourthly, embodiments of this application disclose a computer-readable storage medium, characterized in that it stores a computer program, which is loaded by a processor to execute the CPU power consumption optimization method based on instruction prediction as described in any of the first aspects.

[0040] This application provides a CPU power consumption optimization method and device based on instruction prediction. The method includes: during the CPU instruction fetch stage, simultaneously acquiring the instruction characteristics of a first instruction to be executed and the instruction characteristics of a second instruction pre-fetched from the instruction cache and cache line. Then, based on a preset instruction-resource mapping table and combining the instruction characteristics of the first and second instructions, predicting at least one target resource module that the CPU pipeline needs to call in subsequent cycles. Finally, controlling the shutdown of other pipeline modules in the CPU except for the target resource module, leaving only the target resource module in the working state. This application, by accurately acquiring the characteristics of current and subsequent instructions and predicting target resource modules, only shuts down unnecessary pipeline modules, avoiding continuous power consumption by idle units within the pipeline, significantly improving power utilization efficiency. Furthermore, by pre-fetching the second instruction characteristics from the instruction cache and cache line and combining them with the instruction-resource mapping table for prediction, resource requirements can be determined in advance without waiting for instructions to be executed sequentially, reducing module switching latency. In addition, the embodiments of this application do not rely on complex prediction models, but achieve prediction through a lightweight method that combines instruction features and mapping tables. This results in low hardware overhead and fast execution speed, avoiding the CPU resource consumption of complex models and solving the problem of insufficient accuracy of simple rule-based management, thus balancing power consumption optimization and system operating efficiency. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A flowchart illustrating a CPU power consumption optimization method based on instruction prediction provided in an embodiment of this application;

[0043] Figure 2 This is a schematic diagram of a CPU power consumption optimization device based on instruction prediction, provided in an embodiment of this application. Detailed Implementation

[0044] As described earlier, in the field of microprocessor design, low-power optimization is a core requirement for improving device battery life and expanding application scenarios, especially for resource-constrained MCUs. In one implementation, the CPU in the MCU typically uses global sleep or peripheral clock gating strategies for power management, which cannot achieve fine-grained management of resource modules based on the specific instructions being executed, leading to wasted power from idle resource modules. In another implementation, complex predictive models are used for resource module management. While this can improve the accuracy of resource module management, the model has high hardware overhead and latency, making it unsuitable for resource-constrained MCUs.

[0045] To address this technical problem, this application provides a CPU power consumption optimization method and device based on instruction prediction. The method includes: during the CPU instruction fetch stage, simultaneously acquiring the instruction characteristics of the first instruction to be executed and the instruction characteristics of a second instruction pre-fetched from the instruction cache and cache line. Then, based on a preset instruction-resource mapping table and combining the instruction characteristics of the first and second instructions, predicting at least one target resource module that the CPU pipeline needs to call in subsequent cycles. Finally, controlling the shutdown of other pipeline modules in the CPU except for the target resource module, leaving only the target resource module in the working state. This application, by accurately acquiring the characteristics of current and subsequent instructions and predicting target resource modules, only shuts down unnecessary pipeline modules, avoiding continuous power consumption by idle units within the pipeline, significantly improving power utilization efficiency. Furthermore, by pre-fetching the second instruction characteristics from the instruction cache and cache line and combining them with the instruction-resource mapping table for prediction, resource requirements can be determined in advance without waiting for instructions to be executed sequentially, reducing module switching latency. In addition, the embodiments of this application do not rely on complex prediction models, but achieve prediction through a lightweight method that combines instruction features and mapping tables. This results in low hardware overhead and fast execution speed, avoiding the CPU resource consumption of complex models and solving the problem of insufficient accuracy of simple rule-based management, thus balancing power consumption optimization and system operating efficiency.

[0046] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0047] The CPU power consumption optimization method based on instruction prediction provided in this application is applicable to MCU application scenarios that are resource-constrained, power-sensitive, and require continuous execution of instruction streams. It is particularly widely adapted to devices such as IoT terminals, portable consumer electronics, and industrial control units. When these devices perform tasks such as data acquisition, logic operations, and instruction interaction, the method can extend the device's battery life and improve energy efficiency by precisely controlling the power consumption of resource modules.

[0048] The hardware execution entity of this method can be a dedicated hardware resource prediction controller integrated within the MCU. This controller directly interacts with the CPU's instruction fetch unit, instruction cache, and various pipeline resource modules. The controller may include an instruction feature extraction unit, a prediction unit, and a power control interface. The instruction feature extraction unit is responsible for acquiring the instruction features of the first and second instructions. The prediction unit performs target resource module prediction based on the instruction-resource mapping table. The power control interface generates control signals to shut down non-target pipeline modules. This method does not rely on external hardware components and is compatible with the MCU's hardware architecture design. The MCU also includes a CPU, which executes instructions through the CPU pipeline.

[0049] See Figure 1 , Figure 1 This is a flowchart illustrating a CPU power consumption optimization method based on instruction prediction, provided in an embodiment of this application. The method is described below using an electronic device as the execution subject, and includes:

[0050] S101: During the instruction fetching phase of CPU instruction execution, the controller obtains the instruction characteristics of the first instruction to be executed and reads the instruction characteristics of the second instruction in the same cache line from the instruction cache in advance.

[0051] Wherein, the second instruction is the instruction that needs to be executed after the first instruction has been executed;

[0052] An instruction cache (icache) is a high-speed memory within an MCU used to temporarily store instructions that are about to be executed. The CPU executes instructions much faster than the CPU can read instructions from external memory. The purpose of the icache is to preload potentially needed instructions from memory, avoiding CPU waiting and improving execution efficiency. Although MCUs have limited resources, they still integrate a lightweight icache.

[0053] A cache line is the smallest unit of storage or retrieval in the icache, and its length is fixed. When the CPU needs to read a specific instruction, the icache doesn't just read that instruction; instead, it loads the entire cache line containing that instruction from memory into the icache. Because program execution exhibits locality of reference—for example, after executing instruction A, there's a high probability that adjacent instructions B and C will follow—loading the entire line at once reduces the number of subsequent memory reads, further lowering latency.

[0054] The first execution stage of the CPU pipeline is the instruction fetch stage, where the CPU pipeline reads the instruction to be executed from the instruction cache. The first instruction is the instruction fetched in the current instruction fetch stage that is about to enter the CPU decoding or execution stage. The second instruction is stored in the same cache line as the first instruction, and in the program execution sequence, the second instruction is the instruction immediately following the first instruction.

[0055] Instruction characteristics represent core information about the resources required for instruction execution, including at least the opcode (such as ADD, LD, or JMP) and operand types (such as register operands or memory operands). The opcode is used to determine the instruction type, and the operand type is used to help determine the details of resource calls. Instruction characteristics are the key index for subsequent lookups in the instruction-resource mapping table.

[0056] After the CPU initiates the instruction execution process, when the CPU enters the instruction fetch stage, the controller first works synchronously with the CPU's instruction fetch unit to obtain the first instruction to be executed. Then, it extracts features from the first instruction. The controller uses hardware circuitry to parse the binary code of the first instruction, separating the opcode and operand types, and temporarily stores the extracted features in a temporary register within the controller to ensure that the feature data can be quickly retrieved by subsequent steps.

[0057] The instruction cache-based cache line storage mechanism involves the controller sending an address lookup signal to the instruction cache while acquiring the first instruction's characteristics. Based on the storage address of the first instruction, the controller determines the cache line range in which it resides. For example, if the first instruction is stored at addresses 0x0000~0x0003, corresponding to cache line 0x0000~0x001F (32 bytes), the controller then reads all subsequent consecutive instructions within that cache line, excluding the first instruction, and identifies the second instruction that immediately follows the first instruction in the program execution sequence. Subsequently, the controller uses the same characteristic extraction logic as for the first instruction to parse the opcode and operand type of the second instruction, temporarily storing them along with the first instruction's characteristics. This completes the synchronous acquisition of instruction characteristics for both the currently executing instruction and the subsequently executing instructions.

[0058] By simultaneously acquiring the characteristics of the first and second instructions during the instruction fetch phase, the controller provides complete data support for resource prediction in subsequent steps, including both immediate and future demand, avoiding the predictive bias caused by relying on a single instruction. Furthermore, it leverages the instruction cache's cache line mechanism to pre-fetch the second instruction without adding extra CPU clock cycles, ensuring the solution's low latency. Simultaneously, the controller rapidly extracts instruction characteristics through hardware, avoiding the resource overhead of software parsing. This adapts to the low-power and high-real-time application requirements of MCUs, laying a precise and efficient data foundation for the entire power optimization solution.

[0059] In one possible implementation, to further reduce the amount of data processing for instruction features and meet the core requirements of low latency and low resource overhead for MCUs, after extracting the instruction features of the first and second instructions, the controller can standardize the opcode and operand types through fixed-length binary encoding. This reduces the data volume and improves the response speed of subsequent resource prediction without losing key feature information.

[0060] Specifically, the instruction characteristics include the opcode and operand type. After obtaining the instruction characteristics of the first instruction and the second instruction, the controller uses 8-bit binary encoding for the opcode of the first instruction and the opcode of the second instruction, and uses 4-bit binary encoding for the operand type of the first instruction and the operand type of the second instruction.

[0061] The opcode is a crucial part of the instruction's binary encoding, used to define the core operational function of the instruction. The opcode indicates what operation the instruction should perform, and then, through the instruction-resource mapping table, quickly matches the corresponding target resource module.

[0062] Operand type refers to the source, storage location, and data format of operands involved in computation or data transfer during instruction execution. In MCU instruction execution scenarios, common operand types include: register-register type (operands are all stored in general-purpose registers inside the CPU), register-memory type (one operand is stored in a register, and the other operand is stored in memory), immediate-register type (one operand is an immediate value included in the instruction, and the other operand is stored in a register), and memory-memory type (both operands are stored in memory).

[0063] In simple terms, operand type is essentially the source and interaction method of instruction data. By extracting and encoding this feature, the controller can more accurately determine the auxiliary resource modules required for instruction execution, avoiding resource misjudgment caused by relying solely on opcode prediction (e.g., looking only at the opcode LD cannot distinguish whether a computation module is needed, but combining the operand type can clarify this), thus providing a more comprehensive basis for accurate prediction of the target resource module.

[0064] After the controller synchronously acquires the first and second instructions during the instruction fetch phase, it first parses the binary structure of the two instructions through its internal feature extraction circuit, separating their respective opcodes and operand types. Subsequently, the controller invokes the pre-stored encoding mapping relationship within the controller, performing 8-bit binary encoding on the opcode (e.g., mapping "ADD" to "00000001" and "LD" to "00000010," covering 256 commonly used instruction types in MCUs), and performing 4-bit binary encoding on the operand type (e.g., mapping "register-register" to "0001" and "memory-register" to "0010," covering all common operand combinations). The entire encoding process is directly completed by the hardware circuit without software intervention, and it ends synchronously with feature extraction within one CPU clock cycle. The encoded 12-bit feature data (8-bit opcode + 4-bit operand type) is temporarily stored in a dedicated register of the controller, which can be directly used as a lookup index for the instruction-resource mapping table in subsequent steps. This ensures data standardization and avoids the redundant processing overhead of unencoded features.

[0065] S102: Based on the instruction-resource mapping table, the controller predicts at least one target resource module to be called by the CPU pipeline within a certain number of cycles, according to the instruction characteristics of the first instruction and the instruction characteristics of the second instruction.

[0066] The instruction-resource mapping table is a hardware storage table preset in the embodiments of this application. It can be stored in the CPU's internal configurable registers or read-only memory. The instruction-resource mapping table is used to represent the one-to-one correspondence between instruction features and resource modules. Among them, the instruction features are indexed by a combination of opcode and operand type, and the resource modules are the core functional units of the CPU pipeline. The table can be customized and modified according to the MCU application scenario, and it is the core basis for realizing rapid matching of resource requirements.

[0067] As an example, the instruction-resource mapping table can be shown in the following table.

[0068] Table 1: Command and Resource Mapping Table

[0069]

[0070] The target resource module refers to the resource module that must be activated within the next few CPU cycles based on the execution requirements of the current and subsequent instructions.

[0071] A CPU pipeline is a parallel processing unit within the CPU, divided according to the instruction execution flow, and consists of multiple functionally independent resource modules. This application's embodiments achieve fine-grained power consumption control at the pipeline level by accurately predicting the target resource modules.

[0072] The controller retrieves a pre-defined instruction-resource mapping table from its internal storage. Using the first instruction characteristic as an index, it queries the resource module corresponding to that characteristic in the mapping table. For example, if the opcode of the first instruction is an integer addition instruction (ADD) and the operand type is "register-register", the query result is an arithmetic logic unit (ALU), indicating that the target resource module required for the execution of the first instruction is the ALU. Similarly, using the second instruction characteristic as an index, the controller queries the mapping table. If the opcode of the second instruction is a load instruction (LD) and the operand type is "memory-register", the query result is a load / store unit, indicating that the target resource module required for the execution of the second instruction is the load / store unit.

[0073] Subsequently, the controller merges the results of the two queries. The controller integrates the arithmetic logic unit corresponding to the first instruction with the load / store unit corresponding to the second instruction, forming the set of target resource modules that the CPU pipeline needs to call in the next two CPU cycles. During this process, the controller does not require additional complex calculations; it completes the prediction solely through lightweight logic of feature indexing and mapping queries, avoiding excessive hardware resource consumption or increased execution latency, thus meeting the low-overhead and high-real-time requirements of the MCU.

[0074] This application embodiment establishes a direct association between instruction features and resource modules through an instruction-resource mapping table. By combining the instruction features of the first and second instructions, it completes multi-cycle resource demand prediction, clearly identifying the target resource modules that need to be retained and avoiding functional errors caused by blindly shutting down modules. Simultaneously, the lightweight prediction logic ensures low latency and low overhead, fitting the MCU's hardware architecture and application scenarios, achieving a balance between prediction accuracy and execution efficiency.

[0075] To further improve the accuracy of target resource module prediction and avoid prediction biases in scenarios such as branch instructions and loop instructions caused by relying solely on instruction features, this application embodiment adds a historical execution record-assisted decision-making mechanism during the target resource module prediction process. By combining the historical execution records of the first and second instructions with instruction features, resource prediction is completed collaboratively, ensuring that the prediction results more closely match actual execution needs. The specific implementation process is as follows:

[0076] The controller predicts at least one target resource module to be called by the CPU pipeline when executing the first instruction, based on the instruction characteristics of the first instruction and the historical execution record of the first instruction; and the controller predicts at least one target resource module to be called by the CPU pipeline when executing the second instruction, based on the instruction characteristics of the second instruction and the historical execution record of the second instruction. The historical execution record includes the jump pattern of the program counter for each instruction.

[0077] After acquiring the instruction characteristics of the first and second instructions, the controller first retrieves the historical execution records of each instruction from the internal storage unit. The historical execution record of the first instruction includes the jump patterns of the program counter when the instruction was executed in the past, such as whether a branch jump is likely to be triggered after executing the first instruction, and the distribution of jump target addresses. The historical execution record of the second instruction is executed similarly. For the first instruction, the controller combines its instruction characteristics and jump patterns to determine the branch predictor, address generation unit, and resource modules required by the instruction corresponding to the target address, thus determining the set of target resource modules corresponding to the first instruction. For the second instruction, the same logic is used, combining its instruction characteristics and historical jump patterns to ultimately integrate the target resource modules corresponding to the two instructions, forming a set of target resource modules that the CPU pipeline needs to call within several cycles. The entire prediction process, through the collaborative logic of determining basic resources based on instruction characteristics and supplementing scenario resources with historical jump patterns, ensures both the comprehensiveness of the prediction and improves the prediction accuracy in complex instruction scenarios.

[0078] To accurately cover resource requirements in branch instruction scenarios and avoid missing resources needed for subsequent instructions due to branch jumps, this application further refines the prediction logic for branch instructions. The controller, through basic resource querying and target address prefetching analysis, fully identifies the resource modules directly and indirectly dependent on during the execution of branch instructions, ensuring no omissions in the prediction results. The specific implementation process is as follows:

[0079] The controller queries the instruction-resource mapping table and determines the resource modules that the instruction directly depends on as the target resource modules based on the instruction characteristics. The controller combines the jump patterns of the program counter when executing branch instructions in the past to predict the target address of the branch instruction, and prefetches the instruction corresponding to the target address from the instruction cache to determine the resource modules required by the prefetched instruction as the target resource modules.

[0080] In this embodiment, the instruction is either a first instruction or a second instruction. When the controller performs prediction for the first instruction or the second instruction (hereinafter collectively referred to as the instruction), it first uses the instruction characteristics of the current instruction as an index to query the instruction-resource mapping table to determine the resource modules that the current instruction directly depends on. If the current instruction is a branch instruction, the directly dependent resource modules are the branch predictor and the address generation unit, which are included in the target resource module set. Subsequently, the controller retrieves the jump pattern of the program counter when executing the branch instruction in the past, prioritizes predicting the target address with the highest probability, and sends a prefetch request to the instruction cache to read the prefetch instruction corresponding to the target address. The controller parses the instruction characteristics of the prefetch instruction, determines that it needs to call the multiplier by querying the instruction-resource mapping table, and then adds the multiplier to the target resource module set. If the current instruction is a non-branch instruction (such as an ADD instruction or an LD instruction), only the first step of basic resource query is performed, and no target address prefetching is required, ultimately forming the complete target resource module set required for the execution of the current instruction.

[0081] S103: The controller controls the shutdown of all resource modules in the CPU except for at least one target resource module.

[0082] After determining the target resource module set, the controller iterates through and identifies all resource modules in the CPU pipeline. The controller marks the target resource modules as enabled and the remaining resource modules as pending shutdown, clearly defining the classification boundaries of resource module management and avoiding instruction execution anomalies due to incorrect resource module identification.

[0083] Subsequently, the controller generates corresponding control signals based on the type of resource module to be shut down and the power consumption optimization requirements. For resource modules that only require reduced dynamic power consumption, the controller generates a clock gating signal and sends it to the corresponding clock gating circuit, which cuts off the clock input of the resource module through circuit logic. The resource module stops clock toggling and no longer generates invalid power consumption, but retains its internal register state, allowing for rapid wake-up. For resource modules requiring deep power reduction, the controller generates a power gating signal and sends it to the corresponding power gating circuit, cutting off the power supply path to the resource module. The resource module enters a deep low-power state, while the controller temporarily stores key state information before the module shuts down, preparing for subsequent wake-up.

[0084] The transmission and execution of control signals are completed synchronously within one CPU cycle and only apply to the module to be shut down. The clock signals and power supply of the resource modules are not affected, ensuring that they can respond normally to instruction execution requirements and avoiding interference with the execution rhythm of the CPU pipeline caused by control operations.

[0085] This application's embodiments solve the problems of coarse-grained control and wasted power consumption during idle periods in existing technologies by precisely shutting down non-target resource modules, directly cutting off the sources of ineffective power consumption for idle modules, and significantly improving CPU power utilization efficiency. Simultaneously, through the flexible selection of clock gating and power gating, the control intensity can be dynamically adjusted according to the module's idle time and power consumption requirements, balancing power optimization and module wake-up efficiency. Furthermore, this step achieves module control solely through hardware control signals, without software intervention or additional CPU computing resources, making it suitable for low-overhead, high-real-time MCU application scenarios, ensuring maximum reduction in CPU power consumption without affecting normal instruction execution.

[0086] To achieve precise adaptation to different power optimization scenarios, this application further refines the hierarchical control logic for shutting down non-target resource modules. The controller flexibly selects either clock gating or power gating hardware control methods based on the idle requirements of the module to be shut down, ensuring power optimization while also considering module wake-up efficiency and state stability. The specific implementation process is as follows:

[0087] If it is necessary to reduce the dynamic power consumption of other resource modules, the controller cuts off the clock signal of other resource modules through the clock gating circuit; if it is necessary to reduce the static power consumption of other resource modules, the controller cuts off the power supply of other resource modules through the power gating circuit.

[0088] After marking other resource modules to be shut down, the controller first analyzes the idle characteristics of each module. If a resource module is only temporarily idle (e.g., it may be woken up in the next few CPU cycles), and priority should be given to reducing the ineffective power consumption caused by clock flips, i.e., reducing dynamic power consumption, the controller generates a clock gating control signal and sends it to the clock gating circuit of the corresponding resource module. The circuit logic blocks the transmission of the clock signal to the resource module, causing the resource module to stop clock-driven logic operations and state flips, retaining only the original state of its internal registers, and entering a low-dynamic-power standby state.

[0089] If a resource module is idle for an extended period (e.g., no call requirement within multiple instruction cycles) and it is necessary to significantly reduce the continuous power consumption caused by leakage current, i.e., reduce static power consumption, the controller generates a power gating control signal and sends it to the power gating circuit of the corresponding resource module. This cuts off the power supply path to the resource module, causing it to enter a completely power-off, low static power consumption state. Simultaneously, the controller uses an internal temporary storage unit to synchronously save the core state information of the module before shutdown, providing support for quickly restoring the working state upon subsequent wake-up.

[0090] The control signals for both gating methods are generated and executed in real time by hardware circuits without software intervention, and can be flexibly switched according to the dynamic changes in the module's idle state, ensuring the accuracy and flexibility of power consumption management.

[0091] To further enhance the robustness of the solution and avoid instruction execution anomalies caused by target resource module prediction errors, this embodiment can also dynamically detect the matching between the prediction results and actual execution requirements. Once a target resource prediction error is detected, a module recovery operation is triggered to ensure stable operation of the CPU pipeline. The specific implementation process is as follows:

[0092] If a target resource module prediction error is detected, the controller immediately cancels the control signal to the target resource module with the prediction error and restores the clock signal and power supply to the target resource module with the prediction error.

[0093] After shutting down non-target resource modules, the controller synchronously initiates a prediction error detection mechanism to monitor the resource call status during instruction execution in real time. If it detects that the instruction to be executed actually depends on a closed resource module, such as a prefetched instruction being a multiplication instruction but the multiplier being mistakenly identified as a non-target module that has been shut down, or the actual jump address of the program counter being inconsistent with the target address predicted in step S102, causing the prefetched resource to fail, then it is determined that the target resource module prediction is incorrect.

[0094] At this point, the controller generates a revocation control signal and sends it to the clock gating circuit and power gating circuit corresponding to the mistakenly shut-down module, simultaneously revoking the previously issued shutdown signal. The clock gating circuit restores the clock signal input to the resource module, and the power gating circuit restores the power supply path to the resource module. Simultaneously, the controller quickly loads the core state information temporarily stored before the module shutdown, ensuring that the module recovers to its normal operating state within one CPU cycle, promptly responding to instruction execution requirements, avoiding instruction execution interruptions or errors due to module shutdown, and ensuring the continuous and stable operation of the CPU pipeline.

[0095] To achieve dynamic continuity of power consumption optimization and adapt to the continuous execution characteristics of instruction streams, after each CPU cycle of instruction execution is completed, the controller updates the prediction results of the instruction and target resource modules, and wakes up the modules that have been turned off for the new prediction, ensuring that power consumption optimization and instruction execution requirements are matched in real time.

[0096] After completing the instruction execution of one CPU cycle, the controller takes the second instruction as the new first instruction, reads the next instruction in the same cache line of the second instruction as the new second instruction, reacquires the instruction characteristics of the new first instruction and the new second instruction, and predicts the new target resource module.

[0097] If the new target resource module includes a closed resource module, a wake-up signal is generated to control the closed resource module to resume normal operation.

[0098] Once the instruction execution of a CPU cycle is complete, i.e., the original first instruction has finished executing, the controller automatically triggers the instruction update process. The controller upgrades the second instruction in the original step S101 to a new first instruction, and at the same time, based on the instruction cache line storage mechanism, reads the next consecutive instruction in the cache line where the new first instruction (the original second instruction) is located, and uses it as the new second instruction.

[0099] Subsequently, the controller repeats steps S101 and S102, predicting the new target resource module set required in the next new cycle based on the instruction characteristics of the new first instruction and the new second instruction. If the new target resource module set includes resource modules that have been previously disabled, such as a multiplier that was not originally a target module being included in the new prediction, the controller immediately generates a wake-up signal and sends it to the clock gating circuit and power gating circuit corresponding to that module, canceling the shutdown control signal to restore the clock signal or power supply. At the same time, it loads the state information temporarily stored before the module was disabled, allowing the module to quickly return to normal working state. For other resource modules that are still not target resource modules in the new prediction, they remain disabled to continuously reduce power consumption. The entire update and wake-up process is completed within one CPU cycle, without affecting the continuous execution of the instruction stream, achieving dynamic looping for power optimization.

[0100] This application also provides a CPU power consumption optimization device based on instruction prediction, such as... Figure 2 As shown, the device includes:

[0101] The acquisition module 201 is used to acquire the instruction characteristics of the first instruction to be executed during the instruction fetching stage of CPU instruction execution, and to read the instruction characteristics of the second instruction in the same cache line from the instruction cache in advance; the second instruction is the instruction to be executed after the first instruction is executed;

[0102] The prediction module 202 is used to predict at least one target resource module to be called by the CPU pipeline within a certain number of cycles based on the instruction and resource mapping table, according to the instruction characteristics of the first instruction and the instruction characteristics of the second instruction; the instruction and resource mapping table is used to indicate the correspondence between instruction characteristics and resource modules.

[0103] The control module 203 is used to control the shutdown of other resource modules in the CPU besides the at least one target resource module.

[0104] In one possible implementation, the prediction module 202 is specifically used to predict, based on the instruction characteristics of the first instruction and the historical execution record of the first instruction, at least one target resource module to be called by the CPU pipeline when executing the first instruction; the historical execution record includes the jump pattern of the program counter for the instruction; and to predict, based on the instruction characteristics of the second instruction and the historical execution record of the second instruction, at least one target resource module to be called by the CPU pipeline when executing the second instruction.

[0105] In one possible implementation, the prediction module 202 is specifically used to query the instruction-resource mapping table, determine the resource module that the instruction directly depends on as the target resource module based on the instruction characteristics of the instruction; the instruction is the first instruction or the second instruction; combine the jump pattern of the branch instruction when the program counter executes the branch instruction in the past, predict the target address of the branch instruction, prefetch the instruction corresponding to the target address from the instruction cache, and determine the resource module required for the prefetched instruction as the target resource module.

[0106] In one possible implementation, the acquisition module 201 is further configured to, after completing the instruction execution of one CPU cycle, take the second instruction as a new first instruction, read the next instruction in the same cache line of the second instruction as a new second instruction, reacquire the instruction characteristics of the new first instruction and the new second instruction, and predict a new target resource module; if the new target resource module includes a closed resource module, generate a wake-up signal to control the closed resource module to resume normal operation.

[0107] In one possible implementation, the instruction features include at least an opcode and an operand type;

[0108] The acquisition module 201 is further configured to use 8-bit binary encoding for the opcode of the first instruction and the opcode of the second instruction, and to use 4-bit binary encoding for the operand type of the first instruction and the operand type of the second instruction.

[0109] In one possible implementation, the control module 203 is specifically used to cut off the clock signal of the other resource modules through a clock gating circuit if it is necessary to reduce the dynamic power consumption of the other resource modules; and to cut off the power supply of the other resource modules through a power gating circuit if it is necessary to reduce the static power consumption of the other resource modules.

[0110] In one possible implementation, the control module 203 is further configured to, if a target resource module prediction error is detected, immediately cancel the control signal for the target resource module with the prediction error, and restore the clock signal and power supply of the target resource module with the prediction error.

[0111] This application also provides a control device. The control device may include a memory and a processor. The processor is used to execute the CPU power consumption optimization method based on instruction prediction as described in any of the above embodiments. The memory may be random access memory (RAM), flash memory, read-only memory (ROM), non-volatile read-only memory (EPROM), registers, hard disk, removable disk, etc.

[0112] Memory can store computer instructions. When these instructions are executed by the processor, the processor can use them to perform CPU power optimization methods based on instruction prediction. Memory can also store data.

[0113] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape) or a semiconductor medium (e.g., solid-state disk (SSD)).

[0114] This application also provides a readable storage medium for storing the methods provided in the above embodiments. For example, RAM, flash memory, ROM, EPROM, registers, hard disk, removable disk, or any other form of storage medium in the art.

[0115] In the embodiments of this application, the terms "first" and "second" (if they exist) are used only as name identifiers and do not represent the order of first and second.

[0116] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Regarding the methods disclosed in the embodiments, since they correspond to the product embodiments disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the description of the product embodiments.

[0117] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A CPU power consumption optimization method based on instruction prediction, characterized in that, The method includes: During the instruction fetching phase of CPU execution, the instruction characteristics of the first instruction to be executed are obtained, and the instruction characteristics of the second instruction in the same cache line are read in advance from the instruction cache; the second instruction is the instruction to be executed after the first instruction is executed. Based on the instruction-resource mapping table, and according to the instruction characteristics of the first instruction and the instruction characteristics of the second instruction, at least one target resource module to be called by the CPU pipeline within a certain number of cycles is predicted; the instruction-resource mapping table is used to indicate the correspondence between instruction characteristics and resource modules. Control the shutdown of all resource modules in the CPU except for the at least one target resource module; The step of predicting at least one target resource module to be called by the CPU pipeline within a number of cycles based on the instruction characteristics of the first instruction and the instruction characteristics of the second instruction includes: Based on the instruction characteristics of the first instruction and the historical execution record of the first instruction, predict at least one target resource module to be called by the CPU pipeline when executing the first instruction; the historical execution record includes the jump pattern of the program counter for the instruction; Based on the instruction characteristics of the second instruction and the historical execution record of the second instruction, predict at least one target resource module to be called by the CPU pipeline when executing the second instruction.

2. The method according to claim 1, characterized in that, Based on the instruction characteristics and historical execution records, predict at least one target resource module that the CPU pipeline will call during instruction execution, including: The instruction and resource mapping table is queried, and the resource module that the instruction directly depends on is determined as the target resource module based on the instruction characteristics of the instruction; the instruction is either the first instruction or the second instruction. Based on the jump patterns of the program counter when executing branch instructions in the past, the target address of the branch instruction is predicted, and the instruction corresponding to the target address is prefetched from the instruction cache. The resource module required for the prefetched instruction is then determined as the target resource module.

3. The method according to claim 1, characterized in that, The method further includes: After completing the instruction execution of one CPU cycle, the second instruction is used as the new first instruction, the next instruction in the same cache line of the second instruction is read as the new second instruction, the instruction characteristics of the new first instruction and the new second instruction are re-acquired, and the new target resource module is predicted. If the new target resource module includes a closed resource module, a wake-up signal is generated to control the closed resource module to resume normal operation.

4. The method according to claim 1, characterized in that, The instruction features include at least an opcode and an operand type; After obtaining the instruction features of the first instruction and the instruction features of the second instruction, the method further includes: The opcodes of the first instruction and the second instruction are encoded using 8-bit binary encoding, and the operand types of the first instruction and the second instruction are encoded using 4-bit binary encoding.

5. The method according to claim 1, characterized in that, The control of shutting down other resource modules in the CPU besides the at least one target resource module includes: If it is necessary to reduce the dynamic power consumption of the other resource modules, the clock signal of the other resource modules can be cut off through the clock gating circuit; If it is necessary to reduce the static power consumption of the other resource modules, the power supply to the other resource modules can be cut off through the power gating circuit.

6. The method according to claim 1, characterized in that, The method further includes: If a target resource module prediction error is detected, the control signal for the target resource module with the prediction error is immediately withdrawn, and the clock signal and power supply of the target resource module with the prediction error are restored.

7. A CPU power consumption optimization device based on instruction prediction, characterized in that, The device includes: The fetch module is used to obtain the instruction characteristics of the first instruction to be executed during the instruction fetching phase of CPU execution, and to pre-read the instruction characteristics of the second instruction in the same cache line from the instruction cache; the second instruction is the instruction to be executed after the first instruction is executed; The prediction module is used to predict at least one target resource module to be called by the CPU pipeline within a certain number of cycles, based on the instruction and resource mapping table and according to the instruction characteristics of the first instruction and the second instruction; the instruction and resource mapping table is used to indicate the correspondence between instruction characteristics and resource modules. The control module is used to control the shutdown of other resource modules in the CPU besides the at least one target resource module; The prediction module is specifically used to predict, based on the instruction characteristics of the first instruction and the historical execution record of the first instruction, at least one target resource module to be called by the CPU pipeline when executing the first instruction; the historical execution record includes the jump pattern of the program counter for the instruction; and to predict, based on the instruction characteristics of the second instruction and the historical execution record of the second instruction, at least one target resource module to be called by the CPU pipeline when executing the second instruction.

8. A control device, characterized in that, The system includes a processor and a memory, wherein the memory is used to store programs, instructions, or code, and the processor is used to execute the programs, instructions, or code in the memory to perform the CPU power consumption optimization method based on instruction prediction as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The system contains a computer program that is loaded by a processor to execute the CPU power consumption optimization method based on instruction prediction as described in any one of claims 1-6.

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