Resource utilization rate improving method and system applied to reconfigurable spaceborne computer
By improving the LDPC encoding and decoding algorithms, the problem of data errors in high-density NAND Flash in spaceborne storage systems was solved, improving data reliability and resource utilization, and optimizing the storage performance of spaceborne computers.
Patent Information
- Application Number
- CN202511498280.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-20
- Publication Date
- 2026-01-23
AI Technical Summary
High-density NAND Flash memory in spaceborne storage systems is prone to data errors caused by threshold voltage fluctuations or drift, which reduces data reliability. Existing error correction algorithms are difficult to effectively correct these errors, thus affecting resource utilization.
The coding algorithm is improved to LDPC coding by adopting two-dimensional interleaving technology, and the decoding algorithm is improved to LDPC decoding by combining hyperbolic tangent function and inverse hyperbolic tangent function, thereby enhancing data reliability and decoding performance.
It improved the resource utilization of onboard computers, enhanced the reliability of data storage and the overall performance of the storage system, optimized resource use, and ensured the smooth progress of space missions.
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Figure CN121387622A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of data processing, and in particular to a resource utilization rate improvement method and system applied to a reconfigurable spaceborne computer, an electronic device and a storage medium. BACKGROUND
[0002] The development of a spaceborne storage system is closely related to the development of a spaceborne data storage medium. The development of the medium has experienced a process from a tape drive, SRAM, SDRAM to NAND Flash. NAND Flash has the characteristics of non-volatility, high performance capacity per unit area, etc., and is the preferred medium for current spaceborne data storage.
[0003] However, with the continuous development of NAND Flash storage media, new generations of NAND Flash with higher storage density are emerging in an endless stream. However, due to its own characteristics, NAND Flash with high storage density usually adopts multiple threshold voltages in a storage cell for data storage. With the increase of storage density, the number of threshold voltages in a cell will also increase. Therefore, NAND Flash with high storage density is more prone to data errors caused by threshold voltage fluctuations or drift, thereby reducing the reliability of data. However, NAND Flash with high storage density can greatly improve the storage capacity of a spaceborne storage system, and reduce the size and power consumption of the system. Since the spaceborne storage system has a high requirement for data reliability, solving the problem of data storage reliability is the key to the application of high storage density NAND Flash in aerospace.
[0004] Therefore, it is urgent to develop a resource utilization rate improvement method and system applied to a reconfigurable spaceborne computer, an electronic device and a storage medium to solve one or more of the above problems. SUMMARY
[0005] In view of this, to solve the above technical problems or part of the technical problems, the embodiments of the present application provide a resource utilization rate improvement method and system applied to a reconfigurable spaceborne computer, an electronic device and a storage medium.
[0006] In a first aspect, the present application provides a resource utilization rate improvement method applied to a reconfigurable spaceborne computer, the method comprising:
[0007] obtaining a original encoding algorithm and a original decoding algorithm corresponding to a original error correction algorithm;
[0008] The original encoding algorithm is improved by the two-dimensional interleaving technology to obtain a target encoding algorithm, and the target encoding algorithm is an LDPC encoding algorithm.
[0009] The original decoding algorithm is improved by using hyperbolic tangent function and inverse hyperbolic tangent function, and a target decoding algorithm is obtained, which is an LDPC decoding algorithm.
[0010] In one possible implementation, the method further includes:
[0011] obtaining an error correction strategy of the original error correction algorithm and an error type targeted by the error correction strategy;
[0012] obtaining an encoding rule and a decoding rule corresponding to the original error correction algorithm according to the error correction strategy and the error type targeted by the error correction strategy;
[0013] deriving an original encoding algorithm corresponding to the original error correction algorithm based on the encoding rule;
[0014] deriving an original decoding algorithm corresponding to the original error correction algorithm based on the error correction strategy and the decoding rule.
[0015] In one possible implementation, the method further includes:
[0016] analyzing a first evaluation score of the original encoding algorithm and the original decoding algorithm respectively by using a mathematical tool;
[0017] in a case where the first evaluation score does not meet a preset first evaluation standard, re-executing the step of obtaining the original encoding algorithm and the original decoding algorithm corresponding to the original error correction algorithm;
[0018] in a case where the first evaluation score meets the preset first evaluation standard, generating test data and applying the test data to the original encoding algorithm and the original decoding algorithm to obtain a second evaluation score of the original encoding algorithm and the original decoding algorithm;
[0019] in a case where the second evaluation score does not meet a preset second evaluation standard, re-executing the step of obtaining the original encoding algorithm and the original decoding algorithm corresponding to the original error correction algorithm.
[0020] In one possible implementation, the deriving of the original encoding algorithm corresponding to the original error correction algorithm based on the encoding rule includes:
[0021] determining a basic unit and an encoding structure of the original error correction algorithm encoding based on the encoding rule;
[0022] determining a mapping relationship of information in the encoding structure to code after encoding;
[0023] combing the mapping relationship and the basic unit of the original error correction algorithm encoding to obtain the original encoding algorithm corresponding to the original error correction algorithm.
[0024] In a possible implementation, the deriving the original decoding algorithm corresponding to the original error correction algorithm based on the error correction strategy and the decoding rule comprises:
[0025] setting an initial state of the compiler;
[0026] applying the decoding rule of the original decoding algorithm to the compiler based on the initial state of the compiler, and performing iterative decoding, wherein the value of each node is adjusted according to the received node state and the decoding algorithm result of the last iteration in each iteration;
[0027] outputting the original decoding algorithm when the iterative decoding reaches a decoding convergence condition.
[0028] In a possible implementation, the original encoding algorithm is improved by the two-dimensional interleaving technology to obtain a target encoding algorithm, and the target encoding algorithm is an LDPC encoding algorithm, which comprises:
[0029] interleaving the original encoding algorithm according to a preset two-dimensional interleaving rule to obtain an interleaved interleaving algorithm;
[0030] performing LDPC encoding on the interleaving algorithm according to an encoding rule of the LDPC encoding algorithm to obtain the target encoding algorithm.
[0031] In a possible implementation, the original decoding algorithm is improved by the hyperbolic tangent function and the inverse hyperbolic tangent function to obtain a target decoding algorithm, and the target decoding algorithm is an LDPC decoding algorithm, which comprises:
[0032] performing approximate processing on the hyperbolic tangent function and the inverse hyperbolic tangent function in the original decoding algorithm by using minimum addition and sign multiplication;
[0033] performing improvement processing on the original decoding algorithm according to the function after the approximate processing to obtain the target decoding algorithm.
[0034] In a second aspect, the present application provides a resource utilization rate improvement system applied to a reconfigurable spaceborne computer, which comprises:
[0035] an acquisition module configured to acquire an original encoding algorithm and an original decoding algorithm corresponding to an original error correction algorithm;
[0036] a first improvement module configured to improve the original encoding algorithm by the two-dimensional interleaving technology to obtain a target encoding algorithm, and the target encoding algorithm is an LDPC encoding algorithm;
[0037] a second improvement module configured to improve the original decoding algorithm by the hyperbolic tangent function and the inverse hyperbolic tangent function to obtain a target decoding algorithm, and the target decoding algorithm is an LDPC decoding algorithm.
[0038] In a third aspect, the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method for improving resource utilization of a reconfigurable spaceborne computer according to any one of the embodiments of the first aspect when executing the computer program.
[0039] In a fourth aspect, the present application further provides a computer storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method for improving resource utilization of a reconfigurable spaceborne computer according to any one of the embodiments of the first aspect.
[0040] The above technical solution provided by the embodiments of the present application has the following advantages compared with the prior art: the method provided by the embodiments of the present application further comprises introducing an error detection and correction mechanism in the improved encoding algorithm and decoding algorithm to enhance the reliability of data, aiming at the data error problem caused by threshold voltage fluctuation or drift of the NAND Flash with high storage density. In addition, the decoding performance is improved and the data error rate is reduced by using the amplitude information of the received signal. BRIEF DESCRIPTION OF DRAWINGS
[0041] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.
[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, those drawings can also provide other drawings for those skilled in the art without any creative effort.
[0043] One or more embodiments are exemplarily illustrated by pictures in the drawings corresponding thereto, and these exemplary illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, unless otherwise specified. The drawings in the drawings do not constitute a proportional limitation.
[0044] Figure 1 A flowchart of a method for improving resource utilization of a reconfigurable spaceborne computer provided by the embodiments of the present application is shown in the figure;
[0045] Figure 2 A flowchart of obtaining an original encoding algorithm and an original decoding algorithm provided by the embodiments of the present application is shown in the figure;
[0046] Figure 3 A flowchart of derivation of an original encoding algorithm provided by the embodiments of the present application is shown in the figure, asFigure 3 as shown in
[0047] Figure 4 A flowchart of the original decoding algorithm derivation provided by the embodiment of the present application is shown in Figure 4
[0048] Figure 5 A basic structure diagram of the NAND Flash memory unit provided by the embodiment of the present application is shown in
[0049] Figure 6 A 2D interleaved LDPC error correction algorithm architecture diagram provided by the embodiment of the present application is shown in
[0050] Figure 7 A cyclic matrix Z diagram provided by the embodiment of the present application is shown in
[0051] Figure 8 A structure diagram of a resource utilization rate improvement system applied to a reconfigurable spaceborne computer provided by the embodiment of the present application is shown in
[0052] Figure 9 A structure diagram of an electronic device provided by the embodiment of the present application is shown in Figure 9 DETAILED DESCRIPTION
[0053] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.
[0054] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplifying the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to numbers and / or letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.
[0055] Currently, the error correction algorithm used in storage systems is mostly linear block code. Commonly used linear block codes include BCH error correction code, RS error correction code, LDPC error correction code, etc. Initially, BCH error correction algorithm is usually used to correct errors of disk and tape drives. With the development of solid-state storage media, the storage density is getting higher and higher, and the probability of data storage error is also increasing. Therefore, it is difficult for pure BCH error correction code to effectively correct errors, so new error correction algorithms such as RS error correction code and LDPC error correction code are extended. Currently, SCL type NAND Flash is mostly used in satellite-borne storage systems, and RS(256, 252) error correction algorithm is mostly used for error correction, which can correct two errors in every 256 bytes. However, for storage media with high storage density such as TLC and QLC, RS(256, 252) error correction algorithm is also difficult to effectively correct errors. Therefore, this paper studies LDPC error correction code. LDPC code is a kind of error correction coding with error correction performance close to Shannon limit, and has been widely used in various storage systems and communication systems. The 2D interleaving LDPC error correction algorithm designed in this application mainly includes two steps of encoding algorithm design and decoding algorithm design.
[0056] Figure 1 A flowchart of a resource utilization rate improvement method applied to a reconfigurable satellite computer is provided in this embodiment, as shown in Figure 1 The method specifically includes the following steps.
[0057] S101, obtaining an original encoding algorithm and an original decoding algorithm corresponding to an original error correction algorithm;
[0058] The original encoding algorithm and the original decoding algorithm work together to ensure the accuracy and reliability of data transmission. The original encoding algorithm is responsible for converting the original data into a format suitable for transmission, and the original decoding algorithm restores these formats into the original data at the data receiving end.
[0059] In this embodiment, in order to achieve a deep understanding and further optimization and improvement of the original error correction algorithm, the original encoding algorithm and the original decoding algorithm corresponding thereto are obtained. By analyzing the two algorithms in detail, possible problems are found and corresponding improvement measures are proposed to improve the performance of the entire error correction system.
[0060] S102, improving the original encoding algorithm by using the two-dimensional interleaving technology to obtain a target encoding algorithm, the target encoding algorithm being an LDPC encoding algorithm;
[0061] In this embodiment, the original encoding algorithm is effectively improved and optimized by using the two-dimensional interleaving technology to obtain a target encoding algorithm. The target encoding algorithm has higher performance and efficiency, and is a low-density parity check (LDPC) encoding algorithm.
[0062] S103, the original decoding algorithm is improved by hyperbolic tangent function and inverse hyperbolic tangent function, and a target decoding algorithm is obtained, the target decoding algorithm is an LDPC decoding algorithm.
[0063] In the embodiment, the original decoding algorithm is improved and optimized by applying hyperbolic tangent function (tanh) and its inverse function, i.e. inverse hyperbolic tangent function (artanh), and a new target decoding algorithm is obtained, which has specific performance and characteristics, and is a Low-Density Parity-Check (LDPC) decoding algorithm.
[0064] The resource utilization rate improvement method applied to the reconfigurable satellite computer provided in the embodiment is applied to the reconfigurable satellite computer to improve the resource utilization rate, specifically by integrating the improved LDPC encoding algorithm and LDPC decoding algorithm into the storage system of the reconfigurable satellite computer, effectively managing the high storage density NAND Flash, enhancing the reliability of data, and improving the overall performance of the storage system, which is helpful for optimizing the use of system resources in the resource-limited satellite environment and ensuring the smooth progress of space missions.
[0065] Figure 2 The flowchart for obtaining the original encoding algorithm and the original decoding algorithm provided in the embodiment of the application, the original error correction algorithm corresponding to the original encoding algorithm and the original decoding algorithm, comprises:
[0066] S201, obtaining an error correction strategy of an original error correction algorithm and an error type to which the error correction strategy is directed;
[0067] In the embodiment, the analyzed error correction strategy and the error type to which it is directed are summarized to obtain the basic principle of the algorithm, detailed error correction strategy description (including specific operation steps, mathematical formulas, etc.), error type and cause analysis, experimental verification results, etc. At the same time, the advantages and disadvantages of the algorithm are evaluated, and possible improvement direction and optimization suggestions are proposed to provide comprehensive reference for subsequent algorithm research, application and improvement.
[0068] S202, obtaining an encoding rule and a decoding rule corresponding to the original error correction algorithm according to the error correction strategy and the error type to which the error correction strategy is directed;
[0069] In the embodiment, the encoding rule and the decoding rule corresponding to the original error correction algorithm are derived according to the proposed error correction scheme and the error category to which the scheme is directed.
[0070] S203, derive a original encoding algorithm corresponding to the original error correction algorithm based on the encoding rule;
[0071] In the embodiment, by studying the encoding rule, the original encoding algorithm relied on by the original error correction algorithm is gradually derived and reconstructed. Specifically, the principle and application background of the error correction algorithm are analyzed and logically inferred, the encoding logic hidden behind the error correction mechanism is revealed, and the original encoding algorithm is recovered, which not only helps to optimize the existing error correction algorithm, but also provides valuable reference for developing new encoding technology.
[0072] S204, derive a original decoding algorithm corresponding to the original error correction algorithm based on the error correction strategy and the decoding rule.
[0073] In the embodiment, on the basis of deeply discussing the error correction strategy and the decoding rule, the original decoding algorithm corresponding to the original error correction algorithm is further derived and understood.
[0074] The method for improving resource utilization rate applied to the reconfigurable satellite computer provided by the embodiment of the application realizes in-depth understanding and improvement of the original encoding algorithm and the original decoding algorithm by comprehensively analyzing and optimizing the error correction strategy, the encoding rule and the decoding rule of the original error correction algorithm. Specifically, first, the error types to which the original error correction algorithm is directed are determined, and then the corresponding encoding and decoding rules are derived according to the error types. On this basis, the original encoding algorithm is recovered through detailed research on the encoding rule, and the original decoding algorithm is derived through the decoding rule and the error correction strategy, which not only ensures the accuracy and reliability of the algorithm derivation, but also provides a solid foundation for subsequent algorithm improvement and optimization.
[0075] In an optional scheme of the embodiment of the application, the method further includes:
[0076] using a mathematical tool to analyze a first evaluation score of the original encoding algorithm and the original decoding algorithm respectively;
[0077] in a case where the first evaluation score does not satisfy a preset first evaluation standard, re-executing the step of obtaining the original encoding algorithm and the original decoding algorithm corresponding to the original error correction algorithm;
[0078] in a case where the first evaluation score satisfies the preset first evaluation standard, generating test data and applying the test data to the original encoding algorithm and the original decoding algorithm to obtain a second evaluation score of the original encoding algorithm and the original decoding algorithm;
[0079] in a case where the second evaluation score does not satisfy a preset second evaluation standard, re-executing the step of obtaining the original encoding algorithm and the original decoding algorithm corresponding to the original error correction algorithm.
[0080] In this embodiment, first, the derived original encoding algorithm and original decoding algorithm are preliminarily evaluated in performance by using mathematical tools such as complexity analysis, bit error rate simulation, etc., to obtain a first evaluation score, aiming to verify the correctness and feasibility of the algorithm from the theoretical level, and to evaluate the potential optimization space.
[0081] When the preliminary evaluation result does not meet the preset first evaluation standard, such as the algorithm complexity is too high, the bit error rate is not up to standard, etc., the steps of obtaining the original encoding algorithm and the original decoding algorithm corresponding to the original error correction algorithm will be re-executed, and the algorithm will be modified or optimized until the basic performance requirements are met.
[0082] After meeting the first evaluation standard, test data are further generated, which should cover a variety of possible input situations and error modes to comprehensively test the actual performance of the algorithm. The test data are applied to the original encoding algorithm and the original decoding algorithm respectively, and a second evaluation score is recorded and calculated. This step tests and verifies the actual performance of the algorithm more deeply by simulating real application scenarios.
[0083] If the second evaluation score still does not meet the preset second evaluation standard, such as high bit error rate or excessive resource consumption in actual application, etc., the steps of obtaining the original encoding algorithm and the original decoding algorithm corresponding to the original error correction algorithm will be re-executed, and the algorithm will be further adjusted and optimized until the actual application requirements and performance standards are met; through a series of performance evaluation and optimization steps, it is ensured that the derived original encoding algorithm and original decoding algorithm have high reliability and efficiency in actual application.
[0084] The resource utilization rate improvement method applied to the reconfigurable satellite computer provided in the embodiments of the present application ensures the reliability and efficiency of the original encoding algorithm and the original decoding algorithm in actual application through the performance evaluation and optimization steps of the original encoding algorithm and the original decoding algorithm.
[0085] Figure 3 The flowchart of deriving the original encoding algorithm provided in the embodiments of the present application is shown as Figure 3 Based on the encoding rule, the original encoding algorithm corresponding to the original error correction algorithm is derived, which comprises:
[0086] S301, based on the encoding rule, determining the basic unit and the encoding structure of the original error correction algorithm coding;
[0087] In this embodiment, according to the described encoding rule, the specific composition of the basic unit and the encoding structure of the original error correction algorithm coding is determined, specifically, the basic unit and the encoding structure are the basis for constructing the original encoding algorithm, which determines how the data is encoded and the format of the encoded data.
[0088] S302, determine the mapping relationship between the information in the coding structure and the coded code;
[0089] In this embodiment, it is ensured that there is a clear mapping relationship between the information and the coded code in the described coding structure, so as to facilitate accurate transmission and interpretation of data.
[0090] S303, based on the mapping relationship and the basic unit coded by the original error correction algorithm, the original coding algorithm corresponding to the original error correction algorithm is obtained.
[0091] In this embodiment, by combining the mapping relationship mentioned above and the basic unit coded in the original error correction algorithm, the original coding algorithm corresponding to the original error correction algorithm is combined and constructed, and the specific steps include detailed analysis and adjustment of each parameter in the coding algorithm, to ensure the accuracy and efficiency of the coding process, including optimization of coding length, coding rate, redundancy and other key parameters, and fine design of mathematical operations and logical processing that may be involved in the coding process; Through a series of steps, an original coding algorithm is obtained which not only meets the requirements of the original error correction algorithm, but also has excellent performance, providing a solid foundation for subsequent resource utilization rate improvement.
[0092] The original coding algorithm derivation method provided by the embodiment of the application gradually constructs the original coding algorithm matched with the original error correction algorithm by analyzing the coding rule, which not only ensures the accuracy and reliability of the algorithm, but also provides an important basis for subsequent algorithm optimization and application. In the derivation process, the key parameters of the coding structure, information mapping relationship and coding algorithm are fully considered, and through fine design and optimization of these elements, an original coding algorithm with excellent performance and strong adaptability is obtained, which can efficiently process data coding tasks and improve the accuracy and reliability of data transmission, providing strong support for resource utilization rate improvement of the reconfigurable on-board computer.
[0093] Figure 4 The flowchart of the original decoding algorithm derivation provided by the embodiment of the application is shown in Figure 4 As shown, the original decoding algorithm corresponding to the original error correction algorithm is derived based on the error correction strategy and the decoding rule, which includes:
[0094] S401, set the initial state of the compiler;
[0095] S402, based on the initial state of the compiler, apply the decoding rule of the original decoding algorithm to the compiler to perform iterative decoding, wherein the value of each node is adjusted according to the received node state and the decoding algorithm result of the last iteration in each iteration;
[0096] In the embodiment, the compiler is initialized to ensure that the compiler is in a preset initial state; then, the decoding rule defined in the original decoding algorithm is introduced into the compiler to start the iteration decoding process. In the process, the value of the current node is adjusted and optimized according to the node state information received from the outside and the result obtained in the last iteration process.
[0097] S403, output the original decoding algorithm when the iteration decoding reaches the decoding convergence condition.
[0098] In the embodiment, when the iteration decoding reaches the decoding convergence condition, the system outputs the result generated by the original decoding algorithm.
[0099] The original decoding algorithm derivation method provided by the embodiment can gradually derive and optimize the original decoding algorithm through the iteration decoding process of the compiler, and the value of the node is adjusted according to the node state and the decoding result in the iteration process, so that the decoding process is more accurate and efficient. When the iteration reaches the decoding convergence condition, that is, the decoding result is stable and the bit error rate is low, the final original decoding algorithm is output, which not only ensures the accuracy and reliability of the decoding algorithm, but also improves the decoding efficiency and the reliability of data transmission, and provides strong support for improving the resource utilization rate of the reconfigurable satellite computer. In addition, through the iteration decoding process of the compiler, the decoding algorithm can be further optimized and improved to adapt to different application scenarios and requirements, and provide a wider space for subsequent algorithm research and application.
[0100] In an optional scheme of the embodiment, the original encoding algorithm is improved by the two-dimensional interleaving technology to obtain a target encoding algorithm, and the target encoding algorithm is an LDPC encoding algorithm, which comprises:
[0101] The original encoding algorithm is interleaved according to a preset two-dimensional interleaving rule to obtain an interleaved interleaving algorithm;
[0102] The interleaving algorithm is LDPC encoded according to the encoding rule of the LDPC encoding algorithm to obtain the target encoding algorithm.
[0103] In the embodiment, the original encoding algorithm is first interleaved according to the preset two-dimensional interleaving rule to obtain a new encoding algorithm after interleaving; then, the interleaved algorithm is LDPC encoded according to the specific encoding rule of the LDPC encoding algorithm, and finally the target encoding algorithm required is obtained.
[0104] For example, the 2D interleaving LDPC encoding algorithm design:
[0105] The generating matrix G of the LDPC (8176, 7154) is a 7154*8176 matrix, and G is composed of a k unit matrix I and a 7154*1022 matrix g. The g is composed of 14*2 511*511 cyclic matrices Zij, j=(0, 1), i=(0, 1, 2,..., 13).
[0106] Figure 7 The schematic diagram of the cyclic matrix Z provided by the embodiment of the application is shown in the figure. Figure 7 As shown in the figure, the Zij is composed of the first row element Zi which is cyclically shifted by one bit each time, and the cyclic shift is performed 510 times, wherein i=(0, 1, 2,..., 510). The CCSDS specifies the value of the first row element Zi in each cyclic matrix Zij, and there are 28 groups of Zi which are cyclically composed of 28 cyclic matrices Z.
[0107] Therefore, the following equation is obtained:
[0108]
[0109] Let the information matrix to be encoded be M, and then M should be:
[0110]
[0111] Then, the encoding matrix N1 is obtained by encoding the information matrix M once:
[0112]
[0113] The transposed matrix M2 of the encoding matrix N1 is obtained as follows:
[0114]
[0115] The secondary encoding matrix N is obtained by encoding the transposed matrix M2 of the primary encoding matrix N1 twice:
[0116]
[0117] The secondary encoding matrix N is the output encoding matrix of the 2D interleaved LDPC encoding algorithm.
[0118] In an optional solution of the embodiment of the application, the original decoding algorithm is improved by using the hyperbolic tangent function and the inverse hyperbolic tangent function to obtain a target decoding algorithm, and the target decoding algorithm is an LDPC decoding algorithm, which comprises the following steps.
[0119] The hyperbolic tangent function and the inverse hyperbolic tangent function in the original decoding algorithm are approximately processed by using minimum addition and sign multiplication;
[0120] The original decoding algorithm is improved by using the approximately processed function to obtain the target decoding algorithm.
[0121] In this embodiment, by using the minimum addition and sign multiplication of two mathematical methods, the hyperbolic tangent function and the inverse hyperbolic tangent function involved in the original decoding algorithm are effectively approximated. On this basis, the original decoding algorithm is further improved, and by introducing these approximated functions, the target decoding algorithm is finally obtained.
[0122] For example, the 2D interleaved LDPC decoding algorithm design:
[0123] The check matrix H is a very important part of the LDPC decoding module, and its main function is to check the received information bits. Let Y be the set of code words received by the decoding module. When the following formula is satisfied, it means that the received code word set has no error.
[0124]
[0125] The check matrix H is the CCSDS recommended LDPC (8176, 7154) check matrix, and its generation method is similar to that of the generator matrix G. It is composed of 2x16 511x511 cyclic matrices Aij to form a 1022x8176 matrix H. Aij is composed of the first row elements ai, which are cycled one bit at a time, 510 times, where i=(0, 1, 2, …510). In CCSDS, the corresponding value of the first row element ai in each cyclic matrix Aij is given, and there are 32 groups of ai, which are cycled to form 32 cyclic matrices Aij, i.e.
[0126]
[0127] Where V=(V0, V1, …, V8175) is called the variable node, corresponding to the row of matrix H. C=(C0, C1, …, V1021) is called the check node, corresponding to the row of matrix H.
[0128] The hyperbolic tangent function and the inverse hyperbolic tangent function are used twice in the check node update of the 2D-LDPC interleaved decoding algorithm, which has a large amount of calculation and is difficult to implement in hardware. Therefore, the NMSA decoding algorithm is selected for 2D interleaving to form the 2D-NMSA interleaved decoding algorithm. This algorithm approximates the hyperbolic tangent function and the inverse hyperbolic tangent function used in the check node update twice to minimum addition and sign multiplication and adds a correction coefficient, which reduces the amount of calculation and facilitates hardware implementation. In the check node update, the minimum addition and sign multiplication are used instead of the hyperbolic tangent function and the inverse hyperbolic tangent function, so the steps of the 2D-LDPC interleaved decoding algorithm are as follows.
[0129] The received matrix Y is:
[0130]
[0131] The first NMSA column decoding is performed on the receiving matrix Y, and the initial probability likelihood ratio message is:
[0132]
[0133] The variable node information is initialized:
[0134]
[0135] Wherein P is the connection point of the variable node i and all check nodes in the check matrix H, 0 < P < 1020, that is, the point of the i-th column element in H is 1. According to the check matrix H, the following can be obtained:
[0136] The log-likelihood ratio information of the check node is updated according to the information of the variable node:
[0137]
[0138] The first decision is made according to the posterior probability:
[0139]
[0140] The iteration number is reached, and the error-corrected code word decoding matrix is output.
[0141] Compared with the highest support 320Mbps rate of payload data in the experimental satellite on-board storage system, the highest support 1Gb data throughput of the storage array scheme, the highest payload data rate supported by the single channel is increased from 320Mbps to 1.6Gbps, the highest support data throughput rate of the storage array is increased from 1Gbps to 4Gbps, and the maximum operating bus width is increased from 32bit to 128bit; the storage performance comparison is shown in Table 1:
[0142] Table 1
[0143]
[0144] The 2D interleaved LDPC error correction algorithm designed in the embodiment of the application improves the storage density of the on-board computer, and effectively solves the problem of reduced data reliability of the on-board storage system due to single particle effect and storage medium on the satellite.
[0145] Figure 5 The basic structure diagram of the NAND Flash storage unit provided by the embodiment of the application is as follows: Figure 5As shown, a basic structure of a storage unit of the NAND Flash, which adds a floating gate (FG) between the gate of the MOSFET and the substrate, the FG is generally made of materials such as nitride embedded silicon dioxide, the FG is the core of the NAND Flash to realize the storage function, and due to the structure and material characteristics, the charge stored in the FG will not disappear after power off, realizing the non-volatile storage characteristics of the NAND Flash.
[0146] With the continuous development of the storage medium of the NAND Flash, new generations of NAND Flash with higher storage density are emerging, but due to its own characteristics, the NAND Flash with high storage density usually adopts to divide multiple threshold voltages in one storage unit for data storage, and with the increase of storage density, the types of threshold voltages in one unit will also increase. Therefore, the NAND Flash with high storage density is more prone to data errors caused by threshold voltage fluctuations or drift, thereby reducing the reliability of data. But the NAND Flash with high storage density can greatly improve the storage capacity of the spaceborne storage system, and reduce the volume and power consumption of the system. Since the spaceborne storage system has high requirements for data reliability, solving the reliability problem of data storage is the key to whether the NAND Flash with high storage density can be applied to aerospace. According to the working characteristics of the NAND Flash and the application requirements of the spaceborne storage system, the present application proposes a 2D interleaved LDPC error correction algorithm, that is, a two-dimensional data coding and decoding architecture is adopted for the NMSA algorithm and the LLR-BP algorithm, and the improved 2D interleaved LDPC error correction algorithm selects the LDPC code with a recommended code rate of 7 / 8 in CCSDS.
[0147] Figure 6 The 2D interleaved LDPC error correction algorithm architecture provided by the embodiment of the present application is shown in the figure, Figure 6 As shown, a set of 8176x8176 matrices is generated by twice coding of the data matrix, and the size of the information matrix is 7154x7154. Effectively solve the problem of reducing the data reliability of the spaceborne storage system on the satellite due to single particle effect and storage medium.
[0148] Figure 8 The structure diagram of the resource utilization rate improvement system applied to the reconfigurable spaceborne computer provided by the embodiment of the present application is shown in the figure, Figure 8 As shown, the system specifically comprises:
[0149] The acquisition module 801 is configured to acquire the original coding algorithm and the original decoding algorithm corresponding to the original error correction algorithm.
[0150] The first improvement module 802 is configured to improve the original encoding algorithm by using the two-dimensional interleaving technology to obtain a target encoding algorithm, and the target encoding algorithm is an LDPC encoding algorithm.
[0151] The second improvement module 803 is configured to improve the original decoding algorithm by using the hyperbolic tangent function and the inverse hyperbolic tangent function to obtain a target decoding algorithm, and the target decoding algorithm is an LDPC decoding algorithm.
[0152] In a possible implementation, the acquisition module 801 is further configured to acquire an error correction strategy of the original error correction algorithm and an error type to which the error correction strategy is directed; obtain an encoding rule and a decoding rule corresponding to the original error correction algorithm according to the error correction strategy and the error type to which the error correction strategy is directed; derive the original encoding algorithm corresponding to the original error correction algorithm based on the encoding rule; and derive the original decoding algorithm corresponding to the original error correction algorithm based on the error correction strategy and the decoding rule.
[0153] In a possible implementation, the system further includes an evaluation module 804 configured to analyze a first evaluation score of the original encoding algorithm and the original decoding algorithm by using a mathematical tool; re-execute the steps of acquiring the original encoding algorithm and the original decoding algorithm corresponding to the original error correction algorithm in a case where the first evaluation score does not meet a preset first evaluation standard; generate test data and apply the test data to the original encoding algorithm and the original decoding algorithm to obtain a second evaluation score of the original encoding algorithm and the original decoding algorithm in a case where the first evaluation score meets the preset first evaluation standard; and re-execute the steps of acquiring the original encoding algorithm and the original decoding algorithm corresponding to the original error correction algorithm in a case where the second evaluation score does not meet a preset second evaluation standard.
[0154] In a possible implementation, the acquisition module 801 is further configured to determine a basic unit and an encoding structure of the original error correction algorithm encoding based on the encoding rule; determine a mapping relationship of information in the encoding structure after encoding; and combine the mapping relationship and the basic unit of the original error correction algorithm encoding to obtain the original encoding algorithm corresponding to the original error correction algorithm.
[0155] In a possible implementation, the acquisition module 801 is further configured to set an initial state of a compiler; apply the decoding rule of the original decoding algorithm to the compiler based on the initial state of the compiler to perform iterative decoding, where the value of a node is adjusted according to a received node state and a result of a decoding algorithm of a previous iteration in each iteration; and output the original decoding algorithm in a case where the iterative decoding meets a decoding convergence condition.
[0156] In a possible implementation, the first improvement module 802 is further configured to perform interleaving processing on the original encoding algorithm according to a preset two-dimensional interleaving rule to obtain an interleaved interleaving algorithm; and perform LDPC encoding on the interleaving algorithm according to an encoding rule of the LDPC encoding algorithm to obtain the target encoding algorithm.
[0157] In a possible implementation, the first improvement module 802 is further configured to perform approximate processing on hyperbolic tangent functions and inverse hyperbolic tangent functions in the original decoding algorithm by using minimum addition and sign multiplication; and perform improvement processing on the original decoding algorithm according to the functions after the approximate processing to obtain the target decoding algorithm.
[0158] The resource utilization rate improvement system applied to the reconfigurable spaceborne computer provided in the embodiment can be a resource utilization rate improvement system applied to a reconfigurable spaceborne computer as shown in Figure 8 The resource utilization rate improvement system applied to the reconfigurable spaceborne computer provided in the embodiment can be a resource utilization rate improvement system applied to a reconfigurable spaceborne computer as shown in Figures 1-7 The resource utilization rate improvement system applied to the reconfigurable spaceborne computer provided in the embodiment can be a resource utilization rate improvement system applied to a reconfigurable spaceborne computer as shown in Figures 1-7 The resource utilization rate improvement system applied to the reconfigurable spaceborne computer provided in the embodiment can be a resource utilization rate improvement system applied to a reconfigurable spaceborne computer as shown in Figures 1-7 The resource utilization rate improvement system applied to the reconfigurable spaceborne computer provided in the embodiment can be a resource utilization rate improvement system applied to a reconfigurable spaceborne computer as shown in
[0159] The system embodiments described above are only schematic, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, that is, they can be located in one place or distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment.
[0160] Figure 9 A structural schematic diagram of an electronic device provided in the embodiment is shown in Figure 9 The electronic device provided in the embodiment includes a processor 901, a communication interface 902, a memory 903, and a communication bus 904, wherein the processor 901, the communication interface 902, and the memory 903 complete mutual communication through the communication bus 904; the memory 903 is used to store a computer program; and the processor 901 is used to execute the program stored in the memory 903 to implement the steps of the resource utilization rate improvement method applied to the reconfigurable spaceborne computer provided in any one of the method embodiments.
[0161] The original encoding algorithm and the original decoding algorithm corresponding to the original error correction algorithm are obtained; the original encoding algorithm is improved through the two-dimensional interleaving technology to obtain a target encoding algorithm, which is an LDPC encoding algorithm; the original decoding algorithm is improved through the hyperbolic tangent function and the inverse hyperbolic tangent function to obtain a target decoding algorithm, which is an LDPC decoding algorithm.
[0162] In a possible implementation, an error correction strategy of an original error correction algorithm and an error type targeted by the error correction strategy are obtained; encoding rules and decoding rules corresponding to the original error correction algorithm are obtained according to the error correction strategy and the error type targeted by the error correction strategy; an original encoding algorithm corresponding to the original error correction algorithm is derived based on the encoding rules; and an original decoding algorithm corresponding to the original error correction algorithm is derived based on the error correction strategy and the decoding rules.
[0163] In a possible implementation, a first evaluation score of the original encoding algorithm and the original decoding algorithm is analyzed by using a mathematical tool; in a case where the first evaluation score does not satisfy a preset first evaluation standard, the step of obtaining the original encoding algorithm and the original decoding algorithm corresponding to the original error correction algorithm is re-executed; in a case where the first evaluation score satisfies the preset first evaluation standard, test data is generated, and the test data is applied to the original encoding algorithm and the original decoding algorithm to obtain a second evaluation score of the original encoding algorithm and the original decoding algorithm; and in a case where the second evaluation score does not satisfy a preset second evaluation standard, the step of obtaining the original encoding algorithm and the original decoding algorithm corresponding to the original error correction algorithm is re-executed.
[0164] In a possible implementation, a basic unit and a coding structure of the original error correction algorithm are determined based on the encoding rules; a mapping relationship of information in the coding structure to coded bits after coding is determined; and the original encoding algorithm corresponding to the original error correction algorithm is obtained based on the mapping relationship and the basic unit of the original error correction algorithm.
[0165] In a possible implementation, an initial state of a compiler is set; a decoding rule of the original decoding algorithm is applied to the compiler based on the initial state of the compiler to perform iterative decoding, where a value of a node is adjusted according to a received node state and a result of a decoding algorithm of a previous iteration in each iteration; and the original decoding algorithm is output in a case where the iterative decoding reaches a decoding convergence condition.
[0166] In a possible implementation, the original encoding algorithm is interleaved according to a preset two-dimensional interleaving rule to obtain an interleaved algorithm; and the interleaved algorithm is LDPC encoded according to an encoding rule of an LDPC encoding algorithm to obtain a target encoding algorithm.
[0167] In one possible implementation, the hyperbolic tangent function and the inverse hyperbolic tangent function in the original decoding algorithm are approximated by using minimum addition and sign multiplication; and the original decoding algorithm is improved according to the approximated functions to obtain a target decoding algorithm.
[0168] Those skilled in the art can clearly understand from the above description of the embodiments that the embodiments can be realized by means of software plus a general hardware platform, and of course, can also be realized by hardware. Based on such understanding, the above technical solutions, essentially or in terms of related art, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions to cause a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0169] It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order in which they are described unless specifically indicated as such. It is also to be understood that additional or alternative steps can be employed.
[0170] The above description is merely that of possible implementations, and makes a person skilled in the art understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for improving resource utilization of a reconfigurable spaceborne computer, comprising: The method comprises the following steps: obtaining an original encoding algorithm and an original decoding algorithm corresponding to an original error correction algorithm; improving the original encoding algorithm by using the two-dimensional interleaving technology to obtain a target encoding algorithm, wherein the target encoding algorithm is an LDPC encoding algorithm; improving the original decoding algorithm by using the hyperbolic tangent function and the inverse hyperbolic tangent function to obtain a target decoding algorithm, wherein the target decoding algorithm is an LDPC decoding algorithm.
2. The method of claim 1, wherein, The method further comprises the following steps: obtaining an error correction strategy of the original error correction algorithm and an error type to which the error correction strategy is directed; obtaining an encoding rule and a decoding rule corresponding to the original error correction algorithm according to the error correction strategy and the error type to which the error correction strategy is directed; deducing the original encoding algorithm corresponding to the original error correction algorithm based on the encoding rule; deducing the original decoding algorithm corresponding to the original error correction algorithm based on the error correction strategy and the decoding rule.
3. The method of claim 1, wherein, The method further comprises the following steps: analyzing a first evaluation score of the original encoding algorithm and the original decoding algorithm by using a mathematical tool; re-executing the step of obtaining the original encoding algorithm and the original decoding algorithm corresponding to the original error correction algorithm in a case where the first evaluation score does not satisfy a preset first evaluation standard; generating test data and applying the test data to the original encoding algorithm and the original decoding algorithm to obtain a second evaluation score of the original encoding algorithm and the original decoding algorithm in a case where the first evaluation score satisfies the preset first evaluation standard; re-executing the step of obtaining the original encoding algorithm and the original decoding algorithm corresponding to the original error correction algorithm in a case where the second evaluation score does not satisfy a preset second evaluation standard.
4. The method of claim 2, wherein, The step of deducing the original encoding algorithm corresponding to the original error correction algorithm based on the encoding rule comprises the following steps: determining a basic unit and a coding structure of the original error correction algorithm encoding based on the encoding rule; determining a mapping relationship of information in the coding structure after coding; combining the mapping relationship and the basic unit of the original error correction algorithm encoding to obtain the original encoding algorithm corresponding to the original error correction algorithm.
5. The method of claim 2, wherein, The step of deducing the original decoding algorithm corresponding to the original error correction algorithm based on the error correction strategy and the decoding rule comprises the following steps: setting an initial state of a compiler; applying the decoding rule of the original decoding algorithm to the compiler based on the initial state of the compiler to perform iterative decoding, wherein the value of a node is adjusted according to a received node state and a decoding algorithm result of a previous iteration each time; outputting the original decoding algorithm in a case where the iterative decoding reaches a decoding convergence condition.
6. The method of claim 1, wherein, The step of improving the original encoding algorithm by using the two-dimensional interleaving technology to obtain a target encoding algorithm, wherein the target encoding algorithm is an LDPC encoding algorithm, comprises the following steps: interleaving the original encoding algorithm according to a preset two-dimensional interleaving rule to obtain an interleaved algorithm; performing LDPC encoding on the interleaved algorithm according to an encoding rule of the LDPC encoding algorithm to obtain the target encoding algorithm.
7. The method of claim 1, wherein, The step of improving the original decoding algorithm by using the hyperbolic tangent function and the inverse hyperbolic tangent function to obtain a target decoding algorithm, wherein the target decoding algorithm is an LDPC decoding algorithm, comprises the following steps: The hyperbolic tangent function and the inverse hyperbolic tangent function in the original decoding algorithm are approximated by using minimum addition and sign multiplication; According to the approximated function, the original decoding algorithm is improved to obtain a target decoding algorithm.
8. A resource utilization enhancement system applied to a reconfigurable spaceborne computer, characterized in that, The method comprises the steps of: An acquisition module is configured to acquire an original encoding algorithm and an original decoding algorithm corresponding to an original error correction algorithm; A first improvement module is configured to improve the original encoding algorithm by using the two-dimensional interleaving technology to obtain a target encoding algorithm, wherein the target encoding algorithm is an LDPC encoding algorithm; A second improvement module is configured to improve the original decoding algorithm by using hyperbolic tangent function and inverse hyperbolic tangent function to obtain a target decoding algorithm, wherein the target decoding algorithm is an LDPC decoding algorithm.
9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the resource utilization rate improvement method for the reconfigurable spaceborne computer according to any one of claims 1-7.
10. A storage medium having stored thereon a computer program, characterized in that The computer program is executed by the processor to implement the steps of the resource utilization rate improvement method for the reconfigurable spaceborne computer according to any one of claims 1-7.