Radiation-proof data transmission circuit, device and system

Abstract

The invention discloses an anti-radiation data transmission circuit, device and system, the anti-radiation data transmission circuit comprises a crystal oscillator oscillation starting circuit and a data transmission link, and the crystal oscillator oscillation starting circuit and the data transmission link are structurally enhanced by adopting an annular gate reinforcement technology; the crystal oscillator oscillation starting circuit comprises an external signal branch and an external crystal oscillator branch which are mutually backed up; and the data transmission link is used for converting the basic frequency signal output by the external signal branch or the external crystal oscillator branch into high-speed serial data and sending the high-speed serial data to the off-chip receiving module. According to the application, firstly, a redundant data source, namely an external signal branch and an external crystal oscillator branch which are mutually backed up, is provided, so that the data transmission reliability is improved, and meanwhile, the data reinforcement based on the annular gate is carried out on the first receiving module and the data transmission link, so that the reliability of data transmission is improved. And a high-stability data transmission link is constructed in combination with an external crystal oscillator with anti-radiation capability, so that the anti-radiation capability of the whole data transmission circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, in particular to an anti-radiation data transmission circuit, device and system. BACKGROUND

[0002] As a key channel connecting ADC and off-chip, the core function of the data transmission link is to reliably transmit the encoded data output by ADC. In the link, the stability of the clock reference source directly determines the transmission performance, which needs to be stable.

[0003] However, the anti-radiation capability of the existing clock reference source is insufficient, which easily leads to transmission errors of the data transmission link applied in space cosmic environment, seriously affecting the stability and reliability of the system.

[0004] CONTENT The main purpose of the present application is to provide an anti-radiation data transmission circuit, device and system, which aims to solve the technical problem of insufficient anti-radiation capability of the existing data transmission link.

[0005] To achieve the above purpose, the present application provides an anti-radiation data transmission circuit, which comprises a crystal oscillator starting circuit and a data transmission link, both of which are structurally enhanced by adopting a ring-shaped gate reinforcement technology. The crystal oscillator starting circuit comprises an external signal branch and an external crystal oscillator branch which are backup to each other. The data transmission link is used to convert the basic frequency signal output by the external signal branch or the external crystal oscillator branch into high-speed serial data, and send the high-speed serial data to an off-chip receiving module.

[0006] In an embodiment, the anti-radiation data transmission circuit further comprises a first switch module; the external crystal oscillator branch comprises a series connection of an external crystal oscillator and a driving shaping circuit, and the external signal branch comprises a series connection of a first receiver and the driving shaping circuit; The first switch module is connected with the external crystal oscillator, the first receiver and the driving shaping circuit respectively; The external crystal oscillator branch and the external signal branch are switched and connected to the driving shaping circuit through the first switch module.

[0007] In an embodiment, the first switch module comprises a first switch unit and a second switch unit; The first switch unit is used to connect the external crystal oscillator and the driving shaping circuit to transmit the initial frequency signal generated by the external crystal oscillator to the driving shaping circuit when a start control signal is received; The second switch unit is configured to, when the start control signal is received, connect the first receiver and the drive shaping circuit to transmit the drive frequency signal input by the first receiver to the drive shaping circuit. The drive shaping circuit is configured to perform anti-interference processing on the initial frequency signal or the drive frequency signal to generate the base frequency signal.

[0008] In an embodiment, the data transmission link comprises an internal clock source branch and an external clock source branch which are backup to each other, and a communication module; The internal clock source branch and the external clock source branch are connected with the communication module, and the communication module is connected with the off-chip receiving module; The communication module is configured to transmit high-speed serial data transmitted by the internal clock source branch or the external clock source branch to the off-chip receiving module.

[0009] In an embodiment, the anti-radiation data transmission circuit further comprises a second switch module; the internal clock source branch comprises a phase-locked loop and a parallel-serial conversion circuit connected in series; and the external clock source branch comprises a second receiver and the parallel-serial conversion circuit connected in series. The second switch module is connected with the phase-locked loop, the second receiver and the parallel-serial conversion circuit respectively. The internal clock source branch and the external clock source branch are connected to the parallel-serial conversion circuit through the first switch module.

[0010] In an embodiment, the second switch module comprises a third switch unit and a fourth switch unit. The third switch unit is configured to, when a clock control signal is received, connect the phase-locked loop and the parallel-serial conversion circuit to transmit an internal clock signal generated by the phase-locked loop to the parallel-serial conversion circuit. The second switch module is configured to, when the clock control signal is received, transmit an external clock signal received by the second receiver to the parallel-serial conversion circuit according to the clock control signal. The parallel-serial conversion circuit is configured to generate the high-speed serial data according to encoded parallel data and the internal clock signal or the external clock signal, and transmit the high-speed serial data to the communication module.

[0011] In an embodiment, the phase-locked loop comprises a frequency and phase discriminator, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. The input end of the phase-frequency detector is connected with the output end of the drive shaping circuit and the frequency divider respectively, the output end of the phase-frequency detector is connected with the input end of the charge pump, the output end of the charge pump is connected with the input end of the loop filter, the output end of the loop filter is connected with the input end of the voltage-controlled oscillator, and the output end of the voltage-controlled oscillator is connected with the input of the frequency divider and the second switch module respectively.

[0012] In an embodiment, the ring gate reinforcement technology is implemented in the layout design of the drive shaping circuit, the phase-locked loop, the parallel-serial conversion circuit, the communication module, the first receiver and the second receiver.

[0013] In addition, to achieve the above-mentioned purpose, the application further provides an anti-radiation data transmission device, which comprises the anti-radiation data transmission circuit mentioned above.

[0014] In addition, to achieve the above-mentioned purpose, the application further provides an anti-radiation data transmission system, which comprises the anti-radiation data transmission device mentioned above. An off-chip receiving module for receiving high-speed serial data sent by the anti-radiation data transmission device. An encoder for providing encoded parallel data to the anti-radiation data transmission device.

[0015] In the present application, an anti-radiation data transmission circuit, device and system are disclosed, which comprises a crystal oscillator starting circuit and a data transmission link, both of which are structurally enhanced by adopting a ring gate reinforcement technology; the crystal oscillator starting circuit comprises an external signal branch and an external crystal oscillator branch which are backup to each other; the data transmission link is used to convert a basic frequency signal output by the external signal branch or the external crystal oscillator branch into high-speed serial data and send the high-speed serial data to an off-chip receiving module. The present application first provides a redundant data source, i.e. the external signal branch and the external crystal oscillator branch which are backup to each other to improve the data transmission reliability, at the same time, the present application reinforces the data based on the ring gate for the first receiving module and the data transmission link, and constructs a high-stability data transmission link by combining an external crystal oscillator with anti-radiation capability, thereby improving the anti-radiation capability of the entire data transmission circuit. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 The functional module diagram of the anti-radiation data transmission circuit embodiment of the present application; Figure 2 The module schematic diagram of the crystal oscillator starting circuit of the anti-radiation data transmission circuit embodiment of the present application; Figure 3The module schematic diagram of the data transmission link of the anti-radiation data transmission circuit embodiment of the present application; Figure 4 The structure schematic diagram of the phase-locked loop of the anti-radiation data transmission circuit embodiment of the present application; Figure 5 The reinforcement schematic diagram of the ring gate reinforcement technology of the anti-radiation data transmission circuit embodiment of the present application.

[0017] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0018] It should be understood that the specific embodiments described herein are merely illustrative of the present application and do not limit the present application.

[0019] The technical solutions of the present application will be described clearly and completely in the embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and all the embodiments obtained by those skilled in the art without creative labor based on the embodiments in the present application are within the scope of protection of the present application.

[0020] It should be noted that the description of "first", "second" and the like in the embodiments of the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features with "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of the various embodiments can be combined with each other, but it must be based on the fact that the technical solutions can be realized by those skilled in the art. When the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the scope of protection claimed by the present application.

[0021] The main solution of the present application is to provide an anti-radiation data transmission circuit, which comprises: a crystal oscillator circuit and a data transmission link, both of which are structurally enhanced by adopting a ring gate reinforcement technology; the crystal oscillator circuit comprises an external signal branch and an external crystal oscillator branch which are backup to each other; the data transmission link is used to convert a basic frequency signal output by the external signal branch or the external crystal oscillator branch into high-speed serial data, and send the high-speed serial data to an off-chip receiving module.

[0022] At present, the clock reference source of the data transmission link lacks anti-radiation capability. It is particularly crucial that when the data transmission link is applied to the space cosmic environment, it must have sufficient anti-radiation performance. There are a large number of high-energy particles in space, and if the anti-radiation capability of the link is insufficient, it is easy to cause clock reference source abnormalities, data signal distortion and other problems, ultimately leading to transmission errors, and seriously affecting the reliability and stability of the entire system.

[0023] Therefore, in view of the problem that the lack of anti-radiation capability in the existing data transmission process leads to clock abnormalities, data distortion, transmission errors of the data transmission link in the space environment, and further affects the stability and reliability of the system, the present application provides an anti-radiation data transmission circuit with high anti-radiation performance, to realize stable data transmission of the electronic circuit in a strong radiation environment (such as space, nuclear industry environment). The present application ensures that the encoded data output by the ADC (analog-to-digital converter) can be reliably transmitted to the off-chip through the redundant branch design and ring gate reinforcement technology, and ensures stable and accurate data transmission in a strong radiation environment.

[0024] Reference Figure 1 , Figure 1 is a functional module diagram of the anti-radiation data transmission circuit of the first embodiment of the present application.

[0025] As Figure 1 shown, the anti-radiation data transmission circuit described in the present embodiment includes a crystal oscillator starting circuit 10 and a data transmission link 20, both of which are structurally enhanced by using ring gate reinforcement technology; The crystal oscillator starting circuit 10 includes an external crystal oscillator branch 101 and an external signal branch 102 which are backup to each other; The data transmission link 20 is used to convert the basic frequency signal output by the external signal branch 102 or the external crystal oscillator branch 101 into high-speed serial data, and send the high-speed serial data to the off-chip receiving module 1.

[0026] It should be understood that the above-mentioned crystal oscillator starting circuit 10 can be the core circuit for generating the basic frequency signal required by the data transmission link 20, and is a core component of the clock reference source. The stability of its output signal directly determines the transmission performance of the entire data transmission link 20, and in the present embodiment, the anti-radiation reinforcement process is needed to compensate for the lack of anti-radiation capability in traditional design.

[0027] The external signal branch 102 is one of two backup branches in the crystal oscillator circuit 10, which can be composed of a receiver and a drive shaping circuit 203 in series, and functions to receive an external drive frequency signal and transmit it to the drive shaping circuit 203 as a backup for the external crystal oscillator branch 101. When the external crystal oscillator branch 101 fails due to radiation, the branch can be activated through switching to ensure continuous supply of the basic frequency signal.

[0028] The external crystal oscillator branch 101 is one of two backup branches in the crystal oscillator circuit 10, which can be composed of an external crystal oscillator 202 with anti-radiation characteristics and a drive shaping circuit 203 in series, and is the main signal source when the crystal oscillator circuit 10 is working normally. The external crystal oscillator 202 itself is anti-radiation but needs to cooperate with the drive shaping circuit 203 to form a stable initial frequency signal output path after anti-radiation reinforcement.

[0029] It is easy to understand that the above-mentioned basic frequency signal can be a frequency signal generated by the drive shaping circuit 203 in the crystal oscillator circuit 10 for anti-interference processing (such as filtering and shaping) on the initial frequency signal (generated by the external crystal oscillator 202) or the drive frequency signal (received by the external signal branch 102), which meets the working requirements of the subsequent phase-locked loop 206 circuit and the serial-parallel conversion circuit 205 of the data transmission link 20, and is the core clock reference of the data transmission link 20.

[0030] Therefore, in order to ensure the stable generation of the basic frequency signal, in one embodiment, with reference to Figure 2 , Figure 2 The module diagram of the crystal oscillator circuit of the anti-radiation data transmission circuit embodiment of the present application is shown in Figure 2 The anti-radiation data transmission circuit further comprises a first switch module; the external crystal oscillator branch 101 comprises a series connection of the external crystal oscillator 202 and the drive shaping circuit 203, and the external signal branch 102 comprises a series connection of the first receiver 204 and the drive shaping circuit 203; The first switch module is connected with the external crystal oscillator 202, the first receiver 204 and the drive shaping circuit 203 respectively; The external crystal oscillator branch 101 and the external signal branch 102 are switched and connected to the drive shaping circuit 203 through the first switch module.

[0031] It can be understood that the first switch module can be a switch component for controlling the switching connection of the "external crystal oscillator branch 101" and the "external signal branch 102" in the crystal oscillator starting circuit 10 to the drive shaping circuit 203. The independent on-off of the two branches can be realized according to the external control signal, the signal conflict caused by the simultaneous conduction of the two branches is avoided, and it is a key component for ensuring the effective implementation of the dual backup branch function. The device itself also needs to be reinforced by the ring grid to ensure the switching reliability in the radiation environment.

[0032] The first receiver 204 can be a core signal receiving device in the external signal branch 102, which is used to receive the drive frequency signal sent by the external system, has the functions of signal receiving, preliminary amplification and demodulation, and can convert the weak and modulated signal input from the outside into a drive frequency signal meeting the input requirements of the drive shaping circuit 203. The device also needs to be reinforced by the ring grid to ensure that the signal can be stably received in the radiation environment and avoid the failure of the receiving function caused by irradiation.

[0033] In an implementation manner, as shown in Figure 2 The first switch module includes a first switch unit S1 and a second switch unit S2. The first switch unit S1 is configured to, in a case where a start control signal is received, connect the external crystal oscillator 202 and the drive shaping circuit 203, so as to transmit the initial frequency signal generated by the external crystal oscillator 202 to the drive shaping circuit 203. The second switch unit S2 is configured to, in a case where the start control signal is received, connect the first receiver 204 and the drive shaping circuit 203, so as to transmit the drive frequency signal input from the first receiver 204 to the drive shaping circuit 203. The drive shaping circuit 203 is configured to perform anti-interference processing on the initial frequency signal or the drive frequency signal, and generate the basic frequency signal.

[0034] It is easy to understand that the above initial frequency signal can be a raw clock signal autonomously generated by an external crystal oscillator 202 with anti-radiation characteristics (such as a space-grade quartz crystal oscillator), and the frequency range can be set according to the data transmission requirements (such as 50MHz-200MHz). The signal waveform is initially a sine wave, and there may be small noise jitter (caused by radiation or device characteristics), which needs to be processed by the drive shaping circuit 203 before it can be used as a stable base frequency signal. The drive frequency signal can be a frequency signal generated by the first receiver 204 (a radio frequency receiver reinforced by a ring grid) after receiving the clock signal sent by the external system (such as the main control module of the deep space probe), and then processed by internal demodulation and amplification. The frequency is exactly the same as the initial frequency signal (such as both 100MHz), which ensures the compatibility of the output signals of the two branches, and the initial state of the signal may have waveform distortion, which needs to be further optimized by the drive shaping circuit 203.

[0035] It can be understood that the first switch unit S1 and the second switch unit S2 of the first switch module can both be digital controlled switches, and their control ends are connected with the system control module (which needs to be anti-radiation reinforced) to receive the start control signal to realize the on-off switching. In this embodiment, the on-off state of the first switch unit S1 and the second switch unit S2 can be switched to realize the selective communication of the "external crystal oscillator branch 101" or the "external signal branch 102" with the drive shaping circuit 203.

[0036] Exemplarily, the first switch unit S1 is a digital controlled switch device specially used to control the on-off of the external crystal oscillator branch 101 in the first switch module. At the same time, in the external crystal oscillator branch 101, an external crystal oscillator 202 with anti-radiation characteristics can be selected, and its output end is connected with the fixed end 1.1 of the first switch unit S1, and the fixed end 1.2 of the first switch unit S1 is connected with the input end of the drive shaping circuit 203, forming a series path of "external crystal oscillator 202→first switch unit S1→drive shaping circuit 203", which is the main source of the base frequency signal. In normal operation, the system control module (such as the FPGA reinforced by the ring grid) can send a start control signal to make S1 closed and S2 disconnected, and the initial frequency signal generated by the external crystal oscillator 202 is transmitted to the drive shaping circuit 203 through the first switch unit S1.

[0037] The second switch unit S2 is a digital control switch device specially controlling the on-off of the external signal branch 102 in the first switch module. In the external signal branch 102, the first receiver 204 with the ring-shaped gate reinforcement can be selected, and the output end thereof is connected with the fixed end 2.1 of the second switch unit S2. The fixed end 2.2 of the second switch unit S2 is connected with the input end of the drive shaping circuit 203, forming a serial path of “the first receiver 204→the second switch unit S2→the drive shaping circuit 203”. This branch is a standby path of the external crystal oscillator branch 101. When the system detects the failure of the external crystal oscillator branch 101 (such as the absence of the initial frequency signal or the frequency deviation exceeding the threshold value), the control module can switch the start control signal to make S1 open and S2 close. The drive frequency signal received by the first receiver 204 is transmitted to the drive shaping circuit 203 through the second switch unit S2.

[0038] After receiving the initial frequency signal from the first switch unit S1 or the drive frequency signal from the second switch unit S2, the drive shaping circuit 203 can remove the signal noise through the internal filter circuit (such as RC low-pass filter), reshape the irregular waveform (such as sine wave, distorted square wave) into regular square wave through the Schmidt trigger, and stabilize the signal amplitude at 3.3V standard value through the operational amplifier (amplification factor 2 times), so as to finally generate the basic frequency signal (corresponding to Vref in Figure 2 ) without noise, regular waveform and stable amplitude. The basic frequency signal is output to the data transmission link 20.

[0039] In the embodiment, when the initial frequency signal frequency deviation ≤±0.1% and the waveform is complete are detected, the high-level start control signal can be generated to the control end of S1. The first switch unit S1 is closed, and the second switch unit S2 is opened. The initial frequency signal generated by the external crystal oscillator 202 is transmitted to the drive shaping circuit 203 through S1. When the initial frequency signal is absent, the frequency deviation is >±0.1% or the waveform is severely distorted (such as temporary failure of the external crystal oscillator 202 caused by radiation), the start control signal can be switched to S2. The first switch unit S1 is opened, and the second switch unit S2 is closed. The drive frequency signal received by the first receiver 204 is transmitted to the drive shaping circuit 203 through S2, realizing seamless switching of the branch. The connection mode of the double backup branch can quickly switch to the external signal branch 102 through the first switch module in the case of radiation failure of the external crystal oscillator branch 101. The signal input of the drive shaping circuit 203 is not interrupted in the switching process, realizing seamless connection of the basic frequency signal, improving the fault tolerance of the crystal oscillator starting circuit 10, and further guaranteeing the continuity of the clock reference source. At the same time, the signal transmission path is unique and has no shunt, reducing signal loss and interference, and ensuring the quality of the clock reference source.

[0040] It should be noted that the high-speed serial data described above can be a serial data form converted from the parallel data output by the 8bit / 10bit encoder of the system based on the base frequency signal in the data transmission link 20. Compared with the parallel data, the transmission rate is higher (high-speed transmission is achieved in the design relying on a 500M reference clock), the transmission line required is less, the signal interference in the transmission process can be reduced, and the data transmission is suitable for long-distance and high-reliability data transmission in a space environment.

[0041] In a feasible embodiment, the data transmission link 20 includes an internal clock source branch and an external clock source branch which are backup to each other, and a communication module; The internal clock source branch and the external clock source branch are connected with the communication module, and the communication module is connected with the off-chip receiving module 1. The communication module is configured to send the high-speed serial data transmitted by the internal clock source branch or the external clock source branch to the off-chip receiving module 1.

[0042] It can be understood that the existing data transmission link 20 mostly uses a single clock source (such as only relying on a phase-locked loop 206). If the clock source fails due to radiation, the data transmission will be interrupted, which cannot meet the requirement of “uninterrupted transmission” in a space environment. Therefore, in order to solve the problem of “data transmission interruption caused by single clock source failure”, a “double clock source backup” structure of the data transmission link 20 can be constructed in the embodiment. The internal clock source branch described above can be a core branch of the data transmission link 20 which generates a high-frequency clock signal autonomously, and can be composed of a phase-locked loop 206 and a parallel-serial conversion circuit 205 in series. The function is to multiply the base frequency signal (such as 100MHz) output by the crystal oscillator starting circuit 10 into a high-speed clock signal (such as 500MHz), and to provide clock driving for the parallel-serial conversion circuit 205. It is the main clock source of the data transmission link 20, which ensures that the circuit can still work autonomously without external clock input. The external clock source branch can be a standby branch of the data transmission link 20 which receives an external high-speed clock signal, and is composed of a second receiver 212 (which is reinforced by a ring grid) and a parallel-serial conversion circuit 205 in series. The function is to receive a high-frequency clock signal (such as 500MHz) sent by an external system (such as a ground control center of a deep space exploration landing vehicle), as a backup of the internal clock source branch, to ensure that the clock signal is not interrupted when the internal phase-locked loop 206 fails due to radiation, and to improve the reliability of data transmission.

[0043] Therefore, in a feasible embodiment, in the embodiment, with reference to Figure 3 , Figure 3For the module schematic diagram of the data transmission link of the anti-radiation data transmission circuit embodiment of the present application, the anti-radiation data transmission circuit further comprises: a second switch module; the internal clock source branch comprises a phase-locked loop 206 and a parallel-serial conversion circuit 205 connected in series; the external clock source branch comprises a second receiver 212 and the parallel-serial conversion circuit 205 connected in series; The second switch module is connected with the phase-locked loop 206, the second receiver 212 and the parallel-serial conversion circuit 205 respectively; The internal clock source branch and the external clock source branch are switched and connected to the parallel-serial conversion circuit 205 through the first switch module.

[0044] It should be noted that the phase-locked loop 206 is a core frequency synthesizer of the internal clock source branch, which can work stably in a strong radiation environment after being reinforced by a ring-shaped grid, and its function is to multiply the basic frequency signal (such as 100MHz) output by the crystal oscillator starting circuit 10 to the high-frequency clock signal (such as 500MHz) required by the parallel-serial conversion circuit 205, and to ensure the frequency stability and phase accuracy of the output clock signal through closed-loop feedback, thereby solving the problem that the basic frequency signal cannot directly drive high-speed data conversion and providing an adaptive clock for high-speed data conversion.

[0045] The parallel-serial conversion circuit 205 can be a core data conversion device of the data transmission link 20, which is reinforced by a ring-shaped grid, and the input end includes a parallel data interface (receiving parallel data output by an 8bit / 10bit encoder) and a clock interface (receiving a high-frequency clock signal), and the output end is a serial data interface. Its function is to convert 8bit parallel data into 10bit high-speed serial data (corresponding to out in Figure 3 at a time under the drive of the high-frequency clock signal, the conversion rate is consistent with the clock frequency (such as 500Mbps data rate corresponding to 500MHz clock), which ensures data format compliance and reduces the risk of transmission errors. The encoded parallel data received by the parallel data interface is output by the 8bit / 10bit encoder of the system, and the data format strictly follows the 8bit / 10bit encoding rules, which can expand 8bit effective data into 10bit parallel data containing synchronization code and check code. The synchronization code is used for time sequence synchronization between the parallel-serial conversion circuit 205 and the off-chip receiving module 1, and the check code is used for detecting data errors in the transmission process. Finally, the 10 parallel data lines (each data line is provided with a signal buffer and is reinforced by a ring-shaped grid) can be transmitted to the parallel-serial conversion circuit 205. It is the original data source for generating high-speed serial data, which ensures time sequence synchronization and no delay of each parallel data line, and avoids time sequence deviation of parallel data transmission.

[0046] It is easy to understand that the second receiver 212 can be a core signal receiver of the external clock source branch, a radio frequency receiver reinforced by a ring-shaped grid, and an input end can receive a high-frequency clock signal (such as 500 MHz) sent by an external system, and an output end is connected with the second switch module. The function is to demodulate, amplify, and filter the external input clock signal, remove signal noise and interference, generate a standard clock signal required by the parallel-to-serial conversion circuit 205, and serve as a backup for the internal phase-locked loop 206, so as to solve the problem of clock interruption caused by single phase-locked loop failure. At this time, the second switch module can be a numerical control switch component for controlling the switching connection of the "internal clock source branch" and the "external clock source branch" to the parallel-to-serial conversion circuit 205 in the data transmission link 20, which can be composed of the third switch unit S3 and the fourth switch unit S4. The input ends are respectively connected with the output end of the phase-locked loop 206 and the output end of the second receiver 212, and the output end is connected with the clock input end of the parallel-to-serial conversion circuit 205. The function is to realize accurate switching of the two clock source branches, avoid clock signal conflict, and ensure that the parallel-to-serial conversion circuit 205 always receives stable clock signals.

[0047] In a feasible implementation, in the embodiment, the second switch module includes a third switch unit S3 and a fourth switch unit S4; The third switch unit S3 is configured to, in a case where a clock control signal is received, connect the phase-locked loop 206 and the parallel-to-serial conversion circuit 205, so as to transmit the internal clock signal generated by the phase-locked loop 206 to the parallel-to-serial conversion circuit 205; The second switch module is configured to, in a case where the clock control signal is received, transmit the external clock signal received by the second receiver 212 to the parallel-to-serial conversion circuit 205 according to the clock control signal; The parallel-to-serial conversion circuit 205 is configured to generate the high-speed serial data according to the encoded parallel data and the internal clock signal or the external clock signal, and transmit the high-speed serial data to the communication module.

[0048] It is understood that the third switch unit S3 can be a numerical control switch in the second switch module, which is specially used for controlling the connection between the internal clock source branch (the phase-locked loop 206) and the parallel-to-serial conversion circuit 205. The fixed end 3.1 is hard-connected with the output end of the phase-locked loop 206 through a metal wire, the fixed end 3.2 is hard-connected with the clock input end of the parallel-to-serial conversion circuit 205, and the control end only receives the instruction (such as high-level conduction (corresponding to the clock control signal) and low-level disconnection) for the internal clock source in the clock control signal. The third switch unit S3 has independent on-off logic, ensures that the 500 MHz high-frequency clock signal output by the phase-locked loop 206 is accurately transmitted to the parallel-to-serial conversion circuit 205, and avoids signal interference with the external clock source branch.

[0049] The fourth switch unit S4 can be a digital control switch in the second switch module specially controlling the connection of the external clock source branch (the second receiver 212) and the parallel-serial conversion circuit 205, also reinforced by the ring-shaped grid. The fixed end 4.1 is hard-connected with the output end of the second receiver 212, the fixed end 4.2 is hard-connected with the clock input end of the parallel-serial conversion circuit 205, and the control end receives the instruction for the external clock source in the clock control signal, forming the mutually exclusive control logic with S3 (i.e. S3 is closed when S4 is opened, and S4 is closed when S3 is opened), completely avoiding the signal conflict caused by the simultaneous input of the signals of the two clock branches into the parallel-serial conversion circuit 205, and ensuring the purity and stability of the clock signal.

[0050] It should be understood that the parallel-serial conversion circuit 205 can convert the 8bit / 10bit parallel data into single-channel high-speed serial data under the driving of the high-frequency clock signal (internal or external) according to the logic of "clock rising edge sampling, bit-by-bit serial output". For example, under the driving of a 500MHz clock, a group of 10bit parallel data is sampled every clock cycle (2ns), and is output in the order of "bit 1 (synchronization bit) -> bit 2 -> … -> bit 10 (check bit)" to form a 500Mbps high-speed serial data stream, ensuring that the off-chip receiving module 1 can accurately parse the data.

[0051] For example, when the clock frequency deviation is ≤±0.5% and the phase jitter is ≤100ps, the clock control signal can be generated and output to S3, the internal metal contact of S3 is closed, S4 is opened, the 500MHz clock signal output by the phase-locked loop 206 is transmitted to the main clock input end of the parallel-serial conversion circuit 205 through S3, and is used as the main clock for data conversion. At this time, the parallel-serial conversion circuit 205 enters the "internal clock driving mode"; When the clock frequency deviation of the phase-locked loop 206 is >±0.5% and the phase jitter is >100ps, or the signal is missing (for example, the phase-locked loop 206 or the voltage-controlled oscillator 210 is malfunctioned due to the impact of high-energy particles in space), the clock control signal can be switched to S4 immediately (response time ≤30ns), S3 is opened, S4 is closed, the 500MHz external clock signal received and processed by the second receiver 212 is transmitted to the standby clock input end of the parallel-serial conversion circuit 205 through S4, and is switched to the "external clock driving mode", ensuring uninterrupted clock driving.

[0052] Therefore, the embodiment can realize selective communication of the high-frequency clock signal of the "internal clock source branch" or the "external clock source branch" with the clock interface of the parallel-serial conversion circuit 205 by switching the on-off state of the third switch unit S3 and the fourth switch unit S4 in the second switch module. For example, when the internal clock source is normal, S3 is closed, S4 is disconnected, and the clock signal output by the phase-locked loop 206 is transmitted to the parallel-serial conversion circuit 205; when the internal clock source fails, S3 is disconnected, S4 is closed, and the clock signal output by the second receiver 212 is transmitted to the parallel-serial conversion circuit 205, ensuring uninterrupted supply of the clock signal.

[0053] In addition, the double clock source branch proposed in the embodiment realizes "one main and one backup" switching through the second switch module, without the need to additionally increase the redundant parallel-serial conversion circuit 205. Compared with the existing circuit-level reinforcement redundancy scheme, the circuit area is only increased by 15%, the power consumption is reduced by 20%, and the integrated demand of "small volume and high density" of space equipment, nuclear industrial instruments and the like can be adapted, avoiding the defect that the area occupied by the traditional redundancy design is too large. Among them, the internal clock source can meet the autonomous working scene (such as when the deep space probe lander and the earth communication are interrupted, the probe data needs to be transmitted autonomously), and the external clock source is suitable for the cooperative working scene (such as the low earth orbit satellite and the ground base station synchronous data transmission), compared with the single clock source design, the application scene is more extensive and the flexibility is higher.

[0054] In a feasible implementation mode, referring to Figure 4 , Figure 4 FIG. 2 is a structural schematic diagram of a phase-locked loop of an anti-radiation data transmission circuit embodiment of the present application. In the embodiment, the phase-locked loop 206 includes a frequency discriminator 207, a charge pump 208, a loop filter 209, a voltage-controlled oscillator 210, and a frequency divider 211. The input end of the frequency discriminator 207 is connected with the output end of the drive shaping circuit 203 and the output end of the frequency divider 211, respectively. The output end of the frequency discriminator 207 is connected with the input end of the charge pump 208. The output end of the charge pump 208 is connected with the input end of the loop filter 209. The output end of the loop filter 209 is connected with the input end of the voltage-controlled oscillator 210. The output end of the voltage-controlled oscillator 210 is connected with the input end of the frequency divider 211 and the second switch module, respectively.

[0055] It is easy to understand that in the internal clock source branch, the base frequency signal (such as 100MHz) output by the crystal oscillator starting circuit 10 is input into the phase-locked loop 206, and the signal processing is strictly in accordance with the internal structure of the phase-locked loop 206, that is, the design of the above frequency discriminator and phase discriminator 207, charge pump 208, loop filter 209, voltage controlled oscillator 210, frequency divider 211. Exemplarily, the base frequency signal can be compared with the feedback signal of the frequency divider 211 through the frequency discriminator and phase discriminator 207, the output frequency of the voltage controlled oscillator 210 is adjusted through the charge pump 208 and the loop filter 209, and a 500MHz high frequency clock signal is generated, which is directly transmitted to the clock input end of the parallel-serial conversion circuit 205 to provide driving for parallel data conversion.

[0056] Among them, the frequency discriminator and phase discriminator 207 (PFD, Phase Frequency Detector) is the core comparison device of the phase-locked loop 206, has two signal input ends, and the function is to compare the frequency and phase of the “base frequency signal output by the crystal oscillator starting circuit 10” (reference signal, such as 100MHz) and the “feedback signal output by the frequency divider 211”. If the reference signal frequency is higher than the feedback signal, a high level UP signal is output; if the reference signal frequency is lower than the feedback signal, a high level DN signal is output; if the frequency and phase are consistent, no signal is output, which provides the basis for error control for the subsequent charge pump 208.

[0057] The input end of the charge pump 208 (CP, Charge Pump) receives the UP / DN signal output by the frequency discriminator and phase discriminator 207, and the output end is connected with the loop filter 209. The function is to convert the digital error signal (UP / DN) output by the frequency discriminator and phase discriminator 207 into an analog current signal: when receiving the UP signal, a positive current (such as 100μA) is output to inject into the loop filter 209; when receiving the DN signal, a reverse current (such as -100μA) is output to extract current from the loop filter 209, and the voltage of the loop filter 209 is adjusted through the current change to realize the frequency control of the voltage controlled oscillator 210.

[0058] The loop filter 209 (LF, Loop Filter) can adopt an RC active filter structure composed of a resistor (1kΩ), a capacitor (100pF) and an operational amplifier. The function is to filter out the high frequency noise and ripple (such as high frequency noise caused by radiation) in the output current of the charge pump 208, generate a stable direct current control voltage signal, avoid noise interference to cause the clock signal output by the voltage controlled oscillator 210 to jitter, ensure the loop stability of the phase-locked loop 206, make the phase jitter of the output clock signal ≤50ps, and realize low jitter of the clock signal.

[0059] And the voltage-controlled oscillator 210 (VCO, Voltage-Controlled Oscillator) input end receives the loop filter 209 output of the direct current control voltage signal (such as 0.5V~3.3V), the output end is divided into two ways (one way connection second switch module (in the third switch unit S3), a way connection frequency divider 211). Function is to adjust the output signal frequency according to the size of the input control voltage: control voltage rises, output frequency rises; Control voltage decreases, output frequency decreases, the frequency adjustment range is 200MHz-1GHz, can generate and serial conversion circuit 205 required 500MHz high frequency clock signal.

[0060] Finally, the input end of the frequency divider 211 (Divider) is connected to the output end of the voltage-controlled oscillator 210, and the output end is connected to the feedback signal input end of the phase frequency detector 207. The function is to divide the high frequency clock signal output by the voltage-controlled oscillator 210 according to the preset frequency division ratio (such as 1:5, according to the requirement of "base frequency signal 100MHz→high frequency clock signal 500MHz" setting) to generate 100MHz feedback signal, transmission to the phase frequency detector 207 and reference signal Vref comparison, form the closed loop control of the phase-locked loop 206, ensure the stability of the output frequency of the voltage-controlled oscillator 210. Exemplarily, when the space high energy particle hits the voltage-controlled oscillator 210 and causes the output frequency to drop from 500MHz to 480MHz, the frequency divider 211 can output 96MHz feedback signal, the phase frequency detector 207 detects 4MHz frequency difference, output UP signal, charge pump 208 inject current, loop filter 209 control voltage rises, the output frequency of the voltage-controlled oscillator 210 rises to 500MHz, 1μs relock, ensure the stability of the clock signal.

[0061] In summary, in this embodiment, there is a signal transmission and feedback path of "frequency discriminator and phase detector 207→ charge pump 208→ loop filter 209→ voltage controlled oscillator 210→ frequency divider 211→ frequency discriminator and phase detector 207" inside the phase-locked loop 206. Through this closed loop, the frequency discriminator and phase detector 207 continuously compares the reference signal and the feedback signal, and constantly adjusts the output frequency of the voltage controlled oscillator 210, so that the frequency and phase of the clock signal output by the voltage controlled oscillator 210 are finally completely locked with the reference signal (i.e. "phase-locked" state), ensuring the long-term stability of the high-frequency clock signal. Even if it is disturbed by space high-energy particle radiation, the loop can re-lock the frequency within 1 μs, ensuring that the phase-locked loop 206 can generate a stable high-frequency clock signal in a strong radiation environment, providing reliable driving for the parallel-to-serial conversion circuit 205 and meeting the clock demand of high-speed data transmission. At the same time, compared with the existing circuit-level hardened phase-locked loop 206 (which adopts double-module parallel redundancy), the layout-level ring gate reinforcement in this embodiment only increases the circuit area by 20% and reduces the power consumption by 30%, which adapts to the constraint conditions of "low power consumption and small size" of space equipment and avoids the problem of excessive area occupation of traditional redundancy design.

[0062] In a feasible implementation, in this embodiment, the ring gate reinforcement technology is implemented in the layout design of the drive shaping circuit 203, the phase-locked loop 206, the parallel-to-serial conversion circuit 205, the communication module, the first receiver 204 and the second receiver 212.

[0063] It should be noted that, in this embodiment, the ring gate reinforcement technology belongs to layout-level reinforcement technology, that is, the ring gate structure can be integrated into the device layout in the physical layout design stage of each module of the circuit. In this embodiment, the ring gate structure (such as the ring gate surrounding the source / drain region) can be designed in the transistor layout to reduce single event effect damage. In order to facilitate understanding, reference is made to Figure 5 for example, Figure 5 the reinforcement schematic diagram of the ring gate reinforcement technology of the anti-radiation data transmission circuit embodiment of the present application, Figure 5 (a) is the nmos ring gate layout, Figure 5 (b) is the pmos ring gate layout. Therefore, as Figure 5 shown, the specific implementation can be: for nmos transistors, the structure of "ring-shaped source region surrounding drain region, gate wrapping source and drain region" is adopted, and for pmos transistors, the layout of "symmetrical ring gate, symmetrical distribution of source and drain regions" is adopted. By optimizing the spatial isolation distance of the device (such as increasing the isolation distance between the source and drain regions and the substrate to 0.5 μm) and the charge collection path, the damage of single event effect (such as single event upset and single event latchup) to the function of the device is inhibited, and the function stability of all modules in a strong radiation environment is ensured.

[0064] Exemplarily, the process of driving the layout reinforcement of the shaping circuit 203 can be to perform a ring gate design on the RC filter circuit resistance / capacitance, the Schmidt trigger transistor, and the operational amplifier transistor in the driving shaping circuit 203. For example, the nmos transistor of the Schmidt trigger adopts a ring source-drain region structure (the source region surrounds the drain region, and the gate wraps the source-drain region), the pmos transistor adopts a symmetric ring gate layout, the device spacing isolation distance is set to 0.5 μm, signal crosstalk caused by radiation interference is reduced; at the same time, the wiring rules are optimized, the signal path is separated from the power path, further reducing noise coupling caused by radiation, and ensuring the stable anti-interference processing function of the initial frequency signal / driving frequency signal.

[0065] And the process of locking the layout reinforcement of the phase-locked loop 206 can be to implement ring gate reinforcement on all devices such as the frequency discriminator 207, the charge pump 208, the loop filter 209, the voltage-controlled oscillator 210, and the frequency divider 211. Among them, the oscillation tube of the voltage-controlled oscillator 210 adopts a double-ring gate structure (nmos and pmos ring gate cross layout), which improves the frequency stability; the trigger of the frequency divider 211 adopts a ring gate isolation design to avoid single event upset caused by frequency division ratio error; the operational amplifier of the loop filter 209 adopts a ring gate input stage to reduce the input offset voltage caused by radiation, ensuring the reliability of the closed-loop control of the phase-locked loop 206 and the stability of the output high-frequency clock signal.

[0066] And the process of locking the layout reinforcement of the parallel-serial conversion circuit 205 can be to perform a ring gate design on the storage unit of the parallel data buffer, the trigger of the shift register, and the LVDS driver of the differential output interface. The storage unit adopts a ring gate reinforced SRAM structure to prevent data flip caused by radiation; each trigger stage of the shift register adopts a ring gate transistor to ensure accurate data shift timing; the driver of the differential output interface adopts a symmetric ring gate layout to ensure the amplitude balance of the LVDS signal differential pair and avoid signal distortion caused by radiation.

[0067] The process of locking the layout reinforcement of the communication module (transmitter module) can be to adopt a ring gate structure for the output stage transistor of the LVDS transmitter, optimize the output impedance matching (set to 100 Ω), and reduce the output signal reflection caused by radiation; at the same time, a ring ground shielding ring is arranged around the transmitter to isolate external radiation noise, ensuring that after the high-speed serial data is converted into an LVDS signal, it can be stably transmitted to the off-chip receiving module 1.

[0068] The process of the first receiver 204 and the second receiver 212 layout reinforcement can be to implement ring gate reinforcement on the radio frequency front-end transistor, demodulation circuit device, and signal amplification circuit operational amplifier of the two receivers. The radio frequency front-end adopts a ring gate low noise amplifier to improve the receiving sensitivity while resisting radiation interference; the mixer of the demodulation circuit adopts a ring gate structure to avoid radiation-induced demodulation phase deviation; the input stage of the operational amplifier of the signal amplification circuit adopts a ring gate transistor to reduce the radiation-induced increase in noise figure, ensuring that the two receivers can stably receive the driving frequency signal and the external high-frequency clock signal, respectively.

[0069] In the embodiment, the driving shaping circuit 203, the phase-locked loop 206, the parallel-serial conversion circuit 205, the communication module, the first receiver 204, and the second receiver 212 can be covered by the ring gate reinforcement technology to ensure that all key modules affecting data transmission have strong anti-radiation capabilities, the performance of the circuit is stable in a strong radiation environment, and performance fluctuations caused by reinforcement methods are avoided.

[0070] It can be understood that the communication module described above can be a functional module responsible for sending high-speed serial data to an off-chip in the data transmission link 20, the core device is a transmitter, has signal buffering and level conversion (such as converting LVCMOS level to LVDS level) functions, can reduce signal attenuation during data transmission, and adapts to long-distance (such as 10 m) transmission requirements. It is a key link connecting the parallel-serial conversion circuit 205 and the off-chip receiving module 1, and ensures that high-speed serial data is transmitted without distortion in a radiation environment.

[0071] The off-chip receiving module 1 can be a high-speed data receiving device (such as a signal processing unit of a space probe or a receiving device of a ground receiving station) located outside the anti-radiation data transmission circuit, which needs to have an interface protocol (such as an LVDS protocol) and anti-radiation capability matching the communication module. The function is to receive high-speed serial data sent by the communication module, perform serial-parallel conversion, and then transmit it to a subsequent data processing unit (such as an ADC data analysis module) to complete the data transmission loop.

[0072] At this time, the serial data output end of the parallel-serial conversion circuit 205 can be connected to the input end of the communication module through a differential signal line (such as a twisted pair line). The communication module converts the LVCMOS level (1.8V) high-speed serial data output by the parallel-serial conversion circuit 205 into an LVDS level (±350mV) to reduce transmission attenuation (the LVDS level has stronger anti-radiation interference capability), and then transmits it to the off-chip receiving module 1 through a special shielded cable. The off-chip receiving module 1 receives it, converts it from an LVDS level to an LVCMOS level, and performs serial-parallel conversion to restore it to 8-bit parallel data, completing the data transmission process.

[0073] In summary, the embodiment can construct an anti-radiation data transmission circuit comprising the crystal oscillator starting circuit 10 and the data transmission link 20. The crystal oscillator starting circuit 10 is designed as a double backup structure of "external crystal oscillator branch 101 + external signal branch 102". The external crystal oscillator branch 101 is composed of an anti-radiation external crystal oscillator 202 and a driving shaping circuit 203 in series, and the external signal branch 102 is composed of a receiver and a driving shaping circuit 203 in series. The data transmission link 20 comprises a phase-locked loop 206 circuit, a parallel-serial conversion circuit 205, a receiver module (second receiver 212), and a transmitter module, which are connected in sequence according to the signal transmission sequence.

[0074] Firstly, all devices (external crystal oscillator 202, receiver, driving shaping circuit 203) of the crystal oscillator starting circuit 10 and all modules (phase-locked loop 206, parallel-serial conversion circuit 205, second receiver 212, transmitter) of the data transmission link 20 can be optimized by using the annular gate reinforcement technology for layout design. For example, an annular gate structure is constructed in the nmos device layout of the driving shaping circuit 203, and an annular gate layout is integrated in the pmos device layout of the phase-locked loop 206 circuit, so as to enhance the resistance of each module to single particle effect and realize systematic anti-radiation reinforcement.

[0075] Then, during the signal generation and transmission process, when working normally, the external crystal oscillator branch 101 is preferentially enabled: the external crystal oscillator 202 (with anti-radiation characteristics) generates an initial frequency signal, which is transmitted to the driving shaping circuit 203 to generate a basic frequency signal after anti-interference processing such as filtering and shaping; if the external crystal oscillator branch 101 fails due to radiation (such as abnormal initial frequency signal), the external signal branch 102 is enabled through branch switching: the receiver receives an external driving frequency signal, which is also transmitted to the driving shaping circuit 203 for processing to generate a basic frequency signal. Subsequently, when the basic frequency signal is transmitted to the data transmission link 20, it can be first input to the phase-locked loop 206 circuit, and after the closed-loop processing of the frequency discriminator and phase discriminator 207, the charge pump 208, the loop filter 209, the voltage-controlled oscillator 210, and the frequency divider 211, a high-frequency clock signal (such as a 500M reference clock) is generated, which drives the parallel-serial conversion circuit 205 to convert the parallel data output by the 8bit / 10bit encoder into high-speed serial data, which is sent to the off-chip receiving module 1 according to the preset timing by the transmitter module, completing the data transmission; if the basic frequency signal is problematic, the above process is realized by the alternative external clock signal.

[0076] Therefore, the crystal oscillator starting circuit 10 in the embodiment adopts a "external crystal oscillator branch 101 + external signal branch 102" dual backup design. Even if one branch fails due to radiation, it can quickly switch to the other branch to continuously output the basic frequency signal, avoid the interruption of the clock reference source, provide a stable clock reference for the data transmission link 20, and solve the problem of insufficient reliability of the clock reference source in the prior art.

[0077] At the same time, the clock reference is stable and the circuit has enhanced anti-radiation capability, ensuring that the data transmission link 20 can accurately convert the encoded data output by the ADC into high-speed serial data and transmit it to the outside of the chip, reducing transmission errors and ensuring the long-term stable operation of the entire data transmission system in a space extreme environment. Compared with the prior art (such as a single reinforcement method), the anti-radiation performance and reliability are better.

[0078] Finally, all modules of the circuit are subjected to systematic anti-radiation treatment through the ring gate reinforcement technology. Through this comprehensive reinforcement method, the single particle effect of high-energy particle radiation on the device is effectively suppressed, the risk of radiation-induced abnormal circuit function is reduced, and the circuit can work stably for a long time in a strong radiation environment. This makes up for the short board of the lack of anti-radiation capability of the crystal oscillator starting circuit in the prior art, and ensures the reliability and stability of the clock reference signal in a space environment.

[0079] The embodiment discloses an anti-radiation data transmission circuit, device and system. The anti-radiation data transmission circuit comprises a crystal oscillator starting circuit and a data transmission link. The crystal oscillator starting circuit and the data transmission link are both subjected to structural enhancement by adopting a ring gate reinforcement technology. The crystal oscillator starting circuit comprises an external signal branch and an external crystal oscillator branch which are backup to each other. The data transmission link is used for converting a basic frequency signal output by the external signal branch or the external crystal oscillator branch into high-speed serial data, and sending the high-speed serial data to an off-chip receiving module. Compared with the prior art, the embodiment adopts branch backup (such as a crystal oscillator and a clock branch) and switch control logic throughout the process, thereby enhancing the system redundancy. At the same time, all modules have integrated the ring gate reinforcement technology at the layout design stage, thereby ensuring signal stability in a space radiation environment (such as high-energy particle influence) and reducing the risk of failure. The reliability and stability of the data transmission link in a space environment are significantly improved.

[0080] To achieve the above object, the application further provides an anti-radiation data transmission device, which comprises the anti-radiation data transmission circuit.

[0081] At this time, the anti-radiation data transmission circuit (full module ring-shaped gate reinforcement, optimal anti-radiation capability) can be used as the device core, all devices of the circuit, such as the crystal oscillator starting circuit 10 and the data transmission link 20, are integrated on a ceramic substrate (with radiation shielding capability), and a metal shell package (shell thickness 0.5 mm, titanium alloy material, further blocking external radiation) is adopted; Meanwhile, three interfaces are arranged outside the device: ① power supply interface (adopting an anti-radiation connector, inputting 1.8V DC power supply to supply power to each module of the circuit); ② parallel data input interface (receiving 8bit / 10bit encoded parallel data output by the ADC); and ③ serial data output interface (adopting an LVDS protocol, connecting an off-chip receiving module 1 to transmit high-speed serial data).

[0082] Since the anti-radiation data transmission device adopts all the technical solutions of the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0083] To achieve the above object, the application further provides an anti-radiation data transmission system, which comprises the anti-radiation data transmission device. An off-chip receiving module is configured to receive high-speed serial data transmitted by the anti-radiation data transmission device. An encoder is configured to provide encoded parallel data to the anti-radiation data transmission device.

[0084] It is easy to understand that the anti-radiation data transmission system can be a complete data transmission system composed of the anti-radiation data transmission device, the off-chip receiving module and the encoder, and the function is to realize the whole process of "analog signal→digital parallel data→high-speed serial data→data reception", which guarantees the end-to-end stable transmission of ADC output data in a strong radiation environment.

[0085] The off-chip receiving module is a receiving end device of the system, and the core devices include an LVDS receiver (ring-shaped gate reinforcement) and a serial-parallel conversion circuit (ring-shaped gate reinforcement), and the function is to receive high-speed serial data transmitted by the anti-radiation data transmission device, convert the high-speed serial data into parallel data, and then transmit the parallel data to a subsequent data processing unit (such as a CPU or a storage module).

[0086] The encoder can be the encoding end device of the system, and an 8bit / 10bit encoder (ring fence reinforcement) is adopted. The function is to receive the 8bit original digital data output by the ADC, convert it into 10bit coded parallel data according to the 8bit / 10bit coding rule (such as adding synchronization code and check code), and transmit it to the parallel data input interface of the anti-radiation data transmission device. The coding process needs to ensure data synchronization to avoid subsequent parallel-serial conversion errors.

[0087] The specific structure of the anti-radiation data transmission device refers to the above-mentioned embodiments. Since the encoder, the anti-radiation data transmission device, and the off-chip receiving module of the system are all ring fence reinforced, the anti-radiation data transmission system adopts all the technical solutions of the above-mentioned embodiments, and therefore at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

[0088] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A radiation-resistant data transmission circuit, characterized in that, The radiation-resistant data transmission circuit includes a crystal oscillator circuit and a data transmission link, both of which are structurally reinforced using ring gate hardening technology. The crystal oscillator starting circuit includes an external signal branch and an external crystal oscillator branch that serve as backups for each other. The data transmission link is used to convert the fundamental frequency signal output by the external signal branch or the external crystal oscillator branch into high-speed serial data, and send the high-speed serial data to the off-chip receiving module.

2. The radiation-resistant data transmission circuit as described in claim 1, characterized in that, The radiation-resistant data transmission circuit further includes: a first switching module; the external crystal oscillator branch includes an external crystal oscillator and a driving and shaping circuit connected in series, and the external signal branch includes a first receiver and the driving and shaping circuit connected in series; The first switch module is connected to the external crystal oscillator, the first receiver, and the drive shaping circuit, respectively. The external crystal oscillator branch and the external signal branch are switched to the drive shaping circuit through the first switching module.

3. The radiation-resistant data transmission circuit as described in claim 2, characterized in that, The first switch module includes a first switch unit and a second switch unit; The first switching unit is used to connect the external crystal oscillator and the driving shaping circuit when a start control signal is received, so as to transmit the initial frequency signal generated by the external crystal oscillator to the driving shaping circuit. The second switching unit is used to connect the first receiver and the drive shaping circuit when the start control signal is received, so as to transmit the drive frequency signal input by the first receiver to the drive shaping circuit. The driving shaping circuit is used to perform anti-interference processing on the initial frequency signal or the driving frequency signal to generate the basic frequency signal.

4. The radiation-resistant data transmission circuit as described in claim 3, characterized in that, The data transmission link includes an internal clock source branch and an external clock source branch that serve as backups for each other, as well as a communication module; Both the internal clock source branch and the external clock source branch are connected to the communication module, and the communication module is connected to the off-chip receiving module; The communication module is used to send high-speed serial data transmitted by the internal clock source branch or the external clock source branch to the off-chip receiving module.

5. The radiation-resistant data transmission circuit as described in claim 4, characterized in that, The radiation-resistant data transmission circuit further includes: a second switching module; the internal clock source branch includes a series-connected phase-locked loop and a parallel-to-serial conversion circuit; the external clock source branch includes a series-connected second receiver and the parallel-to-serial conversion circuit; The second switching module is connected to the phase-locked loop, the second receiver, and the parallel-to-serial conversion circuit, respectively. The internal clock source branch and the external clock source branch are switched to the parallel-to-serial conversion circuit through the first switching module.

6. The radiation-resistant data transmission circuit as described in claim 5, characterized in that, The second switch module includes a third switch unit and a fourth switch unit; The third switching unit is used to connect the phase-locked loop and the parallel-to-serial conversion circuit when a clock control signal is received, so as to transmit the internal clock signal generated by the phase-locked loop to the parallel-to-serial conversion circuit. The second switching module is used to transmit the external clock signal received by the second receiver to the parallel-to-serial conversion circuit according to the clock control signal when the clock control signal is received. The parallel-to-serial conversion circuit is used to generate the high-speed serial data based on the encoded parallel data and the internal clock signal or the external clock signal, and to send the high-speed serial data to the communication module.

7. The radiation-resistant data transmission circuit as described in claim 6, characterized in that, The phase-locked loop includes: a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider; The input terminals of the frequency and phase detector are connected to the output terminals of the drive shaping circuit and the frequency divider, respectively. The output terminal of the frequency and phase detector is connected to the input terminal of the charge pump. The output terminal of the charge pump is connected to the input terminal of the loop filter. The output terminal of the loop filter is connected to the input terminal of the voltage-controlled oscillator. The output terminal of the voltage-controlled oscillator is connected to the input of the frequency divider and the second switching module, respectively.

8. The radiation-resistant data transmission circuit as described in claim 7, characterized in that, The ring gate hardening technology is implemented in the layout design of the drive shaping circuit, the phase-locked loop, the parallel-to-serial conversion circuit, the communication module, the first receiver, and the second receiver.

9. A radiation-resistant data transmission device, characterized in that, The radiation-resistant data transmission device includes the radiation-resistant data transmission circuit according to any one of claims 1-8.

10. A radiation-resistant data transmission system, characterized in that, The radiation-resistant data transmission system includes the radiation-resistant data transmission device as described in claim 9; An off-chip receiving module is used to receive high-speed serial data sent by the radiation-resistant data transmission device; An encoder is used to provide encoded parallel data to the radiation-resistant data transmission device.

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