Programmable gate array chip architecture

Abstract

The invention relates to the technical field of integrated circuits. The invention discloses a programmable gate array chip architecture. According to the technical scheme, the system comprises BLOCK modules arranged in an array, each BLOCK module comprises functional modules and an interconnection module, and the system is characterized in that the functional modules are configured on the two sides of the interconnection module to receive data transmitted by the interconnection module. According to the technical scheme, half of interconnection modules of the FPGA chip can be reduced, the area and the cost of the FPGA chip are greatly reduced, the power consumption of the FPGA chip is effectively reduced, and especially for a large-scale integrated circuit (such as a hundred million gate level FPGA chip), the energy-saving effect is very considerable. By adopting the interconnection module provided by the invention, the chip wiring is more flexible, and the chip area can be saved. According to the interconnection circuit, the transmission gate is used as a selection switch, so that the power consumption and the complexity of the circuit are further reduced. The technical scheme provided by the invention is particularly suitable for the FPGA chip with an advanced technological process.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to FPGA (Field Programmable Gate Array), and more particularly to a programmable gate array chip architecture. BACKGROUND

[0003] In FPGA integrated circuits, various functional modules are usually included, such as IOB (Input / Output Block), CLB (Configurable Logic Block), DSP (Digital Signal Processing), etc. These functional modules need to receive data through INTE (Interconnect Tile) to complete their different functions. The functional modules and the interconnection modules together constitute the array unit (BLOCK module) of the FPGA, and the FPGA chip is composed of these BLOCK modules arranged in an array.

[0004] The interconnection module usually includes several interconnection circuits SM (Switch Matrix). The interconnection circuits in the traditional interconnection module do not transmit data between them, and the wiring flexibility is poor. The interconnection module can only be interconnected with the functional module on one side. The architecture of the FPGA is one column of functional modules plus one column of interconnection modules, i.e. one interconnection module corresponds to one side of the functional module, as shown in FIG. 1. Figure 1 In order to improve the routing rate of the chip, more interconnection circuits are needed, which increases the chip area and power consumption.

[0005] On the other hand, in the prior art, the interconnection module using the traditional CMOS (Complementary Metal Oxide Semiconductor) process accounts for about 70% of the entire FPGA chip area. In addition to the above-described reason of more interconnection circuits, the feature size of the traditional CMOS process is relatively large (more than 22 nm), and the interconnection module is the most in the FPGA. In order to save area, the interconnection circuit often uses NMOS transistor as a switching unit. The disadvantage of this single-tube data transmission is that it will cause threshold loss, so the interconnection circuit needs an additional threshold compensation circuit, which invisibly increases the chip area.

[0006] At the same time, a large number of interconnection modules also occupy most of the power consumption of the FPGA. SUMMARY

[0007] The main purpose of the present application is to provide a programmable gate array chip architecture to solve the problem of large chip area and high power consumption in the prior art.

[0008] In order to achieve the above-mentioned purpose, according to one aspect of the embodiment of the present application, a programmable gate array chip architecture is provided, comprising BLOCK modules arranged in an array, the BLOCK module comprising a functional module and an interconnection module, characterized in that the functional module is configured to receive data transmitted by the interconnection module on both sides of the interconnection module.

[0009] Further, the interconnection module comprises j first interconnection circuits and k second interconnection circuits; the first interconnection circuit comprises two n-select-one selectors with the same structure, and the second interconnection circuit comprises a four-select-one selector; the input end of the n-select-one selector is connected to an input signal, and the output end is connected to the input end of the four-select-one selector; the output end of the four-select-one selector is connected to the functional module; wherein j, k, n are all integers greater than or equal to 1.

[0010] Further, the n-select-one selector is connected with a half-latch circuit at the output end.

[0011] Further, the two n-select-one selectors with the same structure share one weak pull-up circuit.

[0012] Further, the output end of the four-select-one selector is connected with a pull-down circuit and an inverter.

[0013] Specifically, the inverter comprises one PMOS transistor and one NMOS transistor, the gate of the PMOS transistor and the gate of the NMOS transistor are connected to form the input end of the inverter, the drain of the PMOS transistor and the drain of the NMOS transistor are connected to form the output end of the inverter, the source of the PMOS transistor is connected to the power supply, and the source of the NMOS transistor is connected to the ground.

[0014] Specifically, the selection switch of the n-select-one selector and the four-select-one selector is composed of a transmission gate.

[0015] Specifically, the transmission gate comprises one PMOS transistor and one NMOS transistor, the gate of the PMOS transistor and the gate of the NMOS transistor are two enable ends of the transmission gate, the drain of the PMOS transistor and the drain of the NMOS transistor are connected to form the input end of the transmission gate, the source of the PMOS transistor and the source of the NMOS transistor are connected to form the output end of the transmission gate, and the substrate of the PMOS transistor and the substrate of the NMOS transistor are respectively connected to the power supply and the ground.

[0016] Further, the enable end is independently configured to ensure that only one transmission gate in the n-select-one selector and the four-select-one selector is in an open state at the same time.

[0017] Further, the BLOCK module data width is not limited by the interconnection module.

[0018] According to the technical scheme of the present application and the further improved technical scheme in some exemplary embodiments, the present application has the following beneficial effects: The technical scheme of the present application can reduce half of the interconnection modules of the FPGA chip, greatly reducing the FPGA chip area and cost, effectively reducing the power consumption of the FPGA chip, and particularly for large-scale integrated circuits (such as billion-gate FPGA chips), the energy-saving effect is very considerable. Using the interconnection module of the present application, the chip wiring is more flexible, which is also beneficial to saving chip area. The interconnection circuit of the present application uses a transmission gate as a selection switch, further reducing power consumption and circuit complexity. The technical scheme of the present application is particularly suitable for advanced process FPGA chips.

[0019] The present application will be further described below in conjunction with the drawings and specific embodiments. The additional aspects and advantages of the present application will be partially given in the following description, partially become apparent from the following description, or be known by the practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings, which form a part of this application, are included to provide a further understanding of the application, and are incorporated in and constitute a part of this application. The specific embodiments of the application and the illustrative examples thereof, and specific examples of the application are intended to explain the application, and are not intended to limit the application. In the drawings: Figure 1 It is a schematic diagram of the existing FPGA array unit structure; Figure 2 It is a schematic diagram of the FPGA chip architecture of the specific embodiment of the present application; Figure 3 It is a schematic diagram of the FPGA array unit structure of the specific embodiment of the present application; Figure 4 It is a schematic diagram of the first interconnection circuit structure of the specific embodiment of the present application; Figure 5 It is a schematic diagram of the second interconnection circuit structure of the specific embodiment of the present application; Figure 6 It is a schematic diagram of the transmission gate structure of the specific embodiment of the present application; Figure 7 It is a schematic diagram of the inverter structure of the specific embodiment of the present application; Figure 8 It is a schematic diagram of the combined threshold design power consumption comparison simulation of the specific embodiment of the present application. DETAILED DESCRIPTION

[0023] It should be noted that the specific embodiments, exemplary embodiments, and features in the present application can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the following contents.

[0024] In order for those skilled in the art to better understand the solutions of the present application, the technical solutions in the specific embodiments, exemplary embodiments of the present application will be described in detail below with reference to the accompanying drawings. Obviously, the described exemplary embodiments are only a part of the embodiments of the present application, not all. Based on the specific embodiments, exemplary embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should be within the scope of protection of the present application.

[0025] The programmable gate array chip architecture of the present application is composed of BLOCK modules arranged in an array as shown in Figure 2 The BLOCK module includes a functional module and an interconnection module. The functional module is configured on both sides of the interconnection module to receive the data transmitted by the interconnection module, as shown in Figure 3 The BLOCK module is also called an array unit. The functional module therein can be an IOB module, a CLB module, or a DSP module, etc. according to needs.

[0026] The data ports of the BLOCK module can be set according to the requirements of different functional modules, and are not limited by the data ports of the interconnection module. They can be greater than or less than the number of data ports of the interconnection module. Embodiment

[0027] The interconnection module in this example includes j first interconnection circuits 314 and k second interconnection circuits 315. The first interconnection circuit 314 includes two n-to-1 selectors 301 and 302 with the same structure. The second interconnection circuit 315 is a 4-to-1 selector, as shown in Figure 4 Figure 5

[0028] Referring to Figure 4 , the input ends of the two n-to-1 selectors are connected to input signals, the output ends are connected to the input ends of the 4-to-1 selector, and the output end of the 4-to-1 selector is connected to the functional module.

[0029] Here, j, k, and n are all integers greater than or equal to 1, and their sizes depend on the external data width.

[0030] In this example, the selection switches of the two n-to-1 selectors and the 4-to-1 selector are all composed of transmission gates. The input ends of the n transmission gates of the n-to-1 selector are respectively connected to input data A0~AN-1 and B0~Bn-1, and the input ends of the 4 transmission gates of the 4-to-1 selector are respectively connected to input data C0~C3, as shown in​​Figure 4 , Figure 5 The input data A0~AN-1 and B0~Bn-1 are all external input data, and the data serial numbers do not represent a specific order, that is, the input ends of the n transmission gates can be connected to any input data, and any input data can be connected to the input end of one or more transmission gates. The input data C0~C3 of the four-to-one selector can be any output data Z0N or Z1N of the two n-to-one selectors, and the output data Z2N of the four-to-one selector is connected to the data input end of the functional module.

[0031] In this example, the enable ends (D0~Dn-1, DN0~DNn-1; E0~En-1, EN0~ENn-1; F0~F3, FN0~FN3) of all the transmission gates are independently configured, and the driving signals are not multiplexed. Only one transmission gate in the n-to-one selector and the four-to-one selector is open at the same time to ensure correct data transmission.

[0032] In the interconnection module, data can be transmitted between the first interconnection circuit 314 and the second interconnection circuit 315, and one interconnection module can include at least one first interconnection circuit 314 and at least one second interconnection circuit 315. In addition to the flexibility of data transmission, this structure brings great flexibility in wiring, which can transmit data for functional modules arranged on both sides of the interconnection module, as shown in Figure 3 This can reduce the number of interconnection modules by half of the FPGA chip, not only reducing the chip area, but also reducing the chip power consumption. For large-scale gate array integrated circuits, the energy-saving effect is very considerable.

[0033] The flexibility of data transmission, the flexibility of the number of interconnection circuits, and the flexibility of the configuration of the first interconnection circuit and the second interconnection circuit can greatly improve the routing rate of the chip, and the number of interconnection circuits used can be greatly reduced. It is very helpful to reduce power consumption and chip area, As shown in Figure 4 The output ends of the two n-to-one selectors in this example are connected with half-latch circuits (PMOS transistor 305 and inverter 303, and PMOS transistor 306 and inverter 304). When the transmission data is logic high, the half-latch circuit locks the data in the loop.

[0034] The half-latch circuit composed of inverter 303 and PMOS transistor 305 shares a weak pull-up circuit 307 with the half-latch circuit composed of inverter 304 and PMOS transistor 306. In this example, the weak pull-up circuit 307 is composed of two PMOS transistors. The gates of both PMOS transistors are grounded, and their sources are connected to the substrate. The sources and drains of both PMOS transistors are connected. The source of one PMOS transistor is grounded, and the drain of the other PMOS transistor is connected to the drains of PMOS transistors 305 and 306. See [link to relevant documentation]. Figure 4 .

[0035] like Figure 5 As shown, the output of this 4-to-1 selector is connected to a pull-down circuit 312 and an inverter 313. The pull-down circuit 312 consists of an NMOS transistor, with its source connected to the input of the inverter 313, its drain and substrate grounded, and its gate connected to the global reset signal INIT. This initial value is assigned to the input of the functional module. The INIT signal is activated by going high initially and then being pulled low after the FPGA chip stabilizes. The input of the inverter 313 is connected to the output of four transmission gates, and its output is the output data Z2N of the 4-to-1 selector. The inverter 313 enhances the driving capability of the output signal.

[0036] In this example, all transmission gate 401 structures are as follows: Figure 6 As shown, it includes one PMOS transistor and one NMOS transistor. The gates of the PMOS and NMOS transistors are the two enable terminals of the transmission gate. Both enable terminals are driven by independent circuits, and the drive signals are not multiplexed.

[0037] Figure 6 In the diagram, the drains of the PMOS and NMOS transistors are connected to form the input terminal A of the transmission gate, and the sources of the PMOS and NMOS transistors are connected to form the output terminal Z of the transmission gate. The substrates of the PMOS and NMOS transistors are connected to the power supply and ground, respectively.

[0038] This example implements a paging design for the enable pin of the transmission gate, that is, enabling signals OEN and OE (see...). Figure 6 The output comes from the configuration unit after voltage boosting. In the static state, the gate of the PMOS transistor in the transmission gate is high. This PMOS transistor uses a low-threshold device, and the voltage applied to the gate differs significantly from the threshold voltage of the PMOS, resulting in complete device turn-off. This is a combined threshold design method that effectively reduces device leakage current, thereby further reducing interconnect power consumption.

[0039] For the inverter structure in this example, please refer to [link / reference]. Figure 7As shown, including a PMOS transistor and an NMOS transistor. PMOS transistor and NMOS transistor gate connected to form the input end P of the inverter, PMOS transistor and NMOS transistor drain connected to form the output end Q of the inverter, PMOS transistor source and substrate connected to the power supply, NMOS transistor source and substrate connected to the ground.

[0040] The simulation results of the threshold value design power consumption of the example combination are as follows Figure 8 As shown, the static power consumption of the transmission gate is reduced by about 19% by using the combination threshold value design. From the whole chip, the interconnection module accounts for a high proportion, which is a very useful design for reducing the power consumption of FPGA chips.

Claims

1. A programmable gate array chip architecture comprising BLOCK modules arranged in an array, the BLOCK modules comprising a functional module and an interconnect module, characterized in that, The functional module is configured to receive data transmitted by the interconnection module.

2. The programmable gate array chip architecture of claim 1, wherein, The interconnection module comprises j first interconnection circuits and k second interconnection circuits; the first interconnection circuit comprises two n-select-one selectors with the same structure, and the second interconnection circuit comprises a four-select-one selector; an input end of the n-select-one selector is connected to an input signal, and an output end thereof is connected to an input end of the four-select-one selector; an output end of the four-select-one selector is connected to the functional module; wherein j, k and n are all integers greater than or equal to 1.

3. The programmable gate array chip architecture of claim 2, wherein, The n-select-one selector is connected to a half-latch circuit.

4. The programmable gate array chip architecture of claim 2, wherein, The two n-select-one selectors with the same structure share one weak pull-up circuit.

5. The programmable gate array chip architecture of claim 2, wherein, The output end of the four-select-one selector is connected to a pull-down circuit and an inverter.

6. The programmable gate array chip architecture of claim 5, wherein, The inverter comprises one PMOS transistor and one NMOS transistor; the gate of the PMOS transistor is connected to the gate of the NMOS transistor to form an input end of the inverter; the drain of the PMOS transistor is connected to the drain of the NMOS transistor to form an output end of the inverter; the source of the PMOS transistor is connected to a power supply; and the source of the NMOS transistor is connected to ground.

7. The programmable gate array chip architecture of claim 2, wherein, The selection switches of the n-select-one selector and the four-select-one selector are formed by transmission gates.

8. The programmable gate array chip architecture of claim 7, wherein, The transmission gate comprises one PMOS transistor and one NMOS transistor; the gate of the PMOS transistor and the gate of the NMOS transistor are two enable ends of the transmission gate; the drain of the PMOS transistor is connected to the drain of the NMOS transistor to form an input end of the transmission gate; the source of the PMOS transistor is connected to the source of the NMOS transistor to form an output end of the transmission gate; and the substrate of the PMOS transistor is connected to a power supply, and the substrate of the NMOS transistor is connected to ground.

9. The programmable gate array chip architecture of claim 8, wherein, The enable ends are independently configured structures, which ensure that only one transmission gate in the n-select-one selector and the four-select-one selector is in an open state at the same time.

10. The programmable gate array chip architecture of claim 1, wherein, The data width of the BLOCK module is not limited by the interconnection module.

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