Control circuit, image compensation control device and display panel

Abstract

This application belongs to the field of display driver technology, specifically relating to a control circuit, an image compensation control device, and a display panel. The control circuit includes a screen detection module configured to convert the refresh rate among the multiple display parameters into a corresponding input voltage signal when the current display screen is determined to be an abnormal screen based on multiple display parameters; a hysteresis comparison module configured to compare the input voltage signal with an upper threshold and a lower threshold based on hysteresis characteristics, and output a corresponding switch control signal; and an execution module configured to respond to the switch control signal and turn on or off the signal path between the image compensation output terminal and the subsequent drive circuit. Therefore, this application, through the coordinated work of the screen detection module, the hysteresis comparison module, and the execution module, sets a stable buffer for the start and stop of the ICA function, eliminating the problem of frequent switching of the ICA function and screen flickering caused by fluctuations in parameters such as refresh rate near critical values.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a control circuit, an image compensation control device, and a display panel. Background Technology

[0002] In the field of display technology, crosstalk, green screen, and other abnormal image problems are common display defects. To address these issues, existing technologies typically integrate ICA (Image Compensation Algorithm) into the timing controller. This involves dynamically adjusting the polarity arrangement of the liquid crystals when abnormal images are detected to suppress in-plane coupling effects and thus improve image quality.

[0003] Currently, the ICA (Interactive Color Assist) function's activation and deactivation mechanism relies on real-time detection of the area and grayscale value of abnormal screen regions, comparing them with preset thresholds. Since crosstalk is more pronounced at high refresh rates, ICA typically needs to be activated when the refresh rate reaches a certain threshold. However, due to the instability of front-end data transmission, the refresh rate tends to fluctuate frequently near critical values ​​(e.g., when the setting is M, both M and M-1 are critical points), causing the ICA function to repeatedly switch between on and off states. This frequent state change can cause screen flickering, severely impacting the user experience.

[0004] It is evident that the ICA function of the relevant technology frequently turns on and off when the refresh rate is near the critical value, resulting in screen flickering and reducing the stability of the displayed image. Summary of the Invention

[0005] This application provides a control circuit, an image compensation control device, and a display panel. Through the coordinated work of the screen detection module, the hysteresis comparison module, and the execution module, this application sets a stable buffer for the start and stop of the ICA function, which greatly improves the stability and reliability of the start and stop of the ICA function, eliminates the problem of frequent switching of the ICA function and screen flickering caused by the fluctuation of parameters such as refresh rate near the critical value, and thus significantly improves the visual experience and user experience of the display screen.

[0006] In a first aspect, embodiments of this application provide a control circuit, the control circuit comprising: a screen detection module configured to detect multiple display parameters of the currently displayed screen, and when determining that the current displayed screen is an abnormal screen based on the multiple display parameters, converting the refresh rate among the multiple display parameters into a corresponding input voltage signal; a hysteresis comparison module, the input terminal of the hysteresis comparison module being connected to the screen detection module, the hysteresis comparison module being configured to compare the input voltage signal with an upper threshold and a lower threshold respectively based on hysteresis characteristics, so as to output a corresponding switch control signal; wherein the upper threshold is greater than the lower threshold; and an execution module, the control terminal of the execution module being connected to the output terminal of the hysteresis comparison module, a first connection terminal of the execution module being connected to an image compensation output terminal, a second connection terminal of the execution module being connected to a subsequent driving circuit, the execution module being configured to respond to the switch control signal by turning on or off the signal path between the image compensation output terminal and the subsequent driving circuit.

[0007] Secondly, embodiments of this application provide an image compensation control device applied to a display panel, the display panel including N display zones, and each display zone corresponding to a data driving circuit; the image compensation control device includes: a main control circuit, the main control circuit being the control circuit, configured to generate a whole-zone control signal based on the display parameters of the display panel; N zone control circuits, each zone control circuit being the control circuit; each zone control circuit being configured to generate a zone control signal based on the display parameters of the corresponding display zone; a mode switching circuit coupled to a mode output terminal, the main control circuit, the N zone control circuits, and the N data driving circuits; the mode switching circuit is configured to input the whole-zone control signal to the N data driving circuits in response to an externally input first mode selection signal; and to input the zone control signal generated by the i-th zone control circuit to the i-th data driving circuit in response to an externally input second mode selection signal, where i=1,...,N.

[0008] Thirdly, embodiments of this application provide a display panel including a display area and a non-display area. The display area includes a pixel array; the non-display area includes a timing controller, a source drive circuit, and an image compensation control device, wherein the image compensation control device is electrically connected to the timing controller and the source drive circuit, respectively.

[0009] The technical solution provided in this application has at least the following beneficial effects:

[0010] This application uses a screen detection module to detect and determine in real time whether there are any abnormalities in the current display screen. When an abnormal screen is detected, the refresh rate parameter of that screen is converted into a corresponding voltage signal and output to the hysteresis comparison module. The hysteresis comparison module introduces a hysteresis range with upper and lower thresholds to perform anti-jitter judgment on the voltage signal, effectively filtering out frequent fluctuations in the refresh rate near the critical value and outputting a stable switching control signal. The execution module responds to this control signal, precisely turning on or off the signal path from the image compensation output to the subsequent drive circuit, achieving hard enable control of the ICA function. Therefore, this application integrates screen detection, intelligent decision-making, and precise execution through the collaborative work of the screen detection module, hysteresis comparison module, and execution module, constructing a closed-loop control that is responsive, stable in judgment, and reliable in execution. Furthermore, by introducing a refresh rate-based hysteresis comparison control mechanism, a stable buffer zone is set for the start and stop of the ICA function, greatly improving the stability and reliability of the ICA function's start and stop, eliminating the frequent switching of the ICA function and screen flickering caused by fluctuations in parameters such as refresh rate near the critical value, thereby significantly improving the visual experience and user experience of the display screen. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0012] Figure 1 The diagram shown is a schematic diagram of a control circuit provided in an embodiment of this application.

[0013] Figure 2 The diagram shown is a circuit diagram of the first type of hysteresis comparison module provided in an embodiment of this application.

[0014] Figure 3 The diagram shown is a schematic diagram of the first voltage transmission characteristic provided in the embodiment of this application.

[0015] Figure 4 The diagram shown is a schematic diagram of the first type of hysteresis interval provided in the embodiment of this application.

[0016] Figure 5 The diagram shown is a circuit diagram of the second type of hysteresis comparison module provided in an embodiment of this application.

[0017] Figure 6 The diagram shown is a circuit diagram of the third type of hysteresis comparison module provided in an embodiment of this application.

[0018] Figure 7The diagram shown is a structural schematic of the first image compensation control device provided in the embodiment of this application.

[0019] Figure 8 The diagram shown is a structural schematic of the second image compensation control device provided in the embodiment of this application.

[0020] Figure 9 The diagram shown is a data polarity diagram provided in an embodiment of this application.

[0021] Figure 10 The diagram shown is a structural schematic of the third image compensation control device provided in the embodiments of this application.

[0022] Figure 11 The diagram shown is a schematic diagram of the structure of the first polarity tuning circuit provided in the embodiment of this application.

[0023] Figure 12 The diagram shown is a schematic diagram of the structure of the second polarity tuning circuit provided in the embodiment of this application.

[0024] Figure 13 The diagram shown is a structural schematic of the third polarity tuning circuit provided in the embodiment of this application.

[0025] Figure 14 The diagram shown is a structural schematic of the fourth polarity tuning circuit provided in the embodiment of this application.

[0026] Figure 15 The diagram shown is a structural schematic of the fifth polarity tuning circuit provided in the embodiment of this application.

[0027] Figure 16 The diagram shown is a flowchart of an AI intelligent large model provided in an embodiment of this application.

[0028] Figure 17 The diagram shown is a structural schematic of an AI intelligent large model provided in an embodiment of this application.

[0029] Explanation of reference numerals in the attached figures:

[0030] 100. Control circuit; 110. Image detection module; 120. Hysteresis comparison module; 130. Execution module; 200. Image compensation output terminal; 210. Whole area compensation output terminal; 220. First zone compensation output terminal; 230. Second zone compensation output terminal; 240. Third zone compensation output terminal;

[0031] 300. Image compensation control device; 310. Main control circuit; 320. Zone control circuit; 321. First zone control circuit; 322. Second zone control circuit; 323. Third zone control circuit; 330. Mode switching circuit; 340. Polarity tuning circuit; 341. First tuning module; 342. Second tuning module; 343. Third tuning module;

[0032] 400, Mode output terminal; 500, Data driver circuit; 510, First data driver circuit; 520, Second data driver circuit; 530, Third data driver circuit; 600, Subsequent driver circuit;

[0033] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; G1, first inverter; G2, second inverter; G3, third inverter; U1, first AND gate; U2, second AND gate; M1, first switch; M2, second switch; M3, third switch; M4, fourth switch; Q1, first transistor; Q2, second transistor. Detailed Implementation

[0034] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0035] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0036] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0037] Firstly, embodiments of this application provide a control circuit, specifically including the following embodiments:

[0038] Figure 1 The diagram shown is a structural schematic of a control circuit 100 provided in an embodiment of this application; as follows: Figure 1 As shown, the control circuit 100 includes a screen detection module 110, which is configured to detect multiple display parameters of the current display screen, and when it is determined that the current display screen is an abnormal screen based on the multiple display parameters, convert the refresh rate of the multiple display parameters into a corresponding voltage signal.

[0039] It should be noted that the control circuit 100 in this embodiment can be applied in the display panel, mainly controlling the opening and closing of the ICA function; the screen detection module 110 can be integrated in the timing controller, and through the built-in algorithm or hardware circuit, it can detect multiple display parameters of the current display screen in real time. The multiple display parameters include at least the area of ​​the abnormal area, the grayscale value of the area, and the screen refresh rate.

[0040] Optionally, the image detection module 110 internally presets an area threshold and a grayscale threshold. Only when the detected area and grayscale simultaneously exceed their respective thresholds will the image detection module 110 determine that the current displayed image is an abnormal image; otherwise, it determines that the current displayed image is a normal image. Further, after determining that it is an abnormal image, the image detection module 110 linearly converts the refresh rate into an analog voltage signal (Ui) through a data converter (e.g., a digital-to-analog converter DAC or a voltage-controlled oscillator VCO). For example, the higher the refresh rate, the higher the output voltage signal Ui value. It can be seen that this embodiment integrates the information of whether image compensation is needed and the refresh rate into a single voltage signal through the image detection module 110, realizing the transformation from complex image parameters to a single, quantifiable electrical signal, laying the foundation for subsequent accurate judgment.

[0041] like Figure 1 As shown, the control circuit 100 of this embodiment further includes a hysteresis comparison module 120. The input terminal of the hysteresis comparison module 120 is connected to the screen detection module 110. The hysteresis comparison module 120 is configured to receive a voltage signal and compare the voltage signal with the upper threshold voltage and the lower threshold voltage based on its inherent hysteresis characteristics, and output a corresponding switch control signal. The upper threshold voltage is greater than the lower threshold voltage. Specifically, when the voltage signal is greater than or equal to the upper threshold voltage, the switch control signal switches to an active level; when the voltage signal is less than or equal to the lower threshold voltage, the switch control signal switches to an inactive level; when the voltage signal is between the upper threshold voltage and the lower threshold voltage, the current level of the switch control signal is maintained.

[0042] It should be noted that the hysteresis comparison module 120 in this embodiment receives the input voltage signal Ui from the screen detection module 110 and compares it based on the module's own hysteresis characteristics. The hysteresis characteristics are represented by the upper threshold UT+ and the lower threshold UT-, with UT+ > UT-. Specifically, when the voltage signal Ui rises from low and first reaches or exceeds the upper threshold voltage UT+, the module's output state flips, outputting a valid level switching control signal. Thereafter, if Ui fluctuates between UT+ and UT-, the output state remains unchanged. Only when Ui falls from high and first reaches or falls below UT- does the module's output state flip again, outputting an invalid level switching control signal. This characteristic of the hysteresis comparison module eliminates frequent switching caused by small signal fluctuations at a single critical point, thereby preventing screen flicker.

[0043] In this embodiment, the control circuit 100 further includes an execution module 130. The control terminal of the execution module 130 is connected to the output terminal of the hysteresis comparison module 120. The first connection terminal of the execution module 130 is connected to the image compensation output terminal 200. The second connection terminal of the execution module 130 is connected to the subsequent driving circuit 600. The execution module 130 is configured to respond to a switch control signal to turn on or off the signal path between the image compensation output terminal 200 and the subsequent driving circuit 600.

[0044] It should be noted that the execution module 130 in this embodiment can be implemented by a switching device, such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Its control terminal receives the switching control signal output from the hysteresis comparison module 120, its first connection terminal is connected to the image compensation output terminal 200, which is directly connected to the hardware output of the ICA function algorithm within the system, and its second connection terminal is connected to the subsequent driving circuit 600, which can be the corresponding control pin of the source driver chip (Source IC). When the switching control signal is at an active level, the execution module 130 is turned on, establishing a signal path; when the signal is at an inactive level, the execution module 130 is turned off, disconnecting the signal path.

[0045] In this embodiment, the execution module 130 is connected in series between the ICA function module and the source driver chip that ultimately performs compensation, acting as an electronic switch. It realizes hard on / off control of the ICA function output signal. Its direct effect is that when the switch is off, even if the ICA algorithm is still running internally, its compensation signal cannot be applied to the panel, thereby ensuring that compensation is only enabled when necessary, avoiding the side effects and power consumption that may be caused by unnecessary compensation.

[0046] The specific working principle of the control circuit 100 provided in this embodiment is as follows:

[0047] (1) After the system is powered on, the screen detection module 110 continuously monitors the display screen.

[0048] (2) When a large area of ​​abnormal image with high grayscale appears, the module determines that compensation is required and converts the current refresh rate into a voltage signal Ui for output.

[0049] (3) The hysteresis comparison module 120 compares Ui with the upper threshold voltage UT+ and the lower threshold voltage UT- based on its hysteresis characteristics; if the refresh rate is very high, Ui ≥ UT+, the hysteresis comparison module 120 outputs a valid level signal, the execution module 130 is turned on, so that the output signal of the ICA function can be transmitted to the subsequent driving circuit 600 (source driving chip) through the turned-on execution module 130, driving the liquid crystal molecules to change the polarity arrangement and implement image compensation.

[0050] (4) If the picture quality improves or the refresh rate drops slightly, causing Ui to fall back, but as long as Ui is still above UT-, the hysteresis comparison module 120 will maintain an effective level output, the switch will remain on, and the ICA function will continue to be effective; only when the refresh rate drops significantly, causing Ui ≤ UT-, will the hysteresis comparison module 120 output an invalid level, and the execution module 130 will be turned off, completely cutting off the transmission path of the ICA signal and stopping the compensation.

[0051] (5) If the refresh rate increases again thereafter, it must reach UT+ again before compensation will be enabled again.

[0052] In summary, this application uses the screen detection module 110 to detect and determine in real time whether there is an abnormality in the current display screen. When an abnormal screen is determined, the refresh rate parameter of the screen is converted into a corresponding voltage signal and output to the hysteresis comparison module 120. The comparison and judgment performed by the hysteresis comparison module 120 based on its inherent hysteresis characteristics effectively filters out frequent fluctuations in the refresh rate near the critical value and outputs a stable switching control signal. The execution module 130 responds to the control signal and precisely turns on or off the signal path from the image compensation output to the subsequent drive circuit, thereby realizing the hard enable control of the ICA function. Therefore, this application integrates screen detection, intelligent decision-making, and precise execution into a single system through the collaborative work of the screen detection module 110, the hysteresis comparison module 120, and the execution module 130, constructing a closed-loop control system that is responsive, stable in judgment, and reliable in execution. Furthermore, by introducing a refresh rate-based hysteresis comparison control mechanism, a stable working range is set for the start and stop of the ICA function, greatly improving the stability and reliability of the ICA function's start and stop. This eliminates the problem of frequent switching of the ICA function and screen flicker caused by fluctuations in parameters such as refresh rate near critical values, thereby significantly improving the visual experience and user experience of the displayed screen.

[0053] In one embodiment, the screen detection module 110 is further configured to: when determining that the current display screen is a normal screen based on multiple display parameters, output a preset voltage to the hysteresis comparison module 120, so that the hysteresis comparison module 120 controls the execution module 130 to disconnect the signal path according to the preset voltage.

[0054] It should be noted that the screen detection module 110 in this embodiment has dual judgment logic, which includes a primary decision unit (e.g., composed of a comparator U0 and logic gates) for determining whether the screen is abnormal. This decision unit continuously performs logical operations (such as AND operations) on the comparison results of the detected abnormal area area and grayscale value with their respective thresholds. Specifically, when the screen is determined to be abnormal: the module performs the operation as described in the above embodiment and outputs a voltage signal Ui corresponding to the refresh rate; when the screen is determined to be normal (i.e., either the area or grayscale value does not meet the standard): the module ignores the current refresh rate value and forcibly outputs a fixed preset voltage. This preset voltage is set to a value much lower than the lower limit threshold of the hysteresis comparison module 120, such as 0V or a constant low-level voltage UT-ΔV.

[0055] The screen detection module 110 in this embodiment ensures that in any non-abnormal screen scenario, no matter how high the refresh rate, as long as the screen content itself does not have any abnormalities that need to be compensated, the ICA function will not be activated. This conforms to the fundamental principle of on-demand compensation in display drivers, thereby achieving higher reliability, lower power consumption, and better overall image quality.

[0056] In one embodiment, such as Figure 2 As shown, the hysteresis comparison module 120 includes a first resistor R1, a second resistor R2, a first inverter G1, and a second inverter G2. Specifically, the first end of the first resistor R1 serves as the input terminal of the hysteresis comparison module 120; the first end of the second resistor R2 is connected to the second end of the first resistor R1, and the second end of the second resistor R2 serves as the output terminal of the hysteresis comparison module 120; the input terminal of the first inverter G1 is connected to the second end of the first resistor R1; the input terminal of the second inverter G2 is connected to the output terminal of the first inverter G1, and the output terminal of the second inverter G2 is connected to the second end of the second resistor R2.

[0057] It should be noted that the hysteresis comparison module 120 in this embodiment consists of two CMOS inverters and two resistors. Its working principle is to use positive feedback to generate hysteresis voltage. The threshold voltage Vth of the first inverter G1 and the second inverter G2 is Vdd / 2. The specific working process is as follows:

[0058] (1) From the perspective of the rising direction of the input voltage Ui, the upper threshold UT+ of the circuit is (1 + R1 / R2)×Vth. When Ui < UT+, the output Uo is at a low level; when Ui > UT+, the output Uo flips to a high level.

[0059] (2) From the perspective of the falling direction of the input voltage Ui, the lower threshold UT- of the circuit is (1 - R1 / R2) ×Vth. When Ui > UT-, the output Uo maintains a high level; when Ui < UT-, the output Uo flips to a low level.

[0060] Thus, during the rising and falling processes of the input voltage, the flip thresholds of the circuit are different, forming a hysteresis region, and its hysteresis voltage Vhys = (UT+) - (UT-) = 2×Vth ×(R1 / R2).

[0061] Here, the switching transistor in the switching module is an N-MOS, and its conduction and cutoff are controlled by the output level of the hysteresis comparison module 120. Combining Figure 3 and Figure 4 , the specific working process is as follows:

[0062] (1) When there is an abnormality in the display screen and the refresh rate parameter is small, the corresponding input voltage Ui is less than UT+, the hysteresis comparison module 120 outputs a low level, the switching transistor is turned off, and the ICA function is turned off; when the abnormal parameter increases and makes Ui rise and exceed UT+, the output of the hysteresis comparison module 120 flips to a high level, the switching transistor is turned on, and the ICA function is turned on. Thereafter, if Ui continues to increase, the ICA remains in the on state.

[0063] (2) When there is an abnormality in the display screen and the refresh rate parameter starts to decrease from a large value, if Ui drops below UT+ but is still higher than UT-, the output of the hysteresis comparison module 120 remains high, the switching transistor remains on, and the ICA function is still on; only when Ui continues to decrease to be lower than UT-, the output of the hysteresis comparison module 120 flips to a low level, the switching transistor is turned off, and the ICA function is turned off. Thereafter, if Ui continues to decrease, the ICA remains in the off state.

[0064] (3) If the refresh rate parameter rises again, the opening process of step 1 is repeated.

[0065] In this embodiment, by adjusting the ratio of the first resistor R1 to the second resistor R2 or the threshold voltage Vth of the CMOS inverter, the size of the hysteresis interval can be changed, thereby realizing hysteresis control with different widths. As Figure 4 shown, the center of this hysteresis interval is located at Vth, corresponding to the required threshold center value.

[0066] In one embodiment, as Figure 5As shown, the hysteresis comparator module 120 includes a first resistor R1, a second resistor R2, a first switch M1, a second switch M2, a third switch M3, and a fourth switch M4. Specifically, the first terminal of the first resistor R1 serves as the input terminal of the hysteresis comparator module 120; the first terminal of the second resistor R2 is connected to the second terminal of the first resistor R1, and the second terminal of the second resistor R2 serves as the output terminal of the hysteresis comparator module 120; the control terminal of the first transistor is connected to the second terminal of the first resistor R1, and the first terminal of the first switch M1 is connected to the power supply terminal; the control terminal of the second switch M2... The first switch M1 is connected to the control terminal of the first switch M1. The first terminal of the second switch M2 is connected to the second terminal of the first switch M1, and the second terminal of the second switch M2 is grounded. The control terminal of the third switch M3 is connected to the first terminal of the second switch M2. The first terminal of the third switch M3 is connected to the power supply terminal, and the second terminal of the third switch M3 serves as the output terminal of the hysteresis comparison module 120. The control terminal of the fourth switch M4 is connected to the control terminal of the third switch M3. The first terminal of the fourth switch M4 is connected to the second terminal of the third switch M3, and the second terminal of the fourth switch M4 is grounded.

[0067] In this embodiment, the first switch M1 and the third switch M3 are P-type MOSFETs, and the second switch M2 and the fourth switch M4 are N-type MOSFETs. The hysteresis comparator module 120 in this embodiment uses four switches and two resistors to form a comparator circuit with hysteresis characteristics. Its operation is as follows:

[0068] (1) Initial state (when the input voltage Ui is low): The control terminal of the first switch M1 (P-type) is at a low level, and the first switch M1 is turned on; the control terminal of the second switch M2 (N-type) is also at a low level, and the second switch M2 is turned off, making node B (the first terminal of the second switch M2) at a high level. The high level of node B turns off the third switch M3 (P-type) and turns on the fourth switch M4 (N-type); therefore, the output terminal is pulled to a low level by the fourth switch M4; at this time, the low level of the output terminal is fed back to node A through the second resistor R2, which plays a role in stabilizing the current state.

[0069] (2) Input voltage Ui rises to the action threshold: When Ui rises, causing the voltage at node A to reach a sufficiently high level (upper limit threshold UT+), the first switch M1 (P-type) turns off, and the second switch M2 (N-type) turns on. Node B is thus pulled low. The low level at node B causes the third switch M3 (P-type) to turn on, and the fourth switch M4 (N-type) to turn off. The output is thus pulled high by the third switch M3. At this time, the high level of the output is fed back to node A through R2, further raising its potential, thereby locking in this new output state.

[0070] (3) When the input voltage Ui drops from a high level: When Ui drops, due to the feedback effect of the second resistor R2 (coupling the high level to node A), the potential of node A is maintained; only when Ui drops to a sufficiently low level (lower threshold UT-) so that the voltage of node A cannot maintain the conduction of the second switch M2 (N-transistor), the circuit will flip back to the initial state: the first switch M1 (P-transistor) is turned on, the second switch M2 (N-transistor) is turned off, which in turn causes the third switch M3 (P-transistor) to be turned off, the fourth switch M4 (N-transistor) to be turned on, and the output terminal returns to a low level.

[0071] Therefore, this embodiment introduces positive feedback through the second resistor R2, which enables the switching transistor combination to have different switching thresholds during the rise and fall of the input voltage, thereby realizing the hysteresis comparison function.

[0072] In one embodiment, such as Figure 6 As shown, the hysteresis comparator module 120 includes a first resistor R1, a second resistor R2, a first transistor Q1, a third resistor R3, a second transistor Q2, and a fourth resistor R4. Specifically, the first end of the first resistor R1 serves as the input terminal of the hysteresis comparator module 120; the first end of the second resistor R2 is connected to the second end of the first resistor R1, and the second end of the second resistor R2 serves as the output terminal of the hysteresis comparator module 120; the base of the first transistor Q1 is connected to the first end of the second resistor R2, and the emitter of the first transistor Q1 is grounded; the first end of the third resistor R3 is connected to the power supply terminal, and the second end of the third resistor R3 is connected to the collector of the first transistor Q1; the base of the second transistor Q2 is connected to the collector of the first transistor Q1, the emitter of the second transistor Q2 is grounded, and the collector of the second transistor Q2 serves as the output terminal of the hysteresis comparator module 120; the first end of the fourth resistor R4 is connected to the power supply terminal, and the second end of the fourth resistor R4 is connected to the collector of the second transistor Q2.

[0073] It should be noted that the hysteresis comparator module 120 in this embodiment consists of two NPN bipolar junction transistors and four resistors forming a comparator circuit with hysteresis characteristics. Its operation is as follows:

[0074] (1) Initial state (low input voltage Ui): When Ui is low, the first transistor Q1 is cut off, and the power supply Vcc provides bias current to the base of the second transistor Q2 through the third resistor R3, so that the second transistor Q2 is saturated and turned on. At this time, the output terminal Uo is pulled to a low level (near ground GND) by the second transistor Q2. At this time, the second resistor R2 feeds back the low level of the output to the emitter of the first transistor Q1 to help maintain the cut-off state of the first transistor Q1.

[0075] (2) Input voltage rises to the turn-on threshold (UT+): When Ui rises, causing the base-emitter voltage of the first transistor Q1 to exceed its turn-on voltage (approximately 0.7V), the first transistor Q1 begins to conduct, its collector voltage decreases, resulting in a decrease in the base current of the second transistor Q2; when the second transistor Q2 exits the saturation region, its collector (output) voltage begins to rise. This rising voltage is fed back to the emitter of the first transistor Q1 through two resistors, raising the emitter potential of the first transistor Q1. In order to maintain the conduction of the first transistor Q1, its base (i.e., input Ui) must reach a higher voltage, which is the upper limit threshold UT+; once exceeded, the circuit quickly flips to a state where the first transistor Q1 is saturated and conducting, and the second transistor Q2 is cut off, and the output Uo jumps to a high level (close to Vcc).

[0076] (3) Input voltage drops to the off threshold (UT-): When Ui drops from high level, the first transistor Q1 gradually exits saturation; as the collector current of the first transistor Q1 decreases, its collector voltage rises, causing the second transistor Q2 to start conducting. The collector voltage of the second transistor Q2 drops, and through the feedback of the second resistor R2, the emitter potential of the first transistor Q1 is pulled down. This allows the first transistor Q1 to remain conducting at a lower input voltage until Ui drops to the lower threshold UT-, at which point the circuit quickly returns to the initial state (the first transistor Q1 is off, and the second transistor Q2 is on), and the output Uo jumps to low level.

[0077] Secondly, embodiments of this application provide an image compensation control device, specifically including the following embodiments:

[0078] Figure 7 The diagram shown is a structural schematic of the first image compensation control device provided in this application embodiment; as follows: Figure 7 As shown, the image compensation control device 300 of this embodiment is applied to a display panel, which includes N display zones, and each display zone corresponds to a data drive circuit 500. With the increasing sophistication of current market products, more display devices adopt zone refresh rates, using different refresh rates in different areas according to image requirements to achieve better energy efficiency. Image distortion is more severe at high refresh rates, while it is slight or nonexistent at low refresh rates. Therefore, this embodiment adds separate control functions to the ICA of different refresh areas, allowing them to switch between a global unified mode and a zone-specific mode as needed. The image compensation output terminal 200 of this embodiment includes, but is not limited to, a whole-zone compensation output terminal 210, a first zone compensation output terminal 220, a second zone compensation output terminal 230, and a third zone compensation output terminal 240.

[0079] Specifically, the image compensation control device 300 in this embodiment includes a main control circuit 310, which is a specific instance of the control circuit 100 in the above embodiment. It is configured to generate a whole-area control signal based on the display parameters of the display panel. It should be noted that the screen detection module 110 in the main control circuit 310 of this embodiment detects the area of ​​abnormal regions, grayscale, and global refresh rate (when all zone refresh rates are consistent) or representative refresh rate of the entire display panel. Its hysteresis comparison module 120 generates a whole-area control signal based on this comprehensive information. This whole-area control signal represents a global perspective on whether and when to enable the ICA function. Therefore, the main control circuit 310 provides a unified ICA control strategy based on the global screen condition, ensuring that the ICA state of the entire screen is synchronized when the full-screen refresh rate is consistent. This not only avoids visual fragmentation caused by inconsistent compensation in different areas but also reduces power consumption.

[0080] Optionally, the image compensation control device 300 of this embodiment further includes N partition control circuits 320, each partition control circuit 320 being a specific instance of the control circuit 100 in the above embodiment; each partition control circuit 320 is configured to generate a partition control signal based on the display parameters of the corresponding display partition. It should be noted that each partition control circuit 320 is a complete and autonomous ICA decision unit, configured to work only based on the display parameters of the specific display partition it is responsible for: that is, the screen detection module 110 of each partition control circuit 320 only detects the abnormal area area, grayscale, and local refresh rate of the corresponding partition; the hysteresis comparison module 120 of each partition control circuit 320 independently generates a partition control signal for that partition; therefore, the N partition control circuits 320 enable each display partition to independently decide whether to enable ICA compensation based on its own actual situation (whether there is an anomaly, the refresh rate), realizing fine control of the ICA function with on-demand allocation and precise compensation, which is particularly suitable for partition refresh scenarios.

[0081] Optionally, the image compensation control device 300 of this embodiment further includes a mode switching circuit 330, coupled to the mode output terminal 400, the main control circuit 310, the N partition control circuits 320, and the N data driving circuits 500; the mode switching circuit 330 is configured to input the whole area control signal to the N data driving circuits 500 in response to a first mode selection signal input from an external source; and to input the partition control signal generated by the i-th partition control circuit 320 to the i-th data driving circuit 500 in response to a second mode selection signal input from an external source, where i=1,...,N.

[0082] It should be noted that the mode output terminal 400 in this embodiment can be the output terminal of an external circuit or another output terminal with mode recognition function in the image compensation control device 300; the mode selection signal output by the mode output terminal 400 includes a first mode selection signal for indicating that the display panel is currently in the whole area refresh mode, and a second mode selection signal for indicating that the display panel is currently in the partition refresh mode.

[0083] In this embodiment, the mode switching circuit 330 routes the correct control signal to the corresponding data driving circuit 500 based on the mode selection signal. Specifically:

[0084] (1) When the first mode selection signal is valid, the mode switching circuit 330 simultaneously inputs the whole area control signal generated by the main control circuit 310 to all N data drive circuits 500. At this time, the ICA state of the entire screen is uniformly determined by the main control circuit 310.

[0085] (2) When the second mode selection signal is valid, the mode switching circuit 330 inputs the partition control signal generated by the i-th partition control circuit 320 to the i-th data drive circuit 500. At this time, the ICA state of each partition is independently controlled by its own partition control circuit 320.

[0086] Therefore, this embodiment enables the ICA control system to dynamically adapt to different operating modes of the display device (global refresh or partition refresh) through the mode switching circuit 330, always maintaining the optimal compensation strategy; and supports two operating modes through a single hardware architecture, eliminating the need to design independent control circuits 100 for each mode, thus saving chip area and cost. This embodiment ensures a smooth transition of ICA function control in different display modes, avoiding screen jitter or flickering caused by mode switching.

[0087] The specific working principle of the image compensation control device 300 provided in this embodiment is as follows:

[0088] (1) After system initialization, the main control circuit 310 and all partition control circuits 320 work in parallel, continuously generating their respective whole-area control signals and partition control signals based on global and local information.

[0089] (2) The timing controller determines and outputs the corresponding mode selection signal to the mode switching circuit 330 based on the current display content and working status.

[0090] (3) The mode switching circuit 330 switches the signal path in real time according to the received mode command: ① In whole-area refresh scenarios such as watching movies or browsing web pages, the mode switching circuit 330 broadcasts the command of the main control circuit 310 to all partitions to achieve unified control. ② In partition refresh scenarios such as games or videos, the mode switching circuit 330 sends the decisions of each partition control circuit 320 to the area it is responsible for to achieve independent control.

[0091] (4) Finally, the control signal selected by the mode switching circuit 330 reaches the data driving circuit 500 to control the final execution of the ICA function.

[0092] This embodiment constructs an intelligent image compensation control device 300 that combines centralized management and distributed control through the coordinated operation of the main control circuit 310, multiple partition control circuits 320, and mode switching circuit 330. It creatively solves the control adaptation problem of ICA function in the new generation of partition refresh display technology, enabling the ICA function to intelligently select the optimal control strategy in both global unified refresh and partition independent refresh modes. While effectively eliminating crosstalk and flicker, it achieves the best balance between power consumption and image quality, greatly improving the overall user experience of partition refresh display devices.

[0093] Figure 8 The diagram shown is a structural schematic of the second image compensation control device provided in an embodiment of this application; as shown Figure 8 As shown, the mode switching circuit 330 includes: N first transistors T1, the control terminal of the first transistor T1 is connected to the mode output terminal 400, the first terminal of the first transistor T1 is connected to the output terminal of the partition control circuit 320, and the second terminal of the first transistor T1 is connected to the data driving circuit 500.

[0094] Optionally, the mode switching circuit 330 of this embodiment further includes N-1 second transistors T2. The control terminal of each second transistor T2 is connected to the mode output terminal 400. The first terminal of the first second transistor T2 is connected to the output terminal of the main control circuit 310 and the first data driving circuit 500, respectively. The first terminal of the j-th second transistor T2 is connected to the second terminal of the (j-1)-th second transistor T2 and the j-th data driving circuit 500, respectively. The second terminal of the (N-1)-th second transistor T2 is connected to the N-th data driving circuit 500; where j=2,...,N-1; the turn-on voltages of the first transistor T1 and the second transistor T2 are opposite.

[0095] Here, taking N=3, with the first transistor T1 being a PMOS transistor and the second transistor T2 being an NMOS transistor as an example, combined with... Figure 11 The working principle of the mode switching circuit 330 in this embodiment will be described in detail below:

[0096] (1) Global control mode, that is: the output signal S of the mode output terminal 400 is high level (that is, the first mode selection signal is valid).

[0097] All first transistors T1 are disconnected when the control terminal is high, thereby disconnecting the signal paths between all partition control circuits 320 and partition data drive circuits 500; all second transistors T2 are turned on when the control terminal is high, and the whole-area control signal generated by the main control circuit 310 acts on the data drive circuit 500 corresponding to each display partition, realizing the ICA function to be turned on or off uniformly throughout the entire screen.

[0098] (2) Partition control mode, that is: the output signal S of the mode output terminal 400 is low (that is, the second mode selection signal is valid).

[0099] All second transistors T2 are turned off when the control terminal is low, thus disconnecting the signal path between the main control circuit 310 and the partition data drive circuit 500; all first transistors T1 are turned on when the control terminal is low, so that the partition control signal generated by each partition control circuit 320 is sent to the corresponding partition data drive circuit 500, so that each display partition receives its own independent partition control signal, and the ICA function is independently controlled in each partition without affecting each other.

[0100] This embodiment provides a specific and feasible implementation of the mode switching circuit 330. Through N first transistors T1 and N-1 second transistors T2 connected in a chain, and with complementary control signals, a reliable switching between global unified control and zone-independent control is clearly and clearly achieved.

[0101] It is worth noting that in display panels using zone-driven architecture, different areas are driven by independent source ICs. Due to the matching requirements between panel resolution and the number of output channels of the driver chip, and the circuit design reasons that some columns need to be used as dummy channels, in practical applications, driver chips with different numbers of channels may be used. For example, some may use all 966 channels (e.g., ...). Figure 9 Some may use out966 channels, while others may only use 960 channels (i.e., out960).

[0102] In normal display mode (i.e., ICA function is off, and the global control signal POL2 is low), the data polarity of the driver chip is arranged cyclically in a standard +-+-+-+-... pattern. Regardless of whether the driver chip is out960 or out966, or how they are combined, this standard arrangement ensures the continuity of polarity connection between adjacent driver chips. That is, the polarity of the last channel of the previous chip is always opposite to the polarity of the first channel of the next chip, forming an ideal state of + connected to - or - connected to +.

[0103] However, when the ICA function is enabled to improve crosstalk and other issues (at which point POL2 is pulled high), the polarity arrangement mode switches to a specific +--++--++... sequence. It is this special sequence, combined with the mixed use of different channel numbers, that causes the polarity discontinuity problem, such as... Figure 9 As shown: (1) For the driver chip with output 960: the sequence +--++--++... is repeated 960 times. Since 960 is divisible by the basic period of the sequence, the polarity of the last channel is fixed as +. (2) For the driver chip with output 966: the same sequence is repeated 966 times. Since 966 is not divisible by the basic period of the sequence, the polarity of the last channel is -.

[0104] However, when an OUT960 driver chip (with the last channel being +) is adjacent to an OUT966 driver chip (with the first channel being +), a +-to-+ polarity combination will appear at their junction. This polarity discontinuity will form a visible abnormal boundary on the screen, manifesting as increased crosstalk, green shadows, or flickering, severely affecting the overall uniformity of the image and the visual experience.

[0105] To address the aforementioned problems, the image compensation control device in this embodiment further includes a polarity tuning circuit 340; such as Figure 10 As shown, the input terminal of the polarity tuning circuit 340 is connected to N partition control circuits 320, and the output terminal of the polarity tuning circuit 340 is connected to N data driving circuits 500 respectively. The polarity tuning circuit 340 is configured to output a polarity tuning signal to the polarity control terminal of at least one data driving circuit 500 in response to the switch control signal output by the partition control circuit 320. The polarity tuning signal is used to make the polarity arrangement of the data signals of adjacent display partitions continuous.

[0106] It should be noted that the polarity tuning circuit 340 in this embodiment continuously monitors the switch control signals of all partitions. When it detects that the switch control signals of two adjacent partitions simultaneously indicate that ICA is enabled, it outputs a valid polarity tuning signal to at least one of the data driving circuits 500 corresponding to these two adjacent partitions. After receiving this polarity tuning signal, the data driving circuit 500 globally flips the data polarity sequence of its entire output channel (for example, changing all + to - and all - to +). By implementing this flip for one of the adjacent partitions, it can be ensured that at the junction of the two partitions on the screen, the polarity arrangement of their driving signals changes from an originally mismatched state (e.g., + to +) to a matched and continuous state (e.g., + to -).

[0107] Therefore, this embodiment adds a polarity tuning circuit 340 to intelligently intervene in the partition control process, actively and selectively adjusting the global polarity of a specific partition, thereby avoiding screen continuity anomalies (such as bright lines and color bands) that may occur in complex partition ICA application scenarios, and ensuring the uniformity of the entire display screen and a high-quality visual experience.

[0108] Figure 11 The diagram shown is a schematic representation of the structure of the first polarity tuning circuit 340 provided in an embodiment of this application; as shown Figure 11 As shown, the polarity tuning circuit 340 includes a first tuning module 341, a second tuning module 342, and a third tuning module 343; the N partition control circuits 320 include a first partition control circuit 321, a second partition control circuit 322, and a third partition control circuit 323; and the data driving circuit 500 includes a first data driving circuit 510, a second data driving circuit 520, and a third data driving circuit 530.

[0109] In this embodiment, the first tuning module 341 includes a third transistor T3 and a fourth transistor T4. The control terminal of the third transistor T3 is connected to the output terminal of the hysteresis comparison module 120 in the first partition control circuit 321. The first terminal of the third transistor T3 is connected to the power supply terminal, and the second terminal of the third transistor T3 is connected to the polarity control terminal of the first data driving circuit 510. The control terminal of the fourth transistor T4 is connected to the control terminal of the third transistor T3. The first terminal of the fourth transistor T4 is connected to the second terminal of the third transistor T3, and the second terminal of the fourth transistor T4 is grounded.

[0110] In this embodiment, the second tuning module 342 includes a fifth transistor T5 and a sixth transistor T6. The control terminal of the fifth transistor T5 is connected to the output terminal of the hysteresis comparison module 120 in the second partition control circuit 322. The first terminal of the fifth transistor T5 is connected to the power supply terminal, and the second terminal of the fifth transistor T5 is connected to the polarity control terminal of the second data driving circuit 520. The control terminal of the sixth transistor T6 is connected to the control terminal of the fifth transistor T5. The first terminal of the sixth transistor T6 is connected to the second terminal of the fifth transistor T5, and the second terminal of the sixth transistor T6 is grounded.

[0111] In this embodiment, the third tuning module 343 includes a seventh transistor T7 and an eighth transistor T8. The control terminal of the seventh transistor T7 is connected to the output terminal of the hysteresis comparison module 120 in the third partition control circuit 323. The first terminal of the seventh transistor T7 is connected to the power supply terminal, and the second terminal of the seventh transistor T7 is connected to the polarity control terminal of the third data drive circuit 530. The control terminal of the eighth transistor T8 is connected to the control terminal of the seventh transistor T7. The first terminal of the eighth transistor T8 is connected to the second terminal of the seventh transistor T7, and the second terminal of the eighth transistor T8 is grounded.

[0112] In this embodiment, the third transistor T3, the fifth transistor T5, and the seventh transistor T7 are N-type MOS transistors, and the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are P-type MOS transistors.

[0113] Figure 12 The diagram shown is a structural schematic of the second polarity tuning circuit 340 provided in an embodiment of this application; Figure 12 and Figure 11 The difference in the polarity tuning circuit 340 shown is: Figure 11 The third transistor T3, the fifth transistor T5, and the seventh transistor T7 are N-type MOSFETs, while the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are P-type MOSFETs; Figure 12 The third transistor T3, the fourth transistor T4, and the seventh transistor T7 are P-type MOS transistors, while the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are N-type MOS transistors.

[0114] Figure 13The diagram shows a third polarity tuning circuit 340 provided in this application embodiment. The first tuning module 341 includes a third transistor T3 and a fourth transistor T4. The control terminal of the third transistor T3 is connected to the output terminal of the hysteresis comparison module 120 in the first partition control circuit 321. The first terminal of the third transistor T3 is connected to the power supply terminal, and the second terminal of the third transistor T3 is connected to the polarity control terminal of the first data driving circuit 510. The control terminal of the fourth transistor T4 is connected to the control terminal of the third transistor T3. The first terminal of the fourth transistor T4 is connected to the second terminal of the third transistor T3, and the second terminal of the fourth transistor T4 is grounded.

[0115] In this embodiment, the second tuning module 342 includes a fifth resistor R5, the first end of the fifth resistor R5 is grounded, and the second end of the fifth resistor R5 is connected to the polarity control terminal of the second data driving circuit 520.

[0116] In this embodiment, the third tuning module 343 includes a seventh transistor T7 and an eighth transistor T8. The control terminal of the seventh transistor T7 is connected to the output terminal of the hysteresis comparison module 120 in the third partition control circuit 323. The first terminal of the seventh transistor T7 is connected to the power supply terminal, and the second terminal of the seventh transistor T7 is connected to the polarity control terminal of the third data drive circuit 530. The control terminal of the eighth transistor T8 is connected to the control terminal of the seventh transistor T7. The first terminal of the eighth transistor T8 is connected to the second terminal of the seventh transistor T7, and the second terminal of the eighth transistor T8 is grounded.

[0117] In this embodiment, the third transistor T3 and the seventh transistor T7 are N-type MOS transistors, and the fourth transistor T4 and the eighth transistor T8 are P-type MOS transistors.

[0118] Figure 14 The diagram shown is a structural schematic of the fourth polarity tuning circuit 340 provided in an embodiment of this application; as shown Figure 14 As shown, the first tuning module 341 includes a third transistor T3 and a fourth transistor T4. The control terminal of the third transistor T3 is connected to the output terminal of the hysteresis comparison module 120 of the first partition control circuit 321. The first terminal of the third transistor T3 is connected to the power supply terminal, and the second terminal of the third transistor T3 is connected to the polarity control terminal of the first data drive circuit 510. The control terminal of the fourth transistor T4 is connected to the control terminal of the third transistor T3. The first terminal of the fourth transistor T4 is connected to the second terminal of the third transistor T3, and the second terminal of the fourth transistor T4 is grounded.

[0119] The second tuning module 342 in this embodiment includes a third inverter G3, a fifth transistor T5, and a sixth transistor T6. The input terminal of the third inverter G3 is connected to the control terminal of the third transistor T3, the control terminal of the fifth transistor T5 is connected to the output terminal of the third inverter G3, the first terminal of the fifth transistor T5 is connected to the power supply terminal, and the second terminal of the fifth transistor T5 is connected to the polarity control terminal of the second data driving circuit 520. The control terminal of the sixth transistor T6 is connected to the control terminal of the fifth transistor T5, the first terminal of the sixth transistor T6 is connected to the second terminal of the fifth transistor T5, and the second terminal of the sixth transistor T6 is grounded.

[0120] The third tuning module 343 in this embodiment includes a seventh transistor T7 and an eighth transistor T8. The control terminal of the seventh transistor T7 is connected to the control terminal of the third transistor T3. The first terminal of the seventh transistor T7 is connected to the power supply terminal, and the second terminal of the seventh transistor T7 is connected to the polarity control terminal of the third data driving circuit 530. The control terminal of the eighth transistor T8 is connected to the control terminal of the seventh transistor T7. The first terminal of the eighth transistor T8 is connected to the second terminal of the seventh transistor T7, and the second terminal of the eighth transistor T8 is grounded.

[0121] In this embodiment, the third transistor T3, the fifth transistor T5, and the seventh transistor T7 are N-type MOS transistors, and the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are P-type MOS transistors.

[0122] Figure 15The diagram shows the structure of the fifth polarity tuning circuit 340 provided in this application embodiment; N partition control circuits 320 include a first partition control circuit 321, a second partition control circuit 322, and a third partition control circuit 323; the polarity tuning circuit 340 includes a first AND gate, a second AND gate, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6; specifically, the first input terminal of the first AND gate is connected to the output terminal of the hysteresis comparison module 120 in the first partition control circuit 321, and the second input terminal of the first AND gate is connected to the output terminal of the hysteresis comparison module 120 in the second partition control circuit 322; the first input terminal of the second AND gate is connected to the output terminal of the hysteresis comparison module 120 in the second partition control circuit 322, and the second input terminal of the second AND gate is connected to the output terminal of the hysteresis comparison module 120 in the third partition control circuit 323. The output terminal of transistor T0 is connected; the control terminal of the third transistor T3 is connected to the output terminal of the first AND gate, the first terminal of the third transistor T3 is connected to the power supply terminal, and the second terminal of the third transistor T3 is connected to the polarity control terminal of the first data drive circuit 510; the control terminal of the fourth transistor T4 is connected to the control terminal of the third transistor T3, the first terminal of the fourth transistor T4 is connected to the second terminal of the third transistor T3, and the second terminal of the fourth transistor T4 is grounded; the control terminal of the fifth transistor T5 is connected to the output terminal of the second AND gate, the first terminal of the fifth transistor T5 is connected to the power supply terminal, and the second terminal of the fifth transistor T5 is connected to the polarity control terminal of the third data drive circuit 530; the control terminal of the sixth transistor T6 is connected to the control terminal of the fifth transistor T5, the first terminal of the sixth transistor T6 is connected to the second terminal of the fifth transistor T5, and the second terminal of the sixth transistor T6 is grounded.

[0123] In this embodiment, the third transistor T3 and the fifth transistor T5 are N-type MOS transistors, and the fourth transistor T4 and the sixth transistor T6 are P-type transistors.

[0124] Here, regarding the above Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 The similarities and differences between the polarity tuning circuits shown are explained in detail:

[0125] (1) The similarities are:

[0126] ①The fundamental purpose is the same: The fundamental purpose of all five circuits is to respond to the switching control signal of the partition control circuit and output the polarity tuning signal (POLC) to the data drive circuit to solve the problem of data polarity discontinuity that may occur when adjacent display partitions enable the ICA function.

[0127] ②The core components are the same: they all use MOS transistors (or combined resistors) as the basic signal switching and output driving units.

[0128] ③ Input signals originate from the same source: The input signals of each tuning module all originate from the switching control signal output by the hysteresis comparison module in the partition control circuit.

[0129] ④ Consistent output target: The final polarity tuning signal is output to the polarity control terminal of the data drive circuit to control whether its global polarity is flipped.

[0130] (2) The difference is:

[0131] ① Figure 11 and Figure 12 This is a direct control type: each zone's tuning module operates independently, and its output logic is determined solely by the switching control signal of its own zone. The difference lies in the transistor type configuration, resulting in opposite effective output logic levels. Figure 11 Low efficiency Figure 12 (For high efficiency), it is suitable for different preset polarity connection schemes.

[0132] ② Figure 13 This is a hybrid control type: some zones (such as zone B) use fixed levels (pull-down resistors), while only specific zones (such as zones A and C) are actively controlled. This is a cost optimization solution for a specific combination of driver chips.

[0133] ③ Figure 14 This belongs to the signal inversion control type: by introducing an inverter, the control signal received by the tuning module of the adjacent partition (such as partition B) is inverted, thereby achieving the opposite logic of the output of the adjacent partition. This is a circuit method to achieve alternating control.

[0134] ④ Figure 15 This is a logic-based control method: it uses AND gates for intelligent judgment, outputting a valid polarity tuning signal only when both adjacent partitions have ICA enabled. This scheme offers the most precise control and avoids unnecessary polarity reversals.

[0135] In one embodiment, the functions of the image detection module and the hysteresis comparison module in the control circuit shown in the above embodiment can be replaced and implemented by a unified AI intelligent big model; this model integrates signal detection, decision-making, and hysteresis control through a built-in artificial intelligence big model algorithm, realizing a leap from passive response to proactive intelligent decision-making, and the processing flow is as follows: Figure 16 Specifically, it includes:

[0136] (1) Pixel architecture analysis: First, determine whether the basic features such as the pixel architecture of the image meet the basic conditions for enabling the ICA function. If not, wait for the next frame to avoid invalid calculations.

[0137] (2) Abnormal area identification: For the screened images, AI image recognition technology is further used to analyze whether there are abnormal images such as high grayscale or large monochrome blocks, and to calculate whether their proportion reaches the threshold that needs to be compensated.

[0138] (3) Multi-parameter fusion decision: Finally, the unit will make a final decision by combining the current refresh rate of the screen and the experience learned from historical data. At this stage, the traditional fixed refresh rate threshold is replaced by a "decision probability" that is dynamically calculated by an AI model and fused with multiple parameters.

[0139] (4) Intelligent voltage conversion: Through the built-in linear fitting function, complex image information (such as abnormal area, refresh rate, color distribution, etc.) is accurately and non-linearly mapped into a high-precision virtual voltage signal. This step replaces the simple linear conversion in the traditional solution.

[0140] (5) Dynamic Hysteresis Control: The AI ​​model integrates a software hysteresis algorithm module. The hysteresis range of this module (equivalent to the hysteresis voltage in hardware) is no longer a fixed value, but can be dynamically adjusted according to the screen content, ambient temperature, and even the aging degree of the panel. For example, for scenes sensitive to motion blur, the AI ​​will appropriately narrow the hysteresis range to respond quickly; for scenes with high signal noise, it will widen the range to prevent flickering.

[0141] In one embodiment, such as Figure 17 As shown, the AI ​​intelligent large model mainly includes: ① Image receiving unit: responsible for receiving and parsing image input, serving as the perception interface of the AI ​​model; ② Image judgment unit: responsible for judging abnormal situations in the input image; ③ Intelligent learning module: the core of the AI ​​unit, containing a deep learning model capable of processing massive amounts of data accumulated in the historical storage unit (including image features, the final compensation scheme adopted, and its actual effect evaluation); ④ Compensation judgment unit: for the current image, the model matches it with the historical database; if highly similar historical data is found, the optimal compensation scheme that has been verified is directly called (calling historical compensation information) to achieve experience reuse. If it is a completely new image, it infers based on the learned general judgment logic to generate a new compensation strategy, which is then evaluated and further learned by the compensation judgment unit; ⑤ Fitting algorithm unit: as part of the intelligent learning module, it is specifically responsible for the above-mentioned linear fitting and other algorithms, ensuring that the AI ​​decisions are efficiently and accurately converted into control signals. In addition, the AI ​​intelligent large model also includes a voltage conversion unit, a hysteresis unit, a compensation output unit, and a historical storage unit.

[0142] This embodiment implements the core hardware module functions of the first three schemes through an AI agent that integrates perception, decision-making, learning, and execution capabilities. It not only covers all its functions but also achieves a qualitative improvement in performance, adaptability, and intelligence, representing the future development direction of ICA control technology.

[0143] Thirdly, embodiments of this application provide a display panel including a display area and a non-display area. The display area includes a pixel array; the non-display area includes a timing controller, a source drive circuit, and the aforementioned image compensation control device. The image compensation control device is electrically connected to the timing controller and the source drive circuit, respectively.

[0144] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0145] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0146] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A control circuit, characterized by The control circuit comprises: a picture detection module configured to detect a plurality of display parameters of a current display picture, and convert a refresh rate in the plurality of display parameters into a corresponding input voltage signal when it is determined that the current display picture is an abnormal picture according to the plurality of display parameters; wherein the picture detection module linearly converts the refresh rate into an analog voltage signal through a data converter; a hysteresis comparison module, an input end of the hysteresis comparison module being connected with the picture detection module, the hysteresis comparison module being configured to compare the input voltage signal with an upper threshold value and a lower threshold value respectively based on a hysteresis characteristic to output a corresponding switch control signal; wherein the upper threshold value is greater than the lower threshold value; an execution module, a control end of the execution module being connected with an output end of the hysteresis comparison module, a first connection end of the execution module being connected with an image compensation output end, and a second connection end of the execution module being connected with a subsequent stage driving circuit, the execution module being configured to turn on or turn off a signal path between the image compensation output end and the subsequent stage driving circuit in response to the switch control signal.

2. The control circuit of claim 1, wherein, The hysteresis comparison module comprises: a first resistor, a first end of the first resistor serving as an input end of the hysteresis comparison module; a second resistor, a first end of the second resistor being connected with a second end of the first resistor, and a second end of the second resistor serving as an output end of the hysteresis comparison module; a first inverter, an input end of the first inverter being connected with the second end of the first resistor; a second inverter, an input end of the second inverter being connected with an output end of the first inverter, and an output end of the second inverter being connected with the second end of the second resistor.

3. The control circuit of claim 1, wherein, The hysteresis comparison module comprises: a first resistor, a first end of the first resistor serving as an input end of the hysteresis comparison module; a second resistor, a first end of the second resistor being connected with a second end of the first resistor, and a second end of the second resistor serving as an output end of the hysteresis comparison module; a first switch tube, a control end of the first switch tube being connected with the second end of the first resistor, and a first end of the first switch tube being connected with a power supply end; a second switch tube, a control end of the second switch tube being connected with the control end of the first switch tube, a first end of the second switch tube being connected with a second end of the first switch tube, and a second end of the second switch tube being grounded; a third switch tube, a control end of the third switch tube being connected with the first end of the second switch tube, a first end of the third switch tube being connected with the power supply end, and a second end of the third switch tube serving as an output end of the hysteresis comparison module; a fourth switch tube, a control end of the fourth switch tube being connected with the control end of the third switch tube, a first end of the fourth switch tube being connected with the second end of the third switch tube, and a second end of the fourth switch tube being grounded; wherein the first switch tube and the third switch tube are P-type MOS tubes, and the second switch tube and the fourth switch tube are N-type MOS tubes.

4. The control circuit of claim 1, wherein, The hysteresis comparison module comprises: a first resistor, a first end of the first resistor serving as an input end of the hysteresis comparison module; a second resistor, a first end of the second resistor being connected with a second end of the first resistor, and a second end of the second resistor being an output end of the phase difference comparison module; a first transistor, a base of the first transistor being connected with the first end of the second resistor, and an emitter of the first transistor being grounded; a third resistor, a first end of the third resistor being connected with a power supply end, and a second end of the third resistor being connected with a collector of the first transistor; a second transistor, a base of the second transistor being connected with the collector of the first transistor, an emitter of the second transistor being grounded, and a collector of the second transistor being the output end of the phase difference comparison module; a fourth resistor, a first end of the fourth resistor being connected with the power supply end, and a second end of the fourth resistor being connected with the collector of the second transistor.

5. An image compensation control device, characterized by comprising: The display panel comprises N display sub-regions, and one display sub-region corresponds to one data driving circuit. The image compensation control device comprises: a total control circuit, the total control circuit being the control circuit of any one of claims 1-4, and being configured to generate a whole-region control signal based on display parameters of the display panel; N sub-region control circuits, each sub-region control circuit being the control circuit of any one of claims 1-4, and each sub-region control circuit being configured to generate a sub-region control signal based on display parameters of a corresponding display sub-region; a mode switching circuit, coupled to a mode output end, the total control circuit, the N sub-region control circuits, and N data driving circuits, and configured to input the whole-region control signal to the N data driving circuits in response to an externally input first mode selection signal, and input a sub-region control signal generated by an i-th sub-region control circuit to an i-th data driving circuit in response to an externally input second mode selection signal, where i = 1,..., N.

6. The image compensation control device according to claim 5, characterized by The mode switching circuit comprises: N first transistors, a control end of each first transistor being connected with the mode output end, a first end of each first transistor being connected with an output end of a corresponding sub-region control circuit, and a second end of each first transistor being connected with a corresponding data driving circuit; wherein the N first transistors are connected with the N sub-region control circuits and the N data driving circuits in a one-to-one correspondence; N-1 second transistors, a control end of each second transistor being connected with the mode output end, a first end of a first second transistor being connected with an output end of the total control circuit and a first data driving circuit respectively, a first end of a j-th second transistor being connected with a second end of a (j-1)-th second transistor and a j-th data driving circuit respectively, and a second end of an (N-1)-th second transistor being connected with an N-th data driving circuit; wherein j = 2,..., N-1; the turn-on voltages of the first transistors and the second transistors are opposite.

7. The image compensation control device according to claim 5, wherein The image compensation control device further comprises: a polarity tuning circuit, input ends of the polarity tuning circuit being connected with the N sub-region control circuits, and output ends of the polarity tuning circuit being connected with the N data driving circuits respectively; The polarity tuning circuit is configured to output a polarity tuning signal to a polarity control terminal of at least one data driving circuit in response to a switch control signal output by the subarea control circuit; wherein the polarity tuning signal is used to make the data signal polarity arrangement of adjacent display subareas continuous.

8. The image compensation control device according to claim 7, characterized by The polarity tuning circuit comprises at least one tuning module. The tuning module comprises an N-type transistor and a P-type transistor, a control terminal of the N-type transistor is connected with the subarea control circuit, a first terminal of the N-type transistor is connected with a power terminal, and a second terminal of the N-type transistor is connected with a polarity control terminal of the data driving circuit; a control terminal of the P-type transistor is connected with the control terminal of the N-type transistor, a first terminal of the P-type transistor is connected with the second terminal of the N-type transistor, and a second terminal of the P-type transistor is grounded.

9. The image compensation control device according to claim 7, wherein The N subarea control circuits comprise a first subarea control circuit, a second subarea control circuit and a third subarea control circuit, and the polarity tuning circuit comprises: a first AND gate, a first input terminal of the first AND gate is connected with an output terminal of a return difference comparison module in the first subarea control circuit, and a second input terminal of the first AND gate is connected with an output terminal of a return difference comparison module in the second subarea control circuit; a second AND gate, a first input terminal of the second AND gate is connected with an output terminal of a return difference comparison module in the second subarea control circuit, and a second input terminal of the second AND gate is connected with an output terminal of a return difference comparison module in the third subarea control circuit; a third transistor, a control terminal of the third transistor is connected with an output terminal of the first AND gate, a first terminal of the third transistor is connected with a power terminal, and a second terminal of the third transistor is connected with a polarity control terminal of a first data driving circuit; a fourth transistor, a control terminal of the fourth transistor is connected with the control terminal of the third transistor, a first terminal of the fourth transistor is connected with the second terminal of the third transistor, and a second terminal of the fourth transistor is grounded; a fifth transistor, a control terminal of the fifth transistor is connected with an output terminal of the second AND gate, a first terminal of the fifth transistor is connected with a power terminal, and a second terminal of the fifth transistor is connected with a polarity control terminal of a third data driving circuit; a sixth transistor, a control terminal of the sixth transistor is connected with the control terminal of the fifth transistor, a first terminal of the sixth transistor is connected with the second terminal of the fifth transistor, and a second terminal of the sixth transistor is grounded.

10. A display panel comprising a display area and a non-display area, characterized in that, The display area comprises a pixel array. The non-display area comprises a timing controller, a source driving circuit and the image compensation control device of any one of claims 5-9, and the image compensation control device is electrically connected with the timing controller and the source driving circuit respectively.

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