Three-phase sepic converter control circuit and control method

Abstract

This application discloses a control circuit and method for a three-phase SEPIC converter, addressing the problem of increased losses during startup caused by voltage inconsistencies before and after the three-phase rectifier bridge, which prevents the switching transistors from achieving valley-level conduction. The hardware solution adds a second sampling circuit after the three-phase rectifier bridge, using the sampled second voltage signal for startup and steady-state control of the switching transistors, while the first voltage signal collected before the three-phase rectifier bridge is used for input voltage protection. The software solution provides a soft-start control method, which performs phase-by-phase startup by detecting whether the first voltage signal reaches the peak input voltage, and adjusts the duty cycle of the drive signal during startup to control the conduction time of the switching transistors until the input voltage crosses zero, at which point it switches to closed-loop control. This application ensures valley-level conduction throughout the entire process from startup to steady state, reducing switching losses and device stress, and improving converter efficiency and reliability.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to the control circuit and control method of a three-phase SEPIC converter. Background Technology

[0002] The three-phase single-ended primary inductor converter (SEPIC) is a highly efficient and compact alternating current to direct current (AC-DC) single-stage converter topology, widely used in charging modules, automotive power supplies, and other applications. To achieve high efficiency and low electromagnetic interference, it is typically necessary to control its switching transistors to operate in a valley conduction state (i.e., zero voltage or low voltage switching).

[0003] Currently, the control loop of SEPIC converters typically relies on sampling the AC input voltage before the rectifier bridge. However, during the initial power-up phase, since the switching transistors have not yet started operating, energy cannot be transferred to the secondary side, causing the capacitor after the rectifier bridge to be charged to the peak value of the AC line voltage and maintained in a high-voltage DC state. At this time, the voltage before and after the rectifier bridge are inconsistent. Directly using the sampled voltage before the rectifier bridge for control algorithm calculations will result in the calculated turn-off time of the switching transistors being much shorter than the actual requirement. This causes the converter to operate in continuous conduction mode during the initial startup phase, preventing the switching transistors from achieving valley-level conduction, resulting in significant switching and conduction losses and reducing system reliability.

[0004] Therefore, how to solve the problem of valley conduction failure caused by voltage inconsistency before and after the rectifier bridge during the startup phase of a three-phase SEPIC converter has become an urgent technical problem to be solved. Summary of the Invention

[0005] This application provides a control circuit and method for a three-phase SEPIC converter. Its core objective is to ensure that the switching transistors of the three-phase SEPIC converter can achieve and maintain valley-level conduction throughout the entire startup process, thereby significantly reducing startup losses and improving system efficiency and reliability. To achieve the above objectives, this application adopts the following technical solution:

[0006] In a first aspect, a control circuit for a three-phase SEPIC converter is provided, comprising a three-phase rectifier bridge, a power circuit, and an output sampling unit: a first sampling circuit, wherein a first input terminal of the first sampling circuit is coupled to the input side of the three-phase rectifier bridge to obtain a first voltage signal; a second sampling circuit, wherein a second input terminal of the second sampling circuit is coupled to the output side of the three-phase rectifier bridge to obtain a second voltage signal; and a controller electrically connected to the first sampling circuit and the second sampling circuit, respectively; wherein the controller is configured to: perform input voltage protection based on the first voltage signal; generate a drive signal based on the second voltage signal during the startup phase of the three-phase SEPIC converter, the drive signal being used to control the switching transistors in the power circuit; and generate the drive signal based on the second voltage signal and the feedback signal of the output sampling unit after entering the steady-state operation phase.

[0007] In conjunction with the first aspect, the second input terminal includes three independent voltage sampling branches for acquiring the voltages of the three output nodes corresponding one-to-one with the three-phase rectifier bridge.

[0008] In conjunction with the first aspect, the controller is configured during the startup phase to control the switching transistor to turn on at the valley of its on-voltage, based on the change in the second voltage signal.

[0009] In conjunction with the first aspect, the controller includes an overvoltage protection module and a pulse width modulation module; the input terminal of the overvoltage protection module is connected to the first output terminal of the first sampling circuit; the input terminal of the pulse width modulation module is connected to the second output terminal of the second sampling circuit and receives the feedback signal.

[0010] It should be noted that, in the absence of conflict, the features in the various embodiments of the first aspect can be combined with each other, and any combination of features in different embodiments is also within the protection scope of this application. That is to say, the various embodiments described above can also be arbitrarily combined according to actual needs.

[0011] In a second aspect, a control method for a three-phase SEPIC converter is provided, applied to the control circuit provided in the first aspect, comprising: acquiring synchronization information of a first voltage signal, the synchronization information including a fundamental frequency, the first voltage signal being any one of the three-phase input voltages; during startup, when the first voltage signal reaches a peak voltage, starting the corresponding switch in the three-phase SEPIC converter; during the time period from the start-up of the switch to the first zero crossing of the first voltage signal, dynamically adjusting the conduction time of the switch based on a periodic function synchronized with the fundamental frequency by a drive signal; when the first zero crossing of the first voltage signal is detected, ending the dynamic adjustment of the switch based on the periodic function, and controlling the conduction time of the switch according to closed-loop feedback.

[0012] In conjunction with the second aspect, the method of dynamically adjusting the on-time of the switch based on a periodic function synchronized with the fundamental frequency includes: calculating the on-time of the switch based on the periodic function, dynamically adjusting the duty cycle of the drive signal through the on-time, and controlling the on-time of the switch through the drive signal.

[0013] In conjunction with the second aspect, the acquisition of synchronization information for the first voltage signal includes: performing zero-crossing detection or spectrum analysis on the first voltage signal to obtain the fundamental frequency.

[0014] Thirdly, a three-phase SEPIC converter is provided, including the control circuit of the three-phase SEPIC converter as described in the first aspect.

[0015] Fourthly, a computer device is provided for use in a three-phase SEPIC converter, including a processor and a memory storing a computer program that, when executed by the processor, causes the computer device to implement the control method for the three-phase SEPIC converter as described in the second aspect above.

[0016] Fifthly, a computer-readable storage medium is provided having computer instructions stored thereon, which, when executed by a processor, implement the control method for a three-phase SEPIC converter as described in the second aspect above.

[0017] Compared with the prior art, this application has the following beneficial effects:

[0018] The hardware solution provided in this application directly corrects the control reference, and the software solution realizes system synchronization. Both can ensure that the switching transistor is turned on at the bottom of the valley throughout the entire process from startup to steady state, thereby reducing switching losses.

[0019] The solution provided in this application reduces the heat loss and electrical stress of power devices during the startup phase when stress is at its highest, thereby improving the lifespan and reliability of the entire converter.

[0020] The solution provided in this application offers two technical paths: hardware improvement and software optimization. These can be selected or combined depending on the product's different requirements for cost, performance, and reliability.

[0021] The software solution provided in this application can make full use of existing hardware, with low upgrade costs. Its zero-crossing switching mechanism ensures a smooth transition from startup to steady-state control, thereby improving system stability. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the overall framework of a three-phase SEPIC converter and its control system provided in an embodiment of this application;

[0024] Figure 2 This is a circuit diagram of a three-phase SEPIC converter provided in an embodiment of this application;

[0025] Figure 3 This is a schematic diagram of the voltage waveform of a three-phase SEPIC converter during normal operation, provided in an embodiment of this application.

[0026] Figure 4 This is a schematic diagram of the switching voltage waveform of a three-phase SEPIC converter during normal operation, provided in an embodiment of this application.

[0027] Figure 5 This is a schematic diagram of the voltage waveform of a three-phase SEPIC converter during abnormal operation, provided in an embodiment of this application.

[0028] Figure 6 This is a schematic diagram of the switching transistor conduction voltage waveform when a three-phase SEPIC converter is malfunctioning, as provided in an embodiment of this application.

[0029] Figure 7 This is a flowchart illustrating a control method provided in an embodiment of this application;

[0030] Figure 8 This is a schematic diagram of a voltage waveform in a control method provided in an embodiment of this application;

[0031] Figure 9 This is a flowchart illustrating another control method provided in an embodiment of this application;

[0032] Figure 10 This is a schematic diagram of the UV phase voltage waveform in a control method provided in an embodiment of this application;

[0033] Figure 11 This is a schematic diagram of the WU phase voltage waveform in a control method provided in an embodiment of this application;

[0034] Figure 12 This is a schematic diagram of the VW phase voltage waveform in a control method provided in an embodiment of this application;

[0035] Figure 13 This is a schematic diagram of a drive signal waveform during the startup phase provided in an embodiment of this application;

[0036] Figure 14 This is a schematic diagram of the hardware structure of a computer device provided in an embodiment of this application;

[0037] Figure 15 This is a schematic diagram of a computer-readable storage medium provided in an embodiment of this application. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0039] It should be understood that "multiple" as mentioned in this application refers to two or more. In the description of this application, unless otherwise stated, " / " indicates "or," for example, A / B can mean A or B; "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist, for example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, to facilitate a clear description of the technical solutions of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0040] The terms "one embodiment" or "some embodiments" used in this application mean that one or more embodiments of this application include the specific features, structures, or characteristics described in that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this application do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, the terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0041] Example 1: Implementation based on hardware architecture.

[0042] In this embodiment of the application, a voltage sampling circuit (i.e., a second sampling circuit) after the rectifier bridge is added to the three-phase SEPIC converter, and the obtained voltage after the bridge (i.e., the second voltage signal) is used as the basis for loop control.

[0043] 1. Overall architecture of the three-phase SEPIC converter.

[0044] Figure 1 This is a schematic diagram of the overall framework of a three-phase SEPIC converter and its control system provided in an embodiment of this application. Figure 1 As shown, the three-phase SEPIC converter includes an AC input unit, a power conversion unit, a DC output unit, an input sampling unit, an output sampling unit, a drive unit, and a control unit. The power conversion unit includes a three-phase rectifier bridge and a power circuit, and the input sampling unit includes a first sampling circuit and a second sampling circuit.

[0045] In this embodiment, the AC input unit inputs three-phase AC power to the power conversion unit. The AC power, after passing through a three-phase rectifier and power circuit, outputs DC power to the DC output unit. The input sampling unit samples and provides the control unit with the electrical signals before and after the three-phase rectifier bridge. The output sampling unit provides the control unit with the electrical signals output from the three-phase SEPIC converter. Based on the acquired electrical signals, the control unit generates drive signals to control the power conversion unit and inputs them to the power circuit through the drive unit.

[0046] In the input sampling unit, the first input terminal of the first sampling circuit is coupled to the input side of the three-phase rectifier bridge to acquire the first voltage signal; the second input terminal of the second sampling circuit is coupled to the output side of the three-phase rectifier bridge to acquire the second voltage signal. The first voltage signal is any one of the three-phase input voltages.

[0047] In some implementations, the controller includes an overvoltage protection module and a pulse width modulation module: the input of the overvoltage protection module is connected to the first output of the first sampling circuit; the input of the pulse width modulation module is connected to the second output of the second sampling circuit and receives a feedback signal. The overvoltage protection module performs input voltage protection based on a first voltage signal.

[0048] During the startup phase of the three-phase SEPIC converter, the pulse width modulation module generates a drive signal based on the second voltage signal to control the switching transistors of the power circuit in the three-phase SEPIC converter.

[0049] After the steady-state operation phase, the pulse width modulation module generates a drive signal based on the second voltage signal and the feedback signal from the three-phase SEPIC converter output sampling unit. The switching transistors are power devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0050] In this embodiment, the startup phase refers to the entire process from the moment the three-phase SEPIC controller first sends a drive signal to the switching transistor, until the voltage waveform after the three-phase rectifier bridge of the three-phase SEPIC converter first enters a stable state, continuously following the phase change of the AC input voltage before the three-phase rectifier bridge, and the output voltage of the converter reaches and stabilizes within the target value range.

[0051] In the embodiments of this application, the stable operation phase refers to the operating state of the three-phase SEPIC converter, which maintains a stable output voltage through closed-loop feedback control immediately following the startup phase, based on the fact that the voltage after the three-phase rectifier bridge is synchronized with the voltage before the bridge.

[0052] In this embodiment, closed-loop feedback refers to the feedback adjustment that adjusts the drive signal of the switching transistor in the three-phase SEPIC converter based on the difference between the feedback signal of the three-phase SEPIC converter and the expected target signal, so as to reduce the difference.

[0053] In this embodiment, the feedback signal refers to the signal collected from the DC output terminal of the three-phase SEPIC converter for closed-loop control, including at least one of the output voltage sampling signal and the output current sampling signal.

[0054] For example, the controller clamps the input voltage to the voltage threshold after the first voltage signal exceeds the threshold voltage to prevent the input voltage from becoming too high, thus providing input voltage protection. The second voltage signal is the input signal of the power circuit. The controller can accurately obtain the on-state voltage of the switching transistor in the power circuit, thereby enabling the switching transistor to be turned on when the on-state voltage is low, achieving valley-level conduction.

[0055] In some embodiments, the input sampling unit may include only the first sampling circuit. The controller achieves graded soft start of the three-phase SEPIC converter by setting different start-up times and waveform generation strategies for the three-phase circuit, thereby achieving valley-level conduction of the switching transistors during the start-up process.

[0056] It is understood that the functional division between the modules illustrated in the embodiments of this application is merely illustrative and does not constitute a functional limitation on the three-phase SEPIC converter. In other embodiments of this application, the three-phase SEPIC converter may also employ different modules or combinations of multiple modules to implement the functions of the three-phase SEPIC converter.

[0057] 2. Specific hardware implementation of the control circuit.

[0058] Figure 2 This is a circuit diagram of a three-phase SEPIC converter provided in an embodiment of this application. Figure 2As shown, the AC input circuit includes U-phase line, V-phase line and W-phase line, and the output AC voltage includes UV-phase, VW-phase and WU-phase. After rectification by the three-phase rectifier bridge, the rectified voltage (i.e., the voltage at points U1V1, V2W2, and W3U3) is output across capacitors C1, C2 and C3.

[0059] The rectified voltage of each phase is input to an independent power circuit: In the UV phase, the power circuit includes a switch Q1, an inductor L1, a transformer T1, and a coupling capacitor C4. In the VW phase, the power circuit includes a switch Q2, an inductor L2, a transformer T2, and a coupling capacitor C5. In the WU phase, the power circuit includes a switch Q3, an inductor L3, a transformer T3, and a coupling capacitor C6.

[0060] Input sampling circuit (i.e., first sampling circuit): Its first input terminal is directly connected to the AC input terminal of the three-phase rectifier bridge, and a voltage divider and isolation scheme can be used to obtain the first voltage signal. For example, resistors are used to divide the UV, VW, and WU phases, followed by an isolation operational amplifier for electrical isolation, and a low-voltage signal is output to the input pin of the controller for input voltage protection and frequency detection.

[0061] Control voltage sampling circuit (i.e., second sampling circuit): The second sampling circuit includes a second input terminal, which consists of three independent voltage sampling branches. These branches are used to acquire the voltages of the three output nodes corresponding one-to-one with the UV, VW, and WU phases of the three-phase rectifier bridge. Specifically, they are directly connected to the output nodes U1V1, V2W2, and W3U3 of the three-phase rectifier bridge to obtain the second voltage signal. This second voltage signal is the actual voltage applied to the input terminals of each phase power circuit.

[0062] For example, a high-input-impedance differential amplifier can be used to convert the high-voltage signal at the output node of the three-phase rectifier bridge into a low-voltage signal. The sampled signals from each of the three phases of the rectifier bridge are then independently sent to the controller. The controller can be a digital signal processor with both analog-to-digital converter (ADC) and pulse-width modulation (PWM) outputs.

[0063] The DC output circuit is used to output DC voltage and DC current from the three-phase SEPIC converter, and obtains electrical signals through the output sampling circuit to feed them back to the controller. The controller combines the electrical signals obtained from the input and output sampling circuits to generate drive signals, and amplifies the drive signals through the drive circuit to control the operation of switches Q1, Q2, and Q3.

[0064] The existing three-phase SEPIC converter lacks a second sampling circuit; the controller directly uses the voltage before the three-phase rectifier bridge to calculate the turn-off time of the switching transistor. For example, the turn-off time Toff is calculated by sampling the voltage Vin_samp at point UV. The reference formula for Toff is: Toff = (Vin_samp / Vo) × Ton, where Ton is the on-time of the switching transistor, and Vo is the output voltage of the three-phase SEPIC converter.

[0065] Figure 3 This is a schematic diagram of the voltage waveform of a three-phase SEPIC converter during normal operation, provided in an embodiment of this application. Figure 3 As shown, taking the UV phase voltage as an example, when the three-phase SEPIC converter is working normally, the UV phase voltage is converted into U1V1 voltage after passing through the three-phase rectifier bridge. The U1V1 voltage waveform is a waveform obtained by taking the absolute value of the UV phase voltage waveform. The controller can convert the input UV phase voltage AC waveform.

[0066] Figure 4 This is a schematic diagram of the switching transistor on-state voltage waveform during normal operation of a three-phase SEPIC converter provided in this application embodiment. Figure 4 As shown, the switching transistor turns on at the valley of its turn-on voltage. The turn-on voltage (i.e., Vds) of the switching transistor is close to zero (such as less than a preset voltage threshold, such as less than 0.3V) when the switching transistor transitions from the off state (corresponding to the Toff time period) to the on state (corresponding to the Ton time period), which can realize the turn-on of the switching transistor at the valley.

[0067] When the AC input circuit is powered on, and the switching transistor is turned off, the voltage of the capacitor after the three-phase rectifier bridge is charged to the peak value of the input line voltage, resulting in the switching transistor being turned on by a DC voltage.

[0068] For example, during the period from when the AC input circuit is powered on until the switching transistors receive the drive signal, switching transistors Q1, Q2, and Q3 are off. During this time, capacitors C1, C2, and C3 after the three-phase rectifier bridge are charged to the peak value of the input phase voltage (e.g., if the input phase voltage is a sinusoidal AC with an effective value of 220V and a peak value of 311V, then the voltage at point U1V1 is 311V DC). Meanwhile, the voltage at point UV before the rectifier bridge is a sinusoidally varying AC current.

[0069] Figure 5 This is a schematic diagram of the voltage waveform of a three-phase SEPIC converter when it is malfunctioning, as provided in an embodiment of this application. Figure 6 This is a schematic diagram of the switching transistor conduction voltage waveform when a three-phase SEPIC converter malfunctions, as provided in an embodiment of this application. Figure 5 and Figure 6As shown, taking the UV phase as an example, the voltage waveform of the UV phase input is less than the actual switching transistor turn-on voltage (i.e., U1V1), which causes the calculated Toff to be less than the actual required value. This causes the three-phase SEPIC converter to operate in an unexpected continuous conduction mode during the initial startup phase. The switching transistor cannot turn on at the bottom of the switching transistor turn-on voltage Vds (i.e., the drain-to-prime voltage), resulting in high-loss turn-on.

[0070] To avoid the above problems, this application provides a three-phase SEPIC converter control method to achieve valley-level conduction of the switching transistor.

[0071] 3. Controller configuration and workflow.

[0072] Figure 7 This is a flowchart illustrating a control method provided in an embodiment of this application. (Reference) Figure 7 In this embodiment of the application, the controller can be configured to execute the following logic:

[0073] S101. Power-on initialization.

[0074] In this embodiment of the application, the controller reads the input voltage (i.e., the first voltage signal) of the AC input circuit and the voltage after passing through the three-phase rectifier (i.e., the second voltage signal), and calculates the effective value and fundamental frequency of the first voltage signal.

[0075] S102. Protection detection.

[0076] In this embodiment, the controller compares the effective value with a preset voltage threshold and clamps the first voltage signal that exceeds the voltage threshold at the voltage threshold to achieve input voltage protection.

[0077] S103. Converter starts.

[0078] During the startup phase of the three-phase SEPIC converter, the second voltage signal indicates the turn-on voltage (Vds) from the drain to the source of the switching transistor. Upon receiving the startup command, the controller calculates the turn-off time Toff of the switching transistor based on the second voltage signal.

[0079] By combining real-time detection of the second voltage signal waveform, the controller controls the switching transistor to turn on at the valley of its conduction voltage according to the changes in the second voltage signal. That is, the controller can issue a drive signal to turn on the switching transistor at the valley of the conduction voltage (i.e., when Vds is at its minimum or less than a preset voltage value, for example, when Vds is 0V or less than a preset 0.3V), thus achieving valley-level conduction.

[0080] After the three-phase SEPIC converter is started, the controller's control strategy remains unchanged, continuously using the second voltage signal and the feedback signal of the three-phase SEPIC converter for closed-loop regulation to ensure the working efficiency and performance of the three-phase SEPIC converter.

[0081] Figure 8 This is a schematic diagram of a voltage waveform in a control method provided in an embodiment of this application. For example... Figure 8 As shown, taking the UV phase voltage as an example, timing begins when the AC input circuit is powered on. During the time period from t=0 to t=A, the AC input circuit is powered on, the switching transistor is off, and the voltage across the capacitor after the three-phase rectifier bridge is the peak value of the AC input voltage, causing the switching transistor's turn-on voltage to be higher than the AC input voltage. When the switching transistor is turned on at t=A, the controller can directly obtain the accurate turn-on voltage of the switching transistor, thereby calculating the actual required turn-off time Toff and turn-on time Ton of the switching transistor, achieving valley-level conduction of the switching transistor.

[0082] Example 2: Implementation based on control strategy optimization.

[0083] In this embodiment of the application, the three-phase SEPIC converter can also be used without adding, for example Figure 2 In the case of the control voltage sampling circuit shown, the switching transistor is turned on at the valley by improving the startup algorithm.

[0084] Figure 9 This is a flowchart illustrating another control method provided in an embodiment of this application. (Reference) Figure 9 In this embodiment of the application, the controller can be configured to execute the following logic:

[0085] S201. Controller preparation.

[0086] In this embodiment, the controller detects that the AC input circuit is powered on, calculates the effective value of the input AC voltage for the first three phases of the three-phase rectifier bridge, and calculates the fundamental frequency f (e.g., 50Hz) through methods such as zero-crossing detection or spectrum analysis.

[0087] The peak value of each phase voltage in the three-phase voltage can be obtained from the effective value. For example, the effective value can be obtained by multiplying the effective value by the square root of 2 or 1.414.

[0088] S202. Start the switching transistor and calculate the conduction time.

[0089] In this embodiment, the controller receives a power-on command and detects a first voltage signal. The first voltage signal is any one of the three-phase input voltages. During startup, when the controller detects that the first voltage signal has reached its peak voltage, it activates the corresponding switch in the three-phase SEPIC converter.

[0090] During the period from the start-up of the switching transistor to the first zero crossing of the first voltage signal, the on-time of the switching transistor is dynamically adjusted by a drive signal based on a periodic function synchronized with the fundamental frequency. Specifically, the on-time is calculated according to a preset waveform generation strategy, the duty cycle of the PWM wave of the drive signal is dynamically adjusted, and the switching transistor is controlled by the drive signal to adjust the on-time accordingly.

[0091] When the first voltage signal is detected to cross zero for the first time, the dynamic adjustment of the switching transistor based on the periodic function ends, and the conduction time of the switching transistor is controlled according to the closed-loop feedback.

[0092] For example, Figure 10 This is a schematic diagram of the UV phase voltage waveform in a control method provided in an embodiment of this application. (Reference) Figure 10 The output voltage waveform of the UV phase in the three-phase voltage is Vuv. After the UV phase switching transistor is started, the voltage waveform of U1V1 through the three-phase rectifier is the absolute value of the Vuv voltage waveform (i.e., |Vuv|). When the instantaneous absolute value of the U1V1 voltage waveform is greater than or equal to the voltage peak value (i.e., |Vuv|≥Vpeaku, where Vpeaku is the pre-calculated or measured peak value of the U1V1 voltage), the start-up time of the UV phase switching transistor is determined (t=A).

[0093] The controller calculates the turn-on time based on the waveform generation strategy: After time t=A, until the first zero crossing of Vuv is detected (time t is denoted as A1), the drive signal for controlling the switch Q1 is a PWM wave. The duty cycle of this PWM wave is determined by the turn-on time Ton_UV of the switch Q1, which can be calculated as follows: Ton_UV=|Ton1×sin(2πft)|. Where f is the fundamental frequency, and Ton1 can be the initial turn-on time preset based on the target output voltage, the effective value of the input voltage, and the transformer turns ratio. The turn-on time Ton_UV is an absolute value sine function, and its waveform frequency is synchronized with the fundamental frequency.

[0094] Similarly, Figure 11 This is a schematic diagram of the WU phase voltage waveform in a control method provided in an embodiment of this application. Figure 12 This is a schematic diagram of the VW phase voltage waveform in a control method provided in an embodiment of this application. (Reference) Figure 11 and Figure 12 The output voltage waveform of phase VW in the three-phase voltage is Vvw. After the switching transistor of phase VW is started, the voltage waveform of V2W2 through the three-phase rectifier is the absolute value of the voltage waveform of Vvw (i.e., |Vvw|). The output voltage waveform of phase WU in the three-phase voltage is Vwu. After the switching transistor of phase WU is started, the voltage waveform of W3U3 through the three-phase rectifier is the absolute value of the voltage waveform of Vwu (i.e., |Vwu|).

[0095] When the instantaneous absolute value of the voltage waveform of V2W2 is greater than or equal to the voltage peak value (i.e., |Vvw|≥Vpeakv, where Vpeakv is the pre-calculated or measured peak value of V2W2 voltage), the start-up time of the VW phase switch is determined (t=C); when the instantaneous absolute value of the voltage waveform of W3U3 is greater than or equal to the voltage peak value (|Vwu|≥Vpeakw, where Vpeakw is the pre-calculated or measured peak value of W3U3 voltage), the start-up time of the WU phase switch is determined (t=B).

[0096] The controller calculates the turn-on time based on the waveform transmission strategy:

[0097] After time t=B, until the first zero crossing of Vwu is detected (time t is denoted as B1), the drive signal for controlling switch Q3 is a PWM wave. The duty cycle of this PWM wave is determined by the on-time Ton_WU of switch Q3, which is calculated as follows: Ton_WU=|Ton1×sin(2πft+4π / 3)|. The on-time Ton_WU is an absolute value sine function, and its waveform frequency is synchronized with the fundamental frequency.

[0098] After time t=C, until the first zero crossing of Vvw is detected (time t is denoted as C1), the drive signal controlling the switch Q2 is a PWM wave. The duty cycle of this PWM wave is determined by the on-time Ton_VW of the switch Q2, which is calculated as follows: Ton_VW=|Ton1×sin(2πft+2π / 3)|. The on-time Ton_VW is an absolute value sine function, and its waveform frequency is synchronized with the fundamental frequency.

[0099] In the embodiments of this application, three functional relationships are used: the three functions Ton_UV, Ton_VW and Ton_WU for the three phases UV, VW and WU have the same waveform shape (all absolute value sine waves) and the same amplitude reference (all Ton1). The only difference is that the phase is shifted by 120 electrical degrees (i.e. 2π / 3 radians) to correspond to the phase relationship of the three-phase input voltage.

[0100] Figure 13 This is a schematic diagram of a drive signal waveform during the startup phase provided in an embodiment of this application. Figure 13 As shown:

[0101] The startup phase of the UV phase switch Q1 is the time period from t=A to t=A1, during which the UV drive signal is emitted in the form of a PWM wave. Based on the aforementioned calculation method for Ton_UV, the conduction time of switch Q1 is obtained, and the duty cycle of the PWM wave gradually decreases during the startup phase.

[0102] The start-up phase of the WU phase switch Q3 is the time period from t=B to t=B1, during which the wu drive signal is emitted in the form of a PWM wave. Based on the aforementioned calculation method of Ton_WU, the conduction time of the switch Q3 is obtained, and the duty cycle of the PWM wave gradually decreases during the start-up phase.

[0103] The startup phase of the VW phase switch Q2 is the time period from t=C to t=C1, during which the vw drive signal is emitted in the form of a PWM wave. Based on the aforementioned calculation method of Ton_VW, the conduction time of the switch Q2 is obtained, and the duty cycle of the PWM wave gradually decreases during the startup phase.

[0104] refer to Figure 13 The drive signal waveform shown is shown during the startup phase. The software control flow of the controller provided in this application is as follows:

[0105] 1. Power module input is powered on.

[0106] 2. Module Initialization Settings: Based on the first voltage signal sampled before the three-phase rectifier bridge, calculate the effective value of the first voltage signal and its fundamental frequency f. The first voltage signal includes any one of the three-phase input voltages, which are: UV phase voltage signal (Vin_samp_UV), VW phase voltage signal (Vin_samp_VW), and WU phase voltage signal (Vin_samp_WU). The three-phase input voltages correspond to the effective values ​​of the three-phase voltages: UV phase voltage effective value (Vuv_RMS), VW phase voltage effective value (Vvw_RMS), and WU phase voltage effective value (Vwu_RMS).

[0107] 3. The module receives the power-on command.

[0108] 4. Upon detecting that the UV phase voltage signal has reached its peak value (i.e., Vin_samp_UV = |Vuv_RMS × 1.414|), timer t begins (at this point, t = A), and the UV phase switching transistors start simultaneously. The duty cycle of the UV drive signal is dynamically adjusted based on the conduction time Ton_UV (calculated as: Ton_UV = |Ton1 × sin(2πft)|).

[0109] 5. Upon detecting that the WU phase voltage signal reaches its peak value (i.e., Vin_samp_WU = |Vwu_RMS × 1.414|), timer t begins (at this point, t = B), and the switching transistor of the WU phase starts up simultaneously. The duty cycle of the wu drive signal is dynamically adjusted based on the conduction time Ton_WU (calculated as: Ton_WU = |Ton1 × sin(2πft + 4π / 3)|).

[0110] 6. The UV phase voltage signal is detected to cross zero for the first time (i.e., Vin_samp_UV=0, at which point t=A1), and the UV phase ends the start-up phase. The calculation of the conduction time Ton_UV is then performed.

[0111] 7. Upon detecting that the VW phase voltage signal has reached its peak value (i.e., Vin_samp_VW = |Vvw_RMS × 1.414|), timer t begins (at this point, t = C), and the VW phase switch starts simultaneously. The duty cycle of the VW drive signal is dynamically adjusted based on the conduction time Ton_VW (calculated as: Ton_VW = |Ton1 × sin(2πft + 2π / 3)|).

[0112] 8. The calculation of the conduction time Ton_WU is performed after the WU phase voltage signal is detected to cross zero for the first time (i.e., Vin_samp_WU=0, at which point t=B1).

[0113] 9. The VW phase voltage signal is detected to cross zero for the first time (i.e., Vin_samp_VW=0, at which point t=C1), and the VW phase ends the start-up phase. The calculation of the conduction time Ton_VW is performed.

[0114] 10. The controller completes the control of the three-phase voltage drive signals during the startup phase.

[0115] S203. Mode switching.

[0116] For the input voltage of the UV phase, when the controller detects the first zero crossing of Vuv (including from positive to negative or from negative to positive), the time t is recorded as A1.

[0117] Simultaneously, the controller immediately terminates the control method for switch Q1 as shown in step S202. Ton_UV is calculated based on the output voltage Vo_samp and output current Io_samp obtained from the output sampling circuit, for example, using a voltage-current dual-loop proportional-integral-derivative (PID) controller, to obtain Ton_UV = Ton1, where Ton1 is the PID output value.

[0118] Similarly, for the switches Q2 and Q3 corresponding to phases VW and WU, the same exit and switching operations as those for switch Q1 are performed at the times when Vvw and Vwu first cross zero (t is time C1 and t is time B1, respectively).

[0119] Based on steps S201 to S203 above, starting from the peak value of the first voltage signal, the on-time of the switching transistor is calculated using a periodic function with the same frequency as the first voltage signal. This ensures that the energy change pattern transferred from the primary to the secondary side of the transformer is consistent with the waveform of the input voltage, thus physically changing the voltage on the capacitors after the three-phase rectifier bridge (such as U1V1, etc.) from the initial high DC potential to the peaked waveform of the three-phase rectifier bridge during normal operation. Simultaneously, once the voltage after the three-phase rectifier bridge is consistent with the phase and shape of the voltage during normal operation, loop control calculations can be performed using the voltage before the three-phase rectifier bridge, thus naturally achieving the valley-level conduction of the switching transistor.

[0120] It should be understood that, as mentioned above Figure 9 The steps in the flowcharts are shown sequentially as indicated by the arrows; however, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order in which these steps are performed, and they can be executed in other orders. Furthermore, as mentioned above... Figure 9 The flowchart may include at least some steps or stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0121] Example 3: Preferred Implementation Method Combining Hardware and Software

[0122] This application embodiment combines the hardware of Embodiment 1 with the software of Embodiment 2. The three-phase SEPIC converter can be equipped with complete first and second sampling circuits. The controller can default to the control strategy of Embodiment 1, directly using the second voltage signal for control, thereby ensuring control accuracy.

[0123] Simultaneously, the algorithm from Embodiment 2 is integrated as a fault-tolerant or optimized startup module. For example, when a sampling circuit fault is detected in a certain phase, the controller can automatically switch to the software algorithm control for that phase; under specific light load conditions, the controller uses the software algorithm to achieve a smoother startup; under specific light load conditions or in situations with stringent requirements for startup current ripple, the software algorithm can be actively enabled for startup to obtain a smoother startup curve. The two work together to provide the highest level of reliability and performance assurance for the system.

[0124] Figure 14 This is a schematic diagram of the hardware structure of a computer device provided in an embodiment of this application. The computer device 1400 is applied to the aforementioned three-phase SEPIC converter and may include the aforementioned... Figure 1The control unit shown and Figure 2 The controller shown. Figure 14 As shown, the computer device 1400 includes: a processor 1401, a memory 1402, a communication module 1404, and a computer program 1403 stored in the memory 1402 and executable on the processor 1401. When the processor 1401 executes the computer program 1403, it implements the aforementioned... Figure 7 and Figure 9 The execution steps are shown. For example, the computer program 1403 described above can be divided into one or more units / modules, which are stored in the memory 1402 and executed by the processor 1401 to complete this application.

[0125] The aforementioned one or more units / modules may be a series of computer program instruction segments capable of performing specific functions. These instruction segments describe the execution process of the aforementioned computer program 1403 in the aforementioned computer device 1400. For example, the aforementioned computer program 1403 may be used to execute a control method for a three-phase SEPIC converter. The specific functions or mechanisms have been described in the above embodiments and will not be repeated here.

[0126] Those skilled in the art will understand that Figure 14 This is merely an example of computer device 1400 and does not constitute a limitation on computer device 1400. It may include more or fewer components than shown, or combine certain components, or different components. For example, the computer device 1400 described above may also include input / output devices, network access devices, buses, etc.

[0127] The processor 1401 mentioned above can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0128] In some embodiments, the processor 1401 may include one or more interfaces. Interfaces may include I2C, I2S, PCM, URAT, MIPI, GPIO, OBD, and / or USB interfaces, etc. It is understood that the interface connection relationships between the modules illustrated in the embodiments of this application are merely illustrative and do not constitute a structural limitation on the computer device 1400. In other embodiments of this application, the computer device 1400 may also employ different interface connection methods or combinations of multiple interface connection methods as described in the above embodiments.

[0129] In some embodiments, the computer device 1400 can connect internal devices and modules through one or more interfaces. The memory 1402 described above can be an internal storage unit of the computer device 1400, such as a hard disk or RAM. The memory 1402 may also include both internal storage units and external storage devices. The memory 1402 is used to store the computer program and other programs and data required by the computer device 1400. The memory 1402 can also be used to temporarily store data that has been output or will be output.

[0130] Communication module 1404 can provide solutions for wireless communication applications on computer device 1400, including Wireless Local Area Network (WLAN), Bluetooth (BT), Global Navigation Satellite System (GNSS), Frequency Modulation (FM), Near Field Communication (NFC), and Infrared (IR). Communication module 1404 can be one or more devices integrating at least one communication processing module. The communication module receives electromagnetic waves via an antenna, demodulates and filters the electromagnetic wave signals, and sends the processed signals to processor 1401. Communication module 1404 can also receive signals to be transmitted from processor 1401, frequency modulate and amplify them, and then convert them into electromagnetic waves for radiation via the antenna.

[0131] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the above equipment can be divided into different functional units or modules to complete all or part of the functions described above.

[0132] The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of software functional units.

[0133] In the embodiments of this application, the specific names of each functional unit and module are only for easy distinction and are not intended to limit the scope of protection of this application. It should be understood that each step in the above-described method embodiments provided in this application can be completed by the integrated logic circuits in the processor hardware or by instructions in software form. The method steps disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or being executed by a combination of hardware and software modules in the processor.

[0134] This application also provides a computer program product comprising: a computer program (also referred to as code or instructions) that, when run, causes a computer to execute the control method of the three-phase SEPIC converter described in the above embodiments.

[0135] The various embodiments of this application can be combined arbitrarily to achieve different technical effects.

[0136] In the embodiments provided in this application, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, in whole or in part, in the form of a computer program product.

[0137] The computer program product includes one or more computer instructions. When these computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0138] This application also provides a computer-readable storage medium storing a computer program (also referred to as code or instructions). When the computer program is run, it causes the computer to perform the method executed by the computer device in any of the foregoing embodiments.

[0139] Figure 15 This is a schematic diagram of a computer-readable storage medium provided in an embodiment of this application. For example... Figure 15 As shown, the computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0140] The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., Digital Universal Optical Discs, DVDs), or semiconductor media (e.g., solid-state drives, SSDs), etc.

[0141] Those skilled in the art will understand that implementing all or part of the processes in the foregoing embodiments can be accomplished by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the foregoing method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or RAM, magnetic disks, or optical disks.

[0142] In summary, the above description is merely an embodiment of the technical solution of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the disclosure of this application should be included within the scope of protection of this application.

Claims

1. A control circuit for a three-phase SEPIC converter, comprising a three-phase rectifier bridge, a power circuit, and an output sampling unit, characterized in that, include: A first sampling circuit, wherein the first input terminal of the first sampling circuit is coupled to the input side of the three-phase rectifier bridge, is used to acquire a first voltage signal; The second sampling circuit has a second input terminal coupled to the output side of the three-phase rectifier bridge to acquire the second voltage signal. The controller is electrically connected to both the first sampling circuit and the second sampling circuit; wherein the controller is configured to: Input voltage protection is performed based on the first voltage signal; During the startup phase of the three-phase SEPIC converter, a drive signal is generated based on the second voltage signal. The drive signal is used to control the switching transistor to turn on at the valley of its on-voltage according to the change of the second voltage signal. After the three-phase SEPIC converter enters the steady-state operating phase, the drive signal is generated based on the second voltage signal and the feedback signal of the output sampling unit.

2. The control circuit according to claim 1, characterized in that, The second input terminal includes three independent voltage sampling branches, used to collect the voltages of the three output nodes corresponding one-to-one with the three-phase rectifier bridge.

3. The control circuit according to claim 1, characterized in that, The controller includes an overvoltage protection module and a pulse width modulation module; the input terminal of the overvoltage protection module is connected to the first output terminal of the first sampling circuit; the input terminal of the pulse width modulation module is connected to the second output terminal of the second sampling circuit and receives the feedback signal.

4. A control method for a three-phase SEPIC converter, characterized in that, The control circuit applied to any one of claims 1 to 3 includes: Acquire synchronization information of a first voltage signal, the synchronization information including the fundamental frequency, wherein the first voltage signal is any one phase input voltage of the three-phase input voltage; During startup, when the first voltage signal reaches its peak voltage, the corresponding switching transistor in the three-phase SEPIC converter is activated by a drive signal. During the time period from the start-up of the switch to the first zero crossing of the first voltage signal, the conduction time of the switch is dynamically adjusted based on a periodic function synchronized with the fundamental frequency. When the first voltage signal is detected to cross zero for the first time, the dynamic adjustment of the switching transistor based on the periodic function ends, and the conduction time of the switching transistor is controlled according to the closed-loop feedback.

5. The control method according to claim 4, characterized in that, The method of dynamically adjusting the on-time of the switching transistor based on a periodic function synchronized with the fundamental frequency includes: The conduction time of the switching transistor is calculated based on the periodic function, the duty cycle of the drive signal is dynamically adjusted based on the conduction time, and the conduction time of the switching transistor is controlled by the drive signal.

6. The control method according to claim 4, characterized in that, The synchronization information for acquiring the first voltage signal includes: The fundamental frequency is obtained by performing zero-crossing detection or spectrum analysis on the first voltage signal.

7. A three-phase SEPIC converter, characterized in that, It includes the control circuit as described in any one of claims 1 to 3.

8. A computer device applied to a three-phase SEPIC converter, characterized in that, It includes a processor and a memory, the memory storing a computer program that, when executed by the processor, causes the computer device to implement the control method for a three-phase SEPIC converter as described in any one of claims 4 to 6.

9. A computer-readable storage medium storing computer instructions thereon, characterized in that, When the computer instructions are executed by the processor, they implement the control method for the three-phase SEPIC converter as described in any one of claims 4 to 6.

Images