Memory device and forming method thereof

Abstract

The memory device includes: a first lower epitaxial source / drain region adjacent to a second lower epitaxial source / drain region; a first lower gate electrode adjacent a first side of the first lower epitaxial source / drain region; a second lower gate electrode adjacent a second side of the second lower epitaxial source / drain region, where the second side is opposite the first side; a dielectric layer under the first lower epitaxial source / drain region, the second lower epitaxial source / drain region, the first lower gate electrode, and the second lower gate electrode; a first docking contact within the dielectric layer, where the first docking contact electrically connects the first lower epitaxial source / drain region to the second lower gate electrode; and a second docking contact within the dielectric layer, where the second docking contact electrically connects the second lower epitaxial source / drain region to the first lower gate electrode. The embodiment of the invention also relates to a method for forming the memory device.

Description

Technical Field

[0001] Embodiments of this application relate to memory devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum part size, allowing more components to be integrated into a given area. As the semiconductor industry further moves towards increased device density, higher performance, and lower costs, challenges from manufacturing and design have led to stacked device configurations, such as stacked transistors, including complementary field-effect transistors (CFETs). While the minimum part size decreases, additional components are introduced. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a memory device, comprising: forming a memory structure on the front side of a substrate, the memory structure including a first pull-up transistor, a first pull-down transistor, a first transmission gate transistor, a second pull-up transistor, a second pull-down transistor, and a second transmission gate transistor; forming a dielectric layer over the back side of the memory structure; forming a hard mask over the dielectric layer; forming a first opening in the hard mask, wherein the first opening extends over the first pull-up transistor and the second pull-up transistor; forming a mask material in the first opening, wherein the mask material divides the first opening into a second opening and a third opening; extending the second opening and the third opening through the dielectric layer; and forming a conductive material in the second opening to form a first mating contact, and forming a conductive material in the third opening to form a second mating contact, wherein the first mating contact electrically contacts the first pull-up transistor, and the second mating contact electrically contacts the second pull-up transistor.

[0005] Other embodiments of this application provide a method for forming a memory device, comprising: depositing a dielectric layer over the back side of a memory cell; depositing a hard mask over the dielectric layer; patterning a first opening in the hard mask, wherein the first opening extends over a first epitaxial source / drain region, a second epitaxial source / drain region, a first gate electrode, and a second gate electrode of the memory cell; depositing photoresist over the hard mask and within the first opening; patterning a second opening in the photoresist, wherein the second opening extends across the first opening; depositing a mask material over the photoresist and within the second opening; removing the photoresist, wherein a region of the mask material remains within the second opening; using the regions of the hard mask and the mask material as an etching mask to etch the dielectric layer, wherein the etching forms a groove in the dielectric layer; and depositing a conductive material in the groove.

[0006] Further embodiments of this application provide a memory device, including: a first lower epitaxial source / drain region adjacent to a second lower epitaxial source / drain region; a first lower gate electrode adjacent to a first side of the first lower epitaxial source / drain region; a second lower gate electrode adjacent to a second side of the second lower epitaxial source / drain region, wherein the second side is opposite to the first side; a dielectric layer located below the first lower epitaxial source / drain region, the second lower epitaxial source / drain region, the first lower gate electrode, and the second lower gate electrode; a first mating contact located within the dielectric layer, wherein the first mating contact electrically connects the first lower epitaxial source / drain region to the second lower gate electrode; and a second mating contact located within the dielectric layer, wherein the second mating contact electrically connects the second lower epitaxial source / drain region to the first lower gate electrode. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A three-dimensional view of an exemplary complementary field-effect transistor (CFET) according to some embodiments is shown.

[0009] Figures 2 to 8 These are various views of intermediate stages in the manufacture of a CFET according to some embodiments.

[0010] Figure 9 A schematic diagram of an SRAM cell according to some embodiments is shown.

[0011] Figure 10 A three-dimensional view of an SRAM cell according to some embodiments is shown.

[0012] Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A and Figure 19B Plan and cross-sectional views of intermediate stages in the formation of mating contacts according to some embodiments are shown.

[0013] Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A and Figure 24B Plan and cross-sectional views of intermediate stages in the formation of mating contacts according to some embodiments are shown.

[0014] Figure 25A , Figure 25B , Figure 26A and Figure 26B Plan and cross-sectional views of intermediate stages in the formation of mating contacts according to some embodiments are shown. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] Complementary field-effect transistor (CFET) structures and methods for forming them are provided. According to various embodiments, CFET interconnects are used to form memory cells, such as static random-access memory (SRAM) cells. The CFETs comprise vertically stacked complementary nanostructure FETs, and the SRAM cell has four transistor overlay regions, for example, four p-type transistors and four overlay regions of above n-type transistors. Methods for forming back-side interconnects between CFETs in a memory cell are provided. The embodiments described herein can allow for improved device scaling, improved yield, improved device reliability, and improved device performance.

[0018] Figure 1 Examples of stacked transistors 10 (including FETs 10U and 10L) according to some embodiments are shown. Figure 1 It is a 3D view, and for clarity, some components of the stacked transistors have been omitted.

[0019] The stacked transistor 10 includes a plurality of vertically stacked FETs. For example, the stacked transistor may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type). When the stacked transistor is a CFET, the second device type of the upper nanostructure FET 10U is opposite to the first device type of the lower nanostructure FET 10L. The nanostructure FETs 10U and 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 serves as a channel region for the nanostructure FET. The lower semiconductor nanostructure 26L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure FET 10U. In other embodiments, the stacked transistor may also be adapted to other types of transistors (e.g., FinFETs, etc.).

[0020] A gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. Source / drain regions 62 (including a lower source / drain region 62L and an upper source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. Each of the source / drain regions 62 may refer to a source or a drain, individually or collectively, depending on the context. Isolation components (not shown) may be formed to separate the desired source / drain regions 62 and / or the desired gate electrode 80.

[0021] Figure 1 Reference cross sections used in later figures are also shown. Cross section A-A' is a vertical cross section parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistor and in the direction of current, for example, between the source / drain regions 62 of the stacked transistor. Cross section B-B' is a vertical cross section perpendicular to cross section A-A' and along the longitudinal axis of the gate electrode 80 of the CFET. Cross section C-C' is a vertical cross section parallel to cross section B-B' and extending through the source / drain regions 62 of the stacked transistor. For clarity, subsequent figures may refer to these reference cross sections.

[0022] Figures 2 to 8 Stacked transistors (such as) according to some embodiments are shown. Figure 1 The figure shows a cross-sectional view of an intermediate stage in the formation of a material (illustrated in the diagram). In the following discussion, unless otherwise stated, the figures show the material along the [missing information - likely a specific direction or path]. Figure 1 A vertical section diagram of a section similar to the vertical reference section A-A' in the diagram. Figure 2 The wafer is provided, and the wafer includes a substrate 20. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., having p-type or n-type dopants) or undoped. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, or combinations thereof.

[0023] Semiconductor strips 28 are formed extending upward from the semiconductor substrate 20. Each of the semiconductor strips 28 includes a semiconductor strip 20' (a patterned portion of the semiconductor substrate 20, also referred to as a semiconductor fin 20') and a multilayer stack 22. The stacked components of the multilayer stack 22 are referred to hereinafter as nanostructures. Specifically, the multilayer stack 22 includes pseudo-nanostructures 24A and 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. Pseudo-nanostructures 24A and 24B can also be collectively referred to as pseudo-nanostructure 24, and the lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can also be collectively referred to as semiconductor nanostructure 26.

[0024] The pseudo-nanostructure 24A is formed of a first semiconductor material, and the pseudo-nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have high etch selectivity towards each other. Therefore, in subsequent processes, the pseudo-semiconductor layer 24B can be removed at a faster rate than the pseudo-semiconductor layer 24A.

[0025] Semiconductor nanostructure 26 (including lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The third semiconductor material can be selected from candidate semiconductor materials of the substrate 20. The lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be formed of the same semiconductor material or different semiconductor materials. Furthermore, the first and second semiconductor materials of the pseudo-nanostructure 24 exhibit high etch selectivity towards the third semiconductor material of the semiconductor nanostructure 26. Therefore, the pseudo-nanostructure 24 can be selectively removed in subsequent process steps without significantly removing the semiconductor nanostructure 26. In some embodiments, the pseudo-semiconductor nanostructure 24A is formed of or includes silicon-germanium, the semiconductor layer 26 is formed of silicon, and the pseudo-semiconductor nanostructure 24B can be formed of germanium or silicon-germanium having a higher percentage of germanium atoms than semiconductor nanostructure 24A.

[0026] The lower semiconductor nanostructure 26L will provide the channel region for the lower nanostructure FET used in the CFET. The upper semiconductor nanostructure 26U will provide the channel region for the upper nanostructure FET used in the CFET. The semiconductor nanostructure 26, located directly above / below (e.g., in contact with) the pseudo-nanostructure 24B, can be used for isolation and may or may not be used as the channel region for the CFET. The pseudo-nanostructure 24B will then be replaced by an isolation structure defining the boundary between the lower and upper nanostructure FETs.

[0027] To form the semiconductor strip 28, layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material (arranged as shown and described above) can be deposited over the semiconductor substrate 20. These layers can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). A patterning process can then be applied to the layers of the first, second, and third semiconductor materials and the semiconductor substrate 20 to define the semiconductor strip 28, which includes a semiconductor strip 20', a pseudo-nanostructure 24, and a semiconductor nanostructure 26.

[0028] Semiconductor fins and nanostructures can be patterned using any suitable method. For example, the patterning process can include one or more photolithography processes, including dual patterning or multi-patterning processes. Typically, dual or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a smaller pitch than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed and patterned using a photolithography process over a substrate. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as an etch mask for the patterning process to etch layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material, as well as the semiconductor substrate 20. Etching can be performed using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic.

[0029] Similarly, Figure 2 As shown, an STI region 32 is formed above the substrate 20 and between adjacent semiconductor strips 28. The STI region 32 may include a dielectric pad and a dielectric material above the dielectric pad. Each of the dielectric pad and the dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, or a combination thereof. Forming the STI region 32 may include: depositing a dielectric layer; and performing a planarization process such as chemical mechanical polishing (CMP), mechanical polishing, etc., to remove excess portions of the dielectric material. The deposition process may include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. In some embodiments, the STI region 32 includes silicon oxide formed by an FCVD process, followed by an annealing process. The dielectric layer is then recessed to define the STI region 32. The dielectric layer may be recessed such that the upper portion of the semiconductor strip 28 (including the multilayer stack 22) protrudes above the remaining STI region 32.

[0030] After forming the STI region 32, a dummy gate stack 42 can be formed over the upper portion of the semiconductor strip 28 (the portion protruding above the STI region 32) and along the sidewalls of the upper portion of the semiconductor strip 28. Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 may be formed or include, for example, silicon oxide, silicon nitride, combinations thereof, etc., and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed over the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 may be conductive or non-conductive and may be selected from the group including amorphous silicon, polycrystalline silicon, poly-SiGe, etc. A mask layer 40, including, for example, silicon nitride, silicon oxynitride, etc., is formed over the planarized dummy gate layer 38. Next, the mask layer 40 can be patterned using photolithography and etching processes to form a mask. The mask is then used to etch and pattern the dummy gate layer 38, and possibly etch and pattern the dummy dielectric layer 36. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form the dummy gate stack 42.

[0031] exist Figure 3 In this process, a gate spacer 44 and a source / drain recess 46 are formed. First, the gate spacer 44 is formed over the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as CVD, ALD, etc.

[0032] Subsequently, source / drain recesses 46 are formed in semiconductor strip 28. The source / drain recesses 46 are formed by etching and can extend through the multilayer stack 22 and into semiconductor strip 20'. The bottom surface of the source / drain recesses 46 can be located above, below, or flush with the top surface of isolation region 32. During the etching process, gate spacers 44 and dummy gate stacks 42 mask portions of semiconductor strip 28. Etching can include a single etching process or multiple etching processes. When the source / drain recesses 46 reach the desired depth, a timing etching process can be used to stop the etching of the source / drain recesses 46.

[0033] exist Figure 4In this process, internal spacers 54 and dielectric isolation layers 56 are formed. Forming the internal spacers 54 and dielectric isolation layers 56 may include an etching process that laterally etches pseudo-nanostructures 24A and removes pseudo-nanostructures 24B. The etching process may be isotropic and may be selective for the material of pseudo-nanostructures 24, such that pseudo-nanostructures 24 are etched at a faster rate than semiconductor nanostructures 26. The etching process may also be selective for the material of pseudo-nanostructures 24B, such that pseudo-nanostructures 24B are etched at a faster rate than pseudo-nanostructures 24A. In this way, pseudo-nanostructures 24B can be completely removed from between the lower semiconductor nanostructures 26L (collectively) and the upper semiconductor nanostructures 26U (collectively), without completely removing pseudo-nanostructures 24A. In some embodiments, wherein pseudo-nanostructures 24B are formed of germanium or silicon-germanium with a high percentage of germanium atoms, pseudo-nanostructures 24A are formed of silicon-germanium with a low percentage of germanium atoms, and semiconductor nanostructures 26 are formed of germanium-free silicon, the etching process may include a dry etching process using chlorine gas, with or without plasma. Because the dummy gate stack 42 wraps around the sidewalls of the semiconductor nanostructure 26 (see...) Figure 2 Therefore, the dummy gate stack 42 can support the upper semiconductor nanostructure 26U, preventing it from collapsing when the dummy nanostructure 24B is removed. Furthermore, although the sidewalls of the dummy nanostructure 24A are shown as straight after etching, the sidewalls can be concave or convex.

[0034] An internal spacer 54 is formed on the sidewall of the recessed pseudo-nanostructure 24A, and a dielectric isolation layer 56 is formed between the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L). As will be described in more detail later, a source / drain region will subsequently be formed in the source / drain recess 46, and the pseudo-nanostructure 24A will be replaced with a corresponding gate structure. The internal spacer 54 serves as an isolation member between the subsequently formed source / drain region and the subsequently formed gate structure. Furthermore, the internal spacer 54 can be used to prevent damage to the subsequently formed source / drain region by subsequent etching processes (such as etching processes for forming the gate structure). On the other hand, the dielectric isolation layer 56 is used to isolate the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L). In addition, the intermediate semiconductor nanostructure (the semiconductor nanostructure 26 in contact with the dielectric isolation layer 56) and the dielectric isolation layer 56 can define the boundary between the lower nanostructure FET and the upper nanostructure FET.

[0035] The internal spacer 54 and dielectric isolation layer 56 can be formed by conformally depositing an insulating material in the source / drain trench 46, on the sidewalls of the pseudo-nanostructure 24, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, and then etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon oxycarbonate, silicon oxycarbonate, silicon oxynitride, etc. Other low dielectric constant (low k) materials with a k value of less than about 3.5 can be used. The insulating material can be formed by deposition processes such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. The insulating material (when etched) has a portion retained in the sidewalls of the pseudo-nanostructure 24A (thus forming the internal spacer 54) and a portion retained between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L (thus forming the dielectric isolation layer 56).

[0036] Similarly, Figure 4 As shown, a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U are formed. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain recess 46. The lower epitaxial source / drain region 62L is in contact with the lower semiconductor nanostructure 26L, but not with the upper semiconductor nanostructure 26U. An internal spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the pseudo-nanostructure 24A, which will be replaced with a replacement gate in a subsequent process.

[0037] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus or arsenic. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon-germanium doped with p-type dopants such as boron or indium. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopants. During the epitaxy of the lower epitaxial source / drain region 62L, the exposed surfaces (e.g., sidewalls) of the upper semiconductor nanostructure 26U may be masked to prevent undesirable epitaxial growth on the upper semiconductor nanostructure 26U. After growing the lower epitaxial source / drain region 62L, the mask on the upper semiconductor nanostructure 26U can then be removed.

[0038] Due to the epitaxial process used to form the lower epitaxial source / drain regions 62L, the upper surface of the lower epitaxial source / drain regions 62L has small planes that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these small planes cause adjacent lower epitaxial source / drain regions 62L of the same FET to merge.

[0039] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed above the lower epitaxial source / drain region 62L. The first CESL 66 can be formed from a dielectric material with high etch selectivity relative to the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed from a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0040] The formation process may include: depositing a conformal CESL layer; depositing material for the first ILD 68; and a subsequent planarization process and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the first CESL 66 unetched. An anisotropic etching process is then performed to remove the portion of the first CESL 66 above the recessed first ILD 68. After recessing, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0041] Then, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U can be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. The material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials used to form the lower source / drain region 62L, depending on the desired conductivity type of the upper epitaxial source / drain region 62U. In embodiments where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be doped in opposite directions to the lower epitaxial source / drain region 62L. Alternatively, the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L can have the same conductivity type. The upper epitaxial source / drain region 62U may be doped in situ with n-type or p-type dopants and / or may be implanted with n-type or p-type dopants. Adjacent upper source / drain regions 62U may remain separated after the epitaxial process, or they may be merged.

[0042] After forming the epitaxial source / drain region 62U, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods can be similar to those of the first CESL 66 and the first ILD 68, respectively, and will not be discussed in detail herein. The formation process may include: depositing layers for CESL 70 and ILD 72; and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the mask 86 (if present) or dummy gate 84 are substantially coplanar (within process variations). Therefore, the top surface of the mask 40 (if present) or dummy gate 38 is exposed through the second ILD 72. In the illustrated embodiment, the mask 40 is retained after the removal process. In other embodiments, the mask 40 is removed, thereby exposing the top surface of the dummy gate 38 through the second ILD 72.

[0043] Figure 5A replacement gate process is illustrated, in which a gate structure 90 replaces the dummy gate stack 42 and the dummy nanostructure 24A. The replacement gate process includes first removing the remaining portions of the dummy gate stack 42 and the dummy nanostructure 24A. The dummy gate stack 42 is removed in one or more etching processes, thereby defining a trench between the gate spacers 44 and exposing the upper portion of the semiconductor strip 28. The remaining portions of the dummy nanostructure 24A are then removed by etching, such that the trench extends between the semiconductor nanostructures 26. In the etching process, the dummy nanostructure 24A is etched at a rate faster than that of the semiconductor nanostructure 26, the dielectric isolation layer 56, and the internal spacers 54. The etching can be isotropic. For example, when the dummy nanostructure 24A is formed of silicon germanium and the semiconductor nanostructure 26 is formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0044] Then, a gate dielectric 78 is deposited in the recesses between the gate spacers 44 and on the exposed semiconductor nanostructure 26. The gate dielectric 78 is conformally formed on the exposed surface of the recesses (removed gate stack 42 and pseudo nanostructure 24A) including the semiconductor nanostructure 26 and the gate spacers 44. In some embodiments, the gate dielectric 78 encapsulates all (e.g., four) sides of the semiconductor nanostructure 26. Specifically, the gate dielectric 78 may be formed on the top surface of the semiconductor strip 20'; the top, sidewalls, and bottom surfaces of the semiconductor nanostructure 26; and the sidewalls of the gate spacers 44. The gate dielectric 78 may include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. The gate dielectric 78 may include high dielectric constant (high k) materials having a k value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric 78 may include molecular beam deposition (MBD), ALD, PECVD, etc., followed by a planarization process (e.g., CMP) to remove the portion of the gate dielectric 78 located above the second ILD 72. Although a single-layer gate dielectric 78 is shown, the gate dielectric 78 may include multiple layers, such as an interface layer and an upper high-k dielectric layer.

[0045] A lower gate electrode 80L is formed on a gate dielectric 78 surrounding the lower semiconductor nanostructure 26L. For example, the lower gate electrode 80L encapsulates the lower semiconductor nanostructure 26L. The lower gate electrode 80L can be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multilayers thereof. Although a single-layer gate electrode is shown, the lower gate electrode 80L may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0046] The lower gate electrode 80L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 80L may include one or more work function adjustment layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 80L includes an n-type work function adjustment layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the lower gate electrode 80L includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, etc. Additionally or optionally, the lower gate electrode 80L may include a dipole inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0047] The lower gate electrode 80L can be formed by: conformally depositing one or more gate electrode layers; or by recessing the gate electrode layers. Any acceptable etching process, such as dry etching, wet etching, or combinations thereof, can be performed to recess the gate electrode layers. The etching can be isotropic. Etching the lower gate electrode 80L can expose the upper semiconductor nanostructure 26U.

[0048] In some embodiments, an isolation layer (not explicitly shown) may optionally be formed on the lower gate electrode 80L. The isolation layer serves as an isolation component between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer may be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc.) and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

[0049] Then, an upper gate electrode 80U is formed on the isolation layer (if present) or lower gate electrode 80L described above. The upper gate electrode 80U is disposed between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U encapsulates the upper semiconductor nanostructures 26U. The upper gate electrode 80U may be formed from the same candidate materials and candidate processes used to form the lower gate electrode 80L. The upper gate electrode 80U is formed from a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 80U may include one or more work function adjustment layers (e.g., n-type work function adjustment layers and / or p-type work function adjustment layers) formed from a material suitable for the device type of the upper nanostructure FET. Although a single-layer gate electrode 80U is shown, the upper gate electrode 80U may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0050] Furthermore, a removal process is performed to make the top surfaces of the upper gate electrode 80U and the second ILD 72 flush. The removal process used to form the gate dielectric 78 can be the same as the removal process used to form the upper gate electrode 80U. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, and combinations thereof can be utilized. After the planarization process, the top surfaces of the upper gate electrode 80U, the gate dielectric 78, the second ILD 72, and the gate spacer 44 are substantially coplanar (within process variations). Each corresponding pair of gate dielectric 78 and gate electrode 80 (including the upper gate electrode 80U and / or the lower gate electrode 80L) can be collectively referred to as a “gate stack” 90 or a “gate structure” 90 (including the upper gate structure 90U and the lower gate structure 90L). Each gate structure 90 extends along three sides (e.g., the top surface, sidewalls, and bottom surface) of the channel region of the semiconductor nanostructure 26 (see Figure 1 The lower gate structure 90L may also extend along the sidewall and / or top surface of the semiconductor strip 20'.

[0051] Similarly, Figure 5 As shown, a gate mask 92 is formed over a gate stack 42. The formation process may include: recessing the gate stack 90; filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, etc.; and performing a planarization process to remove excess portions of the dielectric material located over the second ILD 72.

[0052] exist Figure 6 In the second ILD 72, a metal-semiconductor alloy region 94 and an upper source / drain contact 96U are formed to electrically couple to an upper epitaxial source / drain region 62U. As an example of forming the upper source / drain contact 96U, an opening is formed through the second ILD 72 and the second CESL 70 using acceptable photolithography and etching techniques. A pad (not shown separately), such as a diffusion barrier layer or an adhesive layer, and a conductive material are formed in the opening. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A removal process may be implemented to remove excess material from the top surface of the gate spacer 44 and the second ILD 72. The remaining pad and conductive material form the upper source / drain contact 96U in the opening. In some embodiments, planarization processes such as CMP, etch-back processes, and combinations thereof are utilized. After the planarization process, the top surfaces of the gate spacer 44, the second ILD 72, and the upper source / drain contact 96U are substantially coplanar (within the process variation).

[0053] Optionally, a metal-semiconductor alloy region 94 is formed at the interface between the source / drain region 62 and the upper source / drain contact 96U. The metal-semiconductor alloy region 94 can be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon-germanide region formed from both metal silicides and metal germanides. The metal-semiconductor alloy region 94 can be formed prior to the material of the upper source / drain contact 96U by depositing metal in the opening for the upper source / drain contact 96U and then performing a thermal annealing process. The metal can be any metal capable of reacting with semiconductor materials (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. Metals can be deposited using deposition processes such as ALD, CVD, PVD, etc. Following the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from openings used for the upper source / drain contacts 96U (such as from the surface of the metal-semiconductor alloy region 94). The material for the upper source / drain contacts 96U can then be formed on the metal-semiconductor alloy region 94.

[0054] Then, ESL 104 and third ILD 106 are formed. In some embodiments, ESL 104 may include a dielectric material with high etch selectivity relative to the etching of third ILD 106, such as aluminum oxide, aluminum nitride, silicon nitride, silicon oxynitride, silicon oxycarbide, etc. The third ILD 106 can be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method, such as CVD, PECVD, etc.

[0055] Subsequently, an upper gate contact 108 and an upper source / drain via 110 are formed to contact the upper gate electrode 80U and the upper source / drain contact 96U, respectively. As an example of forming the upper gate contact 108 and the upper source / drain via 110, openings for the upper gate contact 108 and the upper source / drain via 110 are formed through the third ILD 106 and ESL 104. The openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately), such as diffusion barrier layers and adhesive layers, as well as conductive material, are formed in the openings. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be implemented to remove excess material from the top surface of the third ILD 106. The remaining padding and conductive material form the upper gate contact 108 and the upper source / drain via 110 in the opening. The upper gate contact 108 and the upper source / drain via 110 can be formed in different processes or in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the upper gate contact 108 and the upper source / drain via 110 can be formed in a different cross-section, which avoids short circuits in the contacts. In some instances, the resulting structure can be considered a memory device, memory structure, etc., and can be referred to as device layer 112. Additional processing is applied to device layer 112, which is described below.

[0056] Still referencing Figure 6 A front interconnect structure 114 is formed on device layer 112. The front interconnect structure 114 includes a dielectric layer 116 and a layer of conductive components 118 within the dielectric layer 116. Dielectric layer 116 may include a low-k dielectric layer formed of a low-k dielectric material. Dielectric layer 116 may also include a passivation layer formed of a non-low-k and dense dielectric material above the low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, or combinations thereof. Dielectric layer 116 may also include a polymer layer. Conductive components 118 may include wires and vias that can be formed using a damascene process. Conductive components 118 may include metal wires and metal vias, which include diffusion barriers and copper-containing material above the diffusion barriers. Aluminum pads electrically connected to the metal wires and vias may also be present above the metal wires and vias.

[0057] exist Figure 7In some embodiments, a lower source / drain contact 96L is formed to be electrically coupled to a lower epitaxial source / drain region 62L. In some embodiments, the semiconductor strip 20' may optionally be removed and replaced with a dielectric region 176. Replacing the semiconductor strip 20' with the dielectric region 176 can help reduce the parasitic capacitance and / or leakage current of the resulting nanostructured FET, thereby improving its performance. The dielectric region 176 may be formed from a low-k dielectric material, a high-k dielectric material, a combination thereof, etc., and may be formed by thermal oxidation processes, deposition processes, etc. In some embodiments, the dielectric region 176 is formed using techniques and materials similar to those previously described with respect to the first ILD 68. Other formation techniques or materials are also possible.

[0058] As an example of forming dielectric region 176, semiconductor strip 20' is removed to form a groove. Semiconductor strip 20' can be removed using acceptable photolithography and etching techniques, such as using an etching process selectively applied to semiconductor strip 20' (e.g., etching the material of semiconductor strip 20' at a rate faster than that of the material in STI region 32). One or more dielectric materials can then be formed in the groove. The dielectric material can be conformally formed in the groove and on the back side of STI region 32. In some embodiments, the dielectric material comprises a silicon nitride pad layer and a silicon oxide filler layer. After depositing the dielectric material, a removal process is applied to remove excess dielectric material above STI region 32. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, and combinations thereof can be utilized. The dielectric material (when planarized) has a portion remaining in the groove (thus forming dielectric region 176). After the planarization process, the bottom surfaces of STI region 32 and dielectric region 176 can be substantially coplanar (within process variations).

[0059] Next, a lower source / drain contact 96L for the source / drain region 62 is formed. The lower source / drain contact 96L can be physically and electrically coupled to the lower epitaxial source / drain region 62L. As an example of forming the lower source / drain contact 96L, an opening for the lower source / drain contact 96L is formed through the dielectric region 176. The opening can be formed using acceptable photolithography and etching techniques. In some embodiments, the opening is formed by a self-aligned contact (SAC) process. A pad (not shown separately) such as a diffusion barrier layer, an adhesive layer, etc., and a conductive material are formed in the opening. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may include cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A removal process can be performed to remove excess material from the bottom surface of the dielectric region 176. The remaining pad and conductive material form the lower source / drain contact 96L in the opening. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etching back processes, and combinations thereof are utilized. After the planarization process, the bottom surfaces of the dielectric region 176 and the lower source / drain contact 96L can be substantially coplanar (within process variations). Optionally, a metal-semiconductor alloy region 190 is formed at the interface between the lower epitaxial source / drain region 62L and the lower source / drain contact 96L. The metal-semiconductor alloy region 190 can be similar to the previously described metal-semiconductor alloy region 94 and can be formed using similar techniques.

[0060] Optionally, a contact spacer 177 is formed around the lower source / drain contact 96L. The contact spacer 177 can be formed by conformally depositing one or more dielectric materials in the contact openings for the lower source / drain contact 62L and subsequently etching the dielectric material. Acceptable dielectric materials may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), etc. Other insulating materials formed by any acceptable process can be used. Any acceptable etching process, such as dry etching, wet etching, etc., or combinations thereof, can be performed to pattern the dielectric material. The etching can be anisotropic. The dielectric material (when etched) has a portion remaining on the sidewalls of the dielectric region 176 (thus forming the contact spacer 177).

[0061] In the illustrated embodiment, the lower source / drain contact 96L is coupled to the lower epitaxial source / drain region 62L. In some embodiments, some of the lower source / drain contacts 96L are shared source / drain contacts coupled to the lower epitaxial source / drain region 62L and the upper epitaxial source / drain region 62U.

[0062] Still referencing Figure 7 A fourth ILD 194 is deposited over the dielectric region 176, the lower source / drain contact 96L, and the contact spacer 177. In some embodiments, the fourth ILD 194 is a flowable film formed by a flowable CVD method, followed by curing of the flowable film. In some embodiments, the fourth ILD 194 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method, such as CVD, PECVD, etc. Other materials are also possible.

[0063] In some embodiments, an ESL 192 is formed between the fourth ILD 194 and the dielectric region 176, the lower source / drain contact 96L, and the contact spacer 177. The ESL 192 may comprise a dielectric material with high etch selectivity to the dielectric material of the fourth ILD 194, such as silicon nitride, silicon oxide, silicon oxynitride, etc. Other materials are also possible.

[0064] exist Figure 8 In this structure, a lower gate contact 210, a lower source / drain via 208, and a mating contact 212 are formed through the fourth ILD 194 to contact the lower gate electrode 80L and / or the lower source / drain contact 96L. The lower gate contact 210 extends through the fourth ILD 194, ESL 192, and gate dielectric 78 to physically and electrically couple to the lower gate electrode 80L. The lower source / drain via 208 extends through the fourth ILD 194 and ESL 192 to physically and electrically couple to the lower source / drain contact 96L. The mating contact 212 physically and electrically couples the lower gate electrode 80L and the lower source / drain contact 96L. For example, the mating contact 212 may include a via portion similar to the physical and electrical contact of the lower gate contact 210 (lower gate electrode 80L), a via portion similar to the physical and electrical contact of the lower source / drain contact 96L (lower source / drain via 208), and line portions extending between the via portions. Figure 8 As shown, the line portion can be located within the fourth ILD 194 and can extend along ESL 192. Although Figure 8 The exemplary mating contact 212 shown electrically couples the lower gate electrode 80L to the adjacent lower source / drain contact 96L. However, in other embodiments, the mating contact 212 can electrically couple any lower gate electrode 80L to any lower source / drain contact 96L by appropriately configuring the path or size of the line portion of the mating contact 212. Although shown as being formed in the same cross-section, it should be understood that each of the gate contact 210, the source / drain via 208, and the mating contact 212 can be formed in different cross-sections.

[0065] As an example of forming the lower gate contact 210 and the lower source / drain via 208, an opening for the lower gate contact 210 is formed through the fourth ILD 194, ESL 192, gate dielectric 78, and dielectric region 176, and an opening for the lower source / drain via 208 is formed through the fourth ILD 194 and ESL 192. The openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately), such as diffusion barrier layers and adhesive layers, as well as conductive material, are formed within the openings. Pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. Conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be implemented to remove excess material from the bottom surface of the fourth ILD 194. The remaining pads and conductive material form the lower gate contact 210 and the lower source / drain via 208 within the openings.

[0066] The lower gate contact 210 and the lower source / drain via 208 can be formed in different processes or in the same process. In some embodiments, the mating contact 212 can be formed in a different process than the lower gate contact 210 and / or the lower source / drain via 208. In other embodiments, the formation of the lower gate contact 210, the lower source / drain via 208, and / or the mating contact 212 can share one or more process steps, such as photolithography, etching, deposition, or other steps. Some embodiments of the formation of the mating contact 212 are described in more detail below. Figure 8 As shown, device layer 112 includes an upper device 112U and a lower device 112L. The upper device 112U includes, for example, an upper semiconductor nanostructure 26U, an upper gate structure 90U, and an upper epitaxial source / drain region 62U (e.g., an upper nanostructure FET), and includes an upper gate contact 108 and an upper source / drain via 110. The lower device 112L includes, for example, a lower semiconductor nanostructure 26L, a lower gate structure 90L, and a lower epitaxial source / drain region 62L (e.g., a lower nanostructure FET), and includes a lower gate contact 210, a lower source / drain via 208, and a mating contact 212.

[0067] According to some embodiments, a back-side interconnect structure 200 is formed on the back side of device layer 112. The back-side interconnect structure 200 includes a dielectric layer 202 and a layer of conductive components 204 within the dielectric layer 202. The dielectric layer 202 may be formed of a dielectric material such as PSG, BSG, BPSG, USG, silicon oxide, silicon nitride, or combinations thereof. The dielectric layer 202 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 202 may also include a polymer layer. The dielectric layer 202 may be formed using suitable techniques such as FCVD, CVD, PECVD, ALD, etc. The conductive components 204 may include wires and vias that can be formed using a damascene process. The conductive components 204 may include metal wires and metal vias, including diffusion barriers and copper-containing material above the diffusion barriers. Aluminum pads electrically connected to the metal wires and vias may also be present above the metal wires and vias.

[0068] As for what followed Figure 9 and Figure 10 As described, stacked transistors (e.g., CFETs) can be interconnected to form SRAM cells. The SRAM cell includes two cross-coupled inverters. According to various embodiments, in the SRAM cell, a mating contact 212 is formed that couples the lower gate electrode 80 of a lower nanostructured FET to a corresponding lower source / drain contact 96L of another lower nanostructured FET. In this way, in some instances, the mating contact 212 can be considered a “cross-coupled contact.” The output of an inverter (e.g., the lower epitaxial source / drain region 62L) can be connected to the input of another inverter (e.g., the lower gate electrode 80L) using the mating contact 212. Therefore, stacked transistors can be interconnected to form SRAM cells. Forming SRAM cells from CFETs can increase memory density due to the vertically stacked nanostructured FETs. Cross-coupling the inverters to the mating contact 212 allows the CFETs to interconnect at the lower interconnect level, thereby improving device density. The following discussion focuses on… Figures 11A to 19B , Figures 20A to 24B and Figures 25A to 26B An exemplary embodiment for forming a mating contact is described.

[0069] Figure 9 A schematic diagram of an SRAM cell 220 according to some embodiments is shown. Figure 9SRAM cell 220 is a six-transistor SRAM cell. SRAM cell 220 includes a first inverter INV1 and a second inverter INV2 cross-coupled to each other via mating contacts 212. For example, the first mating contact 212 connects the output of the first inverter INV1 to the input of the second inverter INV2, and the second mating contact 212 connects the output of the second inverter INV2 to the input of the first inverter INV1. The first inverter INV1 includes a first pull-up transistor PUA and a first pull-down transistor PDA. The second inverter INV2 includes a second pull-up transistor PUB and a second pull-down transistor PDB. Each of the first pull-up transistor PUA and the second pull-up transistor PUB is coupled to a supply voltage VDD, while each of the first pull-down transistor PDA and the second pull-down transistor PDB is coupled to a reference voltage VSS. SRAM cell 220 also includes a first transmission gate transistor PGA and a second transmission gate transistor PGB. The first transmission gate transistor PGA controls whether the output of the first inverter INV1 is coupled to the bit line BL, and the second transmission gate transistor PGB controls whether the output of the second inverter INV2 is coupled to the complementary bit line BLB. The first transmission gate transistor PGA and the second transmission gate transistor PGB are also coupled to the word line WL and controlled by the word line WL.

[0070] In some embodiments, SRAM cell 220 includes four n-type transistors and two p-type transistors, which can be formed as an n-type nanostructure FET and a p-type nanostructure FET of a CFET. In this way, the CFET for SRAM cell 220 has a coverage area for four transistors, for example, a coverage area for four n-type transistors and four p-type transistors. However, only two p-type transistors are used in SRAM cell 220, and two of the p-type transistors are unused. The lower epitaxial source / drain region can be omitted from the source / drain groove of the unused p-type region. In some instances, the unused p-type transistors can be considered "dummy transistors". In some embodiments, the first pull-down transistor PDA and the second pull-down transistor PDB are n-type nanostructure FETs, and the first pull-up transistor PUA and the second pull-up transistor PUB are p-type nanostructure FETs. In some embodiments, the first transmission gate transistor PGA and the second transmission gate transistor PGB are n-type nanostructure FETs.

[0071] Figure 10 This is a three-dimensional view of an SRAM cell 222 including a CFET according to some embodiments. The SRAM cell 222 can be similar to that used for... Figure 9 The SRAM cell 220 is described, and the CFET can be similar to that used for... Figure 8The stacked transistors are described. For clarity, some components have been omitted. For example, some epitaxial source / drain regions, gate contacts, source / drain vias, and conductive components are not shown. Figure 10 The structure is flipped upside down relative to the previous figures to show the mating contact 212 more clearly. For example, in Figure 10 In the diagram, the lower device 112L is shown above the upper device 112U. It should be understood that the SRAM cell 222 may also have a similar structure that is mirrored in the horizontal direction.

[0072] exist Figure 10 In the illustrated embodiment, the lower nanostructure FET of the CFET (e.g., in the lower device 112L) is a p-type device, and the upper nanostructure FET of the CFET (e.g., in the upper device 112U) is an n-type device. Therefore, the lower nanostructure FET includes a first pull-up transistor PUA and a second pull-up transistor PUB, while the upper nanostructure FET includes a first pull-down transistor PDA, a second pull-down transistor PDB, a first transmission gate transistor PGA, and a second transmission gate transistor PGB. Furthermore, the first pull-down transistor PDA and the second pull-down transistor PDB are vertically stacked above the first pull-up transistor PUA and the second pull-up transistor PUB, respectively. Therefore, the source / drain regions of the first pull-down transistor PDA and the first pull-up transistor PUA are formed in the same source / drain recess, and the source / drain regions of the second pull-down transistor PDB and the second pull-up transistor PUB are formed in the same source / drain recess.

[0073] The first pull-down transistor PDA includes a first upper source / drain region 62U-1, a second upper source / drain region 62U-2, and a first upper gate electrode 80U-1. The second pull-down transistor PDB includes a third upper source / drain region 62U-3, a fourth upper source / drain region 62U-4, and a second upper gate electrode 80U-2. The first pull-up transistor PUA includes a first lower source / drain region 62L-1, a second lower source / drain region 62L-2, and a first lower gate electrode 80L-1. The second pull-up transistor PUB includes a third lower source / drain region 62L-3, a fourth lower source / drain region 62L-4, and a second lower gate electrode 80L-2. The first transmission gate transistor PGA includes a second upper source / drain region 62U-2, a fifth upper source / drain region 62U-5, and a third upper gate electrode 80U-3. The second transmission gate transistor (PGB) includes a fourth upper source / drain region 62U-4, a sixth upper source / drain region 62U-6, and a fourth upper gate electrode 80U-4. Some of these components are... Figure 10 It was not visible in the middle, but in the subsequent targeting Figures 11A to 19AAs can be seen in the described plan view (e.g., top view). In the plan view, the first pull-down transistor PDA is diagonally opposite to the second pull-down transistor PDB, the first pull-up transistor PUA is diagonally opposite to the second pull-up transistor PUB, and the first transmission gate transistor PGA is diagonally opposite to the second transmission gate transistor PGB.

[0074] Furthermore, the first upper gate electrode 80U-1 of the first pull-down transistor PDA is physically and electrically coupled to the first lower gate electrode 80L-1 of the first pull-up transistor PUA, and the second upper gate electrode 80U-2 of the second pull-down transistor PDB is physically and electrically coupled to the second lower gate electrode 80L-2 of the second pull-up transistor PUB. The first transmission gate transistor PGA and the second transmission gate transistor PBB are vertically stacked above the unused p-type region. Additionally, the third upper gate electrode 80U-3 of the first transmission gate transistor PGA is physically and electrically coupled to the third lower gate electrode 80L-3, and the fourth upper gate electrode 80U-4 of the second transmission gate transistor PGB is physically and electrically coupled to the fourth lower gate electrode 80L-4. The source / drain contact 96L is coupled to the second lower source / drain region 62L-2 and the second upper source / drain region 62U-2, and the source / drain contact 96L is coupled to the fourth lower source / drain region 62L-4 and the fourth upper source / drain region 62U-4. Adjacent upper gate electrodes 80U and adjacent lower gate electrodes 80L can be physically and electrically isolated by a gate isolation region 136, which may include, for example, a dielectric region or an insulating region. In this way, the gate isolation region 136 can "cut" the gate structure.

[0075] The mating contact 212 is coupled to the corresponding lower gate electrode 80L and to the lower source / drain contact 96L. Figure 10 Each mating contact 212 shown is L-shaped in the top view, with one end of the L-shaped contact coupled to the lower gate electrode 80L through a through-hole portion 212V, and the other end of the L-shaped contact coupled to the lower source / drain contact 96L through the through-hole portion 212V. In other embodiments, the mating contact 212 may have other shapes or sizes. Similar to Figure 8 The mating contact 212 shown has a via portion 212V extending through ESL 192 to form physical and electrical contacts to the lower gate electrode 80L and the lower source / drain contact 96L. The via portion 212V can extend to different depths. Line portions (not separately labeled) extend between the via portions 212V. The line portions can extend across the gate isolation region 136. In some embodiments, each SRAM cell 222 has two mating contacts 212.

[0076] Figures 11A to 19BIntermediate steps in the formation of the mating contact 212 according to some embodiments are shown. Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A and Figure 19A It shows an orientation similar to Figure 7 The diagram shows a plan view of the back side of the structure. Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B and Figure 19B A cross-sectional view is shown along a section similar to section D-D' shown in the attached figure. Figures 11B to 19B The cross-sectional view relative to Figure 7 Flip vertically. For example, Figure 11B The fourth ILD 194 is shown above ESL 192. Figures 11B to 19B The cross-sectional view does not show the various layers and components that may be located below ESL 192.

[0077] Figures 11A to 19B The process shown includes intermediate steps in the formation of two adjacent SRAM cells 222A and 222B. The regions forming SRAM cells 222A and 222B are designated as SRAM regions 222A' and 222B', respectively. In other words, each SRAM cell 222 is formed within a corresponding SRAM region 222'. For reference, the lower gate electrode 80L and the lower epitaxial source / drain region 62L of SRAM cells 222A-222B are indicated by dashed outlines. The lower gate electrodes 80L-1, 80L-2, 80L-3, and 80L-4, and the lower epitaxial source / drain regions 62L-1, 62L-2, 62L-3, and 62L-4 can be similarly designed for… Figure 10 Those described for a single SRAM cell 222. In some embodiments, the techniques described herein allow mating contacts 212 to be formed across a gate electrode having a spacing width W1 in the range of about 30 nm to about 60 nm, but other widths are also possible. Figures 11A to 19B The structures shown are for illustrative purposes, and other configurations, arrangements, component dimensions, or component shapes are also possible. For clarity, some components or parts are not shown.

[0078] exist Figures 12A to 12BIn some embodiments, a sacrificial layer 224, a hard mask 226, and a photoresist 228 are formed over the fourth ILD 194. The sacrificial layer 224 may be formed of a dielectric material different from that of the fourth ILD 194. For example, the sacrificial layer 224 may be formed of a material with high etch selectivity relative to the etching of the fourth ILD 194, such as alumina, aluminum nitride, silicon nitride, silicon oxynitride, silicon oxycarbide, etc. The sacrificial layer 224 may include other materials, such as polymers. The sacrificial layer 224 can be formed using any suitable deposition process, such as CVD, ALD, etc. Other materials or deposition techniques are also possible. In some embodiments, the sacrificial layer 224 may be a bottom antireflective coating (BARC) layer, an etch stop layer, etc. In other embodiments, the sacrificial layer 224 is not formed. The hard mask 226 is formed over the sacrificial layer 224. The hard mask 226 can be formed of a different dielectric material than the sacrificial layer 224, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by any suitable deposition process, such as CVD, ALD, etc. Other materials or deposition techniques are also possible.

[0079] According to some embodiments, photoresist 228 is formed and patterned over a hard mask 226 to form openings 229 exposing the hard mask 226. The photoresist 228 can be formed using suitable techniques, such as spin coating. The openings 229 can be patterned in the photoresist 228 using suitable photolithography techniques. The openings 229 then define mating contacts 212. Some openings 229A extend over the lower gate electrode 80L-2 and the lower epitaxial source / drain region 62L-2 of the SRAM region 222', and some openings 229B extend over the lower gate electrode 80L-1 and the lower epitaxial source / drain region 62L-4 of the SRAM region 222'. Figure 12A As shown, each opening 229 extends across a portion of two adjacent SRAM regions 222'. For example, some openings 229A may extend over and between the lower gate electrodes 80L-2 of adjacent SRAM regions 222', and over and between the lower epitaxial source / drain regions 62L-2 of the same adjacent SRAM regions 222'. Other openings 229B may extend over and between the lower gate electrodes 80L-1 of adjacent SRAM regions 222', and over and between the lower epitaxial source / drain regions 62L-4 of the same adjacent SRAM regions 222'. In some embodiments, openings 229A and 229B are separated. In some embodiments, each opening 229 has a "top hat" shape, but openings 229 may have a trapezoidal shape or other suitable shape. Forming top hat-shaped openings 229 instead of L-shaped openings 229 allows for more reliable lithographic patterning, smaller part sizes, and improved yield.

[0080] exist Figures 13A to 13B In some embodiments, an etching process is performed to extend the opening 229 through the hard mask 226. The etching process may include a suitable wet etching process and / or a suitable dry etching process. The etching process may be anisotropic. After the etching process is performed, the opening 229 is transferred to the hard mask 226, and the sacrificial layer 224 is exposed by the opening 229. In this way, the etching process uses patterned photoresist 228 as an etching mask. In some embodiments, after etching the hard mask 226, the photoresist 228 is removed using a suitable etching or ashing process.

[0081] exist Figures 14A to 14B In some embodiments, photoresist 230 is formed and patterned over a hard mask 226 and a sacrificial layer 224 to form openings 231 exposing the sacrificial layer 224. The photoresist 230 can be formed using suitable techniques, such as spin coating. Openings 231 can be patterned in the photoresist 230 using suitable photolithography techniques. In some embodiments, each opening 231 is located within the perimeter of a corresponding opening 229. Therefore, some portions of the sacrificial layer 224 within the opening 229 are covered by the photoresist 230, and some portions of the sacrificial layer 224 within the opening 229 are exposed by the opening 231. Each opening 231 defines a separation between opposing regions of a corresponding opening 229, wherein an L-shaped portion of the opening 229 is located on either side of the opening 231. In other embodiments, the portions of the opening 229 located on either side of the opening 231 are formed to have other shapes. In some embodiments, openings 231 are formed between adjacent SRAM regions 222'. For example, opening 231 can be formed between adjacent lower gate electrodes 80L-2 and adjacent lower gate electrodes 80L-3 of opening 229A, and opening 231 can be formed between adjacent lower gate electrodes 80L-1 and adjacent lower gate electrodes 80L-4 of opening 229B.

[0082] exist Figures 15A to 15B In some embodiments, a mask material 232 is deposited over patterned photoresist 230 and within openings 231. For example... Figure 15BAs shown, mask material 232 can fill opening 231, cover the exposed surface of sacrificial layer 224, and cover the surface of photoresist 230. In some embodiments, mask material 232 can be a material similar to that of hard mask 226. For example, mask material 232 can be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, FCVD, ALD, etc. In other embodiments, mask material 232 and hard mask 226 can be different materials. For example, in some embodiments, mask material 232 can include a polymer, metal oxide, or another suitable material. In some embodiments, mask material 232 and sacrificial layer 224 are different materials with etch selectivity. Figure 15B As shown, the upper portion of the mask material 232 includes a lateral portion extending above the top surface of the photoresist 230. In some instances, the thickness of the lateral portion of the mask material 232 above the photoresist 230 is less than the thickness of the photoresist 230 and / or the thickness of the hard mask 226.

[0083] exist Figures 16A to 16B In some embodiments, the upper portions of the photoresist 230 and mask material 232 are removed. The lower portions of the mask material 232 remain on the sacrificial layer 224, where these retained portions form cut regions 232' that separate (e.g., "cut") each opening 229 into two openings 233. Thus, in some instances, the mask material 232 can be considered as a "cutting material," etc. The openings 233 are used to define subsequently formed mating contacts 212. The upper portions of the photoresist 230 and mask material 232 can be removed using suitable techniques, such as stripping processes, ashing processes, and / or one or more etching processes. Etching processes can include wet etching processes and / or dry etching processes. In some embodiments, the lateral portions of the mask material 232 can be etched to expose the top surface of the photoresist 230, and the photoresist 230 can then be removed using an ashing process. In some embodiments, the upper portions of the mask material 232 can be removed using a planarization process, such as a CMP process, and then the photoresist 230 can be removed using an ashing process. In some embodiments, wet chemical etching can be used to completely or partially remove the photoresist 230, which causes the upper lateral portion of the mask material 232 to be stripped away.

[0084] After removing the lateral portion of the mask material 232, the lower portion of the mask material 232 remains to form the cut region 232'. In other words, the cut region 232' is formed by the portion of the mask material 232 deposited on the sacrificial layer 224 within the opening 231. The cut region 232' may have a thickness greater than, less than, or approximately equal to the thickness of the hard mask 226. Each cut region 232' divides the opening 229 into a pair of openings 233. The openings 233 may have an L-shape, such as... Figure 16A As shown, or another shape, such as a triangle. The pairs of openings 233 can have mirror symmetry. As an example, the cut region 232' divides the opening 229A into a pair of openings 233A. One opening 233A extends over the lower gate electrode 80L-2 and the lower epitaxial source / drain region 62L-2 of the first SRAM region 222A', and the other opening 233A extends over the lower gate electrode 80L-2 and the lower epitaxial source / drain region 62L-2 of the adjacent SRAM region 222B'. Similarly, the cut region 232' divides the opening 229B into a pair of openings 233B, wherein each opening 233B extends over the lower gate electrode 80L-1 and the epitaxial source / drain region 62L-4 of the corresponding SRAM region 222'. In some embodiments, the cut region 232' may have a width W2 ranging from about 10 nm to about 50 nm, which in some instances allows for greater device density and / or larger mating contacts 212. Other widths W2 are also possible. Forming the opening 233 by forming the cut region 232' instead of by directly patterning the opening 233 allows for smaller widths W2 between the openings 233, more reliable formation of the openings 233, more reliable formation of the mating contacts 212, improved yield, and higher device density.

[0085] exist Figures 17A to 17B In some embodiments, opening 233 extends through sacrificial layer 224 and fourth ILD 194. Opening 233 can be extended by performing one or more etching processes using a patterned hard mask 226 and a cut region 232' as an etching mask. In some embodiments, opening 233 exposes ESL 192. The etching process may include one or more suitable wet or dry etching processes, which may be anisotropic. In some embodiments, the etching process stops at ESL 192. In some embodiments, one or more timed etching processes are used. In some embodiments, after etching through fourth ILD 194, hard mask 226, cut region 232', and / or sacrificial layer 224 are removed.

[0086] exist Figures 18A to 18BIn some embodiments, a via opening 233V is formed in opening 233. In other embodiments, the via opening 233V may be formed at different process stages. The via opening 233V is the opening of the via portion 212V of the subsequently formed mating contact 212 in ESL 192. In some embodiments, the via opening 233V also extends through other layers, such as through dielectric region 176, to expose the lower gate structure 90L or the lower source / drain contact 96L. In this way, the via portion 212V of the subsequently formed mating contact 212 can physically and electrically contact the lower gate structure 90L or the lower source / drain contact 96L. For example, a via opening 233V can be formed in opening 233A of the lower source / drain contact exposing the lower gate electrode 80L-2 and the lower epitaxial source / drain region 62L-2, and a via opening 233B of the lower source / drain contact exposing the lower gate electrode 80L-1 and the lower epitaxial source / drain region 62L-4. The via opening 233V can be formed using suitable photolithography and etching techniques.

[0087] exist Figures 19A to 19B In some embodiments, a mating contact 212 is formed in the opening 233. In some embodiments, a pad (not shown separately), such as a diffusion barrier layer or an adhesive layer, and a conductive material are formed in the opening 233. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc., or combinations thereof. In some embodiments, a planarization process, such as CMP or etch-back, is performed to remove excess material from the top surface of the fourth ILD 194. The remaining pad and conductive material form the mating contact 212 in the opening 233, including the via portion 212V in the via opening 233V. After the planarization process, the mating contact 212 and the top surface of the fourth ILD 194 are substantially flush or coplanar (within process variations). In some embodiments, pads and / or conductive materials for the mating contact 212, the lower gate contact 210, and / or the lower source / drain via 208 are deposited simultaneously. Each SRAM cell 222 includes mating contacts 212A and 212B. In some embodiments, each mating contact 212A electrically connects a lower gate electrode 80L-2 to a lower epitaxial source / drain region 62L-2, and each mating contact 212B electrically connects a lower gate electrode 80L-1 to a lower epitaxial source / drain region 62L-4. Forming the mating contacts 212 using the techniques described herein allows for smaller mating contacts 212, higher yields, and greater device density.

[0088] Figures 20A to 24BIntermediate steps in the formation of the mating contact 312 according to some embodiments are shown. The mating contact 312 is similar to those previously described for... Figures 9 to 10 The described mating contact 212 differs from the mating contact 312 in that it has a triangular shape instead of an L-shape. Furthermore, the mating contact 312 uses a similar design to... Figures 11A to 19B The materials and techniques described for forming the mating contact 212 are used to form it, except that the cut region 332' is formed within each SRAM region 322A' / 322B' rather than between adjacent SRAM regions 222A' / 222B'. Some of the materials or techniques are similar to those previously described for forming the mating contact 212. Figures 11A to 19B The descriptions are as described, and some details will not be repeated. Figure 20A , Figure 21A , Figure 22A , Figure 23A and Figure 24A It shows something similar to Figures 11A to 19A The floor plan of the plan, and Figure 20B , Figure 21B , Figure 22B , Figure 23B and Figure 24B A cross-sectional view along a section similar to the reference section E-E' shown is presented.

[0089] exist Figures 20A to 20B In some embodiments, a patterned hard mask 226 is formed over the fourth ILD 194. Figures 20A to 20B The structure can be similar to Figures 13A to 13B The structure shown can be formed using similar techniques. For example, a sacrificial layer 224 can be formed over the fourth ILD 194, and a hard mask 226 can be formed over the sacrificial layer 224. The sacrificial layer 224 and the hard mask 226 can be similar to those previously described. Openings 329 are then patterned in the hard mask 226 using suitable photolithography and etching techniques. Openings 329 expose the sacrificial layer 224. Each opening is formed in an SRAM region, and each opening 329 partially defines the region where the mating contact 312 is subsequently formed.

[0090] exist Figures 21A to 21B In some embodiments, photoresist 230 is formed and patterned over the hard mask 226 and the sacrificial layer 224 to form openings 331 exposing the sacrificial layer 224. The photoresist 230 can be similar to that previously used for... Figures 14A to 14B The described photoresist 230, and openings 331 can be patterned in the photoresist 230 using a suitable photolithography technique, similar to... Figures 14A to 14BIn some embodiments, each opening 331 is located within the perimeter of a corresponding opening 329. Therefore, some portions of the sacrificial layer 224 within the opening 329 are covered by photoresist 230, and some portions of the sacrificial layer 224 within the opening 229 are exposed by the opening 331. Each opening 331 defines a separation between opposing regions of a corresponding opening 329, wherein an approximately triangular portion of the opening 329 is located on either side of the opening 331. In other embodiments, the portions of the opening 329 located on either side of the opening 331 are formed to have other shapes. In some embodiments, the opening 331 is formed within a corresponding SRAM region 322'. In some embodiments, the opening 331 may extend at an angle or bevel relative to other components, such as relative to the lower gate electrode 80L or the semiconductor strip 20'.

[0091] exist Figures 22A to 22B In some embodiments, a mask material 232 is deposited over patterned photoresist 230 and within opening 331. The mask material 232 can be similar to that previously used for... Figures 15A to 15B The mask material 232 is described and can be formed using similar techniques. For example, the mask material 232 can fill the opening 331, cover the exposed surface of the sacrificial layer 224, and cover the surface of the photoresist 230.

[0092] exist Figures 23A to 23B In some embodiments, the upper portion of the photoresist 230 and mask material 232 is removed to form a diced region 332'. Similar to... Figures 16A to 16B The remaining lower portion of the mask material 232 forms a cut region 332' that separates (e.g., "cuts") each opening 329 into two openings 333. The openings 333 define the subsequently formed mating contact 312. The upper portions of the photoresist 230 and mask material 232 can be removed using suitable techniques, such as those previously used for... Figures 16A to 16B Those described. Each cutting region 332' divides each opening 329 into a pair of openings 333 (e.g., openings 333A and 333B). The openings 333 may have an approximately triangular shape, such as... Figure 23A As shown, but other shapes are also possible. Opening 333A extends above the lower gate electrode 80L-2 and the lower epitaxial source / drain region 62L-2 of SRAM region 322', and another opening 333B extends above the lower gate electrode 80L-1 and the epitaxial source / drain region 62L-4 of the same SRAM region 322'.

[0093] exist Figures 24A to 24BIn some embodiments, opening 333 extends through the fourth ILD 194, and mating contacts 312 are formed in opening 333. Opening 333 can extend through sacrificial layer 224 and the fourth ILD 194 by performing one or more etching processes using a patterned hard mask 226 and a cut region 332' as an etching mask. In some embodiments, opening 333 exposes ESL 192. The etching process can include one or more suitable wet or dry etching processes, which can be anisotropic. The etching process can be similar to those previously described for… Figures 17A to 17B As described above. In some embodiments, a through-hole opening is formed through ESL 192. A liner and conductive material are then deposited in the opening 333 to form a mating contact 312. The material of the mating contact 312 can be similar to that previously described for... Figures 19A to 19B The described techniques allow for planarization processes to remove excess material. Forming the mating contacts 312 using the techniques described herein can enable higher yields and greater device density.

[0094] Figures 25A to 26B Intermediate steps in the formation of the mating contact 412 according to some embodiments are shown. The mating contact 412 is similar to those previously described for... Figures 9 to 10 The described mating contact 212 differs from the mating contact 412 in that it has a linear shape instead of an L-shape. Furthermore, the mating contact 412 is formed without first forming a cut area. Some aspects of the material or technique are similar to those previously described. Figures 11A to 19B The descriptions are as described, and some details will not be repeated. Figure 25A and Figure 26A It shows something similar to Figures 11A to 19A The floor plan of the plan, and Figure 25B and Figure 26B A cross-sectional view along a section similar to the reference section F-F' shown is presented.

[0095] exist Figures 25A to 25BIn some embodiments, photoresist 430 is formed and patterned over the fourth ILD 196 to form an opening 433. The photoresist 430 can be deposited using suitable techniques. The photoresist 430 can comprise a single layer or multiple layers and can include a hard mask, etc. The opening 433 can be patterned using suitable photolithography techniques. In each SRAM region 422', an opening 433B extends over the lower gate electrode 80L-1 and the lower epitaxial source / drain region 62L-4, and an opening 433A extends over the lower gate electrode 80L-2 and the lower epitaxial source / drain region 62L-2. In some embodiments, the opening 194 can extend at an angle or oblique angle relative to other components (such as relative to the lower gate electrode 80L or semiconductor strip 20'). In some embodiments, forming the opening 194 into an angled and elongated shape can improve the yield and reliability of the mating contact 412.

[0096] exist Figures 26A to 26B In some embodiments, opening 433 extends through the fourth ILD 194, and mating contacts 412 are formed in opening 433. Opening 433 can extend through sacrificial layer 224 and the fourth ILD 194 by performing one or more etching processes using a patterned hard mask 226 and a cut area 332' as an etching mask. In some embodiments, opening 433 exposes ESL 192. The etching process can include one or more suitable wet or dry etching processes, which can be anisotropic. The etching process can be similar to those previously described for… Figures 17A to 17B As described above. In some embodiments, a through-hole opening is formed through ESL 192. A liner and conductive material are then deposited in the opening 433 to form a mating contact 412. The material of the mating contact 412 can be similar to that previously described for... Figures 19A to 19B The described techniques allow for planarization processes to remove excess material. Forming the mating contacts 412 using the techniques described herein can enable higher yields and greater device density.

[0097] The embodiments described herein offer advantages. By using a cut region as an etching mask to form mating contacts in an SRAM cell, smaller or denser mating contacts with improved reliability and yield can be formed. The mating contacts can be formed as part of a stacked transistor memory cell, such as a CFET memory cell. In some embodiments, the cut region can be formed between adjacent memory cells, and in other embodiments, the cut region can be formed within the memory cell. The techniques described herein allow mating contacts to have various shapes, such as L-shapes, linear shapes, triangular shapes, or other shapes. The embodiments described herein can allow for greater device density and can allow for improved physical or electrical coupling through mating contacts.

[0098] In embodiments of this disclosure, the method includes: forming a memory structure including a first pull-up transistor, a first pull-down transistor, a first transmission gate transistor, a second pull-up transistor, a second pull-down transistor, and a second transmission gate transistor on the front side of a substrate; forming a dielectric layer over the back side of the memory structure; forming a hard mask over the dielectric layer; forming a first opening in the hard mask, wherein the first opening extends over the first pull-up transistor and the second pull-up transistor; forming a mask material in the first opening, wherein the mask material divides the first opening into a second opening and a third opening; extending the second opening and the third opening through the dielectric layer; and forming a conductive material in the second opening to form a first mating contact, and forming a conductive material in the third opening to form a second mating contact, wherein the first mating contact electrically contacts the first pull-up transistor, and the second mating contact electrically contacts the second pull-up transistor. In an embodiment, the first pull-up transistor is located in a first memory cell, and the second pull-up transistor is located in a second memory cell adjacent to the first memory cell. In an embodiment, the second opening and the third opening are L-shaped. In one embodiment, a first mating contact electrically contacts the first gate structure of the first pull-up transistor, and a second mating contact electrically contacts the second gate structure of the second pull-up transistor. In another embodiment, a mask material is laterally positioned between the first and second pull-up transistors. In yet another embodiment, the width between the second and third openings is in the range of 10 nm to 50 nm. In yet another embodiment, the memory structure is a single SRAM cell. In yet another embodiment, the first pull-up transistor is part of a stacked transistor structure.

[0099] In embodiments of this disclosure, the method includes: depositing a dielectric layer over the back side of a memory cell; depositing a hard mask over the dielectric layer; patterning a first opening in the hard mask, wherein the first opening extends over a first epitaxial source / drain region, a second epitaxial source / drain region, a first gate electrode, and a second gate electrode of the memory cell; depositing photoresist over the hard mask and within the first opening; patterning a second opening in the photoresist, wherein the second opening extends across the first opening; depositing a mask material over the photoresist and within the second opening; removing the photoresist, wherein a region of the mask material remains within the second opening; etching the dielectric layer using the regions of the hard mask and the mask material as an etch mask, wherein the etching forms a groove in the dielectric layer; and depositing a conductive material in the groove. In embodiments, the second opening is laterally located between the first epitaxial source / drain region and the second epitaxial source / drain region. In embodiments, the second opening is laterally located between the first gate electrode and the second gate electrode. In embodiments, the groove has a triangular shape. In one embodiment, a conductive material electrically contacts a first epitaxial source / drain region, a second epitaxial source / drain region, a first gate electrode, and a second gate electrode. In another embodiment, a region of mask material extends from one side of the first opening to a second side of the first opening. In yet another embodiment, a dielectric layer is deposited over an etch stop layer and includes a patterned via opening within the second opening, wherein the via opening extends through the etch stop layer.

[0100] In embodiments of this disclosure, the memory device includes: a first lower epitaxial source / drain region adjacent to a second lower epitaxial source / drain region; a first lower gate electrode adjacent to a first side of the first lower epitaxial source / drain region; a second lower gate electrode adjacent to a second side of the second lower epitaxial source / drain region, wherein the second side is opposite to the first side; a dielectric layer located below the first lower epitaxial source / drain region, the second lower epitaxial source / drain region, the first lower gate electrode, and the second lower gate electrode; a first mating contact located within the dielectric layer, wherein the first mating contact electrically connects the first lower epitaxial source / drain region to the second lower gate electrode; and a second mating contact located within the dielectric layer, wherein the second mating contact electrically connects the second lower epitaxial source / drain region to the first lower gate electrode. In embodiments, the first mating contact and the second mating contact extend at an oblique angle relative to the first lower gate electrode and the second lower gate electrode. In embodiments, the first mating contact and the second mating contact have a triangular shape. In one embodiment, the memory device includes a first upper epitaxial source / drain region located above a first lower epitaxial source / drain region and a first upper gate electrode located above a first lower gate electrode. In another embodiment, the memory device includes a third lower gate electrode adjacent to a second side of the first lower epitaxial source / drain region, wherein a first mating contact extends above the third lower gate electrode.

[0101] Some embodiments of this application provide a method for forming a memory device, comprising: forming a memory structure on the front side of a substrate, the memory structure including a first pull-up transistor, a first pull-down transistor, a first transmission gate transistor, a second pull-up transistor, a second pull-down transistor, and a second transmission gate transistor; forming a dielectric layer over the back side of the memory structure; forming a hard mask over the dielectric layer; forming a first opening in the hard mask, wherein the first opening extends over the first pull-up transistor and the second pull-up transistor; forming a mask material in the first opening, wherein the mask material divides the first opening into a second opening and a third opening; extending the second opening and the third opening through the dielectric layer; and forming a conductive material in the second opening to form a first mating contact, and forming a conductive material in the third opening to form a second mating contact, wherein the first mating contact electrically contacts the first pull-up transistor, and the second mating contact electrically contacts the second pull-up transistor.

[0102] In some embodiments, the first pull-up transistor is located in a first memory cell, and the second pull-up transistor is located in a second memory cell adjacent to the first memory cell. In some embodiments, the second opening and the third opening are L-shaped. In some embodiments, the first mating contact electrically contacts the first gate structure of the first pull-up transistor, and the second mating contact electrically contacts the second gate structure of the second pull-up transistor. In some embodiments, the mask material is laterally located between the first pull-up transistor and the second pull-up transistor. In some embodiments, the width between the second opening and the third opening is in the range of 10 nm to 50 nm. In some embodiments, the memory structure is a single SRAM cell. In some embodiments, the first pull-up transistor is part of a stacked transistor structure.

[0103] Other embodiments of this application provide a method for forming a memory device, comprising: depositing a dielectric layer over the back side of a memory cell; depositing a hard mask over the dielectric layer; patterning a first opening in the hard mask, wherein the first opening extends over a first epitaxial source / drain region, a second epitaxial source / drain region, a first gate electrode, and a second gate electrode of the memory cell; depositing photoresist over the hard mask and within the first opening; patterning a second opening in the photoresist, wherein the second opening extends across the first opening; depositing a mask material over the photoresist and within the second opening; removing the photoresist, wherein a region of the mask material remains within the second opening; using the regions of the hard mask and the mask material as an etching mask to etch the dielectric layer, wherein the etching forms a groove in the dielectric layer; and depositing a conductive material in the groove.

[0104] In some embodiments, the second opening is laterally located between the first epitaxial source / drain region and the second epitaxial source / drain region. In some embodiments, the second opening is laterally located between the first gate electrode and the second gate electrode. In some embodiments, the groove has a triangular shape. In some embodiments, the conductive material electrically contacts the first epitaxial source / drain region, the second epitaxial source / drain region, the first gate electrode, and the second gate electrode. In some embodiments, the mask material extends from one side of the first opening to a second side of the first opening. In some embodiments, the dielectric layer is deposited over an etch stop layer and further includes a patterned via opening within the second opening, wherein the via opening extends through the etch stop layer.

[0105] Further embodiments of this application provide a memory device, including: a first lower epitaxial source / drain region adjacent to a second lower epitaxial source / drain region; a first lower gate electrode adjacent to a first side of the first lower epitaxial source / drain region; a second lower gate electrode adjacent to a second side of the second lower epitaxial source / drain region, wherein the second side is opposite to the first side; a dielectric layer located below the first lower epitaxial source / drain region, the second lower epitaxial source / drain region, the first lower gate electrode, and the second lower gate electrode; a first mating contact located within the dielectric layer, wherein the first mating contact electrically connects the first lower epitaxial source / drain region to the second lower gate electrode; and a second mating contact located within the dielectric layer, wherein the second mating contact electrically connects the second lower epitaxial source / drain region to the first lower gate electrode.

[0106] In some embodiments, the first mating contact and the second mating contact extend at an oblique angle relative to the first lower gate electrode and the second lower gate electrode. In some embodiments, the first mating contact and the second mating contact have a triangular shape. In some embodiments, the memory device further includes a first upper epitaxial source / drain region located above the first lower epitaxial source / drain region and a first upper gate electrode located above the first lower gate electrode. In some embodiments, the memory device further includes a third lower gate electrode adjacent to a second side of the first lower epitaxial source / drain region, wherein the first mating contact extends above the third lower gate electrode.

[0107] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a memory device, comprising: A memory structure is formed on the front side of a substrate, the memory structure including a first pull-up transistor, a first pull-down transistor, a first transmission gate transistor, a second pull-up transistor, a second pull-down transistor, and a second transmission gate transistor; A dielectric layer is formed above the back side of the memory structure; A hard mask is formed above the dielectric layer; A first opening is formed in the hard mask, wherein the first opening extends above the first pull-up transistor and the second pull-up transistor; A mask material is formed in the first opening, wherein the mask material divides the first opening into a second opening and a third opening; Extending the second opening and the third opening through the dielectric layer; and Conductive material is formed in the second opening to form a first mating contact, and conductive material is formed in the third opening to form a second mating contact, wherein the first mating contact electrically contacts the first pull-up transistor, and the second mating contact electrically contacts the second pull-up transistor.

2. The method according to claim 1, wherein, The first pull-up transistor is located in the first memory cell, and the second pull-up transistor is located in the second memory cell adjacent to the first memory cell.

3. The method according to claim 1, wherein, The second opening and the third opening are L-shaped.

4. The method according to claim 1, wherein, The first mating contact electrically contacts the first gate structure of the first pull-up transistor, and the second mating contact electrically contacts the second gate structure of the second pull-up transistor.

5. The method according to claim 1, wherein, The mask material is laterally positioned between the first pull-up transistor and the second pull-up transistor.

6. The method according to claim 1, wherein, The width between the second opening and the third opening is in the range of 10 nm to 50 nm.

7. The method according to claim 1, wherein, The memory structure is a single SRAM cell.

8. The method according to claim 1, wherein, The first pull-up transistor is part of a stacked transistor structure.

9. A method of forming a memory device, comprising: A dielectric layer is deposited above the back side of the memory cell; A hard mask is deposited over the dielectric layer; A first opening is patterned in the hard mask, wherein the first opening extends over the first epitaxial source / drain region, the second epitaxial source / drain region, the first gate electrode, and the second gate electrode of the memory cell; Photoresist is deposited above the hard mask and within the first opening; A second opening is patterned in the photoresist, wherein the second opening extends across the first opening; A mask material is deposited above the photoresist and within the second opening; Remove the photoresist, wherein the area of ​​the mask material remains within the second opening; The dielectric layer is etched using a region of the hard mask and the mask material as an etching mask, wherein the etching forms grooves in the dielectric layer; and Conductive material is deposited in the groove.

10. A memory device, comprising: The first lower epitaxial source / drain region is adjacent to the second lower epitaxial source / drain region; The first lower gate electrode is located on the first side adjacent to the first lower epitaxial source / drain region; The second lower gate electrode is located on the second side adjacent to the second lower epitaxial source / drain region, wherein the second side is opposite to the first side; A dielectric layer is located below the first lower epitaxial source / drain region, the second lower epitaxial source / drain region, the first lower gate electrode, and the second lower gate electrode; A first mating contact is located within the dielectric layer, wherein the first mating contact electrically connects the first lower epitaxial source / drain region to the second lower gate electrode; and The second mating contact is located within the dielectric layer, wherein the second mating contact electrically connects the second lower epitaxial source / drain region to the first lower gate electrode.

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