Integrated circuit system and method for forming integrated circuit system

Abstract

The invention relates to an integrated circuit system and a method for forming the integrated circuit system. An integrated circuit system includes a stack including vertically alternating insulating levels and conductive levels extending from an array region into a step region. The step region includes step segments, the steps including treads, where individual ones of the treads include a target level of electrical conductivity. A conductive path extends from directly above one of the individual tread surfaces, through one of the individual tread surfaces, and to directly below one of the individual tread surfaces to a bottom of the stack. The conductive path includes a conductor material directly electrically coupled to the conductive material in the target conductive level of the individual tread. The conductor material is in the target conductive level, directly above and directly below the conductive material in the target conductive level. Other embodiments, including methods, are disclosed.

Description

TECHNICAL FIELD

[0001] Embodiments disclosed herein relate to integrated circuitry and methods for forming integrated circuitry. BACKGROUND

[0002] Memory is a type of integrated circuitry and is used in computer systems to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be accessed for writing to or reading from using digit lines (also referred to as bit lines, data lines, or sense lines) and access lines (also referred to as word lines). Sense lines can conductively interconnect memory cells along columns of the array, and access lines can conductively interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of a sense line and an access line.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods without power. Non-volatile memory is conventionally designated as memory having a retention time of at least about 10 years. Volatile memory dissipates, so it is refreshed / re-written to maintain data storage. Volatile memory can have a retention time of a few milliseconds or less. Regardless, memory cells are configured to hold or store memory in at least two different, selectable states. In binary systems, the states are considered either a “0” or a “1”. In other systems, at least some individual memory cells can be configured to store information beyond two levels or states.

[0004] Field effect transistors are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductor channel region therebetween. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is largely prevented. Field effect transistors can also include additional structures, such as reversibly programmable charge storage regions, as part of a gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory and has numerous uses in modern computers and devices. For example, modern personal computers can store the BIOS on a flash memory chip. As another example, computers and other devices increasingly utilize flash memory in solid state drives in place of conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and provides the ability to remotely upgrade devices for enhanced features.

[0006] NAND can be the basic architecture of integrated flash memory. NAND cell components include at least one select device coupled in series to a series combination of memory cells (the series combination often referred to as a NAND string). NAND architecture can be configured in a three-dimensional arrangement including vertically stacked memory cells individually including a reversibly programmable vertical transistor. Control circuitry or other circuitry can be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures can also include vertically stacked memory cells individually including a transistor.

[0007] Memory arrays can be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks), and memory planes, for example as shown and described in any of U.S. Patent Application Publication Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. Memory blocks can be at least partially defined by the longitudinal profile of individual word lines in individual word line levels of the vertically stacked memory cells. Connections to these word lines can occur at the ends or edges of the array of vertically stacked memory cells in so-called "stair-step structures." Stair-step structures include individual "steps" (alternatively referred to as "stages" or "stair-steps") that define contact regions of individual word lines, over which vertically extending conductive vias contact to provide electrical access to the word lines.

[0008] Integrated circuitry other than memory circuitry can also include a stack including vertically alternating insulating levels and conductive levels extending into a stair-step region from an array region, where the array region includes an array of electronic components. SUMMARY

[0009] According to one aspect of the disclosure, a method for forming integrated circuitry is provided. The method includes forming a stack comprising vertically-alternating first and second levels extending from an array region into a staircase region, the staircase region comprising a staircase step, the staircase individually comprising a tread, the tread comprising a target first level, the target first level being one of the first levels; forming an opening in the tread down through the target first level and the vertically-alternating first and second levels immediately therebelow; the second levels comprising insulative material and the first levels comprising conductive material, insulative material having a composition different from a composition of the insulative material in individual ones of the first levels immediately thereabove and therebelow; through the opening, selectively etching the insulative material relative to the insulative and conductive material to form a top void space in the target first level immediately above the conductive material therein, and a bottom void space in the target first level immediately below the conductive material therein; and forming a conductive via within the opening to a material immediately below the stack, the conductive via comprising a conductor material from immediately above the target first level through the target first level and extending to the material immediately below the target first level and below the stack, the conductor material formed in the top and bottom void spaces and directly thereagainst the conductive material in the target first level.

[0010] According to another aspect of the disclosure, a method for forming integrated circuitry is provided. The method includes forming a stack comprising vertically-alternating first and second levels extending from an array region into a staircase region, the staircase region comprising a staircase step, the staircase individually comprising a tread, the tread comprising a target first level, the target first level being one of the first levels; forming an opening in the tread down through the target first level and the vertically-alternating first and second levels immediately therebelow; the second levels comprising insulative material and the first levels comprising conductive material; through the opening, etching the conductive material in the target first level to reduce its thickness in the target first level closer to the opening than at a distal end thereof; and forming a conductive via within the opening to a material immediately below the stack, the conductive via comprising a conductor material directly electrically coupled with the conductive material of the target first level of the tread and from immediately above the target first level through the target first level and extending to the material immediately below the target first level and below the stack of the stack, the conductor material formed in the target first level immediately above and below the conductive material therein.

[0011] According to yet another aspect of the disclosure, a method for forming integrated circuitry is provided. The method includes forming a stack comprising vertically-alternating first and second levels extending from an array region into a staircase region, the levels individually comprising a tread, the tread comprising a target first level, the target first level being one of the first levels; forming an opening in the tread down through the target first level and the vertically-alternating first and second levels immediately therebelow; the second levels comprising insulative material and the first levels comprising conductive material, the conductive material in the target first level comprising a horizontally-elongated seam in a vertical cross-section; through the opening, etching into the horizontally-elongated seam of the conductive material in the target first level to form a horizontally-elongated void space inside the conductive material in the target first level; and forming a conductive via within the opening to material immediately below the stack, the conductive via comprising conductor material passing from immediately above the target first level through the target first level and extending to the material immediately below the target first level to the material immediately below the stack, the conductor material formed directly against the conductive material in the horizontally-elongated void space.

[0012] According to still another aspect of the disclosure, integrated circuitry is provided. The integrated circuitry comprises: a stack comprising vertically-alternating insulative levels and conductive levels extending from an array region into a staircase region, the staircase region comprising a step, the step comprising a tread, individual ones of the treads comprising a target conductive level, the target conductive level being one of the conductive levels; and a conductive via extending from immediately above one of the individual treads, through the one of the individual treads, and to immediately below the one of the individual treads to a bottom of the stack, the conductive via comprising conductor material directly electrically coupled to conductive material in the target conductive level of the one individual tread, the conductor material being in the target conductive level, immediately above and below the conductive material in the target conductive level.

[0013] According to yet another aspect of the present disclosure, an integrated circuit system is provided. The integrated circuit system comprises: a stack comprising vertically alternating insulative levels and electrically conductive levels extending from an array region into a staircase region, the staircase region comprising a stepped terrace, individual of the stepped terraces comprising a target electrically conductive level, the target electrically conductive level being one of the electrically conductive levels; and an electrically conductive via extending from directly above one of the individual stepped terraces, through the one of the individual stepped terraces, and to directly below the one of the individual stepped terraces to a bottom of the stack, the electrically conductive via comprising a conductor material directly electrically coupled to electrically conductive material in the target electrically conductive level, the conductor material directly against the electrically conductive material in the target electrically conductive level within a horizontally elongated void space interior to the electrically conductive material in the target electrically conductive level. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a schematic diagram of a portion of memory circuitry in a process according to embodiments of the invention.

[0015] Figure 3 is a schematic cross-sectional view taken through line 3-3 in Figure 1

[0016] Figure 2 and 4 to 57 are Figure 1 and 3 schematic cross-sectional, expanded, enlarged, and / or partial views of constructions, or portions and / or alternative embodiments, of DETAILED DESCRIPTION

[0017] Embodiments of the invention encompass methods for forming integrated circuitry, such as memory circuitry including memory arrays, such as arrays of NAND or other memory cells (e.g., integrated circuitry components) that can have at least some array-under-peripheral control circuitry (e.g., array-under CMOS). Alternatively, and by way of example only, peripheral control circuitry can be over the array or on a side of the array. Embodiments of the invention encompass so-called "gate-last" or "replacement gate" processes, so-called "gate-first" processes, as well as other processes, existing or to be developed in the future, independent of when transistor gates are formed. Embodiments of the invention also encompass integrated circuitry, independent of the manufacturing method, such as integrated circuitry including memory arrays comprising strings of memory cells (e.g., NAND architecture). Reference is made to Figures 1 to 57 Some example embodiments are described.

[0018] In Figures 1 to 8 ​In the depicted example, the example construction 10 has two memory array regions 12 in which vertically extending strings of transistors and / or memory cells are to be formed. The two memory array regions 12 can have the same construction relative to each other or different constructions. In one embodiment, a staircase region 13 is between the memory array regions 12 and includes a staircase structure as described below. Alternatively, for example, a staircase region can be at an end of a single memory array region (not shown). To make the disclosure clear, Figures 6 to 8 In contrast with Figures 1 to 5 different and varying proportions more relevant to the staircase region 13 than to the memory array regions 12. The example construction 10 includes a base substrate 11 having any one or more of conductive / conductor / conducting, semiconductive / semiconductor / semiconducting, or insulative / insulator / insulating (i.e., electrically insulating) materials. Various materials have been formed vertically over the base substrate 11. The materials can be to the side, vertically inside, or vertically outside of the depicted materials. For example, other portions or all of the manufacturing components of integrated circuitry can be provided somewhere over, around, or inside the base substrate 11. Control and / or other peripheral circuitry for operating components within an array (e.g., an individual array region 12) of vertically extending strings of memory cells can also be fabricated and can or can not be all or partially within the array or subarray. Further, multiple subarrays can also be fabricated and operated independently, in series, or otherwise relative to each other. In this document, a "subarray" can also be considered an array. Figures 1 to 8 The depicted materials are to the side, vertically inside, or vertically outside of the depicted materials. For example, other portions or all of the manufacturing components of integrated circuitry can be provided somewhere over, around, or inside the base substrate 11. Control and / or other peripheral circuitry for operating components within an array (e.g., an individual array region 12) of vertically extending strings of memory cells can also be fabricated and can or can not be all or partially within the array or subarray. Further, multiple subarrays can also be fabricated and operated independently, in series, or otherwise relative to each other. In this document, a "subarray" can also be considered an array.

[0019] A conductor level 16 including a conductor material 17 (e.g., WSi x ) under an electrically conductively doped polysilicon) is over the substrate 11. The conductor level 16 can include portions of control circuitry (e.g., array-under peripheral circuitry and / or common source lines or plates) for controlling read and write access to transistors and / or memory cells in the array 12. A vertical stack 18 including vertically alternating insulative levels 20 and conductive levels 22 is directly over the conductor level 16 and extends from the memory array region 12 into the staircase region 13 along the first direction 55. In some embodiments, the conductive levels 22 can be referred to as first levels 22 and the insulative levels 20 can be referred to as second levels 20, at least in the finished circuitry construction, the first levels 22 are electrically conductive and the second levels 22 are insulative. Example thicknesses for each of the levels 20 and 22 are 20 to 60 nanometers. An example uppermost level 20 can be thicker / thickest compared to one or more other levels 20 and / or 22. An example first level 22 includes a material 26 (in at least one embodiment including a sacrificial material [e.g., silicon nitride] primarily, and in some embodiments referred to as a first sacrificial material), and an example second level 20 includes an insulative material 24 (e.g., silicon dioxide). In Figures 2 to 8While only a limited number of layers 20 and 22 are shown in other figures, stack 18 more likely includes dozens, hundreds, or more layers 20 and 22. Other circuitry, which may or may not be part of the peripheral and / or control circuitry, may be present between conductor layer 16 and stack 18. For example, multiple vertically alternating layers of conductive and insulating materials of such circuitry may be below the lowest layer of conductor layer 22 and / or above the uppermost layer of conductor layer 22. For example, one or more select gate layers (not shown) may be present between conductor layer 16 and the lowest conductive layer 22, and one or more select gate layers may be above the uppermost layer of conductor layer 22 (not shown). Alternatively or additionally, at least one of the uppermost and lowermost conductive layers 22 depicted may be a select gate layer. Circuitry may also be located directly below stack 18, for example, in… Figures 6 to 8 The number 74 is used to designate an example of this circuit system in the insulating material 24, namely a conductive landing pad. This circuit system example includes an array-based CMOS circuit system or other control circuit system, the details of which are not essential to the present invention.

[0020] A channel opening 25 has been formed (e.g., by etching) through insulating layer 20 and conductive layer 22 to conductor layer 16. The channel opening 25 may taper radially inward and / or radially outward (not shown) to extend deeper into the stack 18. In some embodiments, the channel opening 25 may extend into the conductor material 17 of conductor layer 16 as shown, or may stop on top of it (not shown). Alternatively, as an example, the channel opening 25 may stop on top of or inside the lowest insulating layer 20. The reason for extending the channel opening 25 at least to the conductor material 17 of conductor layer 16 is to ensure that direct electrical coupling from the channel material to conductor layer 16 can be achieved without alternative processing and structures and / or to provide an anchoring effect on the material within the channel opening 25. An etch-stop material (not shown) may be inside or on top of the conductor material 17 of conductor layer 16 to facilitate stopping the etching of the channel opening 25 relative to conductor layer 16 when necessary. The etch stop material can be sacrificial or non-sacrificial. For illustrative purposes and for simplicity, the channel openings 25 are shown as groups or columns arranged in staggered rows of four and five openings 25 per row in a finished circuit system configuration, and arranged within a laterally spaced memory block region 58, which will include laterally spaced memory blocks 58. In this document, "block" is generic to include "sub-blocks." The memory block region 58 and the resulting memory blocks 58 (not yet shown) can be considered as longitudinally elongated and oriented, for example, along a first direction 55, where a second direction 99 is orthogonal to the first direction 55. Any alternative existing or future-developed arrangements and configurations can be used.

[0021] Transistor channel materials can be formed vertically along the insulative levels and the conductive levels in the individual channel openings, thus including individual strings of channel material that are directly electrically coupled with conductive material in the conductor levels. Individual memory cells of an example memory array formed can include a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulative charge tunnel material. The storage material (e.g., a floating gate material, such as doped or undoped silicon, or a charge trapping material, such as silicon nitride, metal dots, etc.) of the individual memory cells is vertically along an individual of the charge blocking regions. The insulative charge tunnel material (e.g., a bandgap engineered structure having a nitrogen-containing material, such as silicon nitride, sandwiched between two insulator oxides, such as silicon dioxide) is laterally between the channel material and the storage material.

[0022] The drawing shows one embodiment in which charge blocking material 30, storage material 32, and charge tunnel material 34 have been formed vertically along insulative levels 20 and conductive levels 22 in individual channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed by, for example, depositing respective thin layers thereof over stack 18 and within individual channel openings 25, and then planarizing them back at least to the top surface of stack 18, as shown.

[0023] Channel material 36 has also been formed in channel openings 25 vertically along insulative levels 20 and conductive levels 22, and in one embodiment includes individual channel material strings 53 with memory cell materials (e.g., 30, 32, and 34) along them, with material 24 in insulative levels 20 horizontally between immediately adjacent channel material strings 53. Due to scale, materials 30, 32, 34, and 36 are collectively shown and designated as material 37 in some figures. Example channel material 36 includes suitably doped crystalline semiconductor material, such as one or more of silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 Angstroms. A punch etch can be performed as shown to remove materials 30, 32, and 34 from the base of channel openings 25 to expose conductor level 16 so that channel material 36 (channel material strings 53) is directly electrically coupled with conductor material 17 of conductor level 16. This punch etch can occur separately for each of materials 30, 32, and 34 as shown, or can occur collectively for all of them after deposition of material 34 (not shown). Alternatively, and by way of example only, no punch etch can be performed, and channel material 36 can be directly electrically coupled with conductor material 17 of conductor level 16 by separate conductive interconnections (not shown). Channel openings 25 are shown as including a radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively, and by way of example only, the radially central portion within channel openings 25 can include void space (not shown) and / or be free of solid material (not shown).

[0024] Reference is made to Figure 1 and 6 to 8, and in one embodiment cavities 66 have been formed in stack 18 in staircase region 13 and individually include a staircase structure as described below. Example cavities 66 are longitudinally aligned end-to-end in individual memory block regions 58, with a crown 81 between immediately adjacent cavities 66 (e.g., cavities 66 are spaced relative to each other in first direction 55 by crown 81). Alternatively, only a single cavity can be in individual memory block regions 58 (not shown). However, some method and structure embodiments include fabrication of only a single cavity 66 and the resulting configuration with only a single cavity 66. Cavities 66 are shown as rectangular in horizontal cross-section, but other shapes can be used, and all need not have the same shape relative to each other. For simplicity, only a single cavity 66 is shown in Figure 7 and 8 compared to Figure 3 and 5 fewer levels 20 and 22 are shown in Figure 7 and 8 more levels 20 and 22 are shown in

[0025] The example cavities 66 individually include a flight 67 of steps 70 extending along a first direction (e.g., 55). A mirrored flight (not shown) of steps 70 can be an opposite flight 67 with a landing (not shown) therebetween, and together are considered to include a staircase structure. Individual steps 70 include a tread 75 and a riser 85. Individual treads 75 include a target first level T, which is one of the first levels 22. Cavities 66 with flights 67 and mirrored opposite flights can be formed by any existing or later developed method. As one such example, a masking material (e.g., a photoimageable material such as photoresist) can be formed atop the stack 18, and openings formed therethrough. The masking material can then be used as a mask while etching (e.g., anisotropically) through the openings to extend such openings into at least two outermost two levels 20, 22. The resulting structure can then be subjected to a series of successive alternating lateral trim etches of the masking material, followed by etching deeper into the stack 18, etching at least two levels 20, 22 at a time, using the trimmed masking material with successively widening openings as a mask. This example can result in forming a flight 67 into the stack 18 of vertically alternating levels 20, 22 including different composition materials 24, 26, and forming another flight (again not shown) opposite the flight 67. There can be more steps 70 in the flight 67 than shown. The example steps 70 in the stack 18 are individually shown as including one first level 22 and one second level 20 (which order can be reversed and not shown). Each step 70 can use more first and second levels, e.g., if multiple treads are formed per step (e.g., along a second direction 99 and not shown). Moreover, the horizontal depth of the treads 75 in the direction 55 and the vertical height of the risers 85 can be equal or different relative to each other. The flight 67 and the opposite flight together can be translated (etched) deeper into the stack 18, and / or while one of the flight 67 or the opposite flight is masked, depending on the circuitry being fabricated.

[0026] In one example, in a finished circuitry construction, one of the two opposing tiers 67 and a not shown tier is operational (e.g., tier 67 in this example), and the other of the two opposing tiers is dummy. In this document, a "dummy" tier is one in which the circuit is not operational, it has a step in which no current flows in the step's conductive material, and the step can be a dead end of the circuit that is not part of the circuit's current flow path even if it extends to or from an electronic component. When not operational, the operational versus non-operational position relative to the tiers can of course be reversed. Multiple operational tiers and multiple dummy tiers can be formed in multiple cavities 66, e.g., longitudinally end to end and to different depths within the stack 18 as shown. Several pairs of opposing mirror image operational and dummy tiers can be considered to define a stadium (e.g., a vertically recessed portion with opposing tiers of steps). Alternatively, only a single tier can be formed in one or more individual cavities 66. Regardless, the cavities 66 can be formed before or after the formation of the via material string 53. The cavities 66 can be considered to have laterally outer sidewalls 71 (relative to the second direction 99) and 88 (relative to the first direction 55), with the facade 85 as part of the individual step 70 effectively being part of the cavity 66's sidewall along the second direction 99 along with the sidewall 88, while the sidewall 71 is along the first direction 55. The sidewalls 71, 88 and / or facades can taper laterally inward or outward moving deeper into the stack 18 (not shown). Insulating material 76 (e.g., silicon dioxide formed in a spin-on dielectric manner) within the cavity 66.

[0027] The example tread 75 and facade 85 individually include a sacrificial material 64 (in some embodiments referred to as a second sacrificial material 64) atop the insulating material 24, which order can be reversed. When used, the second sacrificial material 64 is of a different composition than the first sacrificial material 26 (e.g., such that each has different etching characteristics relative to the other). When used, the second sacrificial material 64 can be formed, by way of example only, by ion implanting a substance into the first sacrificial material 26 of the tread 75. For example, and by way of example only, where the first sacrificial material 26 is stoichiometric silicon nitride, the example implanted substance is atomic carbon to form a silicon carbonitride material, whereby phosphoric acid or HF can be used to etch the material 26 relative to the material 64. By way of example only, this is merely one example way of forming a step (e.g., 70) that individually includes a tread (e.g., 75) that includes a second sacrificial material (e.g., 64) in one of the first tiers 22 (e.g., tread 75 for a target first tier T that is subsequently electrically connected thereto) that is of a different composition than the composition of the first sacrificial material (e.g., 26). For clarity, the following primarily refers to processing associated with a single tread 75, and it is to be appreciated that this processing and resulting structure will likely occur with respect to multiple treads.

[0028] Referring Figures 9 to 11 , an opening 77 has been formed in the tread 75 down through the target first tier T and the vertically alternating first and second tiers 22, 20 immediately below it (e.g., and, when present, through the second sacrificial material 64). The opening 77 tapers laterally inward and / or outward in vertical cross-section (not shown). The opening 77 can extend to material below the stack 18, as shown (e.g., to the materials 24 and 74 in the depicted example). Thereafter, and in one embodiment, a third sacrificial material 69 having a composition different from that of the second sacrificial material 64 has been formed (e.g., by exposure to an oxidizing agent, whereby the silicon carbon nitride material 64 forms SiO x 69) directly against the second sacrificial material 64 in the target first tier T of the tread 75. An insulating ring can optionally be formed circumferentially around the opening 77 in the individual one of the first tiers 22 immediately below the target first tier T of the tread 75. For example, the first sacrificial material 26 in the individual first tier 22 immediately below the target first tier T of the tread 75 can be radially recessed through the opening 77 (e.g., by selective etching; e.g., using phosphoric acid or HF if the material 26 is silicon nitride and the other exposed material is silicon dioxide). Thereafter, an insulating ring 72 can be formed circumferentially around the opening 77 in the individual first tier 22 immediately below the target first tier T of the tread 75 (e.g., in the radial recess in the individual first tier 22 immediately below the target first tier T of the tread 75 as a result of the radial recess). The sidewall 78 of the opening 77 can be lined with an insulator material 79 (e.g., silicon dioxide) of the insulating ring 72. The remaining volume of the opening 77 can then be filled with a sacrificial material 80 (e.g., polysilicon).

[0029] Referring Figures 12 to 22A horizontally elongated trench 40 has been formed (e.g., by anisotropic etching) immediately laterally between memory block regions 58. Trench 40 will typically be wider (e.g., 3 to 10 times wider) than channel opening 25. Trench 40 can have a respective bottom directly against (e.g., on top of or within) conductor material 17 of conductor level 16 (as shown), or can have a respective bottom above conductor material 17 of conductor level 16 (not shown). Trench 40 tapers laterally inward and / or outward in vertical cross-section (not shown). Thereafter, first sacrificial material 26 of first level 22 is removed (not shown) by isotropic etching away through trench 40, e.g., by desirably selectively with respect to other exposed materials (e.g., using liquid or vapor H3PO4 as a primary etchant, with material 26 being silicon nitride, and other materials including one or more oxides or polysilicon). In one embodiment and as shown, first sacrificial material 26 (not shown) is selectively etched with respect to second sacrificial material 64 and insulating material 24 (and insulating ring 72, when present) (e.g., if second sacrificial material 64 is a carbonitride silicon material, using the aforementioned H3PO4 as a primary etchant).

[0030] Conductive material 48 has been formed in first level 22 and extends therefrom into staircase region 13 from array region 12. Thereafter conductive material 48 has been removed from trench 40, thus forming individual conductive lines 29 (e.g., word lines) in stack 18 and vertically extending strings 49 of individual transistors and / or memory cells 56 in stack 18. In one embodiment and as shown, after removal of first sacrificial material 26 and before formation of conductive material 48, first level 22 has been lined with insulative material 19 over which conductive material 48 is formed. Insulative material 19 has a different composition than that of insulating material 24, and is immediately above and below conductive material 48 in individual first levels 22. An example insulative material 19 is insulating metal oxide (e.g., where insulating material 24 is silicon dioxide). In one embodiment and as shown, conductive material 48 in target first level T is radially displaced away from aperture 77.

[0031] The approximate locations of the transistors and / or memory cells 56 are indicated in some figures with brackets, and some are indicated in some figures with dashed outlines, in the depicted examples the transistors and / or memory cells 56 are substantially annular or ring-shaped. Alternatively, the transistors and / or memory cells 56 can not completely surround with respect to individual channel openings 25, such that each channel opening 25 can have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells around individual channel openings in individual conductive levels, there can be multiple word lines per channel opening in individual conductive levels, and are not shown). The conductive material 48 can be considered to have a terminal 50 corresponding to a control gate region 52 of an individual transistor and / or memory cell 56. In the depicted embodiment, the control gate region 52 comprises an individual portion of an individual conductive line 29. The materials 30, 32, and 34 can be considered to be memory structures 65 laterally between the control gate region 52 and the channel material 36. In one embodiment and as shown with respect to the example “gate last” process, the conductive material 48 of the conductive level 22 is formed after the channel openings 25 and / or trenches 40 are formed. Alternatively, for example with respect to the “gate first” process, the conductive material of the conductive level (not shown) can be formed before the channel openings 25 and / or trenches 40 are formed.

[0032] A charge blocking region (e.g., charge blocking material 30) is between the storage material 32 and the individual control gate region 52. The charge blocking can have the following function in a memory cell: in a program mode, the charge blocking can prevent charge carriers from the storage material (e.g., floating gate material, charge trapping material, etc.) to travel outward to the control gate, and in an erase mode, the charge blocking can prevent charge carriers from the control gate to flow into the storage material. Thus, the charge blocking can be used to block charge migration between the control gate region and the storage material of an individual memory cell. The example charge blocking region as shown comprises an insulator material 30. By way of further example, the charge blocking region can comprise a lateral (e.g., radial) outer portion of the storage material (e.g., material 32), where this storage material is insulative (e.g., without any distinct composition material between the insulative storage material 32 and the conductive material 48). Regardless, by way of additional example, the interface of the storage material and the conductive material of the control gate can be sufficient to function as a charge blocking region without any separate composition insulator material 30. Further, the interface of the conductive material 48 and the material 30 (when present) in conjunction with the insulator material 30 can together function as a charge blocking region, and alternatively or additionally, as a laterally outer region of insulative storage material (e.g., silicon nitride material 32). The example material 30 is one or more of hafnium silicon oxide and silicon dioxide.

[0033] Intermediary material 57 has been formed in trenches 40 and thereby laterally between and longitudinally along laterally-adjacent memory blocks 58 (material 57 is not shown in trenches 40 in the stepped region for simplicity). Intermediary material 57 can provide lateral electrical isolation (insulation) between laterally-adjacent memory blocks. This can include one or more of insulative, semiconductive, and conductive materials, and in any event can facilitate shorting of conductive levels 22 relative to one another in the finished circuitry construction. Example insulative materials are one or more of SiO2, Si3N4, and Al2O3. Intermediary material 57 can include through-array vias (not shown).

[0034] Referring Figures 23 to 27 , a masking and / or hardmask material 90 has been formed over construction 10, and openings have been formed therethrough to openings 77. Sacrificial material 80 (when used and not shown) can then be removed (e.g., by selective etching) from openings 77. Thereafter, etching can be performed through insulator material 79 (when used and in one embodiment) to line all of openings 77. Thereafter, third sacrificial material 69 (when present and not shown) can be removed / etched through openings 77.

[0035] Referring Figures 28 to 32 , and in one embodiment, sacrificial material 64 (when present and not shown) has been removed (e.g., by selective etching) from target first level T through openings 77 to expose insulative material 19 in target first level T. An example etch chemistry to etch silicon carbonitride material is vapor phase etching using a combination of NF3, SF6, HF, H2, and O2 plus N2 or Ar as a pressure control gas. Alternatively, sacrificial material 64 (not shown) can be removed prior to formation of conductive material 48.

[0036] Referring Figures 33 to 36 , and in one embodiment, insulative material 19 has been selectively etched through openings 77 relative to insulative and conductive materials 24 and 28 to form a top void space 82 Figure 34 and 36 in target first level T directly above conductive material 48 in which it resides, and a bottom void space 83 Figure 34 and 36 in target first level T directly below conductive material 48 in which it resides. Example etch chemistries where insulative material 19 is an insulative metal oxide include at least one of phosphoric acid, sulfuric acid, and HF (e.g., 50% to 100% by weight concentration of the acid at 150°C, atmospheric pressure, if phosphoric or sulfuric acid). In one embodiment, top and bottom void spaces 82, 83 have the same volume relative to one another.

[0037] Referring Figures 37 to 41An electrically conductive via 84 has been formed in the opening 77 to electrically conductive material (e.g., to material 24 and 74 in the depicted example) directly below the stack 18. The electrically conductive via 84 includes a conductor material 86 that extends from directly above the target first level T, through the target first level T, and below the target first level T to the material directly below the stack 18. The conductor material 86 is formed in the top and bottom void spaces 82 and 83 and directly against the electrically conductive material 48 in the target first level T (thereby directly electrically coupled to the electrically conductive material 48 of the target first level T) thereat.

[0038] Any other property or aspect as shown and / or described herein with respect to other embodiments can be used in embodiments shown and described with reference to the above embodiments.

[0039] Referring to Figures 42 to 49 An alternative example embodiment with respect to the construction 10a is shown and described. Where appropriate, the same numerals from the above-described embodiments have been used, with some construction differences indicated with the suffix "a" or with different numerals. Figures 42 to 45 The construction 10a is shown immediately after Figures 28 to 32 Processing after the processing shown with respect to the construction 10 in the initially described embodiment. Figures 42 to 45 The electrically conductive material 48 in the target first level T has been etched through the opening 77 to reduce the thickness of this electrically conductive material 48 in the target first level T closer to the opening 77 than farther from the opening 77. In one such embodiment and as shown, after this etching, the electrically conductive material 48 in the target first level T has a slope (e.g., a straight slope) between its thinnest and thickest portions in a vertical cross-section (e.g., a vertical cross-section of the construction 10a). Figure 43 and / or Figure 45 In one embodiment and as shown, the thinnest portion is pointed in the vertical cross-section. Example etching chemistries where the electrically conductive material 48 is elemental molybdenum and / or elemental tungsten are mixtures of phosphoric acid and nitric acid; mixtures of sulfuric acid and nitric acid; and mixtures of phosphoric acid, sulfuric acid, and hydrogen peroxide (e.g., 0.5 wt% to 10 wt% nitric acid, 10 wt% to 70 wt% sulfuric acid, and / or phosphoric acid, 0% to 5 wt% hydrogen peroxide at 10 °C to 100 °C and atmospheric pressure).

[0040] The insulative material 19 in the above-described embodiments with reference to Figures 1 to 41 is optional in the above-described embodiments with reference to Figures 42 to 49 When the insulative material 19 is present, and only in one such embodiment, the insulative material 19 in the target first level T is etched through the opening 77 at least one of before or during etching the electrically conductive material 48 in the target first level T.

[0041] Referring to Figures 46 to 49An electrically conductive via 84a has been formed in the opening 77 to an electrically conductive material (e.g., to material 24 and 74 in the depicted example) directly below the stack 18. The electrically conductive via 84a includes a conductor material 86 that is directly electrically coupled with the electrically conductive material 48 of the target first level T of the tread 75 and extends through the target first level T directly above the target first level T and below the target first level T to the material directly below the stack 18. The conductor material 86 is formed in the target first level T directly above and below the electrically conductive material 48 in the target first level T.

[0042] Any other attribute or aspect as shown and / or described herein with respect to other embodiments can be used.

[0043] Reference is made to Figures 50 to 57 Alternative example embodiments are shown and described with respect to the construction 10b. Where appropriate, the same numbers from the above described embodiments have been used, with some construction differences indicated with a suffix "b" or with different numbers. Figures 50 to 53 Reference is made to Figures 28 to 32 The example processing shown with respect to the construction 10 in the initially described embodiments is followed. In Figures 50 to 53 In the example shown in Figure 51 and / or Figure 53 The electrically conductive material 48 in the target first level T (e.g., and in the other first levels 22) includes a horizontally elongated seam 87 in a vertical cross-section (e.g., a vertical cross-section of the construction 10b). Such a seam 87 can be inherently formed when the electrically conductive material 48 is deposited into the first level 22 by the trench 40. Such a seam can be present in the embodiments shown in Figures 1 to 49 but are not shown in them for the sake of brevity and are not particularly relevant in those embodiments.

[0044] Reference is made to Figure 54 and 55 and after the processing shown by Figure 51 and 53 The horizontally elongated seam 87 of the electrically conductive material 48 in the target first level T has been etched through the opening 77 to form a horizontally elongated void space 89 inside the electrically conductive material 48 in the target first level T (e.g., using a 1 wt% to 5 wt% aqueous hydrogen peroxide solution where the electrically conductive material 48 is an electrically conductive metallic material [e.g., Mo, W, TiN, etc.]). In one embodiment and as shown, the horizontally elongated void space 89 is higher closer to the opening 77 than at its distal end. In one embodiment and as shown, the horizontally elongated seam 87 and the horizontally elongated void space 89 are vertically centered within the electrically conductive material 48 in the target first level T.

[0045] Reference is made to Figure 56 and 57An electrically conductive via 84b has been formed in the opening 77 to an electrically conductive material (e.g., to material 24 and 74 in the depicted example) directly below the stack 18. The electrically conductive via 84b includes a conductor material 86 that extends from directly above the target first level T, through the target first level T, and below the target first level T to the material directly below the stack 18. The conductor material 86 in the horizontally elongated void space 89 is formed directly against the electrically conductive material 48 (thereby being directly electrically coupled to the electrically conductive material 48 of the target first level T).

[0046] Any other attribute or aspect as shown and / or described herein with respect to other embodiments can be used.

[0047] Alternative embodiment constructions can be derived from or otherwise to the method embodiments described above. Regardless, embodiments of the invention encompass memory arrays independent of the manufacturing method. However, such memory arrays can have any attribute as described herein in the method embodiments. Likewise, the method embodiments described above can incorporate, form, and / or have any attribute described with respect to the device embodiments.

[0048] In one embodiment, integrated circuitry (e.g., 10, 10a) includes a stack (e.g., 18) that includes vertically alternating insulative levels (e.g., 20) and electrically conductive levels (e.g., 22) extending from an array region (e.g., 12) into a staircase region (e.g., 13). The staircase region includes a stair step (e.g., 67) of a stair step (e.g., 70) that includes a tread (e.g., 75). Individual ones of the treads include a target electrically conductive level (e.g., T) that is one of the electrically conductive levels. An electrically conductive via (e.g., 84, 84a) extends from directly above, through, and to directly below one of the individual treads to a bottom (e.g., 98) of the stack. The electrically conductive via includes a conductor material (e.g., 86) that is directly electrically coupled to an electrically conductive material (e.g., 48) in the target electrically conductive level of the one of the individual treads. The conductor material is in the target electrically conductive level, directly above and below the electrically conductive material in the target electrically conductive level (e.g., in voids 82, 83).

[0049] In one embodiment, the conductor material is in an opening (e.g., 77) in the tread that extends downward through a plurality of the vertically alternating insulative and electrically conductive levels directly below the target electrically conductive level, with the electrically conductive material in the target electrically conductive level being radially displaced away from the opening. In one embodiment, all those portions of the electrically conductive material in the target electrically conductive level that are directly above and below the electrically conductive material have the same volume relative to each other.

[0050] In one embodiment, the conductor material is in an opening (e.g., 77) in a tread, the opening extending down through a plurality of vertically alternating insulative and conductive levels directly below a target conductive level, where a thickness of the conductive material in the target conductive level is less closer to the opening than distal thereto (e.g., construction 10a). In one such embodiment of the latter, the conductive material in the target conductive level has a slope between its thinnest and thickest portions in a vertical cross-section. In one such embodiment of the latter, the slope is straight from end to end, and in one such embodiment of the latter, the thinnest portion is pointed in a vertical cross-section. In one example, the integrated circuitry includes memory circuitry and the array region includes an array of memory cells (e.g., 56) including strings of trench material (e.g., 53) extending through a stack in the array region.

[0051] Any other attribute or aspect as shown and / or described herein with respect to other embodiments can be used.

[0052] In some embodiments, integrated circuitry (e.g., 10b) includes a stack (e.g., 18) including vertically alternating insulative levels (e.g., 20) and conductive levels (e.g., 22) extending from an array region (e.g., 12) into a staircase region (e.g., 13). The staircase region includes a run (e.g., 67) of a stair step (e.g., 70) including treads (e.g., 75). Individual ones of the treads include a target conductive level (e.g., T) that is one of the conductive levels. A conductive via (e.g., 84b) extends from directly above, through, and to directly below one of the individual treads to a bottom (e.g., 98) of the stack. The conductive via includes a conductor material (e.g., 86) directly electrically coupled to a conductive material (e.g., 48) in the target conductive level of the one individual tread. The conductor material directly abuts the conductive material in the target conductive level within a horizontally elongated void space (e.g., 89) inside the conductive material in the target conductive level.

[0053] In one embodiment, the conductor material is in an opening (e.g., 77) in a tread, the opening extending down through a plurality of vertically alternating insulative and conductive levels directly below a target conductive level, where a thickness of the conductive material in the target conductive level is less closer to the opening than distal thereto (e.g., construction 10a). In one such embodiment of the latter, the conductive material in the target conductive level has a slope between its thinnest and thickest portions in a vertical cross-section. In one such embodiment of the latter, the slope is straight from end to end, and in one such embodiment of the latter, the thinnest portion is pointed in a vertical cross-section. In one example, the integrated circuitry includes memory circuitry and the array region includes an array of memory cells (e.g., 56) including strings of trench material (e.g., 53) extending through a stack in the array region.

[0054] Any other attribute or aspect as shown and / or described herein with respect to other embodiments can be used.

[0055] In comparison to some existing constructions, the conductive vias as described and shown herein can provide a greater contact area between such conductive vias and the conductive material 48 of the conductive level 22, and thereby reduce contact resistance.

[0056] The memory circuitry described herein (e.g., its conductive vias) can be connected with circuitry on the top or bottom of the stack (i.e., either side of the z-axis), regardless of the orientation of the construction in three-dimensional space, and this is not material to aspects of the invention disclosed herein. For example, and by way of example only, the conductive vias can be connected with peripheral control circuitry that is located below the stack with respect to the orientation shown in the figures. As an alternative example, and by way of example only, the conductive vias can be connected with peripheral control circuitry that is located above the stack with respect to the orientation shown, e.g., to another substrate with such circuitry, and that interfaces with the top of the stack with respect to the orientation shown. In this alternative example, the construction can be inverted from the orientation shown, and then interfaced with another substrate. Further, in this alternative example, the source lines or plates can be fabricated with respect to the orientation shown relative to the bottom of the stack, but inverted therefrom during processing. Such source lines or plates can be connected with conductive vias that extend through the stack to the substrate and interface with another side having such peripheral control circuitry. Regardless, the constructions shown and described herein can be processed, packaged, and / or mounted in any three-dimensional spatial orientation.

[0057] The above processing or constructions can be considered to be with respect to an array of components that are formed as a single stack or a single deck of such components over or as part of an underlying base substrate, or formed within such single stack or single deck (though the single stack / deck can have multiple levels). Control circuitry and / or other peripheral circuitry for operating or accessing such components within the array can also be formed as part of the finished construction at any location, and in some embodiments, can be under the array (e.g., under-array CMOS). Regardless, one or more additional such stacks / decks can be provided or fabricated above and / or below the stack / deck shown in the figures or described above. Further, the arrays of components can be the same or different with respect to each other in different stacks / decks, and different stacks / decks can have the same thickness or different thicknesses with respect to each other. Intermediary structures (e.g., additional circuitry and / or dielectric layers) can be provided between vertically adjacent stacks / decks. Further, different stacks / decks can be electrically coupled with respect to each other. Multiple stacks / decks can be fabricated individually and sequentially (e.g., one on top of the other), or two or more stacks / decks can be fabricated substantially simultaneously.

[0058] The assemblies and structures discussed above can be used in integrated circuits / circuitry and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special- purpose modules, and can include multilayer, multichip modules. The electronic systems can be any one of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0059] In this document, unless otherwise indicated, "vertical," "higher," "upper," "lower," "top," "topmost," "bottom," "over," "under," "below," "beneath," "up," and "down" refer to the vertical direction with respect to the vertical orientation of the substrate. "Horizontal" refers to a direction that is generally parallel to the surface of the main substrate (i.e., within 10 degrees), and can be with respect to the direction in which the substrate is handled during fabrication, and as shown in the figures herein, if present, and vertical is a direction generally orthogonal to horizontal. Reference to "perfectly horizontal" refers to a direction that is parallel to the surface of the main substrate (i.e., no angle to the main substrate surface), and can be with respect to the direction in which the substrate is handled during fabrication. Furthermore, "vertical" and "horizontal" as used herein are directions that are generally perpendicular with respect to each other during fabrication and / or in the finished construction, and are independent of the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "extends vertically" refer to a direction that is at least 45° from perfectly horizontal. Furthermore, with respect to field effect transistors, "vertically extending," "extends vertically," "horizontally extending," "extends horizontally," and the like refer to the orientation of the channel length of the transistor with respect to the direction of current flow between the source / drain regions in operation. For bipolar junction transistors, "vertically extending," "extends vertically," "horizontally extending," and "extends horizontally," and the like refer to the orientation of the base length of the transistor with respect to the direction of current flow between the emitter and collector in operation. In some embodiments, any component, feature, and / or region that extends vertically extends vertically or within 10° of vertical.

[0060] Furthermore, "directly above," "directly below," and "directly under" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components with respect to each other. Furthermore, use of "above" without the word "directly" preceding it only requires that some portion of the stated region / material / component be vertically outward of the other region / material / component (i.e., independent of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, use of "below" and "under" without the word "directly" preceding it only requires that some portion of the stated region / material / component be vertically inward of the other region / material / component (i.e., independent of whether there is any lateral overlap of the two stated regions / materials / components).

[0061] Any of the materials, regions, and structures described herein can be homogenous or non-homogenous, and any material overlying any of the materials, regions, and structures, whether or not homogenous, can be continuous or discontinuous over the material, region, or structure. Where one or more example compositions are provided for any material, the material can comprise, consist essentially of, or consist of the one or more compositions. Furthermore, unless otherwise specified, each of the materials can be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0062] In addition, "thickness" by itself (without a pre-modifying directional adjective) is defined as the average straight-line distance through a given material or region, perpendicular from the closest surface of an immediately-adjacent material or region of different composition. In addition, the various materials or regions described herein can have a generally constant thickness or a variable thickness. If having a variable thickness, unless otherwise indicated, thickness refers to average thickness, and as the thickness is variable, the material or region will have some minimum thickness and some maximum thickness. As used herein, "different composition" only requires that those portions of two stated materials or regions that can be directly against one another are chemically and / or physically different (e.g., if such materials or regions are not homogenous). If two stated materials or regions are not directly against one another, "different composition" only requires that those portions of the two stated materials or regions that are closest to one another are chemically and / or physically different (if such materials or regions are not homogenous). In this document, stated materials, regions, or structures are "directly against" one another when there is at least some physical touch contact of the materials, regions, or structures relative to one another. In contrast, "over," "on," "adjacent," "along," and "against," without the preceding "directly," encompass both "directly against" as well as configurations in which intervening materials, regions, or structures result in no physical touch contact of the stated materials, regions, or structures relative to one another.

[0063] In this document, zone-material-assemblies are "electrically coupled" relative to one another if, in normal operation, current is able to flow continuously from one zone-material-assembly to another and the flow is accomplished primarily through movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic assembly can be between and electrically coupled to the zone-material-assemblies. In contrast, when zone-material-assemblies are referred to as being "directly electrically coupled," there is no intervening electronic assembly (e.g., no diode, transistor, resistor, transducer, switch, fuse, etc.) between the directly electrically coupled zone-material-assemblies.

[0064] Any use of "row" and "column" in this document is to facilitate distinguishing one series or orientation of features from another series or orientation of features and along which the components have been or can be formed. "Row" and "column" are used synonymously with respect to any series of regions, components, and / or features, regardless of function. Regardless, the rows can be straight and / or curved and / or parallel and / or non-parallel with respect to one another, as can the columns. Moreover, the rows and columns can intersect at 90° or at one or more other angles (i.e., other than a right angle) with respect to one another.

[0065] The composition of any of the conductive / conductor / conducting materials herein can be a conductive metallic material and / or a semiconductive / semiconductor / semiconducting material that is conductively doped. A "metallic material" is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more metal compounds.

[0066] Any use of "selectivity" herein with respect to etch / etching, removing / removal, deposition, forming, and / or formation is an action by which one stated material acts on another stated material at a rate of at least 2: 1 by volume. Moreover, any use of selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming at least the first 75 Angstroms of a material at a rate of at least 2: 1 by volume with respect to another or several stated materials.

[0067] Unless otherwise indicated, the use of "or" herein covers any and all of the pertinent items, whether mutually exclusive, overlapping, or otherwise.

[0068] Conclusion

[0069] In some embodiments, a method for forming integrated circuitry includes forming a stack including vertically-alternating first and second levels extending from an array region into a staircase region. The staircase region includes stepped risers. The stepped risers individually include a tread including a target first level, the target first level being one of the first levels. An opening is formed in the tread down through the target first level and the vertically-alternating first and second levels immediately therebelow. The second levels include insulative material and the first levels include conductive material. Insulative material having a composition different from that of the insulative material is formed in individual ones of the first levels immediately above and below the conductive material. Through the opening, the insulative material is selectively etched relative to the insulative and conductive material to form a top void space in the target first level immediately above the conductive material in the target first level and a bottom void space in the target first level immediately below the conductive material in the target first level. A conductive via is formed within the opening to material immediately below the stack. The conductive via includes a conductor material from immediately above the target first level through the target first level and extending immediately below the target first level to the material immediately below the stack. The conductor material is formed in the top and bottom void spaces and directly against the conductive material in the target first level thereat.

[0070] In some embodiments, a method for forming integrated circuitry includes forming a stack including vertically-alternating first and second levels extending from an array region into a staircase region. The staircase region includes stepped risers. The stepped risers individually include a tread including a target first level, the target first level being one of the first levels. An opening is formed in the tread down through the target first level and the vertically-alternating first and second levels immediately therebelow. The second levels include insulative material and the first levels include conductive material. Through the opening, the conductive material in the target first level is etched to reduce its thickness in the target first level closer to the opening than at its distal end. A conductive via is formed within the opening to material immediately below the stack. The conductive via includes a conductor material directly electrically coupled with the conductive material of the target first level of the tread and from immediately above the target first level through the target first level and extending immediately below the target first level to the material immediately below the stack. The conductor material is formed in the target first level immediately above and below the conductive material in the target first level.

[0071] In some embodiments, a method for forming integrated circuitry includes forming a stack including vertically-alternating first and second levels extending from an array region into a staircase region. The levels individually include a tread including a target first level, the target first level being one of the first levels. An opening is formed in the tread down through the target first level and the vertically-alternating first and second levels immediately therebelow. The second levels include insulative material and the first levels include conductive material. The conductive material in the target first level includes a horizontally-elongated seam in a vertical cross-section. Through the opening, the horizontally-elongated seam of the conductive material in the target first level is etched into to form a horizontally-elongated void space inside the conductive material in the target first level. A conductive via is formed within the opening to material immediately below the stack. The conductive via includes conductor material passing through the target first level from immediately above the target first level and extending to the material immediately below the stack immediately below the target first level. The conductor material is formed directly against the conductive material in the horizontally-elongated void space.

[0072] In some embodiments, integrated circuitry includes a stack including vertically-alternating insulative and conductive levels extending from an array region into a staircase region. The staircase region includes a step, the step including a tread. Individual ones of the treads include a target conductive level, the target conductive level being one of the conductive levels. A conductive via extends from immediately above, through, and to immediately below one of the individual treads to a bottom of the stack. The conductive via includes conductor material directly electrically coupled to conductive material in the target conductive level of the one individual tread. The conductor material is in the target conductive level, immediately above and below the conductive material in the target conductive level.

[0073] In some embodiments, integrated circuitry includes a stack including vertically-alternating insulative and conductive levels extending from an array region into a staircase region. The staircase region includes a step, the step including a tread. Individual ones of the treads include a target conductive level, the target conductive level being one of the conductive levels. A conductive via extends from immediately above, through, and to immediately below one of the individual treads to a bottom of the stack. The conductive via includes conductor material directly electrically coupled to conductive material in the target conductive level of the one individual tread. The conductor material is in the target conductive level, immediately above and below the conductive material in the target conductive level.

[0074] In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific to structural and methodical features. It is to be understood that the claims are not limited to the specific features shown and described, since the means herein disclosed include embodiments in addition to those that have been particularly described. The claims should therefore be construed to include all features that within the scope of equivalents of the claims.

Claims

1. A method for forming integrated circuitry comprising: forming a stack comprising vertically-alternating first and second levels extending from an array region into a staircase region, the staircase region comprising a step riser, the step riser individually comprising a tread, the tread comprising a target first level, the target first level being one of the first levels; forming an opening in the tread down through the target first level and the vertically-alternating first and second levels immediately therebelow; the second levels comprising insulative material and the first levels comprising conductive material, insulative material having a composition different from a composition of the insulative material being in individual ones of the first levels immediately above and below the conductive material; through the opening, selectively etching the insulative material relative to the insulative and conductive material to form a top void space in the target first level immediately above the conductive material in the target first level, and a bottom void space in the target first level immediately below the conductive material in the target first level; and forming a conductive via within the opening to a material immediately below the stack, the conductive via comprising a conductor material from immediately above the target first level through the target first level and extending to the material immediately below the target first level, the conductor material being formed in the top and bottom void spaces and directly against the conductive material in the target first level thereat.

2. The method of claim 1 wherein the conductive material in the target first level is radially displaced away from the opening.

3. The method of claim 1 wherein the top and bottom void spaces have the same volume relative to one another.

4. The method of claim 1 wherein the insulative material is insulative metal oxide and the insulative material is silicon dioxide, the etching using an etch chemistry comprising at least one of phosphoric acid, sulfuric acid, and HF.

5. The method of claim 4, wherein the insulating metal oxide is AIO x .

6. The method of claim 1 comprising: the tread comprising a sacrificial material; the opening being formed in the tread through the sacrificial material; and removing the sacrificial material from the target first level through the opening prior to the etching to expose the insulative material in the target first level.

7. The method of claim 1 wherein the integrated circuitry comprises memory circuitry and the array region comprises an array of memory cells including strings of trench material extending through the stack in the array region.

8. A method for forming integrated circuitry comprising: forming a stack comprising vertically-alternating first and second levels extending from an array region into a staircase region, the staircase region comprising a step riser, the step riser individually comprising a tread, the tread comprising a target first level, the target first level being one of the first levels; forming an opening in the tread down through the target first level and the vertically-alternating first and second levels immediately therebelow; The second tiers comprise insulative material and the first tiers comprise conductive material; through the opening, etching the conductive material in the target first tier to reduce its thickness in the target first tier closer to the opening than distal thereto; and forming within the opening a conductive via to material directly below the stack, the conductive via comprising conductor material directly electrically coupled to the conductive material of the target first tier of the landing and extending through the target first tier from directly above the target first tier to the material directly below the target first tier, the conductor material formed in the target first tier directly above and below the conductive material in the target first tier.

9. The method of claim 8 wherein after the etching, the conductive material in the target first tier has a slope between its thinnest and thickest portions in a vertical cross-section.

10. The method of claim 9 wherein the slope is straight from end to end.

11. The method of claim 9 wherein the thinnest portion is pointed in the vertical cross-section.

12. The method of claim 8 wherein the conductive material in the target first tier is displaced radially away from the opening.

13. The method of claim 8 comprising: insulative material having a composition different from that of the insulative material in individual ones of the first tiers directly above and below the conductive material; and at least one of before or during the etching the conductive material in the target first tier, etching the insulative material in the target first tier through the opening.

14. The method of claim 13 comprising the before.

15. The method of claim 13 comprising the during.

16. A method for forming integrated circuitry comprising: forming a stack comprising vertically-alternating first and second tiers extending from an array region into a staircase region, the tiers individually comprising a landing, the landing comprising a target first tier, the target first tier being one of the first tiers; forming an opening in the landing down through the target first tier and the vertically-alternating first and second tiers directly below it; the second tiers comprising insulative material and the first tiers comprising conductive material, the conductive material in the target first tier comprising a horizontally-elongated seam in a vertical cross-section; through the opening, etching into the horizontally-elongated seam of the conductive material in the target first tier to form a horizontally-elongated void space inside the conductive material in the target first tier; and forming a conductive path to the material directly below the stack within the opening, the conductive path comprising a conductor material that passes through the target first level from directly above the target first level and extends to the material directly below the target first level directly against the conductive material in the horizontally elongated void space.

17. The method of claim 16 wherein the horizontally elongated void space is higher nearer the opening than at its distal end.

18. The method of claim 16 wherein the horizontally elongated joint and the horizontally elongated void space are vertically centered within the conductive material in the target first level.

19. Integrated circuitry comprising: a stack comprising vertically alternating insulative levels and conductive levels extending from an array region into a staircase region, the staircase region comprising a stepped flight, the step comprising a tread, individual of the treads comprising a target conductive level, the target conductive level being one of the conductive levels; and a conductive path extending from directly above, through, and to directly below one of the individual treads to a bottom of the stack, the conductive path comprising a conductor material directly electrically coupled to conductive material in the target conductive level of the one individual tread, the conductor material being in the target conductive level, directly above and below the conductive material in the target conductive level.

20. Integrated circuitry comprising: a stack comprising vertically alternating insulative levels and conductive levels extending from an array region into a staircase region, the staircase region comprising a stepped flight, the step comprising a tread, individual of the treads comprising a target conductive level, the target conductive level being one of the conductive levels; and a conductive path extending from directly above, through, and to directly below one of the individual treads to a bottom of the stack, the conductive path comprising a conductor material directly electrically coupled to conductive material in the target conductive level of the one individual tread, the conductor material being within a horizontally elongated void space inside the conductive material in the target conductive level directly against the conductive material in the target conductive level.

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