Integrated circuit system and method for forming integrated circuit system

Abstract

The invention relates to an integrated circuit system and a method for forming the integrated circuit system. An integrated circuit system includes a stack including vertically alternating insulating layers and conductive layers extending from an array region into a step region. Individual treads of the staircase include an electrically conductive material of one of the electrically conductive levels. A conductive path extends from directly above one of the individual tread surfaces, through one of the individual tread surfaces, and directly below one of the individual tread surfaces to a bottom of the stack. The conductive path includes a conductive material directly electrically coupled to a conductive material of the target conductive level of the individual tread. The conductive material of the target conductive layer surface of the individual treads is not located directly above the conductive material in the conductive layer surface that is in close contact with underneath the individual treads. Other embodiments, including methods, are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to integrated circuit systems and methods for forming integrated circuit systems. Background Technology

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be manufactured as one or more individual memory cell arrays. Memory cells can be written to or read from using digital lines (also referred to as bit lines, data lines, or sense lines) and access lines (also referred to as word lines). Sense lines electrically interconnect memory cells along the columns of the array, and access lines electrically interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods without power. Non-volatile memory is typically specified as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of a few milliseconds or less. In any case, memory cells are configured to retain or store memory in at least two different selectable states. In binary systems, these states are considered either "0" or "1". In other systems, at least some individual memory cells can be configured to store information in more than two levels or states.

[0004] A field-effect transistor (FET) is a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region therebetween. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions through the channel region to the other. When the voltage is removed from the gate, current flow is significantly impeded through the channel region. FETs may also include additional structures (e.g., a reversible programmable charge storage region) as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory with numerous applications in modern computers and devices. For example, modern personal computers may store the BIOS on flash memory chips. As another example, the use of flash memory in solid-state drives (SSDs) to replace conventional hard disk drives (HDDs) is becoming increasingly common in computers and other devices. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and provides the ability to remotely upgrade these devices to enhance their features.

[0006] NAND can be a basic architecture for integrated flash memory. A NAND cell unit includes at least one selection device of a series combination of memory cells (wherein the series combination is commonly referred to as a NAND string) series-coupled to the memory cells. The NAND architecture can be configured as a three-dimensional arrangement including vertically stacked memory cells, each individually including a reversible programmable vertical transistor. Control or other circuitry can be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells, each individually including a transistor.

[0007] Memory arrays can be arranged as memory pages, memory blocks, and portions of blocks (e.g., sub-blocks) and memory planes, as shown and described in any of U.S. Patent Application Publications No. 2015 / 0228651, No. 2016 / 0267984, and No. 2017 / 0140833. A memory block may at least partially define the longitudinal profile of individual word lines in an individual word line level of vertically stacked memory cells. Connections to these word lines may appear in so-called “staircase structures” at the ends or edges of the array of vertically stacked memory cells. A staircase structure includes individual “staircases” (alternatively referred to as “steps” or “steps”) defining contact areas for individual word lines, on which vertically extending conductive paths are contacted to provide electrical access to the word lines.

[0008] Integrated circuit systems other than memory circuit systems may also include stacks, which include vertically alternating insulating and conductive layers extending from an array region into a stepped region, wherein the array region includes an array of electronic components. Summary of the Invention

[0009] One aspect of this disclosure relates to a method for forming an integrated circuit system, comprising: forming a stack including vertically alternating first and second layers extending from an array region into a step region, the first layer including a first sacrificial material and the second layer including an insulating material, the step region including a stair section, the stair section individually including a tread comprising a second sacrificial material as one of the first layers, the second sacrificial material having a composition different from that of the first sacrificial material; forming an opening in the tread extending downward through the second sacrificial material and the vertically alternating first and second layers directly below the second sacrificial material; removing the first sacrificial material and the second sacrificial material from the first layer in the array region and the step region; after the removal, forming a conductive material located in the first layer and extending from the array region into the step region; and forming a conductive path within the opening to a material directly below the stack, the conductive path including a conductive material directly electrically coupled to the conductive material of the target first layer of the tread and extending from directly above the target first layer, through the target first layer, and directly below the target first layer into the material directly below the stack.

[0010] Another aspect of this disclosure relates to an integrated circuit system comprising: a stack including vertically alternating insulating and conductive layers extending from an array region into a stepped region, the stepped region including a stair section containing treads, each of the treads including a target conductive layer as one of the conductive layers; a conductive path extending from directly above one of the individual treads, through one of the individual treads, and directly below one of the individual treads to the bottom of the stack, the conductive path including a conductive material directly electrically coupled to a conductive material of the target conductive layer of the individual tread, the conductive path extending through the conductive material of the conductive layer located directly below the individual tread; an insulating ring circumferentially surrounding the conductive path in one of the conductive layers located directly below the individual tread, the insulating ring being laterally interposed between the conductive path and the conductive material of the individual conductive layer located directly below the individual tread; and the conductive material of the target conductive layer of the individual tread located directly above the insulating ring in the conductive layer immediately adjacent to the individual tread.

[0011] Another aspect of this disclosure relates to an integrated circuit system comprising: a stack including vertically alternating insulating and conductive layers extending from an array region into a stepped region, the stepped region including a stair section containing treads, each of the treads including a target conductive layer as one of the conductive layers; a conductive path extending from directly above one of the individual treads, through one of the individual treads, and directly below one of the individual treads to the bottom of the stack, the conductive path including a conductive material directly electrically coupled to a conductive material of the target conductive layer of the individual tread, the conductive path extending through the conductive material of the conductive layer located directly below the individual tread; and the portion of the conductive material of the conductive path located in the target conductive layer that is not directly above the conductive material of the conductive layer immediately below the target conductive layer of the individual tread.

[0012] Another aspect of this disclosure relates to an integrated circuit system comprising: a stack including vertically alternating insulating and conductive layers extending from an array region into a stepped region, the stepped region including a stair section containing treads, each of the treads including a target conductive layer as one of the conductive layers; the insulating layers including an insulating material, wherein an insulating material having a dielectric constant higher than that of the insulating material is located directly above and below the conductive material of each of the conductive layers; a conductive path extending from directly above one of the individual treads, through one of the individual treads, and directly below one of the individual treads to the bottom of the stack, the conductive path including a conductive material directly electrically coupled to the conductive material of the target conductive layer of the individual tread, the conductive path extending through the conductive material of the conductive layer located directly below the individual tread; and the insulating material in the conductive layer of the target conductive layer of the individual tread, which is laterally closer to the conductive path than the insulating material in the conductive layer directly below the individual tread. Attached Figure Description

[0013] Figure 1 This is a schematic view of a portion of a memory circuit system in process according to an embodiment of the present invention.

[0014] Figure 3 Is it through Figure 1 The diagram shows a cross-sectional view taken from line 3-3.

[0015] Figure 2 and 4 Up to 48 is Figure 1 and 3Diagrammatic cross-sections, extended, enlarged, and / or partial views of the structure or parts thereof and / or alternative embodiments thereof. Detailed Implementation

[0016] Embodiments of the present invention cover methods for forming integrated circuit systems, such as memory circuit systems including memory arrays (e.g., arrays of NAND or other memory cells (e.g., integrated circuit system components) that may have at least some under-array peripheral control circuitry (e.g., under-array CMOS). Alternatively, and by way of example only, the peripheral control circuitry may be located above or to one side of the array. Embodiments of the present invention cover so-called “post-gate” or “replacement gate” processes, so-called “gate-before” processes, and other processes (whether existing or future-developed) independent of when the transistor gate is formed. Embodiments of the present invention also cover integrated circuit systems, such as integrated circuit systems including memory arrays comprising strings of memory cells (e.g., NAND architecture) independent of the manufacturing method. Reference Figures 1 to 48 Describe some example implementations.

[0017] exist Figures 1 to 8 In the example configuration 10, two memory array regions 12 are provided, in which vertically extending strings of transistors and / or memory cells will be formed. The two memory array regions 12 may have identical or different configurations relative to each other. In one embodiment, a stepped region 13 is located between the memory array regions 12 and includes a stepped structure as described below. Alternatively, for example, the stepped region may be located at the end of a single memory array region (not shown). For clarity of disclosure, Figures 6 to 8 and Figures 1 to 5 Compared to different and varying proportions, the stepped region 13 is more relevant than the memory array region 12. Example configuration 10 includes a substrate 11 having any one or more of the following: conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, or insulating / insulator / insulating (i.e., electrical in this context) materials. Various materials have been vertically formed on the substrate 11. The materials may be located on... Figures 1 to 8 The material described may be located beside, vertically inside, or vertically outside the substrate. For example, other parts of the integrated circuit system or fully fabricated components may be disposed above, around, or inside the substrate 11. Control and / or other peripheral circuitry systems for components within an array (e.g., individual array regions 12) of vertically extending strings of memory cells may also be fabricated and may or may not be located entirely or partially within the array or subarray. Furthermore, multiple subarrays may be fabricated and operated independently, collaboratively, or otherwise relative to each other. In this document, "subarray" may also be considered as an array.

[0018] Including conductive material 17 (e.g., WSi under conductive doped polycrystalline silicon).x A conductive layer 16 is located above the substrate 11. The conductive layer 16 may include portions of a control circuitry (e.g., peripheral array under-circuitry and / or common source line or board) for controlling read and write access to transistors and / or memory cells in the array 12. A vertical stack 18 comprising alternating vertical insulating layers 20 and conductive layers 22 is located directly above the conductive layer 16 and extends along a first direction 55 from one of the memory array regions 12 into a stepped region 13. In some embodiments, the conductive layer 22 may be referred to as the first layer 22 and the insulating layer 20 as the second layer 20, wherein at least in the finished circuitry configuration, the first layer 22 is conductive and the second layer 20 is insulating. An example thickness of each of layers 20 and 22 is 20 to 60 nanometers. An example of the highest layer 20 may be thicker / the thickest compared to one or more other layers 20 and / or 22. Example first layer 22 includes material 26 (in one embodiment, it at least primarily includes a sacrificial material [e.g., silicon nitride] and in some embodiments, it is referred to as a first sacrificial material), and example second layer 20 includes insulating material 24 (e.g., silicon dioxide). Figures 2 to 8 The figures and other diagrams show only a small number of layers 20 and 22, but it is more likely that stack 18 includes dozens, hundreds, or more layers 20 and 22. Other circuitry, which may or may not be part of the peripheral and / or control circuitry, may be located between conductor layers 16 and stack 18. For example, multiple vertically alternating layers of conductive and insulating material in this circuitry may be located below the lowest of the conductive layers 22 and / or above the highest of the conductive layers 22. For example, one or more select gate layers (not shown) may be located between conductor layers 16 and the lowest conductive layer 22, and one or more select gate layers may be located above the highest of the conductive layers 22 (not shown). Alternatively or additionally, at least one of the depicted highest and lowest conductive layers 22 may be a select gate layer. The circuitry may also be located directly below stack 18, for example, in… Figures 6 to 8 In this circuit system, an example of a conductive landing pad in insulating material 24 is indicated by the numeral 74. Examples of this circuit system may include array-based CMOS circuit systems or other control circuit systems, the details of which are not important to this invention.

[0019] The channel opening 25 is formed (e.g., by etching) through the insulating layer 20 and the conductive layer 22 to the conductor layer 16. The channel opening 25 may taper radially inward and / or radially outward (not shown) to extend deeper into the stack 18. In some embodiments, the channel opening 25 may enter the conductor material 17 of the conductor layer 16 (as shown) or may stop on top of the conductor material 17 (not shown). Alternatively, as an example, the channel opening 25 may stop on top of or inside the lowest insulating layer 20. The reason for extending the channel opening 25 at least to the conductor material 17 of the conductor layer 16 is to ensure direct electrical coupling of the channel material to the conductor layer 16 without the need for alternative processes and structures to do so when this connection is desired, and / or to provide an anchoring effect to the material located within the channel opening 25. An etch-stop material (not shown) may be located inside or on top of the conductor material 17 of the conductor layer 16 to facilitate stopping the etching of the channel opening 25 relative to the conductor layer 16 when desired. This etch-stop material may be sacrificial or non-sacrificial. For example, and for simplicity, the channel openings 25 are shown as groups or columns arranged in staggered rows of four and five openings 25 per row, and arranged in laterally spaced memory block regions 58, which will include laterally spaced memory blocks 58 in the finished circuit system construction. In this document, "block" generally includes "sub-block". The memory block regions 58 and the resulting memory blocks 58 (not shown) can be considered, for example, as extending and oriented longitudinally along a first direction 55, wherein a second direction 99 is orthogonal to the first direction 55. Any alternative existing or future-developed arrangements and constructions may be used.

[0020] Transistor channel material can be formed vertically along the insulating and conductive layers in individual channel openings, thus forming individual channel material strings, which are directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of an example memory array under formation may include a gate region (e.g., a control gate region) and a memory structure laterally located between the gate region and the channel material. In one embodiment, the memory structure is formed to include a charge-blocking region, a storage material (e.g., a charge storage material), and an insulating charge channel material. The storage material of the individual memory cell (e.g., a floating gate material, such as doped or undoped silicon, or a charge-trapping material, such as silicon nitride, a metal point, etc.) is vertically along the individual in the charge-blocking region. The insulating charge channel material (e.g., a bandgap engineered structure having a nitrogen-containing material [e.g., silicon nitride] sandwiched between two insulating oxides [e.g., silicon dioxide]) is laterally located between the channel material and the storage material.

[0021] The figure illustrates one embodiment in which charge blocking material 30, storage material 32, and charge channel material 34 are vertically formed along insulating layer 20 and conductive layer 22 in individual channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed, for example, by depositing their respective thin layers on the stack 18 and within the individual channel openings 25, and then at least planarizing this thin layer back to the top surface of the stack 18, as shown.

[0022] Channel material 36 is also formed vertically along insulating layer 20 and conductive layer 22 in channel opening 25 and constitutes individual channel material strings 53. In one embodiment, memory cell materials (e.g., 30, 32, and 34) are present along insulating layer 20 and conductive layer 22, and material 24 in insulating layer 20 is horizontally located between adjacent channel material strings 53. In some figures, due to scale, materials 30, 32, 34, and 36 are collectively shown and designated only as material 37. Example channel material 36 comprises a suitably doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). The example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 angstroms. A punch etching can be performed as shown to remove materials 30, 32, and 34 from the substrate of the channel opening 25 to expose the conductor layer 16, such that the channel material 36 (channel material string 53) is directly electrically coupled to the conductor material 17 of the conductor layer 16. This punch etching can occur individually with respect to each of materials 30, 32, and 34 (as shown) or can occur jointly with respect to all materials 30, 32, and 34 after the deposition of material 34 (not shown). Alternatively, and by way of example only, punch etching can be omitted and the channel material 36 can be directly electrically coupled to the conductor material 17 of the conductor layer 16 via individual conductive interconnects (not shown). The channel opening 25 is shown to include a radially central solid dielectric material 38 (e.g., spin-coated dielectric, silicon dioxide, and / or silicon nitride). Alternatively, and by way of example only, the radially central portion within the channel opening 25 may contain void spaces (not shown) and / or have no solid material (not shown).

[0023] refer to Figure 1 and 6In one embodiment, cavity 66 is formed in stepped region 13 within stack 18 and individually constitutes a stepped structure as described below. Example cavities 66 are longitudinally end-to-end aligned in individual memory block regions 58 and have apexes 81 between adjacent cavities 66 (e.g., cavities 66 are spaced apart from each other in a first direction 55 by apexes 81). Alternatively, only a single cavity may be located in an individual memory block region 58 (not shown). However, some method and structural embodiments involve the fabrication of only a single cavity 66 and the resulting construction having only a single cavity 66. Cavities 66 are shown as rectangular in horizontal cross-section, but several other shapes may be used and they do not all need to have the same shape relative to each other. For simplicity, with Figure 7 and 8 In comparison, Figure 3 and 5 Fewer layers 20 and 22 are shown, where, for clarity and to better emphasize the instance processing / aspects associated with the structure in instance cavity 66, Figure 7 and 8 The text discusses more aspects, including sections 20 and 22.

[0024] Cavity 66 individually includes a stair section 67 of a staircase 70 extending along a first direction (e.g., 55). A mirror-image stair section (not shown) of staircase 70 may be opposite stair section 67, having a platform (not shown) therebetween, and together considered to constitute a stepped structure. Individual staircase 70 includes treads 75 and risers 85. Individual treads 75 include a first sacrificial material 26 as a target first layer T (e.g., such target first layers 22 are those layers marked within individual treads 75 for subsequent direct electrical coupling with conductive pathways, as described below). Cavity 66 having stair section 67 and mirror-image opposite stair sections can be formed by any of existing or later-developed methods. As an example, a masking material (e.g., an optical imaging material, such as a photoresist) may be formed on top of stack 18, and an opening may be formed through the masking material. The masking material may then be used as a mask when (e.g., anisotropically) etched through the opening to extend it into at least two outermost layers 20, 22. Next, the resulting structure can be etched with a series of alternating transverse trimming etchings of a masking material, and then etched deeper into the stack 18 using a trimmed masking material with progressively widening openings as a mask, at least two layers 20, 22 at a time. This example can result in the formation of a stair section 67 into the stack 18 comprising alternating vertical layers 20, 22 of different compositional materials 24, 26, and result in the formation of another stair section opposite to stair section 67 (also not shown). There may be more stair 70s in stair section 67 than shown. Example stair 70s in stack 18 are individually shown as comprising a first layer 22 and a second layer 20 (the order may be reversed and not shown). More first and second layers may be used per stair 70, for example if multiple treads are formed per stair (e.g., along a second direction 99 and not shown). Furthermore, the horizontal depth of the tread 75 in direction 55 and the vertical height of the riser 85 may be equal to or different from each other. Segment 67 and its counterpart may be translated (etched) together into the stack 18 more deeply, and / or one of segments 67 or its counterpart may be masked at the same time, depending on the circuit system being manufactured.

[0025] In one example, one of two opposing stair sections 67 (and said one is not shown) is operable (e.g., stair section 67 in this example), and the other of the two opposing stair sections is dummy in the finished circuit system construction. In this document, the staircase of the "dummy" stair section is circuitically inoperable, where no current flows in the conductive material of the step and it can be a dead end of circuit inoperability, even if it extends to or from electronic components, the dead end is not part of the current flow path of the circuit. When inoperable, the operable and inoperable positions relative to the stair section can, of course, be reversed. Multiple operable stair sections and multiple dummy stair sections can be formed in multiple cavities 66, for example, longitudinally end-to-end (as shown) and to different depths within the stack 18. Several pairs of opposing mirror-image operable stair sections and dummy stair sections can be considered as defining a grandstand (e.g., a vertical recessed portion of an opposing stair section having a staircase). Alternatively, only a single stair section can be formed in one or more individual cavities 66. Regardless, cavity 66 can be formed before or after forming the channel material string 53. Cavity 66 can be considered as having a transversely outermost wall 71 (relative to the second direction 99) and 88 (relative to the first direction 55), wherein the riser 85, as part of the individual staircase 70, together with the sidewall 88, is actually part of the sidewall of cavity 66 along the second direction 99, wherein the sidewall 71 is along the first direction 55. The sidewalls 71, 88 and / or the riser may taper laterally inward or outward, thereby moving deeper into the stack 18 (not shown).

[0026] refer to Figure 9 and 10 In one embodiment, a layer of the insulating material 24 has been removed, thereby the tread surface 75 and the riser surface 85 now individually include a first sacrificial material 26 on top of the insulating material 24.

[0027] See Figure 11 and 12 In one embodiment, material ions have been implanted into Figure 9 and 10A second sacrificial material 64 is formed in the first sacrificial material 26 of the tread 75, whereby the second sacrificial material 64 has a composition different from that of the first sacrificial material 26 (e.g., to alter the etching properties relative to each other). For example, and by way of example only, in the case where the first sacrificial material 26 is stoichiometric silicon nitride, an example implant material is atomic carbon to form a silicon carbonitride material, whereby phosphoric acid or HF can be used to selectively etch material 26 relative to material 64. By way of example only, this is only one example of forming a staircase (e.g., 70) that individually includes treads (e.g., 75) in which a second sacrificial material (e.g., 64) is formed in one of the first layers 22 (e.g., the target first layer T of tread 75 for subsequent electrical connection thereto), the second sacrificial material having a composition different from that of the first sacrificial material (e.g., 26). For clarity, the following primarily refers only to the processing associated with a single tread 75, where it should be understood that this processing and the resulting structure may occur with respect to multiple treads.

[0028] refer to Figures 13 to 15 The remaining volume of cavity 66 has been filled with insulating material 76 (e.g., spin-coated dielectric). Thereafter, opening 77 has been formed in tread 75 through the second sacrificial material 64 and the vertically alternating first and second layers 22 and 20 located directly below the second sacrificial material 64 (and through insulating material 76, if present). Opening 77 may taper laterally inward and / or outward in a vertical cross-section (not shown). As shown, opening 77 may extend to material located directly below stack 18 (e.g., to materials 24 and 74 in the depicted example). Thereafter, and in one embodiment, a third sacrificial material 69 having a different composition from the second sacrificial material 64 has optionally been formed through opening 77 directly against the target first layer T of tread 75 against the second sacrificial material 64 (e.g., by exposure to an oxidant, thereby forming SiO from silicon carbonitride material 64). x 69).

[0029] In one embodiment, an insulating ring is formed circumferentially around the opening 77 in an individual of the first layer 22 located directly below the target first layer T on the tread surface 75. (See reference...) Figures 16 to 18In one embodiment, a first sacrificial material 26 in an individual first layer 22 directly beneath the target first layer T of the tread surface 75 has been radially recessed through the opening 77 (e.g., by selective etching; for example, if material 26 is silicon nitride and the other exposed material is silicon dioxide, then phosphoric acid or HF is used). Subsequently, an insulating ring 72 can be formed circumferentially around the opening 77 in the individual first layer 22 directly beneath the target first layer T of the tread surface 75 (e.g., in a radial recess in the individual first layer 22 directly beneath the target first layer T of the tread surface 75 as a result of the radial recess). The insulating material 79 (e.g., silicon dioxide) of the insulating ring 72 can be used to line the sidewalls 78 of the opening 77. The remaining volume of the opening 77 can then be filled with a sacrificial material 80 (e.g., polysilicon).

[0030] In array region 12 and step region 13, the first sacrificial material 26 and the second sacrificial material 64 are removed from the first layer 22. For example, and by way of example only, Figures 19 to 24 A horizontally elongated trench 40 is shown as having been formed between laterally adjacent memory block regions 58 (e.g., by anisotropic etching). The trench 40 is typically wider than the channel opening 25 (e.g., 3 to 10 times wider). The trench 40 may have a corresponding bottom (as shown) directly abutting the conductor material 17 of the conductor layer 16 (e.g., on top or inside), or may have a corresponding bottom located above the conductor material 17 of the conductor layer 16 (not shown). The trench 40 may taper laterally inward and / or outward in a vertical cross-section (not shown). Subsequently, the first sacrificial material 26 of the first layer 22 (not shown) is removed, for example by selectively etching it isotropically through the trench 40 relative to other exposed materials, ideally (e.g., using liquid or vapor H3PO4 as the primary etchant, where material 26 is silicon nitride and other materials include one or more oxides or polysilicon). In one embodiment and as shown, the first sacrificial material 26 (not shown) has been selectively etched relative to the second sacrificial material 64 and the insulating material 24 (and the insulating ring 72, when present) (e.g., if the second sacrificial material 64 is silicon carbonitride, then the above-described H3PO4 is used as the primary etchant).

[0031] refer to Figures 25 to 27 The second sacrificial material 64 (not shown) has been selectively etched relative to the insulating material 24 (and the insulating ring 72, when present). An example of an etching chemical reaction used to etch silicon carbonitride material in this way is a vapor-phase etching using a combination of NF3, SF6, HF, H2 and O2 plus N2 or Ar as a pressure control gas.

[0032] refer to Figures 28 to 37Conductive material 48 has been formed in the first layer 22 and extends from the array region 12 into the stepped region 13. Subsequently, conductive material 48 has been removed from the trench 40, thus forming individual conductive lines 29 (e.g., word lines) in the stack 18 and vertically extending strings 49 of individual transistors and / or memory cells 56 in the stack 18. In one embodiment and as shown, after the removal of the first sacrificial material 26 and the second sacrificial material 64 and before the formation of the conductive material 48, an insulating material 19 (in...) has been used... Figures 31 to 33 And 36 are displayed as blank / white layers, and this is due to the scale. Figure 29 , 30 (Only lines 34, 35, and 37 are shown as thick lines) are added as a lining on the first layer 22, wherein conductive material 48 is formed on insulating material 19. Insulating material 19 has a higher dielectric constant than insulating material 24 (e.g., at least twice as high). (For example, compared to SiO2 as material 24 having a dielectric constant of 3 to 4, AlO2 as material 19 has a higher dielectric constant.) x It has a dielectric constant of 9 to 10.

[0033] The approximate locations of transistors and / or memory cells 56 are indicated in brackets in some figures and in dashed outlines in others, wherein in the depicted examples, transistors and / or memory cells 56 are substantially ring-shaped or annular. Alternatively, transistors and / or memory cells 56 may not completely surround individual channel openings 25, such that each channel opening 25 may have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells surrounding individual channel openings in individual conductive layers, wherein each channel opening may have multiple word lines in individual conductive layers, and not shown). Conductive material 48 can be considered as having terminals 50 corresponding to control gate regions 52 of individual transistors and / or memory cells 56. In the depicted embodiment, control gate regions 52 include individual portions of individual conductive lines 29. Materials 30, 32, and 34 can be considered as memory structures 65 laterally located between control gate regions 52 and channel materials 36. In one embodiment, and as shown with respect to the example “post-gate” processing, the conductive material 48 of the conductive layer 22 is formed after the channel opening 25 and / or trench 40 is formed. Alternatively, for example with respect to the “pre-gate” processing, the conductive material of the conductive layer (not shown) may be formed before the channel opening 25 and / or trench 40 is formed.

[0034] A charge blocking region (e.g., charge blocking material 30) is located between the storage material 32 and the individual control gate region 52. The charge block in the memory cell may function to prevent charge carriers from transferring from the storage material (e.g., floating gate material, charge trapping material, etc.) toward the control gate in programming mode, and to prevent charge carriers from flowing from the control gate into the storage material in erase mode. Therefore, the charge block can be used to block charge migration between the control gate region and the storage material of an individual memory cell. As shown in the example, the charge blocking region includes an insulating material 30. As a further example, the charge blocking region may include a lateral (e.g., radial) outer portion of the storage material (e.g., material 32), wherein this storage material is insulating (e.g., in the case where there is a lack of any material of different composition between the insulating storage material 32 and the conductive material 48). However, as an additional example, in the absence of any separately composed insulating material 30, the interface between the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region. Furthermore, the interface combination of conductive material 48 and material 30 (when present) with insulating material 30 can be used together as a charge blocking region, and alternatively or additionally as a lateral outer region of an insulating storage material (e.g., silicon nitride material 32). Example material 30 is one or more of hafnium oxide and silicon dioxide.

[0035] Intermediate material 57 is formed in trench 40 and thus laterally positioned between laterally adjacent memory blocks 58 and longitudinally along the laterally adjacent memory blocks 58 (material 57 is not shown in the trench 40 in the stepped area for simplicity). Intermediate material 57 can provide lateral electrical isolation (insulation) between laterally adjacent memory blocks. This can include one or more of insulating, semiconductive, and conductive materials, and in any case, can facilitate shorting of conductive layers 22 relative to each other in the finished circuit system construction. Examples of insulating materials are one or more of SiO2, Si3N4, and Al2O3. Intermediate material 57 can contain through-array pathways (not shown).

[0036] refer to Figures 38 to 41 A masking and / or hard masking material 90 has been formed on top of the structure 10, and an opening is formed through the masking and / or hard masking material 90 to the opening 77. Next, sacrificial material 80 (when in use and not shown) has been removed from the opening 77 (e.g., by selective etching). Thereafter, etching is performed from the liner through the insulating material 79 (in one embodiment, when in use) across the entire opening 77. Subsequently, as the insulating material 19 (when present) has been removed / etched, a third sacrificial material 69 (when present and not shown) has been removed / etched through the opening 77 to expose the conductive material 48 in the target first layer T of the tread surface 75.

[0037] refer to Figures 42 to 45Conductive pathway 84 is formed within opening 77 to material located directly beneath stack 18 (e.g., materials 24 and 74 in the depicted example). Conductive pathway 84 includes conductive material 86, which is directly electrically coupled to conductive material 48 of the target first layer T of tread 75 and extends from directly above the target first layer T, through the target first layer T, and directly below the target first layer T to the material located directly beneath stack 18.

[0038] In one embodiment, and as shown, the conductive material 48 of the target first layer T of the tread 75 is formed directly above the insulating ring 72 (when present), which is located in the first layer 22 immediately below the target first layer T of the tread 75 (by definition, no first layer 22 is vertically located between the target first layer T of the tread 75 and the first layer 22 immediately below the target first layer T of the tread 75). In one embodiment, and as shown, the conductive material 86 of the conductive path 84 is located in that portion of the target first layer T (e.g., Figure 44 95) is formed above the conductive material 48 in the first layer 22 that is not located directly below the target first layer T on the tread surface 75.

[0039] In one embodiment and as shown, the insulating material 19 in the target first layer T of the tread 75 having the second sacrificial material 64 (e.g., the target first layer T for the tread 75) is laterally closer to the conductive path 84 than the insulating material 19 in the first layer 22 immediately below the target first layer T of the tread 75.

[0040] Alternative embodiments may be constructed using the method embodiments described above or otherwise. In any case, embodiments of the invention cover memory arrays independent of manufacturing methods. However, such memory arrays may have any of the properties described herein in the method embodiments. Similarly, the method embodiments described above may incorporate, form, and / or have any of the properties described with respect to the device embodiments.

[0041] In one embodiment, an integrated circuit system (e.g., 10) includes a stack (e.g., 18) comprising vertically alternating insulating layers (e.g., 20) and conductive layers (e.g., 22) extending from an array region (e.g., 12) into a stepped region (e.g., 13). The stepped region includes a stair section (e.g., 70) containing treads (e.g., 75). Individual treads include a target conductive layer (e.g., T) that is one of the conductive layers. A conductive path (e.g., 84) extends from directly above one of the individual treads, through one of the individual treads, and directly below one of the individual treads to the bottom of the stack (e.g., 98). The conductive path includes a conductor material (e.g., 86) directly electrically coupled to the conductive material (e.g., 48) of the target conductive layer of the individual tread. The conductive path extends through the conductive material of the conductive layer located directly below the individual tread. An insulating ring (e.g., 72) circumferentially surrounds the conductive path in one of the conductive layers located directly beneath the individual tread surfaces. The insulating ring is laterally positioned between the conductive path and the conductive material in the individual conductive layer located directly beneath the individual tread surface. The conductive material of the target conductive layer of the individual tread surface is located directly above the insulating ring in the conductive layer immediately beneath the individual tread surface.

[0042] In one embodiment, and as shown, the conductive material of the individual tread is located directly above the insulating ring in each of the conductive layers beneath the individual tread. In one embodiment, the insulating layer primarily comprises an insulating material (e.g., 24), wherein the insulating ring and the insulating material have the same composition relative to each other.

[0043] In one embodiment, the insulating layer primarily comprises an insulating material and an insulating material (e.g., 19), the insulating material having a higher dielectric constant than the insulating material and located directly above and below the conductive material in an individual conductive layer. The insulating material in the conductive layer of the target conductive layer of the individual tread is laterally closer to the conductive path than the insulating material in the conductive layer immediately below the individual tread.

[0044] In one embodiment, the portion of the conductive material of the conductive path located in the target conductive layer (e.g., 95) is not directly above the conductive material in the conductive layer immediately below the target conductive layer of the individual tread surface. In one embodiment, the integrated circuit system includes a memory circuit system and the array region includes an array of memory cells (e.g., 56), the memory cell array including a string of channel material (e.g., 53) extending through the stack in the array region.

[0045] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0046] exist Figures 42 to 45 In one embodiment, the conductive path 84 may be considered to include a vertically extending portion 96 through the stack, wherein the conductor material 86 protrudes radially from the vertically extending portion 96 of the conductive path 84 into the target conductive layer T of the individual tread surface. Figures 46 to 48 Alternative integrated circuit system 10a is shown. Where appropriate, similar numbers to those used in the embodiments described above have been used, with some construction differences indicated by the suffix "a" or different numbers. Here, the conductor material 86 does not radially protrude from the vertical extension 96 of the conductive path 84 into the target conductive layer T of the individual tread surface. This can be achieved, by way of example only, without forming a third sacrificial material 69. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0047] In one embodiment, an integrated circuit system (e.g., 10) includes a stack (e.g., 18) comprising vertically alternating insulating layers (e.g., 20) and conductive layers (e.g., 22) extending from an array region (e.g., 12) into a stepped region (e.g., 13). The stepped region includes a stair section (e.g., 70) containing treads (e.g., 75). Individual treads include a target conductive layer (e.g., T) that is one of the conductive layers. A conductive path (e.g., 84) extends from directly above one of the individual treads, through one of the individual treads, and directly below one of the individual treads to the bottom of the stack (e.g., 98). The conductive path includes a conductor material (e.g., 86) directly electrically coupled to the conductive material (e.g., 48) of the target conductive layer of the individual tread. The conductive path extends through the conductive material of the conductive layer located directly below the individual tread. The portion of the conductive material of the conductive path located in the target conductive layer (e.g., 95) is not directly above the conductive material in the conductive layer immediately below the target conductive layer of the individual tread surface. In one embodiment, the conductive material 86 protrudes radially from the vertical extension 96 of the conductive path 84 into the target conductive layer T of the individual tread surface. Figures 42 to 45 In alternative embodiments of this kind, the conductor material 86 does not protrude radially from the vertical extension 96 of the conductive path 84 into the target conductive layer T of the individual tread surface. Figures 46 to 48 Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0048] In one embodiment, an integrated circuit system (e.g., 10) includes a stack (e.g., 18) comprising vertically alternating insulating layers (e.g., 20) and conductive layers (e.g., 22) extending from an array region (e.g., 12) into a stepped region (e.g., 13). The stepped region includes a stair section (e.g., 70) containing treads (e.g., 75). Individual treads include a target conductive layer (e.g., T) that is one of the conductive layers. The insulating layers comprise an insulating material (e.g., 24). An insulating material (e.g., 19) having a higher dielectric constant than the insulating material is located directly above and below a conductive material (e.g., 48) in an individual conductive layer. A conductive path (e.g., 84) extends from directly above, through, and below an individual tread to the bottom of the stack (e.g., 98). The conductive path includes a conductor material (e.g., 86) directly electrically coupled to the conductive material of the target conductive layer of the individual tread. The conductive path extends through the conductive material of the conductive layer located directly beneath the individual tread. The insulating material in the conductive layer of the target conductive layer of the individual tread is laterally closer to the conductive path than the insulating material in the conductive layer directly beneath the individual tread. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0049] The treatment described herein can reduce the thinning of insulating material 24 in insulating layer 20, although this is not required. Moreover, providing conductive material 48 and associated insulating material 19 (when used) can provide improved electrical isolation when desired, although this is not required, due to the higher dielectric constant of material 19 compared to materials 24, 79 and 72.

[0050] The memory circuitry described herein (e.g., its conductive paths) can be connected to circuitry located at the top or bottom of a stack (i.e., either z-axis side), regardless of the configuration orientation in three-dimensional space and not important to the aspects of the invention disclosed herein. For example, and by way of example only, conductive paths can be connected to peripheral control circuitry located below the stack relative to the orientation shown in the figures. As an alternative example, and by way of example only, conductive paths can be connected to peripheral control circuitry located above the stack relative to the shown orientation, for example, to another substrate having this circuitry and engaging with the top of the stack relative to the shown orientation. In this alternative example, the configuration can be reversed from the shown orientation and then engaged with another substrate. Furthermore, in this alternative example, source lines or boards can be fabricated relative to the bottom of the stack relative to the shown orientation, but reversed from the shown orientation during processing. Such source lines or boards can be connected to conductive paths extending through the stack to an engagement with the other side having this peripheral control circuitry. In any case, the configurations shown and described herein can be processed, packaged, and / or mounted in any three-dimensional orientation.

[0051] (Several) of the above processing or (several) constructions can be considered relative to an array of components formed as a single stack or single layer of such components above or as part of an underlying substrate, or formed within such a single stack or single layer (although a single stack / layer may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., under-array CMOS). In any case, one or more additional stacks / layers of this type may be disposed or fabricated above and / or below the locations shown in the figures or described above. Furthermore, (several) arrays of components may be the same or different from each other in different stacks / layers, and the different stacks / layers may have the same or different thicknesses relative to each other. Intermediate structures may be disposed vertically adjacent to the stacks / layers (e.g., additional circuitry and / or dielectric layers). Moreover, the different stacks / layers may be electrically coupled relative to each other. Multiple stacks / layers can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / layers can be manufactured substantially simultaneously.

[0052] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can include multi-layered, multi-chip modules. Electronic systems can be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting devices, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0053] In this document, unless otherwise indicated, “vertical,” “higher,” “up,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” means a direction along the general direction of the substrate surface (i.e., within 10 degrees) and relative to the direction in which the substrate is handled during manufacturing and as shown in the accompanying drawings (if any), while vertical is generally orthogonal to the horizontal. The reference to “fully horizontal” is along the direction of the substrate surface (i.e., not at an angle to the substrate surface) and relative to the direction in which the substrate is handled during manufacturing. Furthermore, as used herein, “vertical” and “horizontal” generally refer to directions perpendicular to each other and are independent of the orientation of the substrate in three-dimensional space during manufacturing and / or in the finished product construction. Additionally, “elevationally-extending” and “extend(ing)elevationally” mean a direction at an angle of at least 45° to fully horizontal. Furthermore, this refers to the orientation of the transistor channel length along which the reference current flows between the source / drain regions during operation, relative to the field-effect transistor's "extending elevationally," "elevationally-extending," "extending horizontally," "horizontally-extending," and similar terms. For a bipolar junction transistor, this refers to the orientation of the base length along which the reference current flows between the emitter and collector during operation, relative to the field-effect transistor's "extending elevationally," "elevationally-extending," "extending horizontally," "horizontally-extending," and similar terms. In some embodiments, any vertically extending component, feature, and / or region extends vertically or within a vertical 10°.

[0054] Furthermore, the phrases "directly above," "directly below," and "directly under" require that the two described areas / materials / components have at least some lateral (i.e., horizontal) overlap relative to each other. Moreover, the use of "above" without the preceding "direct" only requires that a portion of the described area / material / component located above another described area / material / component is vertically outside the other described area / material / component (i.e., regardless of whether there is any lateral overlap between the two described areas / materials / components). Similarly, the use of "below" and "under" without the preceding "direct" only requires that a portion of the described area / material / component located below / under another described area / material / component is vertically inside the other described area / material / component (i.e., regardless of whether there is any lateral overlap between the two described areas / materials / components).

[0055] Any of the materials, regions, and structures described herein may be homogeneous or heterogeneous, and in any event may be continuous or discontinuous on any material to which they are superimposed. Where one or more example components are provided for any material, that material may comprise, consist substantially of, or be composed of such one or more components. Furthermore, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, among which atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation are examples.

[0056] Additionally, “thickness” itself (without a directional adjective) is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions of different compositions through a given material or region. Additionally, the various materials or regions described herein may have substantially constant thickness or variable thickness. If variable thickness is present, then unless otherwise indicated, the thickness refers to the average thickness, and due to the variable thickness, the material or region will have a minimum thickness and a maximum thickness. As used herein, “different compositions” requires only that the portions of two stated materials or regions that may be in direct contact with each other are chemically and / or physically different, for example, provided that such materials or regions are not homogeneous. If two stated materials or regions are not in direct contact with each other, then “different compositions” requires only that the portions of two stated materials or regions that are closest to each other are chemically and / or physically different, provided that such materials or regions are not homogeneous. In this document, a stated material, region, or structure is “in direct contact” with another material, region, or structure when there is at least some physical contact between them. Conversely, the words “on top of,” “on,” “near,” “along,” and “against” without the preceding “direct” encompass “direct abutment” and constructions in which (some) intermediate materials, (some) areas, or (some) structures result in the stated materials, areas, or structures not being in physical contact with each other.

[0057] In this document, if current can flow continuously from one zone-material-component to another during normal operation and, when sufficient subatomic positive and / or negative charges are generated, the flow is primarily through the movement of said subatomic positive and / or negative charges, then the zone-material-components are “electrically coupled” relative to each other. Another electronic component may be located between and electrically coupled to the zone-material-components. In contrast, when zone-material-components are referred to as “directly electrically coupled,” no intermediate electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) are located between the directly electrically coupled zone-material-components.

[0058] In this document, any use of the terms "row" and "column" is for the purpose of distinguishing a series or one orientation of features from another series or another orientation of features, and which have been or may form components along said "row" and "column". "Row" and "column" are used synonymously with any series of areas, components, and / or features, and are not related to function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel, and columns may be as well. Furthermore, rows and columns may intersect each other at 90° or one or more other angles (i.e., other than right angles).

[0059] The composition of any of the conductive / conductor / conductive materials mentioned herein may be conductive metallic materials and / or conductive doped semiconducting / semiconductor / semiconductive materials. "Metallic material" is any elemental metal, any mixture or alloy of two or more elemental metals, and any one or more metallic compounds or combinations thereof.

[0060] In this document, any use of “selective” in relation to etch, etching, removing, removal, deposition, forming, and / or formation is an action in which a stated material acts relative to another stated material(s) at a volume ratio of at least 2:1. Furthermore, any use of selective deposition, selective growth, or selective formation is the deposition, growth, or formation of a material relative to another stated material(s) at a volume ratio of at least 2:1 for at least the first 75 angstroms of the deposition, growth, or formation.

[0061] Unless otherwise indicated, the use of "or" in this document covers either or both.

[0062] in conclusion

[0063] In some embodiments, a method for forming an integrated circuit system includes forming a stack comprising vertically alternating first and second layers extending from an array region into a stepped region. The first layer comprises a first sacrificial material and the second layer comprises an insulating material. The stepped region comprises a stair section. The stair section individually includes a tread comprising a second sacrificial material that is a target first layer, which is one of the first layers. The second sacrificial material has a composition different from that of the first sacrificial material. An opening is formed in the tread, extending downward through the second sacrificial material and directly beneath the vertically alternating first and second layers. The first and second sacrificial materials are removed from the first layers in the array region and the stepped region. After removal, a conductive material is formed in the first layer and extending from the array region into the stepped region. A conductive path is formed within the opening to a material directly beneath the stack. The conductive path is directly electrically coupled to the conductive material of the target first layer of the tread and extends from directly above the target first layer, through the target first layer, and directly beneath the target first layer into the material directly beneath the stack.

[0064] In some embodiments, an integrated circuit system includes a stack comprising vertically alternating insulating and conductive layers extending from an array region into a stepped region. The stepped region includes a stair section containing treads. Individual treads include a target conductive layer that is one of the conductive layers. A conductive path extends from directly above one of the individual treads, through one of the individual treads, and directly below one of the individual treads to the bottom of the stack. The conductive path includes a conductive material directly electrically coupled to a conductive material of the target conductive layer of the individual tread. The conductive path extends through the conductive material of the conductive layer located directly below the individual tread. An insulating ring circumferentially surrounds the conductive path in one of the conductive layers located directly below the individual tread. The insulating ring is laterally positioned between the conductive path and the conductive material of the individual conductive layer located directly below the individual tread. The conductive material of the target conductive layer of the individual tread is located directly above the insulating ring in the conductive layer immediately below the individual tread.

[0065] In some embodiments, an integrated circuit system includes a stack comprising vertically alternating insulating and conductive layers extending from an array region into a stepped region. The stepped region includes a stair section containing treads. Individual treads include a target conductive layer that is one of the conductive layers. A conductive path extends from directly above one of the individual treads, through one of the individual treads, and directly below one of the individual treads to the bottom of the stack. The conductive path includes a conductive material directly electrically coupled to the conductive material of the target conductive layer of the individual tread. The conductive path extends through the conductive material of the conductive layer located directly below the individual tread. The portion of the conductive material of the conductive path located in the target conductive layer is not directly above the conductive material of the conductive layer immediately below the target conductive layer of the individual tread.

[0066] In some embodiments, an integrated circuit system includes a stack comprising vertically alternating insulating and conductive layers extending from an array region into a stepped region. The stepped region includes a stair section containing treads. Individual treads include a target conductive layer that is one of the conductive layers. The insulating layers comprise an insulating material. An insulating material having a higher dielectric constant than the insulating material is located directly above and below the conductive material in the individual conductive layers. A conductive path extends from directly above, through, and below one of the individual treads to the bottom of the stack, the conductive path comprising a conductive material directly electrically coupled to the conductive material of the target conductive layer of the individual tread. The conductive path extends through the conductive material of the conductive layer located directly below the individual tread. The insulating material in the conductive layer of the target conductive layer of the individual tread is laterally closer to the conductive path than the insulating material in the conductive layer immediately below the individual tread.

[0067] In accordance with regulations, the subject matter disclosed herein has been described in language that is more or less specific to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims should be given full scope in accordance with their literal wording and properly interpreted according to the doctrine of equivalents.

Claims

1. A method for forming an integrated circuit system, comprising: A stack is formed, comprising vertically alternating first and second layers extending from an array region into a step region, the first layer comprising a first sacrificial material and the second layer comprising an insulating material, the step region comprising a stair section, the stair section individually comprising a tread comprising a second sacrificial material that is a target first layer as one of the first layers, the second sacrificial material having a composition different from that of the first sacrificial material; An opening is formed in the tread surface by the vertically alternating first and second layers passing downward through the second sacrificial material and located directly below the second sacrificial material; Remove the first sacrificial material and the second sacrificial material from the first layer in the array region and the stepped region; After the removal, a conductive material is formed in the first layer and extends from the array region into the stepped region; and Conductive pathways are formed within the opening to the material located directly beneath the stack. The conductive pathways include a conductor material that is directly electrically coupled to the conductive material of the target first layer of the tread and extends from directly above the target first layer, through the target first layer, and directly below the target first layer to the material located directly beneath the stack.

2. The method of claim 1, wherein the removal sequentially comprises: The first sacrificial material is selectively etched relative to the second sacrificial material and the insulating material; and The second sacrificial material is selectively etched relative to the insulating material.

3. The method according to claim 1, comprising, in sequence: Through the opening, a third sacrificial material with a composition different from that of the second sacrificial material is formed directly against the second sacrificial material in the target first layer of the tread surface; and The third sacrificial material is removed through the opening after the first and second sacrificial materials are removed and before the conductive path is formed.

4. The method according to claim 1, comprising: An insulating ring is formed circumferentially around the opening in one of the first layers located directly below the target first layer, which includes the second sacrificial material; and The conductive material of the target first layer of the tread is formed directly above the insulating ring in the first layer that is immediately below the target first layer of the tread.

5. The method of claim 4, wherein the removal sequentially comprises: The first sacrificial material is selectively etched relative to the second sacrificial material, the insulating material, and the insulating ring. and The second sacrificial material is selectively etched relative to the insulating material and the insulating ring.

6. The method of claim 4, further comprising: Through the opening and before forming the insulating ring, the first sacrificial material in the individual first layer located directly below the target first layer of the tread is radially recessed; and As a result of the radial recess, the insulating ring is formed in the radial recess of the individual first layer located directly below the target first layer of the tread.

7. The method of claim 4, further comprising lining the sidewall of the opening with the insulating material of the insulating ring.

8. The method of claim 7, wherein the insulating material passes through the entire stack and is lined to all the sidewalls of the opening.

9. The method of claim 8, further comprising removing the insulating material before forming the conductive path so that it cannot be lined throughout the opening.

10. The method of claim 1, further comprising forming the portion of the conductive material of the conductive path located in the target first layer not directly above the conductive material in the first layer immediately below the target first layer of the tread surface.

11. The method of claim 1, further comprising: After the removal and before the formation of the conductive material, the first layer is lined with an insulating material having a higher dielectric constant than the insulating material. The conductive material is formed on the insulating material; and The insulating material in the target first layer of the tread is laterally closer to the conductive path than the insulating material in the first layer immediately below the target first layer of the tread.

12. The method of claim 1, wherein the integrated circuit system includes a memory circuit system and the array region includes a memory cell array, the memory cell array including a string of channel material extending through the stack in the array region.

13. The method of claim 1, wherein the conductive pathway is formed to include a portion extending vertically through the stack, and the conductive material protruding radially from the vertically extending portion of the conductive pathway into the target conductive layer of the individual tread surface.

14. The method of claim 1, wherein the conductive pathway is formed to include a portion extending vertically through the stack, and the conductive material does not protrude radially from the vertically extending portion of the conductive pathway into the target conductive layer of the individual tread.

15. An integrated circuit system comprising: The stack comprises vertically alternating insulating and conductive layers extending from an array region into a stepped region, the stepped region comprising a stair section containing treads, each of the treads comprising a target conductive layer as one of the conductive layers. A conductive path extends from directly above one of the individual treads, through one of the individual treads, and directly below one of the individual treads to the bottom of the stack. The conductive path includes a conductive material that is directly electrically coupled to a conductive layer of the target conductive layer of the individual treads. The conductive path extends through the conductive material of the conductive layer located directly below the individual treads. An insulating ring circumferentially surrounds the conductive path in one of the conductive layers located directly beneath the individual tread surfaces, the insulating ring being laterally positioned between the conductive path and the conductive material in the individual conductive layer located directly beneath the individual tread surfaces; and The conductive material of the target conductive layer of the individual tread is located directly above the insulating ring in the conductive layer that is immediately below the individual tread.

16. The integrated circuit system of claim 15, wherein the conductive path includes a portion extending vertically through the stack, and the conductive material protrudes radially from the vertically extending portion of the conductive path into the target conductive layer of the individual tread surface.

17. The integrated circuit system of claim 15, wherein the conductive path includes a portion extending vertically through the stack, and the conductive material does not protrude radially from the vertically extending portion of the conductive path into the target conductive layer of the individual tread surface.

18. The integrated circuit system of claim 15, wherein the conductive material of the individual tread is located directly above the insulating ring in each of the conductive layers below the individual tread.

19. An integrated circuit system comprising: The stack comprises vertically alternating insulating and conductive layers extending from an array region into a stepped region, the stepped region comprising a stair section containing treads, each of the treads comprising a target conductive layer as one of the conductive layers. A conductive path extends from directly above one of the individual treads, through one of the individual treads, and directly below one of the individual treads to the bottom of the stack. The conductive path includes a conductive material that is directly electrically coupled to a conductive layer of the target conductive layer of the individual treads. The conductive path extends through the conductive material of the conductive layer located directly below the individual treads. and The portion of the conductive material of the conductive path located in the target conductive layer is not directly above the conductive material in the conductive layer immediately below the target conductive layer of the individual tread surface.

20. An integrated circuit system comprising: The stack comprises vertically alternating insulating and conductive layers extending from an array region into a stepped region, the stepped region comprising a stair section containing treads, each of the treads comprising a target conductive layer as one of the conductive layers. The insulating layer includes an insulating material, wherein an insulating material having a higher dielectric constant than the insulating material is located directly above and directly below the conductive material in an individual of the conductive layers. A conductive path extends from directly above one of the individual treads, through one of the individual treads, and directly below one of the individual treads to the bottom of the stack. The conductive path includes a conductive material that is directly electrically coupled to the conductive material of the target conductive layer of the individual treads. The conductive path extends through the conductive material of the conductive layer located directly below the individual treads. and The insulating material in the conductive layer of the target conductive layer of the individual tread surface is laterally closer to the conductive path than the insulating material in the conductive layer immediately below the individual tread surface.

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