Integrated circuit package and method of forming same

Abstract

Integrated circuit packages and methods of forming the same are provided. The integrated circuit package may include: a first redistribution structure; the first bridging pipe core is positioned above the first redistribution structure; a first encapsulant around the first bridging die; a second redistribution structure over the first bridging die and the first encapsulant; a first logic die, a second logic die, and a first input / output (I / O) die over the second redistribution structure; and a second encapsulant around the first logic die, the second logic die, and the first I / O die. The first I / O die may be between the first logic die and the second logic die in a top view. A first bridging die may electrically connect the first redistribution structure to the second redistribution structure. The first I / O die may electrically connect the first logic die to the second logic die.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuit packages and methods of forming the same. Background Technology

[0002] As semiconductor technology continues to advance, integrated circuit dies are becoming increasingly smaller. Furthermore, more functions are being integrated into the die. Consequently, the number of input / output (I / O) pads required for the die has increased, while the area available for I / O pads has decreased. Over time, the density of I / O pads has risen rapidly, thus increasing the difficulty of die packaging.

[0003] In some packaging technologies, integrated circuit dies are diced from the wafer before being packaged. An advantageous feature of this packaging technology is the possibility of forming fan-out packages, which allows the I / O pads on the die to be redistributed over a larger area. Therefore, the number of I / O pads on the die surface can potentially increase. Summary of the Invention

[0004] Some embodiments of this application provide an integrated circuit package, including: a first redistribution structure; a first bridging die located above the first redistribution structure; a first sealant located around the first bridging die; a second redistribution structure located above the first bridging die and the first sealant, wherein the first bridging die electrically connects the first redistribution structure to the second redistribution structure; a first logic die, a second logic die, and a first input / output die located above the second redistribution structure, wherein the first input / output die is located between the first logic die and the second logic die in a top view, and wherein the first input / output die electrically connects the first logic die to the second logic die; and a second sealant located around the first logic die, the second logic die, and the first input / output die.

[0005] Other embodiments of this application provide a method for forming an integrated circuit package, comprising: forming a first redistribution structure; placing a first bridge die over the first redistribution structure, wherein the first bridge die is electrically connected to the first redistribution structure; forming a second redistribution structure over the first bridge die, wherein the first bridge die is electrically connected to the second redistribution structure; attaching a first logic die, a second logic die, a first input / output die, and a second input / output die over the second redistribution structure, wherein the first input / output die is located between the first logic die and the second logic die in a top view; and forming an opening through the first redistribution structure and the second redistribution structure.

[0006] Further embodiments of this application provide a method for forming an integrated circuit package, comprising: forming a first redistribution structure; connecting a first bridge die to the first redistribution structure; forming a second redistribution structure above the first bridge die, wherein the first bridge die electrically connects the first redistribution structure to the second redistribution structure; connecting a first integrated circuit die cluster to the second redistribution structure, wherein the first integrated circuit die cluster includes a first logic die, a first memory die, and a first input / output die; and forming screw holes through the first redistribution structure and the second redistribution structure. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F Cross-sectional views of various integrated circuit dies according to some embodiments are shown.

[0009] Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 11A and Figure 11B Various views of intermediate steps during the process for forming an integrated circuit package are shown according to some embodiments.

[0010] Figure 12 , Figure 13 and Figure 14 Various views of intermediate steps during the process for forming an integrated circuit package are shown according to some embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0013] According to some embodiments, an integrated circuit package and a method of forming the same are provided. The package assembly may include a first wafer-level redistribution structure, a first integrated circuit die bonded above the first wafer-level redistribution structure, a second wafer-level redistribution structure above the first integrated circuit die, and a second integrated circuit die bonded above the second wafer-level redistribution structure. The first integrated circuit die may be electrically connected to the first and second wafer-level redistribution structures. The second integrated circuit die may be electrically connected to the second wafer-level redistribution structure. In the second integrated circuit die located within a computing region above the second wafer-level redistribution structure, some second integrated circuit dies may be logic dies, some second integrated circuit dies may be memory dies, and some second integrated circuit dies may be input / output (I / O) dies. The I / O dies within the computing region may facilitate communication between the logic dies and memory dies within the computing region. The first integrated circuit die may serve as a bridging die and also facilitate communication between the logic dies and memory dies within the computing region. Therefore, communication between the logic dies and memory dies within the computing region can be improved, thereby improving the performance of the integrated circuit package.

[0014] Figure 1AA cross-sectional view of an integrated circuit die 20 is shown. The integrated circuit die 20 can be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 20 may be an input / output (I / O) die, etc. The integrated circuit die 20 may include a semiconductor substrate 22. The semiconductor substrate 22 may include silicon, germanium, silicon-germanium, etc. The semiconductor substrate 22 may have a front side (e.g., Figure 1A The mid-side facing upwards) and the dorsal side (e.g., Figure 1A (The side facing downwards).

[0015] Devices (not shown) may be located on the front side of semiconductor substrate 22. Devices may be passive devices, such as capacitors, resistors, etc. Integrated circuit die 20 may not have active devices, such as transistors. A transistor may include a source region, a drain region, a channel region between the source and drain regions, and a gate structure on the channel region. Integrated circuit die 20 may include an interconnect structure 23 above the front side of semiconductor substrate 22, which may interconnect devices to form an integrated circuit. Interconnect structure 23 may include a dielectric layer 23A on semiconductor substrate 22 and a metallization pattern 23B in dielectric layer 23A. The metallization pattern 23B may be electrically connected to the devices.

[0016] The integrated circuit die 20 may also include a passivation layer 26 on the interconnect structure 23 and conductive pads 27 in the passivation layer 26. The conductive pads 27 may be physically and electrically connected to the metallization pattern 23B. The passivation layer 26 may include silicon nitride, silicon oxide, polyimide, etc. The conductive pads 27 may include copper, nickel, aluminum, etc., or combinations thereof. Conductive connectors 28 may be located on the conductive pads 27. The conductive connectors 28 may be solder, such as lead-free solder.

[0017] Figure 1B A cross-sectional view of an integrated circuit die 30 is shown. The integrated circuit die 30 can be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 30 can be a logic die, such as a processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc. The integrated circuit die 30 may include a semiconductor substrate 32. The semiconductor substrate 32 may include silicon, germanium, silicon-germanium, etc. The semiconductor substrate 32 may have a front side (e.g., Figure 1B The mid-side facing upwards) and the dorsal side (e.g., Figure 1B (The side facing downwards).

[0018] Device 31 may be located on the front side of semiconductor substrate 32. Device 31 may be an active device, such as a transistor. The transistor may include a source region, a drain region, a channel region between the source and drain regions, and a gate structure on the channel region. Other non-active devices (not shown), such as capacitors and resistors, may also be located on the front side of semiconductor substrate 32. Integrated circuit die 30 may include an interconnect structure 33 above the front side of semiconductor substrate 32. The interconnect structure 33 may interconnect device 31 and other non-active devices to form an integrated circuit. The interconnect structure 33 may include a dielectric layer 33A on semiconductor substrate 32 and a metallization pattern 33B in dielectric layer 33A. The metallization pattern 33B may be electrically connected to device 31 and other non-active devices.

[0019] The integrated circuit die 30 may also include a passivation layer 36 on the interconnect structure 33 and conductive pads 37 in the passivation layer 36. The conductive pads 37 may be physically and electrically connected to the metallization pattern 33B. The passivation layer 36 may include silicon nitride, silicon oxide, polyimide, etc. The conductive pads 37 may include copper, nickel, aluminum, etc., or combinations thereof. Conductive connectors 38 may be located on the conductive pads 37. The conductive connectors 38 may be solder, such as lead-free solder.

[0020] Figure 1C A cross-sectional view of an integrated circuit die 40 is shown. The integrated circuit die 40 can be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 40 may be a memory die, such as dynamic random access memory (DRAM), static random access memory (SRAM), high bandwidth memory (HBM), etc. The integrated circuit die 40 may include a stack of semiconductor substrates 42. The semiconductor substrates 42 may include silicon, germanium, silicon-germanium, etc. The semiconductor substrates 42 may be bonded together through a bonding layer (not shown) between adjacent semiconductor substrates 42. The semiconductor substrates 42 may have a front side (e.g., Figure 1C The mid-side facing upwards) and the dorsal side (e.g., Figure 1C (The side facing downwards).

[0021] Devices (not shown) may be located on the front side of semiconductor substrate 42. Devices may include active devices (such as transistors) and passive devices (such as capacitors, resistors, etc.). A transistor may include a source region, a drain region, a channel region between the source and drain regions, and a gate structure on the channel region. Devices on the front side of each semiconductor substrate 42 may be interconnected via corresponding interconnect structures (not shown) on the front side of semiconductor substrate 42. Integrated circuit die 40 may include interconnect structures 43 above the stack of semiconductor substrate 42, which may interconnect devices via vias 49 in semiconductor substrate 42 to form an integrated circuit. Interconnect structures 43 may include a dielectric layer 43A on the stack of semiconductor substrate 42 and a metallization pattern 43B in the dielectric layer 43A. The metallization pattern 43B may be electrically connected to the devices.

[0022] The integrated circuit die 40 may further include a passivation layer 46 on the interconnect structure 43 and conductive pads 47 in the passivation layer 46. The conductive pads 47 may be physically and electrically connected to the metallization pattern 43B. The passivation layer 46 may include silicon nitride, silicon oxide, polyimide, etc. The conductive pads 47 may include copper, nickel, aluminum, etc., or combinations thereof. Conductive connectors 48 may be located on the conductive pads 47. The conductive connectors 48 may be solder, such as lead-free solder.

[0023] Figure 1D A cross-sectional view of an integrated circuit die 50 is shown. The integrated circuit die 50 can be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 50 can be an input / output (I / O) die, etc. The integrated circuit die 50 can also be used as a bridge die, as described in more detail below. The integrated circuit die 50 may include a semiconductor substrate 52. The semiconductor substrate 52 may include silicon, germanium, silicon-germanium, etc. The semiconductor substrate 52 may have a front side (e.g., Figure 1D The mid-side facing upwards) and the dorsal side (e.g., Figure 1D (The side facing downwards).

[0024] Devices (not shown) may be located on the front side of semiconductor substrate 52. Devices may be passive devices, such as capacitors, resistors, etc. Integrated circuit die 50 may not have active devices, such as transistors. A transistor may include a source region, a drain region, a channel region between the source and drain regions, and a gate structure on the channel region. Integrated circuit die 50 may include an interconnect structure 53 above the front side of semiconductor substrate 52, which may interconnect devices to form an integrated circuit. Interconnect structure 53 may include a dielectric layer 53A on semiconductor substrate 52 and a metallization pattern 53B in dielectric layer 53A. The metallization pattern 53B may be electrically connected to the devices.

[0025] The integrated circuit die 50 may further include a passivation layer 56 on the interconnect structure 53 and conductive pads 57 in the passivation layer 56. The conductive pads 57 may be physically and electrically connected to the metallization pattern 53B. The passivation layer 56 may include silicon nitride, silicon oxide, polyimide, etc. The conductive pads 57 may include copper, nickel, aluminum, etc., or combinations thereof. The integrated circuit die 50 may further include a passivation layer 54 on the back side of the semiconductor substrate 52 and conductive pads 55 in the passivation layer 54. The passivation layer 54 may include silicon nitride, silicon oxide, polyimide, etc. The conductive pads 55 may include copper, nickel, aluminum, etc., or combinations thereof. The conductive pads 55 may be electrically connected to the metallization pattern 53B through vias 59 in the semiconductor substrate 52. Conductive connectors 58 may be located on the conductive pads 55. The conductive connectors 58 may be solder, such as lead-free solder.

[0026] Figure 1E A cross-sectional view of an integrated circuit die 60 is shown. The integrated circuit die 60 can be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 60 can be a logic die, such as a CPU, GPU, SoC, AP, microcontroller, etc. The integrated circuit die 60 can also be used as a bridging die, as described in more detail below. The integrated circuit die 60 may include a semiconductor substrate 62. The semiconductor substrate 62 may include silicon, germanium, silicon-germanium, etc. The semiconductor substrate 62 may have a front side (e.g., Figure 1E The mid-side facing upwards) and the dorsal side (e.g., Figure 1E (The side facing downwards).

[0027] Device 61 may be located on the front side of semiconductor substrate 62. Device 61 may be an active device, such as a transistor. The transistor may include a source region, a drain region, a channel region between the source and drain regions, and a gate structure on the channel region. Other non-active devices (not shown), such as capacitors and resistors, may also be located on the front side of semiconductor substrate 62. Integrated circuit die 60 may include an interconnect structure 63 above semiconductor substrate 62, which may interconnect device 61 and other non-active devices to form an integrated circuit. Interconnect structure 63 may include a dielectric layer 63A on semiconductor substrate 62 and a metallization pattern 63B in dielectric layer 63A. The metallization pattern 63B may be electrically connected to device 61 and other non-active devices.

[0028] The integrated circuit die 60 may further include a passivation layer 66 on the interconnect structure 63 and conductive pads 67 in the passivation layer 66. The conductive pads 67 may be physically and electrically connected to the metallization pattern 63B. The passivation layer 66 may include silicon nitride, silicon oxide, polyimide, etc. The conductive pads 67 may include copper, nickel, aluminum, etc., or combinations thereof. The integrated circuit die 60 may further include a passivation layer 64 on the back side of the semiconductor substrate 62 and conductive pads 65 in the passivation layer 64. The passivation layer 64 may include silicon nitride, silicon oxide, polyimide, etc. The conductive pads 65 may include copper, nickel, aluminum, etc., or combinations thereof. The conductive pads 65 may be electrically connected to the metallization pattern 63B through vias 69 in the semiconductor substrate 62. Conductive connectors 68 may be located on the conductive pads 65. The conductive connectors 68 may be solder, such as lead-free solder.

[0029] Figure 1F A cross-sectional view of an integrated circuit die 70 is shown. The integrated circuit die 70 can be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 70 can be a memory die, such as DRAM, SRAM, HBM, etc. The integrated circuit die 70 can also be used as a bridging die, as described in more detail below. The integrated circuit die 70 may include a semiconductor substrate 72. The semiconductor substrate 72 may include silicon, germanium, silicon-germanium, etc. The semiconductor substrates 72 can be bonded together through a bonding layer (not shown) between adjacent semiconductor substrates 72. The semiconductor substrate 72 may have a front side (e.g., Figure 1F The mid-side facing upwards) and the dorsal side (e.g., Figure 1F (The side facing downwards).

[0030] Devices (not shown) may be located on the front side of semiconductor substrate 72. Devices may include active devices (such as transistors) and passive devices (such as capacitors, resistors, etc.). A transistor may include a source region, a drain region, a channel region between the source and drain regions, and a gate structure on the channel region. Devices on the front side of each semiconductor substrate 72 may be interconnected via corresponding interconnect structures (not shown) on the front side of semiconductor substrate 72. Integrated circuit die 70 may include interconnect structures 73 above the stack of semiconductor substrate 72, which may interconnect devices via vias 79 in semiconductor substrate 72 to form an integrated circuit. Interconnect structures 73 may include a dielectric layer 73A on the stack of semiconductor substrate 72 and a metallization pattern 73B in the dielectric layer 73A. The metallization pattern 73B may be electrically connected to the devices.

[0031] The integrated circuit die 70 may further include a passivation layer 76 on the interconnect structure 73 and conductive pads 77 in the passivation layer 76. The conductive pads 77 may be physically and electrically connected to the metallization pattern 73B. The passivation layer 76 may include silicon nitride, silicon oxide, polyimide, etc. The conductive pads 77 may include copper, nickel, aluminum, etc., or combinations thereof. The integrated circuit die 70 may further include a passivation layer 74 on the back side of the stack of the semiconductor substrate 72 and conductive pads 75 in the passivation layer 74. The passivation layer 74 may include silicon nitride, silicon oxide, polyimide, etc. The conductive pads 75 may include copper, nickel, aluminum, etc., or combinations thereof. The conductive pads 75 may be electrically connected to the metallization pattern 73B through vias 79 in the semiconductor substrate 72. Conductive connectors 78 may be located on the conductive pads 75. The conductive connectors 78 may be solder, such as lead-free solder.

[0032] Figures 2 to 11B Views are shown of various intermediate steps during a process for forming an integrated circuit package, according to some embodiments. Figure 2 In this embodiment, a redistribution structure 108 is formed above a carrier substrate 103. The carrier substrate 103 can be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 103 can be a wafer, thereby allowing the redistribution structure 108 to be a wafer-level redistribution structure. For illustrative purposes, Figure 2 A portion of the carrier substrate 103 and the redistribution structure 108 is shown. An adhesive layer 105 may be located between the carrier substrate 103 and the redistribution structure 108. The adhesive layer 105 can be any suitable adhesive, such as epoxy resin, die-attach film (DAF), photothermal conversion (LTHC) material, etc. The adhesive layer 105 can be removed together with the carrier substrate 103 in a subsequent step.

[0033] The redistribution structure 108 may have a fine feature portion 108A and a coarse feature portion 108B. The fine feature portion 108A and the coarse feature portion 108B may include a dielectric layer and metallization patterns within the dielectric layer. The coarse feature portion 108B may include a dielectric layer and metallization patterns of a larger size than those of the fine feature portion 108A. The dielectric layer of the coarse feature portion 108B may include a different material than the dielectric layer of the fine feature portion 108A. The fine feature portion 108A and the coarse feature portion 108B in... Figure 2 The diagram shows an example with three dielectric layers for each feature portion. More or fewer dielectric layers may be formed in the fine feature portion 108A and the rough feature portion 108B. In some embodiments, the number of dielectric layers in the fine feature portion 108A and the rough feature portion 108B may range from about 5 to about 9.

[0034] A roughened feature portion 108B can be formed on a carrier substrate 103. The roughened feature portion 108B can include multiple layers, and each layer can include a dielectric layer 110 and a corresponding metallization pattern 112 within the dielectric layer 110. The metallization pattern 112 in the dielectric layer 110 can include metal lines and metal vias. The dielectric layer 110 can be formed with the same thickness or different thicknesses. The metal lines of the metallization pattern 112 can be formed with the same thickness or different thicknesses. The thickness of the metal lines of the metallization pattern 112 can range from about 5 μm to about 30 μm. The metal vias of the metallization pattern 112 can be formed with the same thickness or different thicknesses. The thickness of the metal vias of the metallization pattern 112 can range from about 5 μm to about 30 μm.

[0035] As an example of forming the roughened feature portion 108B, a first layer of metallization pattern 112 can first be formed on the carrier substrate 103. The first layer of metallization pattern 112 may include metal lines and metal vias. Initially, a seed layer may be formed on the carrier substrate 103. The seed layer may include a single metal layer or a composite metal layer including multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed by a suitable deposition method, such as physical vapor deposition (PVD).

[0036] A first photoresist can be formed and patterned on the seed layer. Patterning the first photoresist can create openings through it to expose the seed layer. These openings can correspond to metal lines in the first layer of the metallization pattern 112. A conductive material can then be formed in the openings of the first photoresist and on the exposed portions of the seed layer. The conductive material can be a metal, such as copper, titanium, tungsten, or aluminum. It can be formed by plating, such as electroplating or electroless plating. Afterward, the portions of the first photoresist and the seed layer on which no conductive material has been formed can be removed using appropriate ashing and etching processes, respectively. The remaining portions of the conductive material and the seed layer can be referred to as metal lines in the first layer of the metallization pattern 112.

[0037] A second photoresist can be formed and patterned on the metal line. Patterning can create openings through the second photoresist to expose the metal line. The openings in the second photoresist can correspond to metal vias in the first layer of the metallization pattern 112. Then, additional conductive material can be formed in the openings of the second photoresist and on the exposed portions of the metal line formed by plating (such as electroplating or electroless plating). The second photoresist can then be removed by a suitable ashing process. The additional conductive material can be referred to as the metal via in the first layer of the metallization pattern 112.

[0038] Then, a first layer of dielectric layer 110 can be formed around the first layer of metallization pattern 112. The first layer of dielectric layer 110 can be formed of a photosensitive material, such as molding compound, resin, epoxy resin, acrylic resin, polyimide, etc. The first layer of dielectric layer 110 can be formed by compression molding, transfer molding, etc. The photosensitive material can be initially applied in liquid or semi-liquid form and then cured. The first layer of metallization pattern 112 and the first layer of dielectric layer 110 can be collectively referred to as the first layer of roughened feature portion 108B.

[0039] The process of forming the first layer of the roughened feature portion 108B can then be repeated to form the second and third layers of the roughened feature portion 108B. The second layer of the roughened feature portion 108B may include a second layer of metallization pattern 112 and a second layer of dielectric layer 110. The third layer of the roughened feature portion 108B may include a third layer of metallization pattern 112 and a third layer of dielectric layer 110. The metallization pattern 112 in each layer of the roughened feature portion 108B may be physically and electrically connected to the metallization pattern 112 in adjacent layers of the roughened feature portion 108B.

[0040] Fine feature portion 108A can be formed on rough feature portion 108B. Fine feature portion 108A can include multiple layers, and each layer can include dielectric layer 124 and corresponding metallization pattern 126 in dielectric layer 124. Metallization pattern 126 in dielectric layer 124 can include metal lines and metal vias. Dielectric layer 124 can be formed with the same thickness or different thicknesses. The thickness of dielectric layer 124 can be less than the thickness of dielectric layer 110. Metal lines of metallization pattern 126 can be formed with the same thickness or different thicknesses. The thickness of metal lines of metallization pattern 126 can range from about 2 μm to about 20 μm, and can be less than the thickness of metal lines of metallization pattern 112. Metal vias of metallization pattern 126 can be formed with the same thickness or different thicknesses. The thickness of metal vias of metallization pattern 126 can range from about 2 μm to about 20 μm, and can be less than the thickness of metal vias of metallization pattern 112.

[0041] As an example of forming the fine feature portion 108A, a first layer of dielectric layer 124 can first be formed on the rough feature portion 108B. In some embodiments, the first layer of dielectric layer 124 is formed of a photosensitive material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In such embodiments, the first layer of dielectric layer 124 can be formed by a suitable coating process, such as spin coating, lamination, etc. In some embodiments, the first layer of dielectric layer 124 is formed of a dielectric material, such as silicon oxide, silicon nitride, etc. In such embodiments, the first layer of dielectric layer 124 can be formed by a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Then, the first layer of dielectric layer 124 can be patterned by a suitable photolithography process. Patterning can form openings that expose portions of the metallization pattern 112 of the rough feature portion 108B.

[0042] The first layer of the metallization pattern 126 may be formed in an opening in the first layer of the dielectric layer 124. The first layer of the metallization pattern 126 may include metal lines that may be physically and electrically connected to the exposed portions of the metallization pattern 112. The first layer of the metallization pattern 126 may be formed of the same or similar material as the first layer of the metallization pattern 112 and by the same or similar process as the first layer of the metallization pattern 112. The first layer of the metallization pattern 126 and the first layer of the dielectric layer 124 may be collectively referred to as the first layer of the fine feature portion 108A.

[0043] The process of forming the first layer of the fine feature portion 108A can then be repeated to form the second and third layers of the fine feature portion 108A. The second layer of the fine feature portion 108A may include a second layer of metallization pattern 126 and a second layer of dielectric layer 124. The third layer of the fine feature portion 108A may include a third layer of metallization pattern 126 and a third layer of dielectric layer 124. The second and third layers of metallization pattern 126 may include metal lines and metal vias. The metallization pattern 126 in each layer of the fine feature portion 108A may be physically and electrically connected to the metallization pattern 126 in adjacent layers of the fine feature portion 108A.

[0044] exist Figure 3 In this process, a dielectric layer 127 is formed on the top surface of the redistribution structure 108, and an under-bump metallization (UBM) 128 is formed in the dielectric layer 127. The dielectric layer 127 may be formed of the same or similar material as the first layer of the dielectric layer 124 and by the same or similar process as the first layer of the dielectric layer 124. The UBM 128 may have line portions located on the surface of the dielectric layer 127 and via portions extending through the dielectric layer 127 to be physically and electrically connected to the metallization pattern 126 of the redistribution structure 108.

[0045] As an example of forming UBM 128, a dielectric layer 127 can first be patterned. Patterning forms openings in portions of the exposed metallization pattern 126 using a suitable photolithography process. A seed layer can be formed on the dielectric layer 127 and in the openings. The seed layer can comprise a single metal layer or a composite metal layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using a suitable deposition method, such as PVD. Photoresist can be formed and patterned on the seed layer. Patterning forms openings through the photoresist to expose the seed layer. The openings in the photoresist can correspond to via portions of the UBM 128. A conductive material can then be formed in the openings in the photoresist and on the exposed portions of the seed layer. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, etc. Subsequently, the portions of the photoresist and seed layer on which no conductive material has been formed can be removed using a suitable ashing process and a suitable etching process, respectively. The remaining portion of the conductive material and the seed layer is referred to as UBM 128.

[0046] exist Figure 4A In this process, integrated circuit dies 50, 60, and 70 are bonded to UBM 128 and over redistribution structure 108, and an underfill 131 is formed between integrated circuit dies 50, 60, and 70 and dielectric layer 127. Furthermore, vias 130 are formed in UBM 128. Integrated circuit dies 50, 60, and 70 can be bonded to UBM 128 by: placing conductive connectors 58, 68, and 78 on UBM 128 or on conductive connectors (not shown) previously formed on UBM 128; and then reflowing the conductive connectors 58, 68, and 78. After the bonding process, integrated circuit dies 50, 60, and 70 can be electrically connected to redistribution structure 108. Underfill 131 can be formed from molding compound, epoxy resin, etc. Underfill 131 can be formed by a capillary flow process in liquid or semi-liquid form after integrated circuit dies 50, 60, and 70 are bonded to UBM 128, and then subsequently cured. The via 130 can be formed of the same or similar material as the metallization pattern 112 of the redistribution structure 108 and by the same or similar process as the metallization pattern 112 of the redistribution structure 108. The via 130 can be electrically connected to the redistribution structure 108.

[0047] Figure 4BDetailed views of the bonding interface between integrated circuit die 50 and UBM 128 prior to the bonding process, according to some embodiments, are shown. The same detailed views can also be applied to the bonding interface between integrated circuit die 60 and UBM 128, and between integrated circuit die 70 and UBM 128. In some embodiments, UBMs 55 and 128 are single-layer structures formed of a conductive material (such as copper), and conductive connectors 58 may be formed on UBM 55 or UBM 55 and UBM 128. In some embodiments, UBM 55 is a multilayer structure formed of more than one conductive material (such as copper and nickel), and UBM 128 is a single-layer structure formed of a conductive material (such as copper), and conductive connectors 58 may be formed on UBM 55 or UBM 55 and UBM 128. For example, UBM 55 may include a copper layer 55A in contact with a passivation layer 54 and a nickel layer 55B located on the copper layer 55A and in contact with the conductive connector 58. For example, UBM 55 may include a copper layer 55A in contact with the passivation layer 54, a nickel layer 55B on the copper layer 55A, and a copper layer 55C on the nickel layer 55B and in contact with the conductive connector 58.

[0048] In some embodiments, UBMs 55 and 128 are multilayer structures formed of more than one conductive material (such as copper and nickel), and conductive connectors 58 may be formed on UBMs 55 and 128. For example, UBM 55 may include a copper layer 55A in contact with a passivation layer 54 and a nickel layer 55B located on the copper layer 55A and in contact with the conductive connector 58. For example, UBM 128 may include a copper layer 128A in contact with a dielectric layer 127 and a nickel layer 128B located on the copper layer 128A and in contact with the conductive connector 58. For example, UBM 55 may include a copper layer 55A in contact with a passivation layer 54, a nickel layer 55B located on the copper layer 55A, and a copper layer 55C located on the nickel layer 55B and in contact with the conductive connector 58. For example, UBM 128 may include a copper layer 128A in contact with dielectric layer 127, a nickel layer 128B on copper layer 128A, and a copper layer 128C on nickel layer 128B in contact with conductive connector 58.

[0049] exist Figure 5In this process, a sealant 132 is formed around integrated circuit dies 50, 60, and 70, as well as via 130. The sealant 132 can be a molding compound, epoxy resin, etc., and can be applied by compression molding, transfer molding, etc. The sealant 132 can be applied in liquid or semi-liquid form and then subsequently cured. A removal process can then be performed to remove excess sealant 132 and expose integrated circuit dies 50, 60, and 70, as well as via 130. The removal process can be chemical mechanical polishing (CMP), etching back, or a combination thereof. The top surfaces of integrated circuit dies 50, 60, and 70, via 130, and sealant 132 can be coplanar after the removal process (within a process variation).

[0050] exist Figure 6 In this process, a redistribution structure 135 can be formed on integrated circuit dies 50, 60, and 70, via 130, and sealant 132. Furthermore, a dielectric layer 139 is formed on the redistribution structure 135, and a UBM 136 is formed in the dielectric layer 139. The redistribution structure 135 can be a wafer-level redistribution structure. The redistribution structure 135 can include multiple layers, and each layer can include a dielectric layer 133 and a corresponding metallization pattern 134 in the dielectric layer 133. The metallization pattern 134 in the dielectric layer 133 can include metal lines and metal vias. The metallization pattern 134 can be electrically connected to the conductive pads 57 of integrated circuit die 50, the conductive pads 67 of integrated circuit die 60, the conductive pads 77 of integrated circuit die 70, and the via 130. Integrated circuit dies 50, 60, and 70 and via 130 can electrically connect the redistribution structure 135 to the redistribution structure 108.

[0051] The redistribution structure 135 can be formed from the same or similar material as the fine feature portion 108A of the redistribution structure 108, and formed by the same or similar process as the fine feature portion 108A of the redistribution structure 108. The redistribution structure 135 in... Figure 6 The diagram shows an example with three dielectric layers 133. More or fewer dielectric layers 133 may be formed in the redistribution structure 135. Dielectric layer 139 may be formed of the same or similar material as the first layer of dielectric layer 124 and by the same or similar process as the first layer of dielectric layer 124. UBM 136 may have line portions located on the surface of dielectric layer 139 and via portions extending through dielectric layer 139 to be physically and electrically connected to the metallized pattern 134 of redistribution structure 135. UBM 136 may be formed of the same or similar material as UBM 128 and by the same or similar process as UBM 128.

[0052] exist Figure 7A and Figure 7BIn this configuration, integrated circuit dies 20, 30, and 40 are bonded to UBM 136 and over redistribution structure 135, and an underfill 137 is formed between integrated circuit dies 20, 30, and 40 and dielectric layer 139. Figure 7A A cross-sectional view is shown, and Figure 7B A top view is shown, and Figure 7A The cross-sectional view can be along Figure 7B The reference section A-A' in the top view is obtained. Integrated circuit dies 20, 30, and 40 can be coupled to the UBM 136 by: placing conductive connectors 28, 38, and 48 on or on conductive connectors (not shown) previously formed on the UBM 136; and then reflowing the conductive connectors 28, 38, and 48. (Regarding...) Figure 4B The detailed views of the bonding interfaces between IC die 50 and UBM 128 prior to the described bonding process can also be applied to the bonding interfaces between IC die 20 and UBM 136, IC die 30 and UBM 136, and IC die 40 and UBM 136. After the bonding process, IC dies 20, 30, and 40 can be electrically connected to the redistribution structure 135. The underfill 137 can be formed of the same or similar material as the underfill 131 and formed by the same or similar process as the underfill 131.

[0053] like Figure 7B As shown, integrated circuit dies 30 and 40, as well as some of integrated circuit dies 20, are located within a computing region 180 above the redistribution structure 135. Integrated circuit dies 20 outside computing region 180 can be external I / O dies, facilitating communication between integrated circuit dies 30 and 40 within computing region 180 and external devices that can be attached to subsequently formed integrated circuit packages. Integrated circuit dies 20 within computing region 180 can be internal I / O dies, facilitating communication between integrated circuit dies 30 and 40. Integrated circuit dies 30 and 40 within computing region 180, as well as some of integrated circuit dies 20, can be grouped into die clusters 190, and die clusters 1900 can be arranged as an array including horizontal rows and vertical columns.

[0054] exist Figure 7BIn the illustrated embodiment, each die cluster 190 includes an integrated circuit die 30 (e.g., a logic die), with one integrated circuit die 20 (e.g., an I / O die) and two integrated circuit dies 40 (e.g., memory dies) located on opposite horizontal sides of the integrated circuit die 30. The integrated circuit die 20 may be located between two integrated circuit dies 40. The integrated circuit dies 20 within a die cluster 190 may be electrically connected to adjacent integrated circuit dies 30 and 40, and facilitate communication between adjacent die clusters 190 in the same horizontal row. Additional integrated circuit dies 20 may be disposed between the integrated circuit dies 30 of adjacent die clusters 190 in the same vertical column. Such integrated circuit dies 20 may be electrically connected to adjacent integrated circuit dies 30 and 40, and may facilitate communication between adjacent die clusters 190 in the same vertical column.

[0055] Furthermore, the integrated circuit dies 50, 60, and 70 below the redistribution structure 135 can serve as bridging dies (e.g., local interconnects) and can electrically interconnect integrated circuit dies 20, 30, and 40 (including external I / O dies), connecting them to the redistribution structure 108. Therefore, integrated circuit dies 50, 60, and 70 can also facilitate communication between integrated circuit dies 20, 30, and 40. Due to the integrated circuit dies 20 (e.g., internal I / O dies) within the computing region 180 and the integrated circuit dies 50, 60, and 70 (e.g., bridging dies) below the computing region 180, communication between integrated circuit dies 30 (e.g., logic dies) and integrated circuit dies 40 (e.g., memory dies) within the computing region 180 can be improved. Therefore, the performance of the subsequently formed integrated circuit package can be improved.

[0056] Figure 7B The layout of integrated circuit dies 20, 30 and 40 within the die cluster 190 shown is provided as an example, and other layouts of integrated circuit dies 20, 30 and 40 are considered. Figure 7B The layout of the die cluster 190 shown (e.g., three horizontal rows multiplied by five vertical columns) is provided as an example, and other layouts of the die cluster 190 (e.g., four horizontal rows multiplied by four vertical columns, five horizontal rows multiplied by five vertical columns) are considered. Figure 7A The layouts of integrated circuit dies 50, 60, and 70 shown are provided as examples, and other layouts of integrated circuit dies 50, 60, and 70 are considered. In some embodiments, integrated circuit packages including integrated circuit dies 30, such as integrated circuit packages including two or more vertically stacked integrated circuit dies 30, may also be bonded over the redistribution structure 135. Such integrated circuit packages may replace some or all of the integrated circuit dies 30 bonded over the redistribution structure 135.

[0057] exist Figure 8 In this process, a sealant 138 is formed around integrated circuit dies 20, 30, and 40. A carrier substrate 140 is attached to the top surface of the sealant 138 via an adhesive layer 141, and the carrier substrate 103 and adhesive layer 105 are removed. The sealant 138 may be formed from the same or similar material as sealant 132 and by the same or similar process as sealant 132. The carrier substrate 140 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 140 may be a wafer. The adhesive layer 141 may be any suitable adhesive, such as epoxy resin, DAF, LTHC material, etc. The adhesive layer 141 may be removed together with the carrier substrate 140 in a subsequent step. The carrier substrate 103 and adhesive layer 105 may then be removed by projecting a light beam (such as a laser beam) onto the adhesive layer 105. Due to the exposure, the adhesive layer 105 may decompose, and the carrier substrate 103 may be peeled off. Afterward, a cleaning process, such as a plasma cleaning process, may be performed to clean any residue of the adhesive layer 105 from the redistribution structure 108.

[0058] exist Figure 9 In this redistribution structure 108, a dielectric layer 142 is formed on the bottom surface, a UBM 144 is formed within the dielectric layer 142, and a conductive connector 154 is formed on the UBM 144. The dielectric layer 142 may be formed of the same or similar material as the first layer of dielectric layer 124, and formed using the same or similar processes as the first layer of dielectric layer 124. The UBM 144 may have line portions located on the surface of the dielectric layer 142 and via portions extending through the dielectric layer 142 to physically and electrically connect to the metallized pattern 112 of the redistribution structure 108. The UBM 144 may be formed of the same or similar material as UBM 128, and formed using the same or similar processes as UBM 128. The conductive connector 154 may be solder, such as lead-free solder. The UBM 144 and the corresponding conductive connector 154 can be used for connection to external devices. Figure 9 The design of the structure shown can increase the density of UBM 144 and the corresponding conductive connectors 154. Therefore, the performance of the subsequently formed integrated circuit package can be improved.

[0059] exist Figure 10A and Figure 10B middle, Figure 9 The structure shown is placed on a strip 146 supported by a frame 148, with the carrier substrate 140 and adhesive layer 141 removed, and the sealant 138 partially removed to expose the surfaces of integrated circuit dies 20, 30 and 40. Figure 10A A cross-sectional view is shown, and Figure 10B A top view is shown, and Figure 10AThe cross-sectional view can be along Figure 10B The reference section A-A' is obtained in the top view. The carrier substrate 140 and adhesive layer 141 can be removed by the same or similar process as that used to remove carrier substrate 103 and adhesive layer 105. The sealant 138 can be partially removed by processes such as CMP, etch-back, or combinations thereof. The top surfaces of the integrated circuit dies 20, 30, and 40 and the sealant 138 can be coplanar after the removal process (within process variations).

[0060] exist Figure 11A and Figure 11B In the middle, through Figure 10A and Figure 10B The structure shown forms an opening 160 and is truncated. Figure 10A and Figure 10B The outer part of the structure shown. Figure 11A and Figure 11B The structure above strip 146 shown can be referred to as integrated circuit package 200. Figure 11A A cross-sectional view is shown, and Figure 11B A top view is shown, and Figure 11A The cross-sectional view can be along Figure 11B The reference section A-A' is obtained from the top view. For illustrative purposes, Figure 11A and Figure 11B An opening 160 is shown, and more than one opening 160 can be formed at selected locations through the integrated circuit package 200. The opening 160 can extend through sealant 138, redistribution structure 135, sealant 132, and redistribution structure 108. The opening 160 can be a circular bolt hole, which can be used to secure additional components, such as thermal modules, mechanical supports, etc., using bolts in subsequent processes. The opening 160 can be formed by drilling processes, such as laser drilling, mechanical drilling, etc.

[0061] Figure 10A and Figure 10B The outer portion of the structure shown can be truncated using a sawing process or the like. Therefore, the integrated circuit package 200 can have a truncated circular shape, which can reduce the spacing occupied by the integrated circuit package 200 in the system. After truncating the outer portion, the integrated circuit package 200 can have a length L1 ranging from about 80 mm to about 300 mm and a width W1 ranging from about 50 mm to about 300 mm. The redistribution structures 108 and 135 (which are portions of the integrated circuit package 200) can also have the same or similar shapes and dimensions. In some embodiments, Figure 10A and Figure 10B The outer portion of the structure shown is retained, and the integrated circuit package 200 has a circular shape.

[0062] Figures 12 to 14 Various views of intermediate steps during the process for forming an integrated circuit package are shown according to some embodiments. Figure 12 Similar to some embodiments are shown. Figure 5 The structures shown are structurally identical, wherein the same reference numerals indicate the same parts formed by the same process. Figure 12 In this configuration, integrated circuit dies 50', 60', and 70' can be attached to the carrier substrate 104 via adhesive layer 106, and vias 130 can be formed above the carrier substrate 104 and adjacent to the integrated circuit dies 50', 60', and 70'. A sealant 132 can be formed around the integrated circuit dies 50', 60', and 70' and the vias 130. A redistribution structure 108 can be formed on the integrated circuit dies 50', 60', and 70', the vias 130, and the sealant 132.

[0063] The carrier substrate 104 can be similar to the carrier substrate 103, and the adhesive layer 106 can be similar to the adhesive layer 105. The integrated circuit dies 50', 60', and 70' can be similar to the integrated circuit dies 50, 60, and 70. The integrated circuit dies 50', 60', and 70' may be without conductive connectors 58, 68, and 78, respectively. Therefore, the conductive pads 55, 65, and 75 of the integrated circuit dies 50', 60', and 70' can be physically and electrically connected to the metallization pattern 126 of the redistribution structure 108, respectively, and the integrated circuit dies 50', 60', and 70' can be in physical contact with the fine feature portion 108A of the redistribution structure 108. The via 130 can be physically and electrically connected to the metallization pattern 126 of the redistribution structure 108.

[0064] exist Figure 13 In the process, the carrier substrate 104 and adhesive layer 106 are removed, and the carrier substrate 103 is attached to the bottom surface of the redistribution structure 108 via adhesive layer 105. Then, the redistribution structure 135 is formed on the integrated circuit dies 50', 60', and 70', via 130, and sealant 132, and dielectric layer 139 and UBM 136 are formed via the above-mentioned... Figure 6 The same or similar process described is used to form the redistribution structure 135. Next, integrated circuit dies 20, 30, and 40 are bonded to UBM 136, and through the above-described... Figure 7A The same or similar process described herein forms an underfill 137 between integrated circuit dies 20, 30 and 40 and dielectric layer 139.

[0065] exist Figure 14 In the process, sealant 138 is formed around integrated circuit dies 20, 30, and 40, and through the above-mentioned... Figure 8The same or similar process described above is used to remove the carrier substrate 103 and the adhesive layer 105. Then, the dielectric layer 142 and UBM 144 are formed on the bottom surface of the redistribution structure 108, and the conductive connector 154 is connected via the above-described... Figure 9 The same or similar process described is formed on UBM 144. Next, the resulting wafer structure is placed on strip 156, an opening 160 is formed through the wafer structure, and through the above-mentioned... Figures 10A to 11B The same or similar processes are described to truncate the outer portion of the wafer structure. Figure 14 The structure above strip 156 shown can be referred to as integrated circuit package 200'.

[0066] The embodiments described above can achieve certain advantages. By placing integrated circuit die 20 within computing region 180 and placing integrated circuit dies 50, 60, and 70 below computing region 180, communication between integrated circuit dies 30 and 40 within computing region 180 can be improved. Therefore, the performance of integrated circuit packages 200 and 200' can be improved.

[0067] In one embodiment, the integrated circuit package includes: a first redistribution structure; a first bridging die located above the first redistribution structure; a first sealant located around the first bridging die; a second redistribution structure located above the first bridging die and the first sealant, wherein the first bridging die electrically connects the first redistribution structure to the second redistribution structure; a first logic die, a second logic die, and a first input / output (I / O) die located above the second redistribution structure, wherein the first I / O die is located between the first logic die and the second logic die in a top view, and wherein the first I / O die electrically connects the first logic die to the second logic die; and a second sealant located around the first logic die, the second logic die, and the first I / O die. In another embodiment, the integrated circuit package further includes a second I / O die located above the second redistribution structure, wherein the second sealant is located around the second I / O die, and wherein the second I / O die is located between the edge of the second sealant and the first logic die in a top view. In one embodiment, the first I / O die is an internal I / O die configured to communicatively couple a first logic die and a second logic die, and the second I / O die is an external I / O die configured to communicatively couple the first logic die and an external device. In one embodiment, the first bridge die includes a transistor having a source region, a drain region, a channel region between the source and drain regions, and a gate structure on the channel region. In one embodiment, the integrated circuit package further includes bolt holes extending through the first redistribution structure, the first sealant, the second redistribution structure, and the second sealant. In one embodiment, the first and second redistribution structures are wafer-level redistribution structures. In one embodiment, the integrated circuit package further includes a first memory die located above the second redistribution structure, wherein a second sealant is located around the first memory die. In one embodiment, the first redistribution structure includes a first portion and a second portion, wherein the first portion is located between the first bridge die and the second portion, and wherein the metal lines in the second portion are thicker than the metal lines in the first portion.

[0068] In an embodiment, the method includes: forming a first redistribution structure; placing a first bridge die over the first redistribution structure, wherein the first bridge die is electrically connected to the first redistribution structure; forming a second redistribution structure over the first bridge die, wherein the first bridge die is electrically connected to the second redistribution structure; bonding a first logic die, a second logic die, a first input / output (I / O) die, and a second input / output (I / O) die over the second redistribution structure, wherein the first I / O die is located between the first logic die and the second logic die in a top view; and forming an opening through the first redistribution structure and the second redistribution structure. In an embodiment, the opening is formed by laser drilling. In an embodiment, the opening may be located between the second I / O die and the first logic die in a top view. In an embodiment, the method further includes bonding a first memory die over the second redistribution structure, wherein the first memory die is located between the second I / O die and the first logic die in a top view. In an embodiment, the first redistribution structure includes a fine feature portion and a coarse feature portion, wherein the fine feature portion includes a dielectric layer and metal lines thinner than the coarse feature portion. In one embodiment, the method further includes forming a first conductive via next to the first bridge pipe core, wherein the first conductive via is electrically connected to the first redistribution structure and the second redistribution structure.

[0069] In an embodiment, the method includes: forming a first redistribution structure; connecting a first bridge die to the first redistribution structure; forming a second redistribution structure above the first bridge die, wherein the first bridge die electrically connects the first redistribution structure to the second redistribution structure; connecting a first integrated circuit die cluster to the second redistribution structure, wherein the first integrated circuit die cluster includes a first logic die, a first memory die, and a first input / output (I / O) die; and forming screw holes through the first and second redistribution structures. In an embodiment, the first integrated circuit die cluster further includes a second memory die and a second I / O die, wherein the first memory die and the first I / O die are along a first side of the first logic die in a top view, and wherein the second memory die and the second I / O die are along a second side of the first logic die opposite to the first side in a top view. In an embodiment, the first integrated circuit die cluster further includes a third memory die along the first side of the first logic die in a top view, and wherein the first I / O die is located between the first memory die and the third memory die. In one embodiment, the method further includes connecting a second integrated circuit die cluster to a second redistribution structure, wherein the second integrated circuit die cluster includes a second logic die, a second memory die, and a second I / O die, and wherein the second memory die and the second I / O die are located between the first logic die and the second logic die in a top view. In another embodiment, the method further includes: connecting the second integrated circuit die cluster to the second redistribution structure, wherein the second integrated circuit die cluster includes a second logic die, a second memory die, and a second I / O die; and connecting a third I / O die to the second redistribution structure, wherein the third I / O die is located between the first integrated circuit die cluster and the second integrated circuit die cluster. In another embodiment, the first redistribution structure includes a first portion and a second portion, wherein the first portion is located between a first bridging die and the second portion, wherein the first portion includes a first plurality of dielectric layers of a first material, wherein the second portion includes a second plurality of dielectric layers of a second material, and wherein the first material is different from the second material.

[0070] Some embodiments of this application provide an integrated circuit package, including: a first redistribution structure; a first bridging die located above the first redistribution structure; a first sealant located around the first bridging die; a second redistribution structure located above the first bridging die and the first sealant, wherein the first bridging die electrically connects the first redistribution structure to the second redistribution structure; a first logic die, a second logic die, and a first input / output die located above the second redistribution structure, wherein the first input / output die is located between the first logic die and the second logic die in a top view, and wherein the first input / output die electrically connects the first logic die to the second logic die; and a second sealant located around the first logic die, the second logic die, and the first input / output die.

[0071] In some embodiments, the integrated circuit package further includes a second input / output die located above the second redistribution structure, wherein the second sealant is located around the second input / output die, and wherein the second input / output die is located between the edge of the second sealant and the first logic die in the top view. In some embodiments, the first input / output die is an internal input / output die configured to communicatively couple the first logic die and the second logic die, and wherein the second input / output die is an external input / output die configured to communicatively couple the first logic die and an external device. In some embodiments, the first bridge die includes a transistor having a source region, a drain region, a channel region between the source region and the drain region, and a gate structure on the channel region. In some embodiments, the integrated circuit package further includes bolt holes extending through the first redistribution structure, the first sealant, the second redistribution structure, and the second sealant. In some embodiments, the first redistribution structure and the second redistribution structure are wafer-level redistribution structures. In some embodiments, the integrated circuit package further includes a first memory die located above the second redistribution structure, wherein the second sealant is located around the first memory die. In some embodiments, the first redistribution structure includes a first portion and a second portion, wherein the first portion is located between the first bridge tube core and the second portion, and wherein the metal wire in the second portion is thicker than the metal wire in the first portion.

[0072] Other embodiments of this application provide a method for forming an integrated circuit package, comprising: forming a first redistribution structure; placing a first bridge die over the first redistribution structure, wherein the first bridge die is electrically connected to the first redistribution structure; forming a second redistribution structure over the first bridge die, wherein the first bridge die is electrically connected to the second redistribution structure; attaching a first logic die, a second logic die, a first input / output die, and a second input / output die over the second redistribution structure, wherein the first input / output die is located between the first logic die and the second logic die in a top view; and forming an opening through the first redistribution structure and the second redistribution structure.

[0073] In some embodiments, the opening is formed by laser drilling. In some embodiments, the opening may be located between the second input / output die and the first logic die in the top view. In some embodiments, the method further includes bonding a first memory die over the second redistribution structure, wherein the first memory die is located between the second input / output die and the first logic die in the top view. In some embodiments, the first redistribution structure includes a fine feature portion and a rough feature portion, wherein the fine feature portion includes a dielectric layer and metal lines thinner than the rough feature portion. In some embodiments, the method further includes forming a first conductive via next to the first bridge die, wherein the first conductive via is electrically connected to the first redistribution structure and the second redistribution structure.

[0074] Further embodiments of this application provide a method for forming an integrated circuit package, comprising: forming a first redistribution structure; connecting a first bridge die to the first redistribution structure; forming a second redistribution structure above the first bridge die, wherein the first bridge die electrically connects the first redistribution structure to the second redistribution structure; connecting a first integrated circuit die cluster to the second redistribution structure, wherein the first integrated circuit die cluster includes a first logic die, a first memory die, and a first input / output die; and forming screw holes through the first redistribution structure and the second redistribution structure.

[0075] In some embodiments, the first integrated circuit die cluster further includes a second memory die and a second input / output die, wherein the first memory die and the first input / output die are located along a first side of the first logic die in a top view, and wherein the second memory die and the second input / output die are located along a second side of the first logic die opposite to the first side in the top view. In some embodiments, the first integrated circuit die cluster further includes a third memory die along the first side of the first logic die in the top view, and wherein the first input / output die is located between the first memory die and the third memory die. In some embodiments, the method further includes connecting the second integrated circuit die cluster to the second redistribution structure, wherein the second integrated circuit die cluster includes a second logic die, a second memory die, and a second input / output die, and wherein the second memory die and the second input / output die are located between the first logic die and the second logic die in a top view. In some embodiments, the method further includes: connecting a second integrated circuit die cluster to the second redistribution structure, wherein the second integrated circuit die cluster includes a second logic die, a second memory die, and a second input / output die; and connecting a third input / output die to the second redistribution structure, wherein the third input / output die is located between the first integrated circuit die cluster and the second integrated circuit die cluster. In some embodiments, the first redistribution structure includes a first portion and a second portion, wherein the first portion is located between the first bridging die and the second portion, wherein the first portion includes a first plurality of dielectric layers of a first material, wherein the second portion includes a second plurality of dielectric layers of a second material, and wherein the first material is different from the second material.

[0076] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. An integrated circuit package comprising: a first redistribution structure; a first bridge die over the first redistribution structure; a first encapsulant around the first bridge die; a second redistribution structure over the first bridge die and the first encapsulant, wherein the first bridge die electrically connects the first redistribution structure to the second redistribution structure; a first logic die, a second logic die, and a first input / output die over the second redistribution structure, wherein the first input / output die is between the first logic die and the second logic die in a top view, and wherein the first input / output die electrically connects the first logic die to the second logic die; and a second encapsulant around the first logic die, the second logic die, and the first input / output die.

2. The integrated circuit package of claim 1, further comprising a second input / output die located above the second redistribution structure, wherein, the second encapsulant is around the second input / output die, wherein the second input / output die is between an edge of the second encapsulant and the first logic die in the top view.

3. The integrated circuit package of claim 2, wherein, the first input / output die is an internal input / output die configured to communicatively couple the first logic die and the second logic die, and wherein the second input / output die is an external input / output die configured to communicatively couple the first logic die and an external device.

4. The integrated circuit package of claim 1, wherein, the first bridge die includes a transistor, wherein the transistor has a source region, a drain region, a channel region between the source region and the drain region, and a gate structure over the channel region.

5. The integrated circuit package of claim 1, further comprising a bolt hole extending through the first redistribution structure, the first encapsulant, the second redistribution structure, and the second encapsulant.

6. The integrated circuit package of claim 5, wherein, the first redistribution structure and the second redistribution structure are wafer-level redistribution structures.

7. The integrated circuit package of claim 5, further comprising a first memory die located above the second redistribution structure, wherein, the second encapsulant is around the first memory die.

8. The integrated circuit package of claim 1, wherein, the first redistribution structure includes a first portion and a second portion, wherein the first portion is between the first bridge die and the second portion, and wherein metal lines in the second portion are thicker than metal lines in the first portion.

9. A method of forming an integrated circuit package comprising: forming a first redistribution structure; placing a first bridge die over the first redistribution structure, wherein the first bridge die is electrically connected to the first redistribution structure; forming a second redistribution structure over the first bridge die, wherein the first bridge die is electrically connected to the second redistribution structure; bonding a first logic die, a second logic die, a first input / output die, and a second input / output die over the second redistribution structure, wherein the first input / output die is between the first logic die and the second logic die in a top view; and forming an opening through the first redistribution structure and the second redistribution structure.

10. A method of forming an integrated circuit package comprising: forming a first redistribution structure; connecting a first bridge die to the first redistribution structure; forming a second redistribution structure over the first bridge die, wherein the first bridge die electrically connects the first redistribution structure to the second redistribution structure; connecting a first integrated circuit die cluster to the second redistribution structure, wherein the first integrated circuit die cluster includes a first logic die, a first memory die, and a first input / output die; and forming a screw hole through the first redistribution structure and the second redistribution structure.

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