FinFET device and preparation method of epitaxial source and drain thereof
By employing selective epitaxial processes and cyclic deposition etching techniques in FinFET devices to form diamond-like phosphorus-doped silicon epitaxial layers, the problem of source-drain connection between adjacent fins in FinFET devices is solved, thereby improving the performance and reliability of the devices.
Patent Information
- Application Number
- CN202411098222.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-12
- Publication Date
- 2026-01-23
AI Technical Summary
In the prior art, when fabricating the source and drain electrodes of FinFET devices, the source and drain electrodes between adjacent fins are easily connected, which can lead to stress release, increased contact resistance, or even short circuits, affecting device performance.
Grooves are formed on the fins using selective epitaxy, and phosphorus-doped silicon epitaxial layers are deposited and trimmed. The thickness and shape of the phosphorus-doped silicon epitaxial layers are controlled by cyclic deposition and etching steps. By utilizing the difference in etching rates in different crystal orientations, diamond-like epitaxial layer contours are formed, suppressing lateral growth.
It effectively reduces the risk of source-drain connection between adjacent fins, maintains stress, reduces contact resistance, avoids short circuits, and improves device performance.
Smart Images
Figure CN121398043A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor technology, in particular to a FinFET device and a preparation method of an epitaxial source / drain thereof. BACKGROUND
[0002] With the development of semiconductor process technology, the gate width is continuously reduced, and the traditional planar CMOS device cannot meet the requirements of the device, such as the control of short channel effect. For a 20nm technology node, a fin field effect transistor (FinFET) structure has better electrical performance. Since the channel of the fin field effect transistor is surrounded by a 3D gate, the drain power line terminates at the gate and cannot reach the source. Therefore, the potential in the channel is completely controlled by the gate, which is the reason why the fin field effect transistor has good short channel effect control.
[0003] From 90nm, SiGe source / drain epitaxy is a key factor to improve the performance of PMOS devices, and from 20nm, SiP source / drain epitaxy technology is used to improve the performance of NMOS, different epitaxial profiles have different stresses, which in turn affect the performance of the device. When the NMOS tube is converted from a planar structure to a FinFET fin structure, the volume, morphology, and doping concentration of the SiP source / drain epitaxy are increasingly demanding due to the influence of the structural environment.
[0004] Generally, the larger the volume of the SiP source / drain epitaxy is required to provide sufficient stress to increase the performance of the device. When the fin pitch of the FinFET fin structure is large enough, the source / drain between adjacent fins will not have the risk of connection, but as the device size continues to shrink, in order to maintain the stress requirement, the spacing between adjacent fins is continuously reduced, and the source / drain between adjacent fins will have the risk of connection. This phenomenon will release stress, increase contact resistance, and even cause short circuit risk. SUMMARY
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a FinFET device and a preparation method of an epitaxial source / drain thereof, which is used to solve the problem that the source / drain between adjacent fins will be connected when an in-situ doped epitaxy process is used to prepare the source / drain of an N-type FinFET device in the prior art, resulting in stress release, increased contact resistance, and even short circuit, thereby reducing the performance of the device.
[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a preparation method of an epitaxial source / drain of a FinFET device, which comprises:
[0007] providing a substrate, two or more fins are formed on the substrate with a spacing, an isolation structure is formed between adjacent fins, a gate is formed on the fin, and a groove is formed on the fin on both sides of the gate;
[0008] A phosphorus-doped first silicon epitaxial layer is deposited in the groove using a selective epitaxial process, wherein the thickness of the phosphorus-doped first silicon epitaxial layer is less than the depth of the groove;
[0009] A second phosphorus-doped silicon epitaxial layer is deposited on the phosphorus-doped first silicon epitaxial layer, the surface of the second phosphorus-doped silicon epitaxial layer being higher than the surface of the groove. The method for depositing the second phosphorus-doped silicon epitaxial layer includes performing a series of cycles consisting of deposition and etching steps until the desired thickness of the second phosphorus-doped silicon epitaxial layer is achieved.
[0010] The deposition step includes: introducing silicon reactive gas and phosphorus doping gas into a selective epitaxial deposition chamber to deposit and form a phosphorus-doped second silicon epitaxial layer of a predetermined thickness;
[0011] The etching step includes: introducing a chlorine-containing etching gas, the silicon reactive gas, and an arsenic-doped gas into the selective epitaxial deposition chamber to trim the contour of the phosphorus-doped second silicon epitaxial layer of a predetermined thickness formed in the deposition step; wherein the temperature of the etching step is at least 50°C higher than the temperature of the deposition step, and the flow rate of the silicon reactive gas in the etching step is not greater than 10% of the flow rate of the silicon reactive gas in the deposition step.
[0012] Optionally, each of the cycles further includes introducing the chlorine-containing etching gas into the selective epitaxial deposition chamber during the deposition step, wherein the flow rate of the chlorine-containing etching gas introduced during the deposition step is less than the flow rate of the silicon reactive gas introduced during the deposition step.
[0013] Furthermore, the flow rate of the chlorine-containing etching gas in the etching step of each cycle is more than twice the flow rate of the chlorine-containing etching gas in the deposition step.
[0014] Optionally, each of the etching steps in the cycle further includes introducing the phosphorus-doped gas into the selective epitaxial deposition chamber, and the arsenic-doped gas flow rate in the etching step is: the phosphorus-doped gas flow rate = (1~4):1.
[0015] Furthermore, the flow rate of the phosphorus-doped gas introduced in the etching step of each cycle is 10 sccm to 100 sccm.
[0016] Optionally, the preset thickness of the phosphorus-doped second silicon epitaxial layer deposited in the deposition step of each cycle is [missing information].
[0017] Furthermore, the same parameters are used for the deposition steps in all the cycles, and the same parameters are used for the etching steps in all the cycles.
[0018] Furthermore, the parameters used in the deposition and etching steps in each cycle are as follows: temperature 400℃~680℃, pressure 10Torr~300Torr, silicon reaction gas is DCS or TCS, phosphorus doping gas is PH3, arsenic doping gas is AsH3, chlorine-containing etching gas is at least one of HCl, Cl and Cl2, and the carrier gas introduced into the selective epitaxial deposition chamber of the chlorine-containing etching gas includes hydrogen.
[0019] Optionally, the groove is U-shaped or Sigma-shaped; a dielectric layer is formed on both sides of the groove.
[0020] The present invention also provides a method for fabricating a FinFET device, including the method for fabricating the epitaxial source and drain of the FinFET device as described in any of the above claims.
[0021] As described above, the method for fabricating the FinFET device and its epitaxial source / drain of the present invention, in fabricating the upper silicon epitaxial layer, i.e., the phosphorus-doped second silicon epitaxial layer, of the epitaxial source / drain of the FinFET device, employs a cycle consisting of a deposition step and an etching step, performed several times to the desired thickness. In the deposition step of each cycle, a phosphorus-doped second silicon epitaxial layer of a predetermined thickness is selectively deposited. Then, in the etching step of the same cycle, the contour of the phosphorus-doped second silicon epitaxial layer of the predetermined thickness deposited in that cycle is trimmed. In the etching step, not only is a chlorine-containing etching gas introduced, but also a silicon reactive gas and arsenic-doped... In the presence of impurity gases, the silicon reactive gas reacts with the arsenic-doped gas to form an arsenic-doped silicon layer on the phosphorus-doped second silicon epitaxial layer. Due to the different etching rates of the chlorine-containing etching gas on the phosphorus-doped and arsenic-doped silicon materials in the <1,1,1> and <1,0,0> crystal directions, the etching rate is slowest in the <1,0,0> crystal direction and fastest in the <1,1,1> crystal direction for both phosphorus-doped and arsenic-doped silicon materials. Simultaneously, the chlorine-containing etching gas exhibits a relatively slow etching rate on the <1,1,1> crystal direction of both phosphorus-doped and arsenic-doped silicon materials. It is stated that the etching rate of arsenic-doped silicon in the <1,1,1> crystal direction is greater than that of phosphorus-doped silicon in the <1,1,1> crystal direction due to the chlorine-containing etching gas. Therefore, in the etching process, the arsenic-doped silicon layer formed on the phosphorus-doped second silicon epitaxial layer is etched first. Since the <1,1,1> crystal direction is etched faster, the chlorine-containing etching gas will etch the phosphorus-doped second silicon epitaxial layer below it before the arsenic-doped silicon layer is completely etched. At this time, because the phosphorus-doped second silicon epitaxial layer has the slowest etching rate in the <1,0,0> crystal direction, the etching rate in the <1,1,1> crystal direction is... The etching rate is the fastest, so the contour of the phosphorus-doped second silicon epitaxial layer can be trimmed, the lateral growth of the phosphorus-doped second silicon epitaxial layer is suppressed, and the contour is diamond-like. When the arsenic-doped silicon material layer is completely etched or even the phosphorus-doped second silicon epitaxial layer is partially etched, the contour of the remaining phosphorus-doped second silicon epitaxial layer is effectively trimmed, achieving the effect of suppressing the lateral growth of the phosphorus-doped second silicon epitaxial layer. After several cycles of this process, the lateral growth of the phosphorus-doped second silicon epitaxial layer that has been continuously thickened is effectively suppressed, and the contour is diamond-like, thereby effectively reducing the risk of source-drain connection between adjacent fins. Attached Figure Description
[0022] Figures 1 to 3 The diagrams shown are cross-sectional views of the epitaxial source and drain fabrication process of several FinFET devices, which are cut across the region where the epitaxial source or drain of the FinFET device is located.
[0023] Figures 4 to 8The diagram shows cross-sectional structural schematics of each step in the fabrication method of the epitaxial source and drain of the FinFET device according to the present invention. These cross-sectional structural schematics are cut in the region where the epitaxial source or drain of the FinFET device is located.
[0024] Figure 9 This is an example diagram showing the relationship between gas flow rate and deposition and etching time when preparing a phosphorus-doped second silicon epitaxial layer in the method for preparing the epitaxial source and drain of the FinFET device of the present invention.
[0025] Component designation explanation
[0026] 10 Substrates
[0027] 11 fins
[0028] 12. Isolation Structure
[0029] 13 Grooves
[0030] 14 Phosphorus-doped first silicon epitaxial layer
[0031] 15 Phosphorus-doped second silicon epitaxial layer
[0032] 16 Dielectric Layer
[0033] 21 Lower source / drain doped layers
[0034] 22 Upper source / drain doped layer
[0035] 23 fins Detailed Implementation
[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0037] Please see Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0038] As described in the background section, when the fin spacing of a FinFET fin structure is large enough, such as Figure 1As shown, the spacing between adjacent fins 23 is large enough that there is no risk of connection between the source and drain electrodes of fins 23. Currently, the source and drain electrodes of FinFETs are phosphorus-doped silicon epitaxy fabricated using selective epitaxy processes and are lightly doped / heavily doped bilayer structures based on device performance considerations, such as... Figure 1 The lower and middle source / drain doped layers 21 are lightly doped, while the upper source / drain doped layer 22 is heavily doped. The lower source / drain doped layer 21 has a lower risk of interconnection due to the constraint of the dielectric layer, while the upper source / drain doped layer 22 grows beyond the top surface of the dielectric layer. Therefore, once it exceeds the top surface of the dielectric layer, it will... Figure 2 As shown, the semiconductor device grows both vertically and horizontally. However, with the continuous miniaturization of semiconductor devices, the spacing between adjacent fins 23 is constantly decreasing to maintain stress requirements. This poses a risk of interconnection between the source and drain electrodes of adjacent fins 23, especially the upper source and drain doped layer 22. Figure 2 A connection has already formed in the middle. At this point, even if the contour of the upper source-drain doped layer 22 is subsequently etched and trimmed, the connection cannot be etched away. Figure 3 As shown, after the contour of the upper source and drain doped layer 22 is etched and trimmed to form a diamond-like shape, the upper source and drain doped layers 22 between adjacent fins 23 are still connected together. This phenomenon will release stress, increase contact resistance, and even generate short circuit risk.
[0039] Based on this, this embodiment provides a method for fabricating epitaxial source and drain electrodes for a FinFET device, the method comprising:
[0040] A substrate is provided, on which two or more fins are formed at intervals, an isolation structure is formed between adjacent fins, a gate is formed on the fin, and grooves are formed on the fins on both sides of the gate;
[0041] A phosphorus-doped first silicon epitaxial layer is deposited in the groove using a selective epitaxial process, wherein the thickness of the phosphorus-doped first silicon epitaxial layer is less than the depth of the groove;
[0042] A second phosphorus-doped silicon epitaxial layer is deposited on the phosphorus-doped first silicon epitaxial layer, the surface of the second phosphorus-doped silicon epitaxial layer being higher than the surface of the groove. The method for depositing the second phosphorus-doped silicon epitaxial layer includes performing a series of cycles consisting of deposition and etching steps until the desired thickness of the second phosphorus-doped silicon epitaxial layer is achieved.
[0043] The deposition step includes: introducing silicon reactive gas and phosphorus doping gas into a selective epitaxial deposition chamber to deposit and form a phosphorus-doped second silicon epitaxial layer of a predetermined thickness;
[0044] The etching step includes: introducing a chlorine-containing etching gas, the silicon reactive gas, and an arsenic-doped gas into the selective epitaxial deposition chamber to trim the contour of the phosphorus-doped second silicon epitaxial layer of a predetermined thickness formed in the deposition step; wherein the temperature of the etching step is at least 50°C higher than the temperature of the deposition step, and the flow rate of the silicon reactive gas in the etching step is not greater than 10% of the flow rate of the silicon reactive gas in the deposition step.
[0045] The method for fabricating the epitaxial source and drain of the FinFET device in this embodiment involves, during the fabrication of the upper silicon epitaxial layer (i.e., the phosphorus-doped second silicon epitaxial layer) of the FinFET device epitaxial source and drain, performing a series of cycles consisting of deposition and etching steps to the desired thickness. In each cycle, the deposition step first selectively deposits a phosphorus-doped second silicon epitaxial layer of a predetermined thickness. Then, in the etching step of that cycle, the contour of the phosphorus-doped second silicon epitaxial layer of the predetermined thickness deposited in that cycle is trimmed. In the etching step, not only a chlorine-containing etching gas is introduced, but also a silicon reactive gas and an arsenic-doped gas are introduced. The silicon reactive gas reacts with the arsenic-doped gas to form an arsenic-doped silicon layer on the phosphorus-doped second silicon epitaxial layer. Due to the different etching rates of the chlorine-containing etching gas on the phosphorus-doped and arsenic-doped silicon materials in the <1,1,1> and <1,0,0> crystal directions, the etching rate is slowest in the <1,0,0> crystal direction and fastest in the <1,1,1> crystal direction for both phosphorus-doped and arsenic-doped silicon materials. Furthermore, the chlorine-containing etching gas has a relatively high etching rate in the <1,1,1> crystal direction for both phosphorus-doped and arsenic-doped silicon materials. The etching rate of chlorine-containing etching gas on arsenic-doped silicon in the <1,1,1> crystal orientation is greater than that on phosphorus-doped silicon in the <1,1,1> crystal orientation. Therefore, in the etching process, the arsenic-doped silicon layer formed on the phosphorus-doped second silicon epitaxial layer is etched first. Because the <1,1,1> crystal orientation is etched faster, the chlorine-containing etching gas will etch the underlying phosphorus-doped second silicon epitaxial layer before the arsenic-doped silicon layer is completely etched. At this point, the phosphorus-doped second silicon epitaxial layer has the slowest etching rate in the <1,0,0> crystal orientation and the slowest etching rate in the <1,1,1> crystal orientation. The process is the fastest, so it can achieve the contour trimming of the phosphorus-doped second silicon epitaxial layer, suppress the lateral growth of the phosphorus-doped second silicon epitaxial layer and make the contour diamond-like. When the arsenic-doped silicon material layer is completely etched or even the phosphorus-doped second silicon epitaxial layer is partially etched, the contour of the remaining phosphorus-doped second silicon epitaxial layer is effectively trimmed, achieving the effect of suppressing the lateral growth of the phosphorus-doped second silicon epitaxial layer. After several cycles of this process, the lateral growth of the phosphorus-doped second silicon epitaxial layer that has been continuously thickened is effectively suppressed and the contour is diamond-like, thereby effectively reducing the risk of source-drain connection between adjacent fins.
[0046] The fabrication method of the epitaxial source and drain of the FinFET device in this embodiment will be described in detail below with reference to the specific accompanying drawings.
[0047] like Figure 4 As shown, step S1 is performed first, a substrate 10 is provided, on which two or more fins 11 are formed at intervals, an isolation structure 12 is formed between adjacent fins 11, a gate (not shown in the figure) is formed on the fin 11, and grooves 13 are formed on the fins 11 on both sides of the gate.
[0048] As an example, the substrate 10 can be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator). The semiconductor substrate can also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and can also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Silicon Germanium On Insulator). In this embodiment, any substrate material suitable for fabricating a FinFET structure is selected, such as a bulk silicon substrate.
[0049] Furthermore, the structure on the substrate 10 can be prepared using any existing suitable method, without any excessive restrictions.
[0050] In this embodiment, the isolation structure 12 adopts a shallow trench isolation structure (STI).
[0051] The specific shape of the groove 13 is not limited, as long as it meets the requirements for fabricating the source and drain electrodes. Preferably, the shape of the groove 13 can be set to U-shape or Sigma-shape.
[0052] As an example, a dielectric layer 16 may be formed on both sides of the groove 13 to restrict the growth direction of the material subsequently selectively epitaxially grown in the groove 13. Preferably, the dielectric layer 16 is made of a low-k dielectric material, such as silicon oxide.
[0053] like Figure 5 As shown, then step S2 is performed, in which a phosphorus-doped first silicon epitaxial layer 14 is deposited in the groove 13 using a selective epitaxial process, wherein the thickness of the phosphorus-doped first silicon epitaxial layer 14 is less than the depth of the groove 13.
[0054] Selective epitaxial growth (SEG) is a technique that utilizes the basic principles of epitaxial growth and the characteristic that silicon is difficult to nucleate and form films on insulators to grow epitaxial layers in specific areas of the silicon surface while not growing them in other areas.
[0055] The phosphorus-doped first silicon epitaxial layer 14 is generally lightly doped, and the specific doping concentration is set according to actual needs, without excessive restrictions here.
[0056] like Figure 8 As shown, in step S3, a second phosphorus-doped silicon epitaxial layer 15 is deposited on the phosphorus-doped first silicon epitaxial layer 14. The surface of the second phosphorus-doped silicon epitaxial layer 15 is higher than the surface of the groove 13. The method for depositing the second phosphorus-doped silicon epitaxial layer 15 includes performing a series of cycles consisting of deposition and etching steps until the desired thickness of the second phosphorus-doped silicon epitaxial layer 15 is achieved.
[0057] like Figure 6 As shown, the deposition step includes: introducing silicon reactive gas and phosphorus doping gas into a selective epitaxial deposition chamber to deposit and form a phosphorus-doped second silicon epitaxial layer 15 of a predetermined thickness;
[0058] like Figure 7 As shown, the etching step includes: introducing a chlorine-containing etching gas, the silicon reactive gas, and an arsenic-doped gas into the selective epitaxial deposition chamber to trim the contour of the phosphorus-doped second silicon epitaxial layer 15 of a predetermined thickness formed in the deposition step; wherein, the temperature of the etching step is at least 50°C higher than the temperature of the deposition step, and the flow rate of the silicon reactive gas in the etching step is not greater than 10% of the flow rate of the silicon reactive gas in the deposition step.
[0059] As a specific example, each of the cycle's deposition steps further includes introducing the chlorine-containing etching gas into the selective epitaxial deposition chamber, and the flow rate of the chlorine-containing etching gas in this deposition step is less than the flow rate of the silicon reactive gas in this deposition step. Simultaneous introduction of the chlorine-containing etching gas during deposition can improve the growth quality of the phosphorus-doped second silicon epitaxial layer 15 and reduce or even prevent the growth of phosphorus-doped second silicon epitaxial layers in other regions. Preferably, the flow rate of the chlorine-containing etching gas in the etching step of each cycle is more than twice the flow rate of the chlorine-containing etching gas in the deposition step.
[0060] As another specific example, the etching step in each cycle further includes introducing the phosphorus-doped gas into the selective epitaxial deposition chamber, and the arsenic-doped gas flow rate in this etching step is: the phosphorus-doped gas flow rate = (1~4):1. Introducing phosphorus-doped gas in the etching step of each cycle is beneficial because the phosphorus-silicon bond energy is lower than the arsenic-silicon bond energy. Before the arsenic-doped silicon material has fully grown, the phosphorus-doped silicon material grows first and is directly etched. Therefore, adding a certain amount of phosphorus-doped gas (i.e., the range of (1~4):1) in the etching step prevents the growth of additional thin film layers during the entire etching process, allowing only the contour of the already deposited thin film layer to be refined, thus improving etching efficiency. In this embodiment, the flow rate of the phosphorus-doped gas introduced in the etching step of each cycle is selected to be 10 sccm to 100 sccm, for example, it can be 10 sccm, 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, 100 sccm, etc.
[0061] As another specific example, the preset thickness of the phosphorus-doped second silicon epitaxial layer deposited in the deposition step of each cycle is [missing information]. For example, it can be... etc.
[0062] It should be noted that the source and drain materials formed in this embodiment are phosphorus-doped silicon materials. Therefore, although a film layer is deposited in each etching cycle, the deposited film layer will be etched away during the etching process. In fact, in order to ensure the etching effect, a portion of the thickness of the film layer formed in the deposition step will be etched. In addition, the number of cycles performed when forming the phosphorus-doped second silicon epitaxial layer in this embodiment is set according to actual needs, and is generally more than twice.
[0063] This embodiment does not excessively restrict whether the implementation time of the corresponding steps in each cycle is the same. That is, the implementation time of the deposition steps in two different cycles can be the same or different. In addition, the implementation time of the etching steps in two different cycles can be the same or different. As long as the etching step can effectively refine the contour of the film deposited in the deposition step within the same cycle, it is acceptable. Preferably, the parameters used for the deposition steps in all the cycles can be set to the same, and the parameters used for the etching steps in all the cycles can be set to the same, that is, all cycles are formed by several identical single cycles, so as to facilitate process control.
[0064] In this embodiment, the specific parameters used for the deposition and etching steps in each cycle are as follows: temperature 400℃~680℃, pressure 10Torr~300Torr, silicon reaction gas is DCS or TCS, phosphorus doping gas is PH3, arsenic doping gas is AsH3, chlorine-containing etching gas is at least one of HCl, Cl and Cl2, and the carrier gas introduced into the selective epitaxial deposition chamber includes hydrogen.
[0065] like Figure 9 As shown, this is a preferred technical solution for depositing the phosphorus-doped second silicon epitaxial layer 15 in this embodiment: where Dep represents the deposition step and OE represents the etching step; the parameters used in Dep in all cycles are the same, and the parameters used in OE in all cycles are the same; the gas introduced into Dep in each cycle includes silicon reactive gas, chlorine-containing etching gas, and phosphorus-doped gas, and the flow rate of silicon reactive gas is greater than the flow rate of chlorine-containing etching gas; the gas introduced into OE in each cycle includes chlorine-containing etching gas, silicon reactive gas, arsenic-doped gas, and phosphorus-doped gas, and the flow rate of chlorine-containing etching gas is greater than the flow rate of silicon reactive gas, and the flow rate of arsenic-doped gas is greater than the flow rate of phosphorus-doped gas.
[0066] This embodiment also provides a method for fabricating a FinFET device, which includes the fabrication of source and drain electrodes, and the fabrication of source and drain electrodes is performed using the method for fabricating epitaxial source and drain electrodes of the FinFET device in this embodiment.
[0067] In summary, this invention provides a method for fabricating epitaxial source and drain electrodes for FinFET devices. When fabricating the upper silicon epitaxial layer (i.e., the phosphorus-doped second silicon epitaxial layer) of the FinFET device's epitaxial source and drain electrodes, a cycle consisting of deposition and etching steps is performed several times to reach the desired thickness. In each cycle's deposition step, a phosphorus-doped second silicon epitaxial layer of a predetermined thickness is selectively deposited. Then, in the etching step of that cycle, the contour of the phosphorus-doped second silicon epitaxial layer of the predetermined thickness deposited in that cycle is trimmed. The etching step introduces not only a chlorine-containing etching gas but also a silicon reactive gas and arsenic. The silicon reactive gas reacts with the arsenic doping gas to form an arsenic-doped silicon layer on the phosphorus-doped second silicon epitaxial layer. Due to the different etching rates of the chlorine-containing etching gas on the phosphorus-doped and arsenic-doped silicon materials in the <1,1,1> and <1,0,0> crystal directions, the etching rate is slowest in the <1,0,0> direction and fastest in the <1,1,1> direction for both phosphorus-doped and arsenic-doped silicon materials. Simultaneously, the chlorine-containing etching gas exhibits a relatively slow etching rate on the <1,1,1> direction of both phosphorus-doped and arsenic-doped silicon materials. It is stated that the etching rate of arsenic-doped silicon in the <1,1,1> crystal direction is greater than that of phosphorus-doped silicon in the <1,1,1> crystal direction due to the chlorine-containing etching gas. Therefore, in the etching process, the arsenic-doped silicon layer formed on the phosphorus-doped second silicon epitaxial layer is etched first. Since the <1,1,1> crystal direction is etched faster, the chlorine-containing etching gas will etch the phosphorus-doped second silicon epitaxial layer below it before the arsenic-doped silicon layer is completely etched. At this time, because the phosphorus-doped second silicon epitaxial layer has the slowest etching rate in the <1,0,0> crystal direction, the etching rate in the <1,1,1> crystal direction is... The fastest etching rate allows for the trimming of the contour of the phosphorus-doped second silicon epitaxial layer, suppressing its lateral growth and resulting in a diamond-like contour. When the arsenic-doped silicon layer is completely etched, or even partially etched, the contour of the remaining phosphorus-doped second silicon epitaxial layer is effectively trimmed, suppressing its lateral growth. After several cycles of this process, the lateral growth of the continuously thickening phosphorus-doped second silicon epitaxial layer is effectively suppressed, resulting in a diamond-like contour and effectively reducing the risk of source-drain interconnection between adjacent fins. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.
[0068] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating epitaxial source and drain electrodes for a FinFET device, characterized in that, The preparation method includes: A substrate is provided, on which two or more fins are formed at intervals, an isolation structure is formed between adjacent fins, a gate is formed on the fin, and grooves are formed on the fins on both sides of the gate; A phosphorus-doped first silicon epitaxial layer is deposited in the groove using a selective epitaxial process, wherein the thickness of the phosphorus-doped first silicon epitaxial layer is less than the depth of the groove; A phosphorus-doped second silicon epitaxial layer is deposited on the phosphorus-doped first silicon epitaxial layer, the surface of the phosphorus-doped second silicon epitaxial layer being higher than the surface of the groove. The method for depositing the phosphorus-doped second silicon epitaxial layer includes performing a cycle consisting of a deposition step and an etching step several times until the phosphorus-doped second silicon epitaxial layer of the desired thickness is reached. The deposition step includes: introducing a silicon reactive gas and a phosphorus doping gas into a selective epitaxial process deposition chamber to deposit and form the phosphorus-doped second silicon epitaxial layer of the predetermined thickness. The etching step includes: introducing a chlorine-containing etching gas, the silicon reactive gas, and an arsenic-doped gas into the selective epitaxial deposition chamber to trim the contour of the phosphorus-doped second silicon epitaxial layer of a predetermined thickness formed in the deposition step; wherein the temperature of the etching step is at least 50°C higher than the temperature of the deposition step, and the flow rate of the silicon reactive gas in the etching step is not greater than 10% of the flow rate of the silicon reactive gas in the deposition step.
2. The method for fabricating the epitaxial source and drain of a FinFET device according to claim 1, characterized in that: Each of the cycles further includes introducing the chlorine-containing etching gas into the selective epitaxial deposition chamber during the deposition step, wherein the flow rate of the chlorine-containing etching gas introduced during the deposition step is less than the flow rate of the silicon reactive gas introduced during the deposition step.
3. The method for fabricating the epitaxial source and drain electrodes of a FinFET device according to claim 2, characterized in that: The flow rate of the chlorine-containing etching gas in the etching step of each cycle is more than twice the flow rate of the chlorine-containing etching gas in the deposition step.
4. The method for fabricating the epitaxial source and drain of a FinFET device according to claim 1, characterized in that: Each of the said cycles includes the etching step of introducing the phosphorus-doped gas into the selective epitaxial deposition chamber, and the arsenic-doped gas flow rate in this etching step is: the phosphorus-doped gas flow rate = (1~4):
1.
5. The method for fabricating the epitaxial source and drain electrodes of a FinFET device according to claim 4, characterized in that: The flow rate of the phosphorus-doped gas introduced in the etching step of each cycle is 10 sccm to 100 sccm.
6. The method for fabricating epitaxial source and drain electrodes of a FinFET device according to claim 1, characterized in that: The preset thickness of the phosphorus-doped second silicon epitaxial layer deposited in the deposition step of each cycle is [missing information].
7. The method for fabricating the epitaxial source and drain of a FinFET device according to any one of claims 1 to 6, characterized in that: The same parameters are used for the deposition steps in all the cycles, and the same parameters are used for the etching steps in all the cycles.
8. The method for fabricating the epitaxial source and drain of a FinFET device according to any one of claims 1 to 6, characterized in that, The parameters used in the deposition and etching steps of each cycle are as follows: temperature 400℃~680℃, pressure 10Torr~300Torr, silicon reaction gas is DCS or TCS, phosphorus doping gas is PH3, arsenic doping gas is AsH3, chlorine-containing etching gas is at least one of HCl, Cl and Cl2, and the carrier gas of the chlorine-containing etching gas introduced into the selective epitaxial deposition chamber includes hydrogen.
9. The method for fabricating epitaxial source and drain electrodes of a FinFET device according to claim 1, characterized in that: The groove is U-shaped or Sigma-shaped; a dielectric layer is formed on both sides of the groove.
10. A method for fabricating a FinFET device, characterized in that, This includes the method for fabricating the epitaxial source and drain of a FinFET device as described in any one of claims 1 to 9.