A low scratch back contact cell and method of making the same

Abstract

The application belongs to the technical field of back contact cells, and particularly relates to a low-scratch back contact cell and a preparation method thereof, which comprises the following steps: S2, sequentially forming a first semiconductor layer and a mask layer on the back surface of a silicon wafer; S3, performing etching opening on the back surface to form a second semiconductor opening area; S4, performing texturing and cleaning; S5, sequentially forming a third semiconductor layer and a sacrifice layer on the front surface of the silicon wafer; S6, performing groove cleaning on the back surface and the second semiconductor opening area obtained in S5, wherein the groove cleaning comprises acid solution cleaning, RCA cleaning and backwashing, and the sacrifice layer is removed in the RCA cleaning and backwashing; and S7, depositing a second semiconductor layer on the back surface. The groove cleaning method is used to replace the chain cleaning method, the back surface plating layer can be fully removed, the front surface anti-reflection layer is protected from corrosion, the anti-reflection effect of the front surface is not affected, mechanical damage or pollution of the back surface of the silicon wafer can be avoided, the overall passivation level can be improved, the back surface scratch can be reduced, and the fill factor and the cell efficiency can be improved.

Description

Technical Field

[0001] This invention belongs to the field of back contact battery technology, specifically relating to a low-scratch back contact battery and its preparation method. Background Technology

[0002] The current low-cost process for back-contact solar cells is post-texturing, which involves removing the back-side coating after depositing a passivation and antireflection layer on the front side. Removing the back-side coating often employs a chain cleaning method, where mechanical transmission and a cleaning solution work together to efficiently remove the coating while keeping the back of the silicon wafer in close contact with the solution, thus preventing corrosion of the front side.

[0003] However, in the actual chain cleaning mechanical transmission process, the silicon wafer surface is easily affected by the mechanical rollers, causing unnecessary scratches or other impurities, which leads to a serious decrease in the fill factor and affects the battery efficiency.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or known technology. Summary of the Invention

[0005] The purpose of this invention is to overcome the defects of existing technologies where silicon wafer scratches or contamination during the texturing process after back contact cells lead to a severe decrease in fill factor and affect cell efficiency. This invention provides a low-scratch back contact cell and its preparation method. This invention uses a tank cleaning method instead of a chain cleaning method, which can fully remove the back-side coating and protect the front anti-reflective layer from corrosion without affecting the anti-reflective effect on the front side. At the same time, it can avoid mechanical damage or contamination to the back of the silicon wafer, improve the overall passivation level, reduce back-side scratches, and improve fill factor and cell efficiency.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a method for preparing a low-scratch back contact battery, comprising the following steps:

[0007] S1. Provides double-sided polished silicon wafers;

[0008] S2. A first semiconductor layer and a mask layer are sequentially formed on the back side of the silicon wafer;

[0009] S3. An opening is etched on the back side obtained in S2 to form a second semiconductor opening region;

[0010] S4. By texturing and cleaning, the residual mask layer and the first semiconductor layer in the second semiconductor opening area are removed, and a textured surface is formed on the front side of the silicon wafer and the second semiconductor opening area. Then, at least part of the mask layer is removed.

[0011] S5. A third semiconductor layer and a sacrificial layer are sequentially formed on the front side of the silicon wafer. The third semiconductor layer includes a passivation layer and an anti-reflection layer. The sacrificial layer is at least one of the following: amorphous silicon layer, microcrystalline silicon layer, nitrogen-doped amorphous silicon layer, nitrogen-doped microcrystalline silicon layer, oxygen-doped amorphous silicon layer, and oxygen-doped microcrystalline silicon layer.

[0012] S6. Perform a tank cleaning on the back side and the second semiconductor opening area obtained in S5. The tank cleaning includes sequential acid solution cleaning and RCA cleaning backwashing, and the sacrificial layer is removed in the RCA cleaning backwashing.

[0013] S7. Deposit a second semiconductor layer on the back side.

[0014] In some preferred embodiments of the present invention, S5 further includes: measuring the thickness D1 of the naturally formed wrap-around coating on the back side in step S5; and controlling the acid solution cleaning time t1 in S6 to satisfy: D1 / a≤t1≤D2 / b, where D2 is the thickness of the sacrificial layer, and D1 and D2 are both values ​​in nm, a is between 0.01 and 0.3, and b is between 0.02 and 0.4.

[0015] In some preferred embodiments of the present invention, the thickness D2 of the sacrificial layer is 1.5-10 nm, and / or the acidic solution cleaning time t1 is 30-450 s.

[0016] In some preferred embodiments of the present invention, in S6, the acidic solution is an HF solution with a mass concentration of 0.5%-10%, and / or the treatment temperature for acidic solution cleaning is 20°C-30°C.

[0017] In some preferred embodiments of the present invention, in S6, the RCA cleaning and backwashing process includes sequentially performing SC1 cleaning solution cleaning, primary water washing, SC2 cleaning solution cleaning, secondary water washing, and acid cleaning and dehydration.

[0018] In some preferred embodiments of the present invention, in S6, the cleaning time t2 of the SC1 cleaning solution, in seconds, satisfies: t2≥D2 / c, where D2 is the thickness of the sacrificial layer in nm, and c is between 0.1 and 0.5.

[0019] In some preferred embodiments of the present invention, the cleaning time t2 of SC1 cleaning solution and the cleaning time of SC2 cleaning solution are each independently 120-480s.

[0020] In some preferred embodiments of the present invention, in S6, the SC1 cleaning solution is a mixed aqueous solution containing ammonia or alkali and hydrogen peroxide, wherein the volume percentage of ammonia or alkali: hydrogen peroxide: water is 1:(1-2):(5-10); the SC2 cleaning solution is a mixed aqueous solution containing hydrochloric acid and hydrogen peroxide, wherein the volume percentage of hydrogen peroxide: hydrochloric acid: water is 1:(1-2):(5-20).

[0021] In some preferred embodiments of the present invention, the temperature of the RCA cleaning backwash in S6 is 30-75°C.

[0022] In some preferred embodiments of the present invention, the preparation method further includes at least one of the following processes:

[0023] Process 1: The sacrificial layer is an amorphous silicon layer;

[0024] Process 2: The mask layer is at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0025] Process 3: Remove all mask layers in S4;

[0026] In process four, S2, the first semiconductor layer is a combination of a first tunneling oxide layer and an N-type polysilicon layer;

[0027] In process 5, S7, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped silicon layer, or a stack of a second tunneling oxide layer and a P-type doped polycrystalline silicon layer.

[0028] In process six, S5, the passivation layer is at least one of amorphous silicon, oxygen-doped amorphous silicon, phosphorus-doped amorphous silicon, silicon oxide, and aluminum oxide film, and the antireflection layer is at least one of silicon nitride, silicon oxynitride, carbon-doped silicon nitride, silicon oxide, and carbon-doped silicon oxide.

[0029] In some preferred embodiments of the present invention, the preparation method further includes the following steps:

[0030] S8. An opening is etched on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0031] S9. Deposit a conductive film layer on the back side obtained in S8;

[0032] S10. A third etching opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an insulating trench.

[0033] S11. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0034] Secondly, the present invention provides a low-scratch back contact battery, which is prepared by the low-scratch back contact battery preparation method described in the first aspect.

[0035] Beneficial effects:

[0036] The present invention, through the above-mentioned technical solution, especially the sacrificial layer formed after the third semiconductor layer is formed on the front side in S5, can withstand the corrosion of acidic solution during the further purification of the second semiconductor opening area in the tank cleaning process in S6, protecting the front anti-reflection layer from acidic solution corrosion. Moreover, the sacrificial layer can be removed in the RCA cleaning backwash solution after the final RCA cleaning backwash, without affecting the anti-reflection effect on the front side. Furthermore, replacing the chain cleaning with the tank cleaning method can fully remove the back-side coating, while avoiding mechanical damage or contamination to the back side of the silicon wafer, improving the overall passivation level, reducing back-side scratches, and improving the fill factor and cell efficiency. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 The image shows the result of a PL (photoluminescence analyzer) test on an existing back-contact battery after it has been cleaned and scratched using a chain cleaning process.

[0039] Figure 2 This image shows the result of a PL (photoluminescence analyzer) test after replacing chain cleaning with a tank cleaning method in one embodiment of the preparation method of the back contact battery of the present invention. Detailed Implementation

[0040] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0042] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of the ranges, the endpoint values ​​of the ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "optional" mean that they may or may not be included (or may or may not be present).

[0043] In this invention, the area closer to the silicon wafer is considered the inside, and the area farther from the silicon wafer is considered the outside.

[0044] In a first aspect, the present invention provides a method for preparing a low-scratch back contact battery, comprising the following steps:

[0045] S1. Provides double-sided polished silicon wafers;

[0046] S2. A first semiconductor layer and a mask layer are sequentially formed on the back side of the silicon wafer;

[0047] S3. An opening is etched on the back side obtained in S2 to form a second semiconductor opening region;

[0048] S4. By texturing and cleaning, the residual mask layer and the first semiconductor layer in the second semiconductor opening area are removed, and a textured surface is formed on the front side of the silicon wafer and the second semiconductor opening area. Then, at least part of the mask layer is removed.

[0049] S5. A third semiconductor layer and a sacrificial layer are sequentially formed on the front side of the silicon wafer;

[0050] S6. Perform a tank cleaning on the back side and the second semiconductor opening area obtained in S5. The tank cleaning includes sequential acid solution cleaning and RCA cleaning backwashing, and the sacrificial layer is removed in the RCA cleaning backwashing.

[0051] S7. Deposit a second semiconductor layer on the back side.

[0052] Preferably, in S5, the third semiconductor layer includes a passivation layer and an anti-reflection layer.

[0053] In some preferred embodiments of the present invention, in step S5, the passivation layer is at least one of amorphous silicon, oxygen-doped amorphous silicon, phosphorus-doped amorphous silicon, silicon oxide, and aluminum oxide film. More preferably, the passivation layer is a combination of silicon oxide and aluminum oxide film, wherein the thickness of the silicon oxide is 1-2 nm and the thickness of the aluminum oxide film is 3-7 nm.

[0054] Preferably, the antireflection layer of the present invention is at least one selected from silicon nitride, silicon oxynitride, carbon-doped silicon nitride, silicon oxide, and carbon-doped silicon oxide. More preferably, the antireflection layer is a combination of silicon nitride and silicon oxide, wherein the thickness of silicon nitride is 50-100 nm and the thickness of silicon oxide is 80-150 nm.

[0055] Preferably, the sacrificial layer of the present invention is at least one of the following: amorphous silicon layer, microcrystalline silicon layer, nitrogen-doped amorphous silicon layer, nitrogen-doped microcrystalline silicon layer, oxygen-doped amorphous silicon layer, and oxygen-doped microcrystalline silicon layer.

[0056] In some preferred embodiments of the present invention, the sacrificial layer is an amorphous silicon layer, which is more conducive to protecting the antireflection layer while being easily removed in subsequent cleaning. The amorphous silicon layer can be deposited by plate PECVD or tubular PECVD, preferably by tubular PECVD. More preferably, the deposition conditions of the amorphous silicon layer include: a temperature of 300-600°C, silane introduction, a silane flow rate of 300-3000 sccm, a gas pressure of 1500-4000 mtorr, and a power of 5000-15000 W.

[0057] In some preferred embodiments of the present invention, step S5 further includes: measuring the thickness D1 of the coating layer naturally formed on the back side in step S5.

[0058] In a further preferred embodiment of the present invention, the acidic solution cleaning time t1 in S6, measured in seconds, satisfies the following condition: D1 / a ≤ t1 ≤ D2 / b, where D2 is the thickness of the sacrificial layer, and both D1 and D2 are measured in nm, with a between 0.01 and 0.3 and b between 0.02 and 0.4. This preferred scheme, which measures the thickness of the coating and controls the acidic solution cleaning time to satisfy a specific relationship, is beneficial for removing the coating around the back edge while simultaneously protecting the anti-reflective layer on the front side from corrosion by the acidic solution. It also improves the overall passivation effect while avoiding scratches during tank cleaning.

[0059] In some preferred embodiments of the present invention, the thickness D2 of the sacrificial layer is 1.5-10 nm, specifically 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, or 10 nm, or any range between two values, more preferably 4-10 nm. The present invention uses a suitablely thin sacrificial layer, which facilitates its rapid removal in subsequent solutions, thus preventing parasitic absorption on the front side from reducing optical performance.

[0060] Preferably, the acidic solution cleaning time t1 is 30-450s, specifically 30s, 40s, 50s, 60s, 70s, 80s, 90s, 100s, 110s, 120s, 130s, 140s, 150s, 170s, 200s, 220s, 250s, 270s, 300s, 320s, 350s, 370s, 400s, 420s, 440s, or 450s, as well as any range between two points, for example, more preferably 30-300s.

[0061] In step S6 of this invention, the back side and the second semiconductor opening area obtained in step S5 are subjected to tank cleaning. The cleaning area includes the back side edge plating area and the second semiconductor opening area. This invention uses tank cleaning instead of chain cleaning, which can effectively remove the back side plating layer, while avoiding mechanical damage or contamination to the back side of the silicon wafer. It can improve the overall passivation level, reduce back side scratches, and improve the fill factor and cell efficiency.

[0062] In some preferred embodiments of the present invention, in S6, the acidic solution is an HF solution with a mass concentration of 0.5%-10%.

[0063] Preferably, the treatment temperature for acidic solution cleaning is 20℃-30℃.

[0064] In some preferred embodiments of the present invention, in S6, the RCA cleaning and rewashing process includes sequential SC1 cleaning solution cleaning, a first water wash, SC2 cleaning solution cleaning, a second water wash, and acid cleaning and dehydration. This preferred approach better ensures the cleanliness of the silicon wafer interface and improves the passivation level of the battery.

[0065] In the acid washing and dehydration process, the acid solution is preferably an HF solution, and the mass concentration of the HF solution can preferably be 0.5%-10%.

[0066] In some preferred embodiments of the present invention, in step S6, the cleaning time t2 of the SC1 cleaning solution, expressed in seconds, satisfies: t2 ≥ D2 / c, where D2 is the thickness of the sacrificial layer, expressed in nanometers (nm), and c is between 0.1 and 0.5. The present invention determines the cleaning time of the SC1 cleaning solution based on the thickness of the sacrificial layer, which facilitates thorough removal of the sacrificial layer, effectively preventing residual sacrificial layer that could lead to severe light absorption on the front side and loss of optical performance, and further improves the overall passivation effect and battery efficiency.

[0067] In some preferred embodiments of the present invention, the cleaning time t2 of SC1 cleaning solution and the cleaning time of SC2 cleaning solution are each independently 20-480s, more preferably 120-480s.

[0068] In some preferred embodiments of the present invention, in S6, the cleaning solution SC1 is a mixed aqueous solution containing ammonia or alkali and hydrogen peroxide, wherein the volume percentage of ammonia or alkali: hydrogen peroxide: water is 1:(1-2):(5-10).

[0069] Preferably, the SC2 cleaning solution is a mixed aqueous solution containing hydrochloric acid and hydrogen peroxide, wherein the ratio of hydrogen peroxide:hydrochloric acid:water is 1:(1-2):(5-20) by volume percentage.

[0070] The water in each cleaning solution of the present invention S6 is preferably deionized water.

[0071] In some preferred embodiments of the present invention, the temperature of the RCA cleaning backwash in S6 is 30-75°C, more preferably 60-75°C.

[0072] In some preferred embodiments of the present invention, in S2, the mask layer is at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Further, the mask layer thickness can be, for example, 40-90 nm.

[0073] In some preferred embodiments of the present invention, all mask layers are removed in S4.

[0074] Preferably, the first semiconductor layer comprises a first passivation layer and a first doped silicon layer, and the second semiconductor layer comprises a second passivation layer and a second doped silicon layer. The first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer. The first doped silicon layer and the second doped silicon layer are each independently polycrystalline silicon, amorphous silicon, or microcrystalline silicon. The second doped silicon layer can be doped amorphous silicon or microcrystalline silicon. The intrinsic silicon layer is preferably an intrinsic amorphous silicon layer. One of the first doped polycrystalline silicon layer and the other of the second doped silicon layer is N-type and the other is P-type.

[0075] In some preferred embodiments of the present invention, in S2, the first semiconductor layer is a combination of a first tunneling oxide layer and an N-type polysilicon layer.

[0076] In some preferred embodiments of the present invention, the second semiconductor layer in S7 is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped silicon layer or a stack of a second tunneling oxide layer and a P-type doped polycrystalline silicon layer.

[0077] The thicknesses and corresponding doping concentrations of the first tunneling oxide layer, the second tunneling oxide layer or the intrinsic hydrogenated amorphous silicon layer, the N-type polycrystalline silicon layer, the P-type doped silicon layer, and the P-type doped polycrystalline silicon layer in this invention can all refer to the ranges of existing technologies and can all be used in this invention. For example, the thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are each independently 1-2 nm, and the thickness of the intrinsic hydrogenated amorphous silicon layer is 3-10 nm; the thickness of the P-type doped silicon layer is 5-15 nm, the thickness of the P-type doped polycrystalline silicon layer is 60-100 nm, and the effective doping concentrations of the P-type doped silicon layer and the P-type doped polycrystalline silicon layer are each independently 1e18 cm⁻¹. -3 -9e19cm -3 The thickness of the N-type polycrystalline silicon layer is 70-120 nm, and the effective doping concentration is greater than 5e18 cm⁻¹. -3 .

[0078] In some preferred embodiments of the present invention, the preparation method further includes the following steps:

[0079] S8. An opening is etched on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0080] S9. Deposit a conductive film layer on the back side obtained in S8;

[0081] S10. A third etching opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an insulating trench.

[0082] S11. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0083] Secondly, the present invention provides a low-scratch back-contact battery, which is prepared by the low-scratch back-contact battery preparation method described in the first aspect. The low-scratch back-contact battery of the present invention has intact protection of each film layer on both the front and back sides, and a clean interface in the second semiconductor opening region. This significantly reduces scratches on the back side of the silicon wafer, improving the overall passivation level, fill factor, and battery efficiency.

[0084] The embodiments of the present invention described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0085] Example 1

[0086] A method for preparing a back-contact battery is as follows:

[0087] S1 and N-type monocrystalline silicon wafers are polished and cleaned on both sides.

[0088] S2. A first semiconductor layer and a mask layer are sequentially formed on the back side of the silicon wafer. The first semiconductor layer is a tunneling oxide layer with a thickness of 1.5 nm and an N-type polysilicon layer (thickness of 120 nm, effective doping concentration of 5e19cm). -3 The combined layer consists of a 50nm thick silicon oxide layer as a mask.

[0089] S3. A first laser-drilled opening is made on the first semiconductor layer and its mask layer on the back side of the silicon wafer to form a second semiconductor opening region arranged at intervals.

[0090] S4. The front side of the silicon wafer is texturized and cleaned to remove the mask layer and the first semiconductor layer remaining in the second semiconductor opening area. At the same time, a texturized surface is formed on the front side of the silicon wafer and the second semiconductor opening area. Finally, the entire mask layer on the back side of the silicon wafer is also removed by the HF cleaning solution.

[0091] S5. A third semiconductor layer and a sacrificial layer are sequentially formed on the front side of the silicon wafer, and the thickness D1 of the naturally formed wraparound layer on the back side in step S5 is measured to be 9 nm. The third semiconductor layer includes a passivation layer and an antireflection layer sequentially disposed. The passivation layer is a combination stack of silicon oxide and aluminum oxide films sequentially disposed, with the silicon oxide layer having a thickness of 1 nm and the aluminum oxide film having a thickness of 6 nm. The antireflection layer is a combination stack of silicon nitride and silicon oxide sequentially disposed, with the silicon nitride layer having a thickness of 80 nm and the silicon oxide layer having a thickness of 110 nm.

[0092] The sacrificial layer is an amorphous silicon layer with a thickness D2 of 7 nm. The amorphous silicon layer is formed by tubular PECVD, and the tubular PECVD conditions include: temperature of 400℃, silane flow rate of 1500 sccm, gas pressure of 1900 mtorr, and power of 8500 W.

[0093] S6. The back side of the silicon wafer and the second semiconductor opening area are cleaned. The cleaning is carried out by a tank cleaning method to clean the edge plating area of ​​the back side of the silicon wafer and the second semiconductor opening area. The cleaning is first done with an acidic solution and then RCA cleaning is performed.

[0094] The acid solution used for cleaning is a 2% HF solution with the remainder being deionized water. The conditions for acid solution cleaning are: a treatment temperature of 25℃ and a cleaning time t1 of 120s. t1, D1, and D2 satisfy: D1 / a < t1 < D2 / b, where a is 0.2 and b is 0.035.

[0095] The RCA cleaning and backwashing process includes sequential SC1 cleaning solution cleaning, a first water rinse, SC2 cleaning solution cleaning, a second water rinse, and HF acid solution (2% mass concentration) cleaning and dehydration. The RCA cleaning and backwashing temperature is 30℃. SC1 cleaning solution is a mixed aqueous solution containing ammonia and hydrogen peroxide, with a volume percentage ratio of ammonia:hydrogen peroxide:water of 1:1.5:7. SC2 cleaning solution is a mixed aqueous solution containing hydrochloric acid (HCl) and hydrogen peroxide, with a volume percentage ratio of hydrogen peroxide:hydrochloric acid:water of 1:1:10. The cleaning times t2 for SC1 and SC2 are 240s and 240s, respectively. t2 satisfies: t2 > D2 / c, where c is 0.18.

[0096] After tank cleaning, there are virtually no scratches on the back of the silicon wafer, such as... Figure 2 As shown.

[0097] S7. A second semiconductor layer is formed on the back side of the silicon wafer; the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous silicon layer. The thickness of the intrinsic hydrogenated amorphous silicon layer is 8 nm, and the thickness of the P-type doped amorphous silicon layer is 13 nm with an effective doping concentration of 3e19cm. -3 .

[0098] S8. A second etching opening is made on the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0099] S9. Deposit a transparent conductive film layer ITO on the back side of the silicon wafer;

[0100] S10. A third etching opening is made on the back of the silicon wafer to form an insulating trench; after etching, the resistance between the first semiconductor and the second semiconductor is greater than 1kΩ.

[0101] S11. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0102] Example 2

[0103] The procedure was carried out in accordance with Example 1, except that the sacrificial layer was a nitrogen-doped amorphous silicon layer with the same thickness.

[0104] Example 3

[0105] The procedure was carried out in accordance with Example 1, except that the sacrificial layer was an oxygen-doped amorphous silicon layer with the same thickness.

[0106] Example 4

[0107] The procedure was carried out in accordance with Example 1, except that the time t1 for cleaning with the acidic solution in S6 was controlled to be 450s.

[0108] Example 5

[0109] The procedure was carried out in accordance with Example 1, except that the thickness D2 of the sacrificial layer was adjusted to 3 nm in S6.

[0110] Example 6

[0111] The procedure was carried out in accordance with Example 1, except that the cleaning time t2 of the SC1 cleaning solution was adjusted to 20s in S6.

[0112] Example 7

[0113] The procedure was carried out in accordance with Example 1, except that the SC2 cleaning solution cleaning and secondary water washing steps in S6 were not performed.

[0114] Comparative Example 1

[0115] The conventional preparation method differs from Example 1 in that no sacrificial layer is formed in S5, and step S6 is replaced with a chain-type cleaning method to remove the back-side coating and further clean the second semiconductor opening area. The chain-type cleaning method utilizes mechanical transmission and the synergistic effect of the cleaning solution to ensure efficient cleaning and removal of the coating by keeping the back side of the silicon wafer in close contact with the solution, while the front side remains uncontacted to avoid corrosion. However, in the actual chain-type cleaning process, the silicon wafer surface is susceptible to unnecessary scratches caused by the mechanical rollers, such as… Figure 1 As shown.

[0116] Test case

[0117] The back-contact batteries obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The fill factor, minority carrier lifetime, battery conversion efficiency, and the proportion of PL test scratches exceeding 1 cm for each embodiment and comparative example were all calculated using Embodiment 1 as the reference benchmark. The data for Embodiment 1 was normalized to a benchmark of 1.000. Other examples were calculated based on Embodiment 1; for example, the fill factor of Comparative Example 1 / the fill factor of Embodiment 1 is 0.978, and the proportion of PL test scratches exceeding 1 cm in Comparative Example 1 / the proportion of PL test scratches exceeding 1 cm in Embodiment 1 is 60.667.

[0118] The percentage of scratches larger than 1cm in the PL test refers to the percentage of batteries with scratches larger than 1cm in a batch of back contact cells obtained from the test. For example, if 5 out of 100 cells in a batch are scratched, the corresponding percentage is 5%.

[0119] Table 1

[0120] Performance indicators Fill factor Low birth rate life expectancy Battery conversion efficiency PL test shows the proportion of scratches larger than 1cm. Example 1 1.000 1.000 1.000 1.000 Example 2 0.998 0.981 0.988 1.083 Example 3 0.999 0.980 0.996 1.750 Example 4 0.980 0.667 0.950 1.250 Example 5 0.993 0.823 0.973 2.333 Example 6 0.985 0.660 0.963 1.000 Example 7 0.982 0.706 0.962 2.417 Comparative Example 1 0.978 0.535 0.954 60.667

[0121] The results above show that, compared with the comparative example, the embodiment of the present invention is beneficial to improving the overall passivation level, reducing back scratches, and improving fill factor and battery efficiency.

[0122] Furthermore, as can be seen from Examples 1 and 2-7, the preferred scheme of the present invention is more conducive to reducing scratches on the back side and improving filler factor and battery efficiency.

[0123] The preferred embodiments of the present invention have been described in detail above; however, the present invention is not limited thereto. Within the scope of the inventive concept, various simple modifications can be made to the technical solutions of the present invention, including combinations of various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in the present invention and are all within the protection scope of the present invention.

Claims

1. A method for preparing a low-scratch back contact battery, characterized in that, Includes the following steps: S1. Provides double-sided polished silicon wafers; S2. A first semiconductor layer and a mask layer are sequentially formed on the back side of the silicon wafer; S3. An opening is etched on the back side obtained in S2 to form a second semiconductor opening region; S4. By texturing and cleaning, the residual mask layer and the first semiconductor layer in the second semiconductor opening area are removed, and a textured surface is formed on the front side of the silicon wafer and the second semiconductor opening area. Then, at least part of the mask layer is removed. S5. A third semiconductor layer and a sacrificial layer are sequentially formed on the front side of the silicon wafer. The third semiconductor layer includes a passivation layer and an anti-reflection layer. The sacrificial layer is at least one of an amorphous silicon layer and a microcrystalline silicon layer. S6. Perform a tank cleaning on the back side and the second semiconductor opening area obtained in S5. The tank cleaning includes sequential acid solution cleaning and RCA cleaning backwash, and the sacrificial layer is removed in the RCA cleaning backwash. The RCA cleaning backwash process includes sequential SC1 cleaning solution cleaning, first water wash, SC2 cleaning solution cleaning, second water wash, and acid cleaning dehydration. S7. Deposit a second semiconductor layer on the back side.

2. The method for preparing a low-scratch back contact battery according to claim 1, characterized in that, S5 also includes: measuring the thickness D1 of the naturally formed wrap-around coating on the back side in step S5; and controlling the acid solution cleaning time t1 in S6 to satisfy: D1 / a≤t1≤D2 / b, where D2 is the thickness of the sacrificial layer, and both D1 and D2 are values ​​in nm, a is between 0.01 and 0.3, and b is between 0.02 and 0.

4.

3. The method for preparing a low-scratch back contact battery according to claim 2, characterized in that, The thickness D2 of the sacrificial layer is 1.5-10 nm, and / or the acidic solution cleaning time t1 is 30-450 s.

4. The method for preparing a low-scratch back contact battery according to claim 1, characterized in that, In S6, the acidic solution is an HF solution with a mass concentration of 0.5%-10%, and / or the acidic solution cleaning treatment temperature is 20℃-30℃.

5. The method for preparing a low-scratch back contact battery according to any one of claims 1-4, characterized in that, In S5, the sacrificial layer is at least one of nitrogen-doped amorphous silicon layer, oxygen-doped amorphous silicon layer, nitrogen-doped microcrystalline silicon layer, and oxygen-doped microcrystalline silicon layer.

6. The method for preparing a low-scratch back contact battery according to claim 1, characterized in that, In S6, the cleaning time t2 of SC1 cleaning solution, in seconds, satisfies: t2≥D2 / c, where D2 is the thickness of the sacrificial layer in nm, and c is between 0.1 and 0.

5. And / or, the cleaning time t2 of SC1 cleaning solution and the cleaning time of SC2 cleaning solution are each independently 120-480s.

7. The method for preparing a low-scratch back contact battery according to claim 1, characterized in that, In S6, SC1 cleaning solution is a mixed aqueous solution containing alkali and hydrogen peroxide, with the volume percentage ratio of alkali:hydrogen peroxide:water being 1:(1-2):(5-10); SC2 cleaning solution is a mixed aqueous solution containing hydrochloric acid and hydrogen peroxide, with the volume percentage ratio of hydrogen peroxide:hydrochloric acid:water being 1:(1-2):(5-20). And / or, the temperature for RCA cleaning and backwashing in S6 is 30-75℃.

8. The method for preparing a low-scratch back contact battery according to claim 1, characterized in that, The preparation method also includes at least one of the following processes: Process 1: The sacrificial layer is an amorphous silicon layer; Process 2: The mask layer is at least one of silicon oxide, silicon nitride, and silicon oxynitride. Process 3: Remove all mask layers in S4; In process four, S2, the first semiconductor layer is a combination of a first tunneling oxide layer and an N-type polysilicon layer; In process 5, S7, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped silicon layer, or a stack of a second tunneling oxide layer and a P-type doped polycrystalline silicon layer. In process six, S5, the passivation layer is at least one of amorphous silicon, silicon oxide, and aluminum oxide film, and the antireflection layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide. In process seven, S5, the passivation layer is at least one of oxygen-doped amorphous silicon and phosphorus-doped amorphous silicon, and the antireflection layer is at least one of silicon carbonitride and silicon carbon oxide.

9. The method for preparing a low-scratch back contact battery according to claim 1, characterized in that, The preparation method also includes the following steps: S8. An opening is etched on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region. S9. Deposit a conductive film layer on the back side obtained in S8; S10. A third etching opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an insulating trench. S11. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

10. A low-scratch back contact battery, characterized in that, It is prepared by the method for preparing a low-scratch back contact battery as described in any one of claims 1-9.

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