Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention provides a solar cell, a preparation method thereof and a photovoltaic module. The solar cell comprises a crystalline silicon substrate, and a tunneling oxide layer, an N-type doped polycrystalline silicon layer and a back passivation layer are sequentially arranged on the back face of the crystalline silicon substrate; the back surface of the crystalline silicon substrate is provided with a rhombic tower footing structure, the size of the rhombic tower footing structure is L, and the L is larger than or equal to 3 microns and smaller than or equal to 7.5 microns, so that the interface contact performance of a back surface electrode and the N-type doped polycrystalline silicon layer can be improved, and uniform distribution of electrode slurry in a contact area of the N-type doped polycrystalline silicon layer is promoted; and the open-circuit voltage, the filling factor and the photoelectric conversion efficiency of the solar cell are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of solar cells, in particular to a solar cell, a preparation method thereof and a photovoltaic module. BACKGROUND

[0002] The passivated contact cell is a kind of solar cell based on selective carrier transport, which has wide application prospects.

[0003] The back surface of the passivated contact cell includes a tunneling oxide layer, an N-type doped polysilicon layer and a back surface electrode, forming a passivated contact structure. How to improve the interface contact performance between the N-type doped polysilicon layer and the back surface electrode to improve the performance of the passivated contact cell has become a technical problem to be solved. SUMMARY

[0004] In order to solve the above technical problems, the present application discloses a solar cell, a preparation method thereof and a photovoltaic module, so as to improve the interface contact performance between the N-type doped polysilicon layer and the back surface electrode.

[0005] In a first aspect, the present application provides a solar cell, comprising:

[0006] a crystalline silicon substrate, the back surface of the crystalline silicon substrate being sequentially provided with a tunneling oxide layer, an N-type doped polysilicon layer and a back surface passivation layer;

[0007] The back surface of the crystalline silicon substrate has a rhombic base structure, and the size of the rhombic base structure is L, 3 μm≤L≤7.5 μm.

[0008] In some embodiments of the present application, the N-type doped polysilicon layer includes a first dopant sublayer, a silicon oxide sublayer and a second dopant sublayer which are stacked.

[0009] In some embodiments of the present application, the second dopant sublayer contains P-O bonds.

[0010] In some embodiments of the present application, the N-type doped polysilicon layer satisfies at least one of the following characteristics:

[0011] a) the thickness of the first dopant sublayer is 5 nm-15 nm, and the doping concentration is 9×10 19 cm 3 -5×10 21 cm 3 ;

[0012] b) the thickness of the second dopant sublayer is 10 nm-60 nm, and the doping concentration is 3×10 20 cm 3 -9×10 21 cm 3 .

[0013] In some embodiments of the present application, the thickness of the N-type doped polysilicon layer is 25-75 nm.

[0014] In some embodiments of the present application, the sheet resistance of the N-type doped polysilicon layer is 20-60 Ω sq -1 -1 .

[0015] In some embodiments of the present application, the front side of the crystalline silicon substrate is sequentially provided with a P-type doped layer, a front side passivation layer and an anti-reflection layer.

[0016] In a second aspect, the present application provides a method for preparing the solar cell according to the first aspect, comprising the following steps:

[0017] providing a crystalline silicon substrate with double-side texturing, and performing boron diffusion treatment on the crystalline silicon substrate to form a P-type doped layer and an alkali etching sacrificial layer with a thickness of 30-100 nm on the back side of the crystalline silicon substrate;

[0018] performing alkali etching treatment on the crystalline silicon substrate with the alkali etching sacrificial layer in an alkali etching tank, wherein the reaction time of the alkali etching tank in the alkali etching treatment is 120-250 s;

[0019] forming a tunneling oxide layer, an N-type doped polysilicon layer and a back side passivation layer on the back side of the crystalline silicon substrate, and forming a front side passivation layer and an anti-reflection layer on the front side of the crystalline silicon substrate.

[0020] In some embodiments of the present application, the growth time of the alkali etching sacrificial layer in the boron diffusion treatment is 60-120 min.

[0021] In some embodiments of the present application, the formation of the N-type doped polysilicon layer comprises:

[0022] sequentially forming a first dopant layer, a silicon oxide layer and a second dopant layer on the back side of the tunneling oxide layer, and introducing oxygen or ozone for oxygen doping during the formation of the second dopant layer.

[0023] In some embodiments of the present application, the flow rate of the introduced oxygen is 400-1000 sccm.

[0024] In a third aspect, the present application provides a photovoltaic module, which comprises the solar cell according to the first aspect, or the solar cell prepared by the preparation method according to the second aspect.

[0025] Compared with the prior art, the present application has at least the following beneficial effects: ​

[0026] The application provides a solar cell and a preparation method thereof and a photovoltaic module, wherein the solar cell comprises a crystalline silicon substrate, and a back surface of the crystalline silicon substrate is sequentially provided with a tunneling oxide layer, an N-type doped polysilicon layer and a back surface passivation layer; the back surface of the crystalline silicon substrate has a rhombic tower base structure, and the rhombic tower base structure has a size L, 3 μm≤L≤7.5 μm. The size L of the rhombic tower base structure in the application is in the above range, which can significantly increase the number of the rhombic tower base structures in a unit area of the back surface of the crystalline silicon substrate, can greatly increase the contact sites of the N-type doped polysilicon layer and electrode paste, effectively improve the interface contact performance of the back surface electrode and the N-type doped polysilicon layer, and promote the uniform distribution of the electrode paste in the area in contact with the N-type doped polysilicon layer, thereby significantly reducing the risk of the electrode paste burning through the N-type doped polysilicon layer during sintering for preparing the back surface electrode, avoiding the increase of the surface recombination of the crystalline silicon substrate caused by this, and improving the open circuit voltage, the fill factor and the photoelectric conversion efficiency of the solar cell. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0028] Figure 1 FIG. 1 is a structural schematic diagram of a solar cell in an embodiment of the application;

[0029] Figure 2 FIG. 3 is a 3D microscope photo of a rhombic tower base structure of a solar cell in an embodiment of the application;

[0030] Figure 3 FIG. 5 is a structural schematic diagram of a rhombic tower base structure in an embodiment of the application;

[0031] Figure 4 FIG. 7 is a structural schematic diagram of an N-type doped polysilicon layer in an embodiment of the application.

[0032] EXPLANATION OF REFERENCE NUMERALS:

[0033] 1-crystalline silicon substrate, 2-tunneling oxide layer, 3-N-type doped polysilicon layer, 4-back surface passivation layer, 5-P-type doped layer, 6-front surface passivation layer, 7-anti-reflection layer, 8-front surface electrode, 9-back surface electrode, 11-rhombic tower base structure, 31-first dopant layer, 32-silicon oxide layer, 33-second dopant layer. DETAILED DESCRIPTION

[0034] With reference to the drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0035] In the present application, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the present application and its embodiments, and are not intended to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0036] In addition, in addition to indicating the orientation or positional relationship, the above-mentioned partial terms may also be used to indicate other meanings, for example, the term "upper" may also be used to indicate a certain dependent relationship or connection relationship in some cases. Those of ordinary skill in the art can understand the specific meaning of these terms in the present application according to the specific situation.

[0037] In addition, the terms "mount", "set", "provided with", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, detachably connected, or integrally constructed; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or internal communication between two devices, elements or components. Those of ordinary skill in the art can understand the specific meaning of the above-mentioned terms in the present application according to the specific situation.

[0038] In addition, the terms "first", "second" and the like are mainly used to distinguish different devices, elements or components (the specific types and structures may be the same or different), and are not intended to indicate or imply the relative importance and quantity of the indicated devices, elements or components. Unless otherwise specified, the meaning of "multiple" is two or more.

[0039] The technical solutions of the present application will be further described below in combination with the embodiments and drawings.

[0040] To improve the photoelectric conversion efficiency of the passivated contact cell, the related art adopts a method of reducing the non-ideal optical loss of the back surface, for example, reducing the thickness of the back surface Poly layer (i.e. doped polysilicon layer) to increase the short-circuit current. However, compared with the solar cell with the conventional Poly layer thickness, due to the thinner back surface Poly layer, a large number of phosphorus atoms are prone to penetrate the tunneling oxide layer structure during the high-temperature annealing process, resulting in the occurrence of the film explosion phenomenon, the increase of the surface recombination of the solar cell, and the decrease of the open-circuit voltage. In addition, due to the large internal expansion of the phosphorus atoms, the surface phosphorus concentration of the N-type doped polysilicon layer is low, resulting in the decrease of the contact performance of the back surface passivation contact structure. Furthermore, due to the significant reduction of the thickness of the back surface Poly layer, the paste is prone to burn through during the screen sintering process, resulting in the decrease of the open-circuit voltage and the fill factor (FF), and the damage of the photoelectric conversion efficiency of the passivated contact cell.

[0041] Therefore, in a first aspect, the present application provides a solar cell. As shown in the drawings, the solar cell comprises a crystalline silicon substrate 1, and the back surface of the crystalline silicon substrate 1 is sequentially provided with a tunneling oxide layer 2, an N-type doped polysilicon layer 3 and a back surface passivation layer 4. Referring to the drawings and Figure 1 Figure 2 and Figure 3 The back surface of the crystalline silicon substrate 1 has a rhombic tower base structure 11, and the size of the rhombic tower base structure 11 is L, 3 μm≤L≤7.5 μm. For example, L is 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm or 7.5 μm. The size L of the rhombic tower base structure is within the above range, which can significantly increase the number of rhombic tower base structures per unit area of the back surface of the crystalline silicon substrate. Since the back electrode mainly forms contact with the rhombic corners of the rhombic tower base structure, the number of rhombic tower base structures increases, the contact sites of the N-type doped polysilicon layer and the electrode paste will be greatly increased, thereby effectively improving the interface contact performance of the back electrode and the N-type doped polysilicon layer. In addition, in the screen printing process, in addition to the contact with the rhombic corners of the rhombic tower base structure, a part of the electrode paste will also stay at the low points around the rhombic tower base structure. Under the condition of a certain amount of electrode paste and electrode grid line width, the smaller the rhombic tower base structure, the more rhombic corners and low points in the rhombic tower base structure, the more uniform the dispersion of the electrode paste on the surface of the N-type doped polysilicon layer, thereby promoting the uniform distribution of the electrode paste in the area in contact with the N-type doped polysilicon layer, significantly reducing the risk of the electrode paste burning through the N-type doped polysilicon layer during the sintering process to prepare the back electrode, and avoiding the increase of the surface recombination of the crystalline silicon substrate caused thereby, thereby improving the open-circuit voltage, the fill factor and the photoelectric conversion efficiency of the solar cell.

[0042] ​In the present application, the size of the diamond-shaped base structure refers to the length of any side of the bottom surface of the diamond-shaped base structure. The Zeta 3D microscope can be used to observe the back surface of the crystalline silicon substrate of the solar cell, so as to determine the size of the diamond-shaped base structure.

[0043] In an alternative embodiment, referring to Figure 4 , the N-type doped polysilicon layer 3 comprises a first doped sub-layer 31, a silicon oxide sub-layer 32 and a second doped sub-layer 33 stacked together. The first doped sub-layer 31 is in contact with the tunneling oxide layer on the side away from the silicon oxide sub-layer 32, the second doped sub-layer 33 is in contact with the back surface passivation layer on the side away from the silicon oxide sub-layer 32, and the silicon oxide sub-layer 32 is located between the first doped sub-layer 31 and the second doped sub-layer 33. The N-type doped polysilicon layer formed by stacking the plurality of sub-layers has better contact performance with the back surface electrode, and the silicon oxide sub-layer therein also has the effect of inhibiting a large number of P atoms in the N-type doped polysilicon layer from diffusing into the silicon of the crystalline silicon substrate, thereby preventing the tunneling oxide layer from being damaged, and reducing the surface recombination of the crystalline silicon substrate.

[0044] In an alternative embodiment, the second doped sub-layer has P-O bonds. The bond energy of the P-O bond is 410 kJ / mol, and the P-O bond is less likely to break at high temperatures. Therefore, under the action of the P-O bond, the diffusion of a large number of phosphorus into the crystalline silicon substrate during high-temperature annealing can be significantly inhibited, thereby increasing the surface phosphorus doping concentration of the N-type doped polysilicon layer, inhibiting the destruction of the tunneling oxide layer structure, and facilitating the improvement of the passivation performance at the interface between the N-type doped polysilicon layer and the tunneling oxide layer.

[0045] In an alternative embodiment, referring to Figure 4 , the thickness of the first doped sub-layer 31 is H1, and 5 nm≤H1≤15 nm. The doping concentration of the first doped sub-layer is 9×10 19 cm 3 -5×10 21 cm 3 -1. The thickness and doping concentration of the first doped sub-layer within the above range have a better buffering effect on the internal diffusion of a large number of phosphorus atoms, thereby inhibiting the internal diffusion of a large number of phosphorus atoms into the crystalline silicon substrate, and further reducing the damage of the internally diffused phosphorus atoms to the tunneling oxide layer.

[0046] In an alternative embodiment, referring to Figure 4 , the thickness of the second doped sub-layer 33 is H2, and 10 nm≤H2≤60 nm. The doping concentration of the second doped sub-layer is 3×10 20 cm 3 -9×10 21 cm 3The thickness and doping concentration of the second doped sub-layer within the above range can further improve the contact performance between the back electrode and the N-type doped polysilicon layer. Increasing the phosphorus doping concentration in the N-type doped polysilicon layer can increase the carrier concentration in the N-type doped polysilicon layer, more carriers participate in the conduction process, which can enhance the transport capacity of the carriers, making it easier for the current to transmit between the N-type doped polysilicon layer and the back electrode, thereby improving the contact effect. According to the metal-semiconductor contact theory, high-concentration phosphorus atoms can reduce the barrier height of the metal-semiconductor contact area, and the carriers can still more easily cross the barrier through the tunneling effect, thereby reducing the contact resistance, making the current transmission smoother, and improving the contact performance.

[0047] In an alternative embodiment, referring to Figure 4 The thickness of the N-type doped polysilicon layer 3 is H0, and 25nm≤H0≤75nm. The N-type doped polysilicon layer within the above thickness range in combination with the diamond-shaped base structure within the size range of the present application can enable the N-type doped polysilicon layer to maintain a relatively thin thickness while improving the uniform distribution of the electrode paste, avoiding the N-type doped polysilicon layer from being burned through during the sintering process to prepare the back electrode, and enabling the N-type doped polysilicon layer and the back electrode to have better interface contact performance.

[0048] In an alternative embodiment, the sheet resistance of the N-type doped polysilicon layer is 20Ωsq -1 - 60Ωsq -1 Thus, it indicates that the surface phosphorus-doped polysilicon concentration of the N-type doped polysilicon layer is relatively high, which is conducive to further improving the contact performance with the back electrode.

[0049] In an alternative embodiment, referring to Figure 1 The front surface of the crystalline silicon substrate 1 is sequentially provided with a P-type doped layer 5, a front passivation layer 6, and an anti-reflection layer 7. In addition, the front surface of the solar cell is also provided with a front electrode 8.

[0050] The material of the front passivation layer and the anti-reflection layer is not particularly limited in the present application as long as it can achieve the purpose of the present application. For example, the material of the front passivation layer includes aluminum oxide, and / or the material of the anti-reflection layer includes at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

[0051] The tunneling oxide layer material of the present application can include a variety of dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polysilicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the tunneling oxide layer can be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation performance, can minimize the recombination loss of minority carriers on the surface of the semiconductor substrate, and is a thin film with excellent durability to subsequent high-temperature processes. In order to better provide interface passivation for the substrate, the thickness of the tunneling oxide layer can be 0.1 nm to 5 nm. For example, the thickness of the tunneling oxide layer can be 0.1 nm, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 3 nm, 4 nm, 5 nm, etc., however, the present application is not limited thereto, and the thickness of the tunneling oxide layer can have various values. The tunneling oxide layer, as a potential barrier for electrons and holes, can be combined with a polysilicon layer to prevent the passage of minority carriers. The tunneling oxide layer can also have a pinhole channel effect, allowing the free movement of carriers within the solar cell, and selectively passing majority carriers through the heavily doped polysilicon, which helps to reduce the recombination loss of minority carriers. In addition, the tunneling oxide layer can be used as a diffusion barrier to prevent the diffusion of dopants from the doped polysilicon layer into the semiconductor substrate.

[0052] In the present application, the front electrode and the back electrode can be formed by screen printing, and the present application does not have special restrictions on the preparation process, as long as the front electrode and the back electrode can be formed. The material of the front electrode can be silver, nickel-copper alloy, aluminum, etc., see Figure 1 The front electrode 8 is in contact with the P-type doped layer 5; the back of the present application is also provided with a back electrode 9, and the material of the back electrode can be silver, nickel-copper alloy, aluminum, etc., and the back electrode 9 is in contact with the N-type doped polysilicon layer 3.

[0053] The present application does not have special restrictions on the thickness of each functional layer, as long as the purpose of the present application can be achieved. For example, the thickness of the front passivation layer is 3 nm to 7 nm, the thickness of the anti-reflection layer is 50 nm to 120 nm, and the thickness of the back passivation layer is 50 nm to 120 nm.

[0054] The passivated contact cell of the present application includes a TOPCon solar cell.

[0055] In a second aspect, the present application provides a method for preparing a solar cell as described in the first aspect, comprising the following steps:

[0056] Step A, providing a crystalline silicon substrate with double-sided texturing, and performing boron diffusion treatment on the crystalline silicon substrate to form an alkali etching sacrificial layer with a thickness of 30 nm to 100 nm on the back of the crystalline silicon substrate;

[0057] Step B, performing an alkaline etching process on the crystalline silicon substrate with the alkaline-etching sacrificial layer in an alkaline etching tank, wherein the reaction time of the alkaline etching tank is 120s-250s;

[0058] Step C, forming a P-type doped layer, a front passivation layer and an anti-reflective layer on the front side of the crystalline silicon substrate, and forming a tunneling oxide layer, an N-type doped polysilicon layer and a back passivation layer on the back side of the crystalline silicon substrate.

[0059] In Step A, the thickness of the alkaline-etching sacrificial layer is 30nm-100nm. On the one hand, the alkaline-etching sacrificial layer has a thicker thickness. On the other hand, the main component of the alkaline-etching sacrificial layer is boron-doped silicon oxide, so the reaction rate of the alkaline-etching sacrificial layer with the alkaline etching solution is slower, so that the alkaline-etching sacrificial layer can be removed more slowly in the alkaline etching process. Thus, when the alkaline-etching sacrificial layer is removed, the alkaline etching solution will contact the crystalline silicon substrate originally under the alkaline-etching sacrificial layer later, thereby facilitating the formation of the diamond-shaped base structure in the size range of the present application.

[0060] In Step B, the reaction time of the alkaline etching tank is controlled in the range of the present application to avoid excessive corrosion of the alkaline etching solution to the crystalline silicon substrate, thereby facilitating the formation of the diamond-shaped base structure in the size range of the present application.

[0061] However, the alkaline-etching sacrificial layer should not be too thick, otherwise a longer reaction time of the alkaline etching tank is needed to remove the alkaline-etching sacrificial layer, which increases the risk of damage to the front surface texturing structure of the crystalline silicon substrate. Moreover, the reaction time of the alkaline etching tank should not be too short, otherwise the alkaline-etching sacrificial layer is difficult to be removed. Based on this, the present application controls the thickness of the alkaline-etching sacrificial layer and the reaction time of the alkaline etching tank in coordination, so that the alkaline-etching sacrificial layer can be effectively removed while avoiding damage to the front surface texturing structure during the alkaline etching process.

[0062] In Step C, the other film layers of the front and back sides of the solar cell, and the front and back electrodes can be prepared by the following steps:

[0063] Preparation of the tunneling oxide layer: a tubular plasma enhanced chemical vapor deposition (PECVD) device is used to deposit a tunneling oxide layer on the back side of the silicon substrate;

[0064] Preparation of the N-type doped polysilicon layer: a tubular PECVD device is used to deposit a phosphorus-doped amorphous silicon layer on the tunneling oxide layer, and then the phosphorus-doped amorphous silicon layer is annealed in a nitrogen atmosphere to crystallize the amorphous silicon in the phosphorus-doped amorphous silicon layer, thereby forming an N-type doped polysilicon layer to form a passivation contact structure with the tunneling oxide layer;

[0065] Preparation of the front passivation layer: an atomic layer deposition (ALD) device is used to deposit an aluminum oxide layer on the P-type doped layer as a front passivation layer;

[0066] Preparation of back passivation layer: A silicon nitride layer is deposited on an N-type doped polysilicon layer using a PECVD device as the back passivation layer;

[0067] Fabrication of antireflection layer: A silicon oxynitride layer is deposited on the front passivation layer using a PECVD device as an antireflection layer;

[0068] Preparation of front and back electrodes: Electrode pastes are printed on the front and back of the initial structure of the solar cell by screen printing, and the front electrode is formed after sintering.

[0069] In one optional embodiment, during the boron diffusion treatment, the growth time of the alkaline polishing sacrificial layer is 60 min to 120 min, which is beneficial for forming an alkaline polishing sacrificial layer within the thickness range of this application.

[0070] In one alternative implementation, during the boron diffusion process of this application:

[0071] During the source-passing stage, the source-passing time is 5 min to 15 min, the temperature is 750℃ to 900℃, the BCl3 flow rate is 70 sccm to 130 sccm, the O2 flow rate is 250 sccm to 600 sccm, and the N2 flow rate is 2000 sccm to 6500 sccm.

[0072] During the propulsion phase, the propulsion time is 5 min to 20 min, the temperature is 800℃ to 950℃, the BCl3 flow rate is 0 sccm, the O2 flow rate is 0 sccm, and the N2 flow rate is 2000 sccm to 6500 sccm.

[0073] During the alkaline sacrificial layer formation stage, the deposition time was 60 min to 120 min, the temperature was 900℃ to 1200℃, the BCl3 flow rate was 0 sccm, the O2 flow rate was 15000 sccm to 20000 sccm, and the N2 flow rate was 1000 sccm to 3500 sccm.

[0074] In one alternative implementation, the formation process of the N-type doped polysilicon layer includes:

[0075] A first doped sublayer, a silicon oxide sublayer, and a second doped sublayer are sequentially formed on the back side of the tunneling oxide layer. Oxygen is introduced during the formation of the second doped sublayer for oxygen doping. This allows phosphorus in the second doped sublayer to form PO bonds with oxygen. The PO bonds can significantly suppress the diffusion of a large amount of phosphorus into the crystalline silicon substrate during high-temperature annealing, thereby increasing the surface phosphorus doping concentration of the N-type doped polycrystalline silicon layer, reducing the degree of damage to the tunneling oxide layer structure, and improving the passivation performance at the interface between the N-type doped polycrystalline silicon layer and the tunneling oxide layer.

[0076] In one alternative embodiment, during the formation of the N-type doped polysilicon layer of this application:

[0077] In the first doped sub-layer forming stage, the reaction time is 10s-50s, the PH3 flow rate is 150sccm-500sccm, the SiH4 flow rate is 1500sccm-3500sccm, the N2O flow rate is 0sccm, the O3 flow rate is 0sccm, the power is 11500W-15500W, and the power source frequency is 150Hz-300Hz.

[0078] In the silicon oxide sub-layer forming stage, the reaction time is 10s-40s, the SiH4 flow rate is 0sccm, the N2O flow rate is 5000sccm-14500sccm, the PH3 flow rate is 0sccm, the O3 flow rate is 0sccm, the power is 6000W-13000W, and the power source frequency is 150Hz-300Hz.

[0079] The second doped sub-layer forming stage includes a first sub-film layer forming stage, an oxygen doping stage, and a second sub-film layer forming stage, wherein:

[0080] In the first sub-film layer forming stage, the reaction time is 220s-350s, the PH3 flow rate is 150sccm-500sccm, the SiH4 flow rate is 1400sccm-3500sccm, the N2O flow rate is 0sccm, the O3 flow rate is 0sccm, the power is 11500W-15500W, and the power source frequency is 150Hz-300Hz.

[0081] In the oxygen doping stage, the reaction time is 20s-60s, the PH3 flow rate is 0sccm, the SiH4 flow rate is 0sccm, the N2O flow rate is 0sccm, the O3 or O2 flow rate is 400sccm-1000sccm, the power is 11500W-15500W, and the power source frequency is 150Hz-300Hz.

[0082] In the second sub-film layer forming stage, the reaction time is 100s-200s, the PH3 flow rate is 150sccm-500sccm, the SiH4 flow rate is 1400sccm-3500sccm, the N2O flow rate is 0sccm, the O3 flow rate is 0sccm, the power is 11500W-15500W, and the power source frequency is 150Hz-300Hz.

[0083] Then, an annealing process is performed to form an N-type doped polysilicon layer, specifically a phosphorus-doped polysilicon layer, and the annealing temperature is 850°C-920°C.

[0084] The inventors have found that, in the oxygen doping stage, when the flow rate of oxygen is too small (for example, less than 400 sccm), it is difficult to have sufficient oxygen elements to form P-O bonds with phosphorus elements in the second dopant layer; when the flow rate of oxygen is too large (for example, greater than 1000 sccm), a large amount of oxygen atoms will be introduced into the second dopant layer, resulting in a decrease in the doping vacancy of P atoms, a decrease in the phosphorus doping concentration on the surface of the second dopant layer, and an impact on the contact performance of the solar cell. By controlling the flow rate of oxygen within the above range, P-O bonds can be formed in the second dopant layer, thereby reducing the damage degree of the tunnel oxide layer structure, and the phosphorus doping concentration on the surface of the N-type doped polysilicon layer can be ensured, which is beneficial to improving the passivation performance at the interface between the N-type doped polysilicon layer and the tunnel oxide layer.

[0085] In an optional embodiment, after the second dopant layer is formed, a silicon oxide mask layer can be prepared on the back surface of the N-type doped polysilicon layer, which can be used to prepare a selective Poly layer, and then the silicon oxide mask layer is removed during RCA cleaning. In the silicon oxide mask layer forming stage, the reaction time is 30 s to 70 s, the PH3 flow rate is 0 sccm, the SiH4 flow rate is 1400 sccm to 2400 sccm, the N2O flow rate is 7000 sccm to 10000 sccm, the power is 11000 W to 16000 W, and the power frequency is 150 Hz to 230 Hz.

[0086] The preparation method of the solar cell provided in the present application can form the diamond tower base structure in the size range of the present application by synergistically regulating the thickness of the alkali etching sacrificial layer and the reaction time of the alkali etching treatment. The tower base structure with smaller size can significantly increase the number of diamond tower base structures in a unit area on the back surface of the crystalline silicon substrate, which can greatly increase the contact sites between the N-type doped polysilicon layer and the electrode paste, effectively improve the interface contact performance between the back electrode and the N-type doped polysilicon layer, and promote the uniform distribution of the electrode paste in the area in contact with the N-type doped polysilicon layer, thereby significantly reducing the risk of the electrode paste burning through the N-type doped polysilicon layer during the sintering process for preparing the back electrode, avoiding the increase in the surface recombination of the crystalline silicon substrate caused thereby, and improving the open-circuit voltage, the fill factor, and the photoelectric conversion efficiency of the solar cell.

[0087] The texturing process is not particularly limited in the present application, as long as a crystalline silicon substrate with a front surface texturing structure can be formed.

[0088] The alkali etching solution is not particularly limited in the present application, as long as the purpose of the present application can be achieved. For example, the texturing solution can be obtained through a commercial channel, and the main components thereof are a solution providing hydroxide ions (such as NaOH or KOH) and hydrogen peroxide (H2O2).

[0089] In a third aspect, the present application provides a photovoltaic module, which comprises the solar cell according to the first aspect, or which comprises the solar cell prepared by the preparation method according to the second aspect.

[0090] The present application also provides a photovoltaic module, which is used for converting received light energy into electric energy and transmitting the electric energy to an external load. The photovoltaic module comprises at least one cell string connected by a plurality of the above-mentioned solar cells, an encapsulating adhesive film for covering the surface of the cell string, and a cover plate for covering the surface of the encapsulating adhesive film away from the cell string.

[0091] Embodiment

[0092] The solar cell and the preparation method thereof, and the photovoltaic module according to the embodiments of the present application will be further described below in combination with more specific embodiments.

[0093] Embodiment 1

[0094] <boron diffusion>

[0095] A crystalline silicon substrate with double-textured back is provided, and boron diffusion treatment is performed on the crystalline silicon substrate to form a P-type doped layer and an alkali-etching sacrificial layer with a thickness of 50 nm on the back surface of the crystalline silicon substrate;

[0096] <alkali-etching>

[0097] The crystalline silicon substrate with the alkali-etching sacrificial layer is subjected to alkali-etching treatment in an alkali-etching tank, and the alkali-etching sacrificial layer is removed and a rhombic pedestal structure is formed on the back surface of the crystalline silicon substrate during the alkali-etching treatment, with a reaction time of 200 s;

[0098] <Preparation of the tunneling oxide layer>

[0099] The tunneling oxide layer is deposited on the back surface of the silicon substrate by using a tube PECVD device;

[0100] <Preparation of the N-type doped polysilicon layer>

[0101] The first doped sublayer, the silicon oxide sublayer and the second doped sublayer are sequentially formed on the back surface of the tunneling oxide layer by using a tube PECVD device, and oxygen doping is performed by introducing oxygen gas during the formation of the second doped sublayer, with a flow rate of 700 sccm, to obtain an N-type doped polysilicon layer with a thickness of about 50 nm after crystallization annealing at 900 ℃;

[0102] <Preparation of the front passivation layer>

[0103] The aluminum oxide layer is deposited on the P-type doped layer as the front passivation layer by using an ALD device;

[0104] <Preparation of the back passivation layer>

[0105] A silicon nitride layer is deposited on the N-type doped polysilicon layer as a back passivation layer using a PECVD apparatus;

[0106] <Preparation of electrodes>

[0107] A front electrode and a back electrode are respectively prepared on the front surface and the back surface of the solar cell semi-finished product by screen printing to form a solar cell structure as shown in Figure 1

[0108] Examples 2 to 3

[0109] Except for adjusting the thickness of the sacrificial layer and the reaction time of the alkali tank in the <Boron diffusion> according to Table 1, the rest is the same as Example 1.

[0110] Example 4

[0111] Except for adjusting the oxygen flow rate of oxygen doping to 400 sccm in the <Preparation of N-type doped polysilicon layer>, the rest is the same as Example 1.

[0112] Example 5

[0113] Except for adjusting the oxygen flow rate of oxygen doping to 1000 sccm in the <Preparation of N-type doped polysilicon layer>, the rest is the same as Example 1.

[0114] Comparative Example 1

[0115] Except for adjusting the thickness of the sacrificial layer and the reaction time of the alkali tank in the <Boron diffusion> according to Table 1, and not introducing oxygen in the <Preparation of N-type doped polysilicon layer>, the rest is the same as Example 1.

[0116] Comparative Example 2

[0117] Except for adjusting the oxygen flow rate of oxygen doping to 700 sccm in the <Preparation of N-type doped polysilicon layer> during the formation of the second dopant layer, the rest is the same as Comparative Example 1.

[0118] Table 1: Related preparation parameters of Examples 1 to 3 and Comparative Example 1

[0119]

[0120] In Table 1, " / " indicates that the related preparation parameter does not exist.

[0121] Performance test:

[0122] Size test of diamond tower base structure:

[0123] ​Place the solar cell on the base of the Zeta 3D microscope, and observe the back surface of the solar cell by magnifying different magnifications (for example, 20x, 50x, 100x), refer to Figure 2 , and calculate the size of the rhombic tower base structure.

[0124] Determination of P-O bonds in the second doped sub-layer:

[0125] Place the prepared solar cell on the machine table of the infrared spectrometer, and then perform scanning to measure the corresponding infrared absorption spectrum, so as to determine whether the P-O bond is present therein.

[0126] Thickness test of the first doped sub-layer, the second doped sub-layer and the N-type doped layer:

[0127] The thickness of the first doped sub-layer, the second doped sub-layer and the N-type doped layer is tested by an ellipsometer.

[0128] Sheet resistance test of the N-type doped polysilicon layer:

[0129] The sheet resistance of the N-type doped polysilicon layer is tested by a four-probe sheet resistance tester.

[0130] Doping concentration test of the first doped sub-layer and the second doped sub-layer:

[0131] Place the solar cell sample to be tested on the test machine table of the ECV tester, so that the probe contacts the surface of the phosphorus doped polysilicon layer on the back surface of the solar cell to perform ECV test, and an ECV curve is obtained. In the ECV curve, a relatively obvious concentration reduction can be observed. The curve region with higher concentration corresponds to the second doped sub-layer, and the curve region with lower concentration corresponds to the first doped sub-layer, so that the phosphorus doping concentrations of the first doped sub-layer and the second doped sub-layer are measured.

[0132] Open-circuit voltage, short-circuit current, fill factor and photoelectric conversion efficiency test:

[0133] The current (I)-voltage (V) of the solar cells of each example and the comparative example is measured by using an I-V tester (model: MX-MPVC-A20, manufacturer: Suzhou Mayfor Technology Co., Ltd.), so as to obtain the open-circuit voltage (Voc), the short-circuit current (Isc), the fill factor (FF) and the photoelectric conversion efficiency (Eff) of the solar cell.

[0134] Table 2: Performance data of each example and the comparative example

[0135] Voc (V) Isc (A) FF (%) Eff (%) Example 1 0.7377 18.570 86.45 26.880 Example 2 0.7378 18.571 86.41 26.879 Example 3 0.7382 18.575 86.65 26.946 Example 4 0.7381 18.573 86.56 26.921 Example 5 0.7375 18.571 86.40 26.852 Comparative Example 1 0.7342 18.567 86.22 26.701 Comparative Example 2 0.7344 18.566 86.31 26.734

[0136] As can be seen from Examples 1 to 3 and Comparative Example 1, the open-circuit voltage, short-circuit current and fill factor of the solar cell of Comparative Example 1 are low, resulting in a relatively low photoelectric conversion efficiency, which can be due to the fact that the size of the diamond-shaped tower base structure of Comparative Example 1 is large, resulting in a small number of diamond-shaped tower base structures per unit area on the back surface of the crystalline silicon substrate, which makes it difficult to improve the interface contact performance between the back electrode and the N-doped polysilicon layer and to promote the uniform distribution of the electrode paste in the area in contact with the N-doped polysilicon layer. In the present application, the open-circuit voltage, short-circuit current and fill factor of the solar cell are all improved, resulting in an improved photoelectric conversion efficiency of the solar cell.

[0137] As can be seen from Examples 4 to 5 and Comparative Example 2, the open-circuit voltage, short-circuit current and fill factor of the solar cell of Comparative Example 2 are low, resulting in a low photoelectric conversion efficiency, which can be due to the fact that although the second sub-doped layer of Comparative Example 2 is also oxygen-doped, the size of the diamond-shaped tower base structure is large, which affects the performance of the solar cell. In the present application, the size of the diamond-shaped tower base structure is controlled within the range of the present application, and the second sub-doped layer is further oxygen-doped, which further improves the photoelectric conversion efficiency of the solar cell.

[0138] The above describes in detail a solar cell and a preparation method thereof and a photovoltaic module disclosed in the present application. The principles and implementation modes of the present application are described by applying specific examples. The above description of the examples is only used to help understand the technical solutions and core invention points of the embodiments of the present application. Meanwhile, for those skilled in the art, the specific implementation modes and application ranges can be changed according to the idea of the present application. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A solar cell, characterized by, The solar cell comprises: a crystal silicon substrate, a back surface of the crystal silicon substrate being sequentially provided with a tunneling oxide layer, an N-type doped polysilicon layer and a back passivation layer; the back surface of the crystal silicon substrate has a rhombic base structure, and the rhombic base structure has a size L, 3 μm≤L≤7.5 μm.

2. The solar cell according to claim 1, characterized in that, The N-type doped polysilicon layer comprises a first doped sub-layer, a silicon oxide sub-layer and a second doped sub-layer which are stacked.

3. The solar cell according to claim 2, characterized in that, The second doped sub-layer has P-O bonds.

4. The solar cell according to claim 2, characterized in that, The N-type doped polysilicon layer satisfies at least one of the following characteristics: a) the first doped sub-layer has a thickness of 5 nm to 15 nm and a doping concentration of 9 x 1018cm-3to 5 x 1019cm-3; 19 3 21 3 ;​​​ b) the second doped sub-layer has a thickness of 10 nm to 60 nm and a doping concentration of 3 x 1018cm-3 to 9 x 1018cm-3. 20 3 21 3 .​​​​ 5. The solar cell according to claim 1, characterized in that, The thickness of the N-type doped polysilicon layer is 25 nm-75 nm.

6. The solar cell according to claim 1, characterized in that, The sheet resistance of the N-type doped polysilicon layer is 20 Ωsq -1 ~ 60 Ωsq -1 .

7. The solar cell according to claim 1, characterized in that, The front surface of the crystal silicon substrate is sequentially provided with a P-type doped layer, a front passivation layer and an anti-reflection layer.

8. A method of producing a solar cell as claimed in any one of claims 1 to 7, characterized by, The method comprises the following steps: a crystal silicon substrate which has been double-textured is provided, and boron diffusion treatment is performed on the crystal silicon substrate to form a P-type doped layer and an alkali etching sacrificial layer with a thickness of 30 nm-100 nm on the back surface of the crystal silicon substrate; alkali etching treatment is performed on the crystal silicon substrate with the alkali etching sacrificial layer in an alkali etching tank, and the reaction time of the alkali etching tank in the alkali etching treatment is 120 s-250 s; a tunneling oxide layer, an N-type doped polysilicon layer and a back passivation layer are formed on the back surface of the crystal silicon substrate, and a front passivation layer and an anti-reflection layer are formed on the front surface of the crystal silicon substrate.

9. The production method according to claim 8, characterized by, In the boron diffusion treatment, the growth time of the alkali etching sacrificial layer is 60 min-120 min.

10. The preparation method according to claim 8, characterized in that, The formation process of the N-type doped polysilicon layer comprises: a first doped sub-layer, a silicon oxide sub-layer and a second doped sub-layer are sequentially formed on the back surface of the tunneling oxide layer, and oxygen or ozone is introduced for oxygen doping during the formation of the second doped sub-layer.

11. The method of claim 10, wherein, The flow rate of the introduced oxygen is 400 sccm-1000 sccm.

12. A photovoltaic module, characterized by The photovoltaic module comprises the solar cell of any one of claims 1-7, or the photovoltaic module comprises the solar cell prepared by the preparation method of any one of claims 8-11.

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