LED chip

Abstract

This invention provides a light-emitting diode (LED) chip. The LED chip includes an LED unit and a hard mask covering the sidewalls of the LED unit. An insulating layer is covered on the sidewalls of the hard mask, and the sidewalls of the insulating layer extend continuously downwards, such that the outer wall of the insulating layer does not form a step at the connection point between the electrode layer and the light-emitting body. The step is defined as a wall surface with a predominantly horizontal extension direction. Because no step is formed, the size of the light-emitting body of the LED unit can be made larger within a given pixel size, thereby obtaining a larger light-emitting area and improving the light extraction efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more specifically to a light-emitting diode chip. Background Technology

[0002] Existing micro-LED chips use large-sized pixel units, typically 10μm or larger. Because the pixel unit itself is large enough, the maximum horizontal width of the LED body can be smaller than the horizontal width of the bottom electrode layer while still ensuring the area of ​​the light-emitting region. Furthermore, since the maximum horizontal width of the LED body in existing micro-LED chips is smaller than the horizontal width of the bottom electrode layer, and LEDs typically include an insulating layer, the sidewalls of the insulating layer (i.e., the portion of the insulating layer located on the sidewall of the LED) often form a stepped structure in certain sections; that is, existing micro-LED chips exhibit a stepped structure. Typically, the width of this stepped structure is greater than 1μm.

[0003] As the size of micro-LEDs continues to shrink, the impact of the aforementioned stepped structure becomes increasingly prominent. For example, for a single LED with a diameter of 4μm, a 1μm step space is equivalent to encroaching on a considerable portion of the volume of the light-emitting element. That is, for small-sized pixel units, the presence of the stepped structure results in a smaller width of the light-emitting element of the LED for a given pixel unit size, thus a smaller area of ​​the light-emitting region and a significant reduction in luminous efficiency.

[0004] Therefore, there is a need to provide a light-emitting diode chip to at least partially solve the above problems. Summary of the Invention

[0005] According to one aspect of the present invention, a light-emitting diode (LED) chip is provided. According to one aspect of the present invention, the sidewalls of the insulating layer of the LED cell of the LED chip extend continuously downwards, such that the outer wall of the insulating layer does not form a step at the connection point between the electrode layer and the light-emitting body. Since the sidewalls of the insulating layer do not form steps, the size of the light-emitting body of the LED cell can be made larger while maintaining a fixed pixel size, thereby obtaining a larger light-emitting area and improving the light extraction efficiency.

[0006] According to one aspect of the present invention, a light-emitting diode (LED) chip is provided, comprising a substrate and a plurality of LED units arranged in an array on the substrate, wherein each LED unit comprises:

[0007] The light-emitting body comprises, from bottom to top, a first type of semiconductor, a light-emitting layer, and a second type of semiconductor, stacked sequentially.

[0008] An electrode layer, the radial dimension of which is larger than the radial dimension of the light-emitting body and positioned at the bottom of the light-emitting body, thereby electrically connecting the electrodes of the light-emitting body and the light-emitting diode chip.

[0009] A hard mask covering the light-emitting layer and the sidewalls of the first type of semiconductor; and

[0010] An insulating layer covering the sidewalls of the electrode layer and the sidewalls of the hard mask.

[0011] Wherein, the insulating layer extends in a continuous downward trend at the connection position between the light-emitting body and the electrode layer, so that the outer wall of the insulating layer does not form a step at the connection position between the electrode layer and the light-emitting body, and the step is defined as a wall surface with the main extension direction being horizontal.

[0012] In one embodiment, each of the light-emitting diode units is integrally formed into a columnar structure with its radial dimension gradually decreasing from bottom to top, and the insulating layer includes a top section covering the outside of the light-emitting body and a bottom section covering the outside of the electrode layer, wherein:

[0013] The inclination angle of the outer wall of the top section of the insulating layer is greater than the inclination angle of the outer wall of the bottom section of the insulating layer; or

[0014] The inclination angle of the outer wall of the top section of the insulation layer is equal to the inclination angle of the outer wall of the bottom section of the insulation layer; or

[0015] The inclination angle of the outer wall of the top section of the insulation layer is smaller than the inclination angle of the outer wall of the bottom section of the insulation layer.

[0016] In one embodiment, the outer wall of the top section of the insulation layer has a constant angle of inclination from its top to its bottom, and / or

[0017] The outer wall of the bottom section of the insulation layer has a constant tilt angle from its top to its bottom.

[0018] In one embodiment, the junction of the outer wall of the bottom section of the insulating layer and the outer wall of the top section of the insulating layer forms only one edge surrounding the light-emitting diode unit; or

[0019] The outer wall of the top section of the insulation layer smoothly transitions to the outer wall of the bottom section of the insulation layer.

[0020] In one embodiment, at least one edge surrounding the light-emitting diode unit is formed on the outer wall of the bottom section of the insulating layer; and / or at least one edge surrounding the light-emitting diode unit is formed on the top section of the insulating layer.

[0021] Wherein, the vertical tilt component of the wall surface between any pair of adjacent edges on the outer wall of the insulating layer is greater than the horizontal tilt component.

[0022] In one embodiment, the hard mask extends downward from the top of the light-emitting body and terminates at the bottom of the light-emitting body, while the insulating layer extends from the top of the light-emitting body to the bottom of the electrode layer.

[0023] In one embodiment, the hard mask comprises a plurality of sublayers arranged radially from the inside out.

[0024] In one embodiment, the light-emitting diode chip further includes:

[0025] A top conductive layer covers the top surface and sidewalls of the light-emitting body.

[0026] In one embodiment, the top conductive layer includes a first top conductive layer that covers only the top surface of the light-emitting body and a second top conductive layer that covers the top surface of the first top conductive layer and the outer wall of the insulating layer, wherein:

[0027] The top edge of the insulating layer is lower than the top surface of the first top conductive layer, or the top edge of the insulating layer is flush with the top surface of the first top conductive layer.

[0028] In one embodiment, the light-emitting diode chip further includes:

[0029] A first electrode is disposed on the substrate and positioned at the bottom of the light-emitting diode unit, and the first electrode is electrically connected to the first type of semiconductor via the electrode layer; and

[0030] A second electrode, a portion of which is disposed on the substrate and positioned between a pair of light-emitting diode cells having a first adjacent relationship, wherein the portion of the second electrode is conductively connected to the second type of semiconductor.

[0031] The portion of the second electrode is embedded in the substrate.

[0032] In one embodiment, the second electrode is disposed around each of the light-emitting diode cells to form between the light-emitting diode cells having a first adjacent relationship, and / or

[0033] On a predetermined cross section taken from the plane containing the axis of the light-emitting diode unit, the second electrode is formed as a trapezoidal cross section with radial dimensions gradually increasing or decreasing from bottom to top.

[0034] In one embodiment, the light-emitting diode chip further includes a top conductive layer covering the outside of the insulating layer.

[0035] The top opening of the insulating layer allows the top conductive layer to make conductive contact with the second type of semiconductor, and the dielectric material opening between adjacent light-emitting diode units allows the top conductive layer to make conductive contact with the second electrode.

[0036] In one embodiment, the electrode layer includes:

[0037] The bottom conductive layer located on the bottom side of the first type of semiconductor;

[0038] The bonding layer located on the bottom side of the bottom conductive layer.

[0039] In one embodiment, the ratio of the thickness of the bonding layer to the thickness of the hard mask is 10:1 to 1:1.

[0040] In one embodiment, the ratio of the thickness of the bonding layer to the thickness of the hard mask is 2:1; and / or the thickness of the bonding layer is 400 nm and the thickness of the hard mask is 200 nm.

[0041] In one embodiment, the first electrode includes a top segment and a bottom segment, at least one of the top segment and the bottom segment being formed as a columnar structure perpendicular to the substrate, the radial dimension of the top segment being smaller than the radial dimension of the bottom segment, and the second electrode being located between the top segments of adjacent first electrodes.

[0042] In one embodiment, the bottom surface of the top segment of the first electrode is flush with the bottom surface of the second electrode; and / or

[0043] At least one of the top segment and the bottom segment gradually increases in radial dimension from bottom to top.

[0044] In one embodiment, a gap exists between the pair of light-emitting diode units having a first adjacent relationship, and a portion of the second electrode is positioned directly below the gap.

[0045] Furthermore, the bottom ends of the pair of light-emitting diode units having a second adjacent relationship are adjacent to each other.

[0046] In one embodiment, the electrode layers of a pair of light-emitting diode units having a second adjacent relationship at least partially block the second electrode between the pair of light-emitting diode units in the vertical direction.

[0047] In one embodiment, the light-emitting diode chip is a micro light-emitting diode chip that uses micron-scale LEDs as light-emitting diodes.

[0048] In one embodiment, the insulating layer extends from the top of the sidewall of the light-emitting body to the bottom of the sidewall of the electrode layer in a continuous downward trend, such that no step is formed on the outer wall of the insulating layer on the complete sidewall of the light-emitting diode unit.

[0049] In one embodiment, the angle between the principal extension direction of any segment of the insulating layer and the vertical plane is less than 30°.

[0050] In one embodiment, the outer wall of the insulating layer includes a segment whose main extension direction is horizontal, but whose radial extension dimension in the horizontal direction does not exceed 100 nm.

[0051] In one embodiment, the maximum horizontal width of the light-emitting diode unit is less than or equal to 4 μm. Attached Figure Description

[0052] To better understand the above and other objects, features, advantages, and functions of the present invention, reference can be made to the preferred embodiments shown in the accompanying drawings. The same reference numerals in the drawings refer to the same parts. Those skilled in the art should understand that the drawings are intended to schematically illustrate preferred embodiments of the invention and do not limit the scope of the invention in any way; the parts in the drawings are not drawn to scale.

[0053] Figure 1A A top view of a light-emitting diode chip according to one aspect of the present invention is shown, in which structures such as microlenses are omitted to show the light-emitting diode unit;

[0054] Figure 1B This is a top view of the second electrode of the LED chip;

[0055] Figure 2 For along Figure 1A A portion of the cross-sectional view taken from the ABD line, or the corresponding Figure 1A A view of the ABD cross-section of the LED chip shown;

[0056] Figure 3A for Figure 2 A magnified view of part E in the image;

[0057] Figures 3B-3E for Figure 3A The deformation;

[0058] Figure 4A and Figure 4B for Figure 2 The deformation;

[0059] Figures 5A-5D This is a schematic diagram of the manufacturing process of a light-emitting diode (LED) unit.

[0060] Figures 6A-6D This is a flowchart illustrating the manufacturing process of a light-emitting diode unit according to a preferred embodiment of the present invention.

[0061] Explanation of reference numerals in the attached figures:

[0062] 100 miniature LED chips

[0063] 1 substrate

[0064] 11 openings

[0065] 12 top substrate layers

[0066] 13 Substrate Layer

[0067] 14. Medium Materials

[0068] 21 LED unit

[0069] 211 Light-emitting body

[0070] 2111 Type II Semiconductor

[0071] 2112 Emissive Layer

[0072] 2113 Type I Semiconductor

[0073] 212 electrode layer

[0074] 2121 Bottom Conductive Layer

[0075] 2122 Bonding Layer

[0076] 2123 electrode layer blank

[0077] 214 hard mask

[0078] 2141 Horizontal section

[0079] 216 Top Conductive Layer

[0080] 2161 First Top Conductive Layer

[0081] 2162 Subsidence Contact Section

[0082] 2163 Third Top Conductive Layer

[0083] 217 insulation layer

[0084] 2171 Insulation Layer Top Section

[0085] 2172 Insulation Layer Bottom Section

[0086] 2173 edges

[0087] 2174a First Edge

[0088] 2174b Second Edge

[0089] 2175 step surface

[0090] 2176 The wall between adjacent edges

[0091] 22 Light-transmitting partition

[0092] 23 microlenses

[0093] 3 First electrode

[0094] 31 Top Section

[0095] 32 bottom segment

[0096] 4 Second electrode

[0097] 43 Hollow section

[0098] 5 Photoresist

[0099] 6 dashed boxes

[0100] 7 Top Mask Detailed Implementation

[0101] Now, with reference to the accompanying drawings, specific embodiments of the present invention will be described in detail. The embodiments described herein are merely preferred embodiments of the invention; those skilled in the art can conceive of other ways to implement the invention based on these preferred embodiments, and such other ways also fall within the scope of the invention.

[0102] Figures 1A-6D A miniature light-emitting diode chip according to the present invention is shown. It should first be noted that the directional and positional terms used in this invention should be understood as relative directions and positions, not absolute directions and positions. The directional and positional terms used in this invention can be referred to... Figures 1A-6D The exemplary structure shown is explained.

[0103] Specifically, "axial direction" can be understood as the axial direction of the roughly columnar structure formed by the light-emitting diode units 21 of the micro LED chip 100. Figure 1A The light-emitting diode unit 21 is indicated by X. It should be noted that the light-emitting diode unit 21 can be formed into various structures such as a cylinder, a truncated cone, a prism, or other shapes with a height extending along the X direction. For ease of description, these structures are all considered to have an axial direction X. "Radial direction" refers to the radial direction with respect to the axial direction X. Figure 1A The direction is indicated by R; the "circumferential direction" is the circumferential direction around the axial direction X. Figure 1AThe symbol C represents the direction of height and thickness, which are parallel to or coincide with the axial direction X.

[0104] Location terminology should also be combined Figures 2-6D Understanding. For example, expressions such as "above," "below," "bottom," and "top" can all be referenced. Figures 2-6D Understand the relative positions of the components shown.

[0105] Furthermore, "gradually decreasing from top to bottom..." only indicates the relative positional characteristics of two components in a certain state, and does not represent the final relative positional characteristics of the two components. In certain cases, such as before the product is inverted, the relative positional characteristics of the two components may be that the radial dimension gradually decreases from bottom to top, while after the product is inverted, the relative positional characteristics become that the radial dimension gradually decreases from top to bottom.

[0106] First refer to Figure 1A-Figure 2 Some preferred embodiments of the present invention provide a light-emitting diode chip, particularly a micro-light-emitting diode chip 100, i.e., a high pixel density LED formed in micrometer-scale cycles. The micro-light-emitting diode chip 100 includes a substrate 1 and a plurality of light-emitting diode units 21 arranged in an array on the substrate 1, as well as microlenses 23 and light-transmitting spacers 22. The substrate 1 can be, for example, an IC driving backplane, and includes a dielectric layer and driving circuitry (not shown) housed within the dielectric layer; the dielectric layer is, for example, a SiO2 layer. Each light-emitting diode unit 21 is generally formed as a truncated cone about an axis X, with its radial dimension gradually decreasing (but not necessarily uniformly decreasing) from bottom to top, on a predetermined cross-section (e.g., on a plane containing the axis X of the light-emitting diode unit 21)... Figure 2 The cross-section of the light-emitting diode unit 21 shown is formed as a trapezoid with its radial dimension gradually decreasing from bottom to top. In other embodiments, the cross-section of the light-emitting diode unit may be formed as a trapezoid with its radial dimension gradually decreasing from top to bottom. This patent... Figures 1A-6D The implementation methods are applicable to LED chips with LED units whose radial dimensions gradually decrease from bottom to top, and also applicable to LED chips with LED units whose radial dimensions gradually increase from top to bottom.

[0107] It should be noted that the shapes of the components described in this invention do not necessarily imply that the components have strictly defined geometric shapes; they only need to roughly conform to specific shape characteristics visually. In some embodiments, the substrate may also contain circuits other than the IC driver circuit. In other embodiments, the light-emitting diode chip may be a large-particle LED light-emitting diode chip.

[0108] refer to Figure 2Each light-emitting diode unit 21 includes a light-emitting body 211, which includes a light-emitting layer 2112, a first-type semiconductor 2113 located on the bottom side of the light-emitting layer 2112, and a second-type semiconductor 2111 located on the top side of the light-emitting layer 2112. The light-emitting body 2111 is also referred to as an epitaxial layer, and the light-emitting layer 2112 is also referred to as an active layer. The first-type semiconductor 2113 can be either an N-type semiconductor or a P-type semiconductor, and the second-type semiconductor 2111 can be either an N-type semiconductor or a P-type semiconductor.

[0109] Continue to refer to Figure 2 Each light-emitting diode unit 21 further includes an electrode layer 212, the radial dimension of which is larger than that of the light-emitting body 211 and is positioned at the bottom of the light-emitting body, thereby electrically connecting the light-emitting body and the electrodes of the light-emitting diode chip (e.g., the first electrode 3, which will be discussed later). The electrode layer 212 includes a bottom conductive layer 2121 located on the bottom side of the first type semiconductor 2113 and a bonding layer 2122 located on the bottom side of the bottom conductive layer 2121.

[0110] The micro LED chip 100 also includes a first electrode 3 and a second electrode 4. The first electrode 3 is disposed on the substrate 1 and positioned at the bottom of each LED unit 21, and is electrically connected via a bottom conductive layer 2121, a bonding layer 2122, and a first-type semiconductor 2113. The second electrode 4 is disposed on the substrate 1 and positioned between adjacent LED units 21, and is electrically connected to the second-type semiconductor 2111. The first electrode 3 has the same polarity as the first-type semiconductor 2113, and the second electrode 4 has the same polarity as the second-type semiconductor 2111. In some embodiments, the first-type semiconductor 2113 is a P-type semiconductor, the second-type semiconductor 2111 is an N-type semiconductor, the first electrode 3 is a P-type electrode, and the second electrode 4 is an N-type electrode.

[0111] In this embodiment, the light-emitting diode unit 21 does not include the first electrode 3 and the second electrode 4, and the light-emitting diode unit 21 can also be referred to as a light-emitting mesa.

[0112] The light-emitting diode unit 21 further includes a hard mask 214 covering the outer sides of the light-emitting layer 2112 and the first type semiconductor 2113. The light-emitting diode unit 21 also includes an insulating layer 217 covering the sidewalls of the electrode layer 212 and the hard mask 214. In some embodiments, the insulating layer 217 extends completely from the top side of the light-emitting diode unit 21 to the bottom side of the light-emitting diode unit 21. In some embodiments, the hard mask 214 extends downward from the top of the light-emitting body 211 and terminates at the bottom of the light-emitting body 211, while the insulating layer 217 extends from the top of the light-emitting body 211 to the bottom of the electrode layer 212.

[0113] In some embodiments, the hard mask 214 is a transparent insulating material, and the electrode layer 212 and the hard mask 214 have a high selectivity ratio. In this embodiment, the selectivity ratio between the electrode layer 212 and the hard mask 214 is greater than or equal to 2. (See below for further details.) Figure 2 and Figure 3A It can be seen that the insulating layer 217 extends along the side wall of the light-emitting body 211 (there is a hard mask 214 between the insulating layer 217 and the light-emitting body 211) in a continuous downward trend, so that the outer wall of the insulating layer 217 does not form a step at the connection position of the electrode layer 212 and the light-emitting body 211. Furthermore, the outer wall of the insulating layer 217 does not form a step at any position from the top to the bottom of the self-emissive diode unit 21.

[0114] It should be noted that in some embodiments, "downward extension trend" refers to the main extension direction of the component being downward, that is, the vertical component is greater than the horizontal component, or the angle between it and the vertical plane is less than the angle between it and the horizontal plane; "continuous" means that any section of the sidewall of the insulating layer conforms to the above-mentioned "downward extension trend"; if a part can form a "step", it means that the main extension direction of this part is horizontal, and "main extension direction is horizontal" means that the horizontal component is greater than the vertical component, that is, the angle between it and the horizontal plane is less than the angle between it and the vertical plane. More preferably, for any section of the sidewall of the insulating layer, the angle between its main extension direction and the vertical plane is less than 30°. That is to say, in this invention, a "step" is defined as a wall surface with a main extension direction of horizontal. It is understandable that errors are unavoidable in production. If a small horizontally extending section exists on the outer wall of the insulation layer due to process errors, but the horizontal radial dimension of this section is less than 100 nm, then such a section still does not constitute a "step". In other words, a wall surface with a horizontal extension section (which is only a result of the error) but a very small horizontal radial dimension (less than 100 nm) due to process errors does not meet the definition of a "step".

[0115] In other words, for any given section of the wall, the whole extends roughly in the vertical direction. Therefore, it can be understood that with a fixed pixel size, the width of the light-emitting body 211 can be further increased (imagine, with a fixed pixel size, if the angle between the outer wall of the insulating layer 217 and the horizontal plane is small, then the width of the light-emitting body 211, as the upper half of the roughly trapezoidal structure formed by the light-emitting diode unit 21, can only be made smaller).

[0116] In some embodiments, the insulating layer 217 may extend continuously downward only at the connection point between the electrode layer 212 and the light-emitting body 211, so that the outer wall of the insulating layer 217 does not form a step at the connection point between the electrode layer 212 and the light-emitting body 211. More specifically, the insulating layer 217 includes a top insulating layer section 2171 covering the outside of the light-emitting body 211 and a bottom insulating layer section 2172 covering the outside of the electrode layer 212. It should be noted that "covering" does not necessarily mean that the two components are in direct contact. For example, there may be a hard mask 214 between the insulating layer 217 and the light-emitting body 211, but the insulating layer 217 can still be referred to as covering the outside of the light-emitting body 211.

[0117] from Figure 2 and Figure 3A As can be seen, the bottom section 2172 of the insulating layer includes only a portion of the insulating layer 217, while the top section 2171 of the insulating layer includes both the hard mask 214 and a portion of the insulating layer 217. It should be noted that "outer wall of the insulating layer" refers to the outermost wall surface of the entire insulating layer.

[0118] refer to Figure 3A The inclination angle of the outer wall of the top section 2171 of the insulating layer (the angle between the wall surface and the vertical direction) is smaller than the inclination angle of the outer wall of the bottom section 2172 of the insulating layer (the angle between the wall surface and the vertical direction). Because the outer walls of the top section 2171 and the bottom section 2172 of the insulating layer have different inclination angles, an edge 2173 is formed around the light-emitting diode unit 21 at the junction of the outer walls of the bottom section 2172 and the top section 2171 of the insulating layer. Although the edge 2173 exists, a single edge obviously cannot form a stepped structure.

[0119] Furthermore, in Figure 2 and Figure 3AIn the structure shown, the outer wall of the top section 2171 of the insulating layer has a constant angle of inclination from its top to its bottom, and the outer wall of the bottom section 2172 of the insulating layer also has a constant angle of inclination from its top to its bottom. That is, the outer wall of the top section 2171 of the insulating layer is smooth and without edges or steps, and the outer wall of the bottom section 2172 of the insulating layer is also smooth and without edges or steps. It should be noted that in some other embodiments, the outer wall of the top section 2171 of the insulating layer may have a varying angle of inclination. In this case, the "angle of inclination of the outer walls of the top section 2171 and the bottom section 2172 of the insulating layer" refers to the approximate angle of the overall extension of the outer wall or the approximate angle of its main section. It should also be noted that even if the outer walls of the top section 2171 and the bottom section 2172 of the insulating layer are each non-smooth, there will still be no steps on the outer wall of the insulating layer 217.

[0120] For example, the outer wall of the bottom section 2172 of the insulating layer may have at least one edge surrounding the light-emitting diode unit 21, and the top section 2171 of the insulating layer may also have at least one edge surrounding the light-emitting diode unit 21. That is, there are multiple edges on the entire outer wall of the insulating layer 217. However, for the wall between any pair of adjacent edges, the vertical tilt component of the wall is greater than the horizontal tilt component, that is, the angle between the wall and the vertical plane is less than 45°, while the angle with the horizontal plane is greater than 45°, so the wall formed between any pair of adjacent edges does not constitute a step. In some more preferred embodiments, the angle between the wall surface and the vertical plane between any pair of adjacent edges on the outer wall of the insulating layer 217 is less than 30°, that is, the wall surface extends more vertically. Therefore, it can be understood that with a fixed pixel size, the width of the light-emitting body 211 can be further increased (imagine, with a fixed pixel size, if the angle between the outer wall of the insulating layer 217 and the horizontal plane is small, then the width of the light-emitting body 211, as the upper half of the roughly trapezoidal structure formed by the light-emitting diode unit 21, can only be made smaller).

[0121] Figures 3B-3E It shows Figure 3A Some deformations.

[0122] refer to Figure 3B The inclination angle of the outer wall of the top section 2171 of the insulation layer (the angle between the outer wall and the vertical direction) is greater than the inclination angle of the outer wall of the bottom section 2172 of the insulation layer (the angle between the outer wall and the vertical direction), and an edge 2173 is formed between the outer wall of the top section 2171 of the insulation layer and the outer wall of the bottom section 2172 of the insulation layer, instead of a step.

[0123] refer to Figure 3CThe inclination angle of the outer wall of the top section 2171 of the insulation layer is equal to the inclination angle of the outer wall of the bottom section 2172 of the insulation layer. The outer wall of the top section 2171 of the insulation layer smoothly transitions to the outer wall of the bottom section 2172 of the insulation layer. Therefore, there is no edge 2173 between the outer wall of the top section 2171 of the insulation layer and the outer wall of the bottom section 2172 of the insulation layer, and there is no step.

[0124] Referring to 3D, the outer wall of the bottom section 2172 of the insulating layer may have at least one edge surrounding the light-emitting diode unit 21 (in other cases, the top section 2171 of the insulating layer may also have at least one edge surrounding the light-emitting diode unit 21). That is, the entire outer wall of the insulating layer 217 has multiple edges, such as the first edge 2174a and the second edge 2174b. However, for the wall surface 2176 between any pair of adjacent edges, the vertical tilt component of the wall surface is greater than the horizontal tilt component, that is, the angle between the wall surface and the vertical plane is less than 45°, while the angle with the horizontal plane is greater than 45°, so the wall surface 2176 formed between any pair of adjacent edges does not constitute a step. In some more preferred embodiments, the angle between the wall surface 2176 between any pair of adjacent edges on the outer wall of the insulating layer 217 and the vertical plane is less than 30°. That is, the wall surface extends more vertically. Therefore, it can be understood that with a fixed pixel size, the width of the light-emitting body 211 can be further increased (imagine, with a fixed pixel size, if the angle between the outer wall of the insulating layer 217 and the horizontal plane is small, then the width of the light-emitting body 211, as the upper half of the roughly trapezoidal structure formed by the light-emitting diode unit 21, can only be made smaller).

[0125] refer to Figure 3E The insulating layer 217 has two edges on its sidewall, a first edge 2174a and a second edge 2174b. Due to manufacturing tolerances, the wall 2176 between the first edge 2174a and the second edge 2174b extends approximately horizontally, but the radial dimension of this horizontal extension is less than 100 nm. This structure still conforms to the definition of "stepless".

[0126] In other words, "stepless" has different meanings in different implementations, such as... Figures 2-3D In the illustrated embodiment, for any segment of the insulating layer 217, the main extension direction of the segment is downward (it may have a certain horizontal component, but the overall extension direction is downward) and it does not have any horizontally extending segments. Such a structure is called "stepless"; while in... Figure 3E In the embodiment shown, a section of the insulating layer 217 extends horizontally, but this is merely due to error; its radial dimension is very small, less than 100 nm. Figure 3EThe implementation shown is also referred to as "stepless".

[0127] Since no steps are formed at the connection between the sidewalls of the top section 2171 and the bottom section 2172 of the insulating layer, or on the sidewalls of the top section 2171 and the bottom section 2172 of the insulating layer, the size of the light-emitting body of the LED unit can be made larger and the area of ​​the light-emitting region can be larger when the pixel size is fixed, thereby improving the light extraction efficiency. (Imagine, if there are steps on the sidewalls of the insulating layer when the pixel size is fixed, the width of the light-emitting body itself must be reduced in order to make room for the steps, and the area of ​​the light-emitting region will be reduced, thus affecting the light extraction efficiency.)

[0128] Whether the implementation has a single edge or multiple edges, the presence of edges is a result of process optimization. That is, allowing the presence of edges can reduce the precision requirements in the process, improve production efficiency, and will not adversely affect product performance. As mentioned above, the edges do not form steps, and the overall diode chip still has good light extraction efficiency.

[0129] In some embodiments, the hard mask 214 itself may comprise a plurality of sublayers arranged radially from the inside to the outside. The oxide forming the outermost layer of the hard mask 214 enables the absence of steps during the overall molding process of the insulating layer 217 (as will be described in detail later). It should be noted that the hard mask 214 and at least its outermost layer may also be made of other materials, and obtaining a stepless structure from other materials also falls within the scope of this invention.

[0130] In each of the above embodiments, the maximum horizontal width of the light-emitting diode unit 21 is less than or equal to 4 μm.

[0131] The following is about Figure 2 Some other preferred configurations are described below. The light-emitting diode chip 100 includes a top conductive layer 216 integrally coated on a plurality of light-emitting diode cells 21. The top conductive layer 216 contacts a second type semiconductor 2111 on the top of each light-emitting diode cell 21, and contacts a second electrode 4 embedded in the substrate 1 between light-emitting diode cells 21 having a first adjacent relationship. That is, the second electrode 4 is electrically connected via the top conductive layer 216 and the second type semiconductor 2111.

[0132] As mentioned above, the second electrode 4 is embedded in the substrate 1, so that the bottom end of the second electrode 4 is lower than the bottom end of the plurality of light-emitting diode units 21. The connection relationship between the second electrode 4 and the top conductive layer 216 also has certain preferred settings.

[0133] refer to Figure 2 ,Will Figure 2The pair of adjacent LED units 21 on the right side of the center are referred to as a pair of LEDs with a first adjacent relationship. Figure 2 The pair of adjacent LED units 21 on the left side of the center are called a pair of LEDs with a second adjacent relationship, that is... Figure 2 The light-emitting diode unit 21 located in the middle is both one of the light-emitting diodes with a first adjacent relationship and one of the light-emitting diodes with a second adjacent relationship. There is a gap between the pair of light-emitting diode units 21 with the first adjacent relationship, and the second electrode 4 is partially located directly below the gap, while the bottom ends (the part above the substrate 1) of the pair of light-emitting diode units 21 with the second adjacent relationship are close to each other with a smaller gap or no gap.

[0134] Furthermore, the top conductive layer 216 extends from the top of the second type semiconductor 2111 to the top of the second electrode 4. Since the second electrode 4 is partially embedded in the substrate 1, it is located below the top conductive layer 216. To allow the second electrode 4 to contact the top conductive layer 216 and avoid short circuits, the insulating layer 217 extends downwards from the top of the light-emitting diode unit 21 and terminates above the second electrode 4 near the first adjacent light-emitting diode units 21, without reaching the top of the second electrode 4 (the insulating layer 217 terminates at the horizontally extending portion above the substrate 1). That is, the insulating layer 217 forms an opening at the top of the second electrode 4, and the dielectric layer of the substrate 1 also forms an opening there, thereby allowing the recessed contact section 2162 of the top conductive layer 216 and the second electrode 4 to contact each other at the opening. The insulating layer 217 and the dielectric layer of the substrate 1 can be collectively referred to as the dielectric material.

[0135] Continue to refer to Figure 2 The top conductive layer 216 is separated from the second electrode 4 by a substrate dielectric material 14 in the portion between any pair of light-emitting diode units 21 having a second adjacent relationship. The bonding layer 2122 or the bottom conductive layer 2121 of the pair of light-emitting diode units 21 having a second adjacent relationship at least partially shields the second electrode 4 between the pair of light-emitting diode units 21 in the vertical direction; that is, the pair of light-emitting diode units 21 having a second adjacent relationship overlaps with the second electrode 4 in the vertical direction. Partially embedding the second electrode 4 into the substrate 1 reduces the area occupied by the second electrode 4 in the light-emitting diode unit array. Even when the second electrode 4 is completely embedded in the substrate, it does not occupy any area in the light-emitting diode unit array. This arrangement ensures that, with a fixed overall chip size, the light-emitting diode units 21 can be made larger, resulting in better optical performance of the chip.

[0136] In fact, reference Figure 1B and Figure 2The second electrode 4 is disposed around almost every light-emitting diode unit 21, thus forming between any adjacent light-emitting diode units 21. Specifically, in a micro light-emitting diode chip 100, the second electrode 4 is integrally connected and formed in a grid shape, with each light-emitting diode unit 21 positioned within the grid. This part can be referred to... Figure 1B The top view of the second electrode 4 shown. Figure 1B As shown, the mesh-like structure formed by the second electrode 4 includes an array of hollow portions 43. Each light-emitting diode unit 21 is positioned correspondingly in one of the hollow portions 43. However, each light-emitting diode unit 21 is not directly placed within its corresponding hollow portion 43, but may be located directly above it. For the integrated second electrode 4, a portion of its structure contacts the top conductive layer 216 (e.g., located in...). Figure 2 (As shown, there are light-emitting diodes with a first adjacent relationship), while a portion of the section is spaced apart from the top conductive layer 216. For example... Figure 1A As shown, an opening 11 is formed at a specific location on the substrate 1 to expose the second electrode 4 or the top conductive layer 216 on top of the second electrode 4, etc. Figure 2 As can be seen, on a predetermined cross section taken from the plane containing the axis X of the light-emitting diode unit, the second electrode is formed as a trapezoidal cross section with radial dimensions gradually increasing or decreasing from bottom to top.

[0137] The second electrode 4 is at least partially embedded in the dielectric layer of the substrate 1, which reduces the space occupied by the second electrode 4 between adjacent light-emitting diode units 21 and allows the gap between adjacent light-emitting diode units 21 to be adaptively reduced, thereby reducing the overall size of the chip 100, so that it can be matched with thinner and more portable electronic devices and adapt to more application scenarios.

[0138] In some embodiments, both the bottom conductive layer 2121 and the top conductive layer 216 can be transparent conductive layers made of, for example, ITO. The bonding layer 2122 is used to bond the light-emitting body 211 to the substrate 1, and the material of the bonding layer 2122 can be selected from at least one of Ag, Pt, Au, Sn, Cr, and Ti. Specifically, the bonding layer 2122 includes a mirror layer (e.g., P-mirror) on top of it, and the mirror layer is made of pure silver, pure gold, a gold-chromium alloy, or a silver-copper alloy. Alternatively, the mirror layer may contain gold and trace elements, with gold as the main component and the trace elements including at least one of chromium, titanium, and nickel. Specifically, different metals have different reflectivities for red, green, and blue wavelengths, and specific materials can be selected for different colors. Pure silver and silver-copper alloys are particularly suitable for yellow-green LEDs. Pure silver, pure gold, and gold-chromium alloys are particularly suitable for red LEDs.

[0139] In some embodiments, the thickness ratio of the bonding layer 2122 and the hard mask 214 can have a specific relationship, for example, the ratio of the thickness of the bonding layer 2122 to the thickness of the hard mask 214 can be 10:1 to 1:1. The ratio of the thickness of the bonding layer 2122 to the thickness of the hard mask 214 can be 2:1. For example, the thickness of the bonding layer 2122 can be 400 nm, and the thickness of the hard mask 214 can be 200 nm. Such a size structure is particularly suitable for small-sized light-emitting diode (LED) chips, such as LED chips with a pixel size (typically, one pixel contains one LED unit and a microlens on top of it) of less than 3 μm.

[0140] The correlation between the thickness of the bonding layer 2122 and the thickness of the hard mask 214 is very important in terms of process and finished product performance. Setting it to 10:1-1:1, preferably 2:1, can ensure that the thickness of each layer is within the process window and avoid manufacturing failure due to thickness mismatch.

[0141] like Figure 2 , Figure 4A and Figure 4B As shown, the top conductive layer 216 includes a first top conductive layer 2161 covering only the top surface of the light-emitting body 211, and a second top conductive layer 2163 covering the top surface of the first top conductive layer 2161 and covering the outer sidewall of the insulating layer 217. Figure 2 In the middle, the top of the insulating layer 217 and the hard mask 214 is higher than the top surface of the first top conductive layer 2161; while Figure 4A In the structure shown, the top surfaces of the insulating layer 217, the hard mask 214, and the first top conductive layer 2161 are flush; Figure 4B In the structure shown, the top surface of the insulating layer 217 and the hard mask is lower than the top surface of the first top conductive layer 2161.

[0142] Figure 4A and Figure 4B The structure shown can improve the performance of the light-emitting diode unit 21. For example, it can increase the area of ​​the ohmic contact at the top of the light-emitting body, which can produce better conductivity and current expansion effect. On the other hand, as the pixel size shrinks, the top size of the light-emitting diode unit 21 will also be smaller, and the insulating layer 217 does not extend to the top, thus exposing its top layer, which can reduce the requirements for photolithography linewidth. Furthermore, such a setting will make the top layer without the corner of the insulating layer protrusion better, resulting in better coverage and continuity of the top conductive layer 216, and more reliable and stable electrical connection.

[0143] The first electrode 3 may also have some preferred configurations. The first electrode 3 includes a top segment 31 and a bottom segment 32, at least one of the top segment 31 and the bottom segment 32 being formed as a columnar structure perpendicular to the substrate 1. The radial dimension of the top segment 31 is smaller than the radial dimension of the bottom segment 32, and the second electrode 4 is located between the top segments 31 of adjacent first electrodes 3. The bottom surface of the top segment 31 of the first electrode 3 is flush with the bottom surface of the second electrode 4, and the radial dimension of at least one of the top segment 31 and the bottom segment 32 gradually increases from bottom to top.

[0144] Corresponding to the top section 31 and bottom section 32 of the first electrode 3, the substrate 1 also includes a top substrate layer 12 that accommodates the top section 31 of the first electrode 3 and a bottom substrate layer 13 that accommodates the bottom section 32 of the first electrode 3. The top substrate layer 12 and the bottom substrate layer 13 can be integrally formed without obvious boundaries.

[0145] The bottom segment 32 is located at the bottom surface layer of the substrate 1. No special manufacturing process is required for the bottom surface layer of the substrate 1 during the manufacturing process. The top substrate layer 12 serves as a redistribution layer, being higher than the bottom substrate layer 13, facilitating the processing of its top surface during manufacturing. Preferably, the junction cross-section between the first type semiconductor 2113 and the bottom conductive layer 2121 is flat, and the junction cross-section between the bottom conductive layer 2121 and the bonding layer 2122 is also flat. This arrangement increases light reflection from the bottom side of the light-emitting layer 2112, thereby increasing light emission.

[0146] Figures 5A-6D A method for manufacturing a light-emitting diode chip is shown. Figures 5A-5D One method is shown. Figures 6A-6D Another method is shown. Figures 6A-6D The method shown is superior to Figures 5A-5D The method shown, therefore Figures 6A-6D The manufactured LED chip has better performance than Figures 5A-5D LED chips produced using advanced technology.

[0147] First of all Figures 5A-5D The process is described below. Part of the process flow includes:

[0148] STEP 1: Provide a substrate 1, an electrode layer blank 2123, and a light-emitting body blank stacked sequentially from bottom to top. The light-emitting body blank includes a first-type semiconductor blank, a light-emitting layer blank, and a second-type semiconductor blank stacked sequentially from bottom to top (i.e., a precursor to the light-emitting body 211 containing a first-type semiconductor 2113, a second-type semiconductor 2111, and a light-emitting layer 2112). STEP 2: Etch the light-emitting body blank to form multiple light-emitting bodies 211, exposing the top surface of the electrode layer blank 2123 between adjacent light-emitting bodies. After this step, a... Figure 5A The structure shown.

[0149] The process also includes STEP3: covering the light-emitting body 211 and the electrode layer blank 2123 with a hard mask 214; and STEP4: etching downward between adjacent light-emitting bodies 211 to form an electrode layer 212, exposing the top surface of the substrate 1 between adjacent electrode layers 212.

[0150] The STEP4 process is in Figure 5B and Figure 5C The text shows ( ) Figure 5B and Figure 5C (These are two phases that appear sequentially in the etching step). In this step, photoresist 5 needs to be applied to each light-emitting element. Due to the special nature of the hard mask 214 material (e.g., silicon oxide), the portion covering the sidewalls of the light-emitting element (referred to as the sidewall portion) has the same etching rate as the portion covering the electrode layer 2123 blank (referred to as the horizontal portion 2141). It can be understood that during the etching process, although the target is only to etch the horizontal portion 2141, the sidewall portion inevitably gets etched due to its equally high etching rate, resulting in damage to the light-emitting element structure. To avoid this, the photoresist 5, in addition to covering the sidewalls of the light-emitting element, also needs to partially cover a portion of the horizontal portion 2141 of the hard mask 214. In this step, the hard mask 214 that is etched away is shown by the dashed box 6.

[0151] from Figure 5C As can be seen, after the etching process, the hard mask 214 itself forms a stepped structure consisting of a horizontal portion 2141 on the sidewall of the light-emitting diode.

[0152] Then proceed to STEP 5: remove the photoresist 5, and completely cover the substrate 1 and the light-emitting diode including the electrode layer 212 and the light-emitting body 211 with the insulating layer 217. The morphology after this process is as follows: Figure 5D As shown, since the hard mask 214 has a stepped structure, the insulating layer 217 covering it also forms a stepped surface 2175. The two ends of this stepped surface 2175 are referred to as the first edge 2174a and the second edge 2174b. It can be seen that the wall defined between the first edge 2174a and the second edge 2174b is set to extend horizontally, thus forming a stepped surface. The first edge 2174a is formed between the stepped surface 2175 of the insulating layer 217 and the top section 2171 of the insulating layer, and the second edge 2174b is formed between the stepped surface 2175 of the insulating layer 217 and the bottom section 2172 of the insulating layer. The first edge 2174a and the second edge 2174b respectively constitute corner structures.

[0153] Figures 6A-6DIt shows the Figures 5A-5D The process has been improved. Part of the process includes:

[0154] STEP 1: Provide a substrate 1, an electrode layer blank 2123 and a light-emitting body blank stacked from bottom to top. The light-emitting body blank includes a first type semiconductor blank, a light-emitting layer blank and a second type semiconductor blank stacked from bottom to top (i.e., the precursor of the light-emitting body 211 containing the first type semiconductor 2113, the second type semiconductor 2111 and the light-emitting layer 2112). A first top conductive layer blank (corresponding to the precursor of the first top conductive layer 2161) is also stacked on the light-emitting body blank.

[0155] STEP 2: Apply a top mask 7 at a predetermined position on the top of the first top conductive layer blank, then etch the light-emitting body blank to form a plurality of light-emitting bodies 211. Each light-emitting body 211 has a first top conductive layer 2161 on its top. The top surface of the electrode layer blank 2123 is exposed between adjacent light-emitting bodies 211. After this step, the desired result is obtained. Figure 6A The structure shown.

[0156] STEP 3: Cover the light-emitting body 211 and the electrode layer blank 2123 with the hard mask 214. After this step, the desired result is obtained. Figure 6B The structure shown.

[0157] In some embodiments, the hard mask 214 is a transparent insulating material, and there is a high selectivity between the electrode layer blank 2123 and the hard mask 214. In this embodiment, the selectivity between the electrode layer blank 2123 and the hard mask 214 is greater than or equal to 2.

[0158] STEP4: Apply photoresist 5 to each light-emitting body and etch downward between adjacent light-emitting bodies 211 to form an electrode layer 212, exposing the top surface of the substrate 1 between adjacent electrode layers 212.

[0159] The form after STEP4 is completed is Figure 6C As shown in the figure. In this embodiment, the photoresist 5 only covers the sidewalls and top surface of the hard mask 214, and does not extend to the top surface of the electrode layer blank 2123. Since the surface of the light-emitting body 211 is covered with photoresist 5, the hard mask 214 on the top and sidewalls of the light-emitting body can be protected, while the portion of the hard mask covering the electrode layer blank 2123 (shown in dashed box 6) is not protected. Ultimately, the hard mask 214 on the top and sidewalls of the light-emitting body is retained, while the portion of the hard mask covering the electrode layer blank 2123 (shown in dashed box 6) is etched away.

[0160] Furthermore, since there is a high selectivity between the electrode layer blank 2123 and the hard mask 214, it can be ensured that when the photoresist 5 is partially consumed during the etching process, the electrode layer blank 2123 will be etched away before the hard mask 214 due to the high selectivity. This ensures that the hard mask 214 on the sidewall of the light-emitting body 211 will not be etched when the electrode layer 212 is formed.

[0161] from Figure 6C As can be seen, after the etching process and removal of the photoresist, the sidewalls of the light-emitting diode (not yet covered with an insulating layer) have a smooth structure and do not have steps.

[0162] Then proceed to STEP 5: The insulating layer 217 is completely applied over the substrate 1 and the light-emitting diode, including the electrode layer 212 and the light-emitting body 211. The morphology after this process is... Figure 6D As shown, since the sidewalls of the light-emitting diode do not have a stepped structure before the insulating layer 217 is applied, the insulating layer 217 covering it will not form a stepped structure either.

[0163] according to Figures 6A-6D The manufacturing method shown, due to the unique application method of the hard mask 214 and photoresist 5, ensures that neither the etching step nor the subsequent application of the insulating layer 217 creates steps on the sidewalls of the light-emitting diode. Since no steps are formed on the sidewalls of the insulating layer, the size of the light-emitting body of the light-emitting diode unit can be made larger and the light-emitting area larger, thus improving the light extraction efficiency, given a fixed pixel size.

[0164] Figures 6A-6D And the light-emitting diode chip manufactured by its modified scheme can be used with Figures 1A-4B The structures in them are the same or similar, for Figures 1A-4B The description of the implementation methods should be understood as an explanation of the methods used. Figures 6A-6D Description of the manufactured product.

[0165] From the above, those skilled in the art will readily recognize that alternative structures to the structures disclosed in this invention can be used as feasible alternative implementations, and that the implementations disclosed in this invention can be combined to produce new implementations, which also fall within the scope of the appended claims.

Claims

1. A light emitting diode chip (100), characterized in that The light emitting diode chip comprises a substrate (1) and a plurality of light emitting diode units (21) arranged in an array on the substrate, wherein each of the light emitting diode units comprises: a light emitting body (211) comprising a first type semiconductor (2113), a light emitting layer (2112) and a second type semiconductor (2111) stacked in sequence from bottom to top, an electrode layer (212) having a radial dimension greater than that of the light emitting body (211) and positioned at the bottom of the light emitting body to conductively connect the light emitting body and the electrode of the light emitting diode chip, a hard mask (214) covering the sidewalls of the light emitting layer and the first type semiconductor; and an insulating layer (217) covering the sidewalls of the electrode layer (212) and the sidewalls of the hard mask (214), wherein the insulating layer extends in a continuous downward extending trend at the connecting position of the light emitting body and the electrode layer, so that the outer wall of the insulating layer does not form a step at the connecting position of the electrode layer and the light emitting body, the step being defined as a wall surface extending mainly horizontally.

2. The light emitting diode chip of claim 1, wherein, Each of the light emitting diode units forms a columnar structure with a radial dimension gradually decreasing from bottom to top, and the insulating layer (217) comprises an insulating layer top section (2171) covering the outer side of the light emitting body and an insulating layer bottom section (2172) covering the outer side of the electrode layer (212), wherein: the inclination angle of the outer wall of the insulating layer top section (2171) is greater than that of the insulating layer bottom section (2172); or the inclination angle of the outer wall of the insulating layer top section (2171) is equal to that of the insulating layer bottom section (2172); or the inclination angle of the outer wall of the insulating layer top section (2171) is less than that of the insulating layer bottom section (2172).

3. The light emitting diode chip of claim 2, wherein, the outer wall of the insulating layer top section (2171) has an unchanging inclination angle from its top end to its bottom end, and / or the outer wall of the insulating layer bottom section (2172) has an unchanging inclination angle from its top end to its bottom end.

4. The light emitting diode chip of claim 2, wherein, the connecting position of the outer wall of the insulating layer bottom section (2172) and the outer wall of the insulating layer top section (2171) forms only one edge (2173) around the light emitting diode unit; or the outer wall of the insulating layer top section smoothly transitions to the outer wall of the insulating layer bottom section.

5. The light emitting diode chip of claim 4, wherein, the outer wall of the insulating layer bottom section (2172) forms at least one edge around the light emitting diode unit; and / or the insulating layer top section forms at least one edge around the light emitting diode unit, wherein the vertical inclination component of the wall surface (2176) between any pair of adjacent edges on the outer wall of the insulating layer is greater than the horizontal inclination component.

6. The light emitting diode chip of claim 1, wherein, The hard mask extends downward from a top end of the light emitting body and stops at a bottom end of the light emitting body, and the insulating layer extends from the top end of the light emitting body to a bottom end of the electrode layer (212).

7. The light emitting diode chip of claim 6, wherein, The hard mask comprises a plurality of sub-layers arranged radially from inside to outside.

8. The light emitting diode chip of claim 1, wherein, The light emitting diode unit further comprises: a top conductive layer (216) covering a top surface and a sidewall of the light emitting body.

9. The light emitting diode chip of claim 8, wherein, The top conductive layer (216) comprises a first top conductive layer (2161) covering only the top surface of the light emitting body (211) and a second top conductive layer (2163) covering a top surface of the first top conductive layer (2161) and covering an outer sidewall of the insulating layer (217), wherein: a top end of the insulating layer (217) is lower than a top surface of the first top conductive layer (2161), or the top end of the insulating layer and the top surface of the first top conductive layer are flush.

10. The light emitting diode chip of any of claims 1-7, wherein, The light emitting diode chip further comprises: a first electrode (3) disposed at the substrate and positioned at a bottom of the light emitting diode unit, the first electrode being conductively connected via the electrode layer and the first type semiconductor (2113); and a second electrode (4), a portion of the second electrode being disposed at the substrate and positioned between a pair of the light emitting diode units having a first adjacent relationship, the portion of the second electrode being conductively connected with the second type semiconductor (2111), wherein the portion of the second electrode is embedded in the substrate (1).

11. The light emitting diode chip of claim 10, wherein, The second electrode (4) is disposed around each of the light emitting diode units to form between the light emitting diode units having the first adjacent relationship, and / or In a predetermined cross section taken by a plane in which an axis of the light emitting diode unit lies, the second electrode is formed as a trapezoidal cross section whose radial dimension gradually increases or decreases from bottom to top.

12. The light emitting diode chip of claim 10, wherein, The light emitting diode chip further comprises a top conductive layer coated outside the insulating layer, a top opening of the insulating layer to allow the top conductive layer to conductively contact the second type semiconductor, and a dielectric material opening between adjacent light emitting diode units to allow the top conductive layer to conductively contact the second electrode.

13. The light emitting diode chip of any of claims 1-7, wherein, The electrode layer comprises: a bottom conductive layer (2121) located at a bottom side of the first type semiconductor (2113); a bonding layer (2122) located at a bottom side of the bottom conductive layer.

14. The light emitting diode chip of claim 13, wherein, A ratio of a thickness of the bonding layer to a thickness of the hard mask is 10:1-1:

1.

15. The light emitting diode chip of claim 14, wherein, A ratio of a thickness of the bonding layer to a thickness of the hard mask is 2:1; and / or the thickness of the bonding layer is 400 nm and the thickness of the hard mask is 200 nm.

16. The light emitting diode chip of claim 10, wherein, The first electrode (3) comprises a top segment (31) and a bottom segment (32), at least one of the top segment and the bottom segment is formed as a columnar structure perpendicular to the substrate, a radial dimension of the top segment is smaller than a radial dimension of the bottom segment, and the second electrode (4) is located between the top segments (31) of adjacent first electrodes.

17. The light emitting diode chip of claim 16, wherein, a bottom surface of the top section of the first electrode and a bottom surface of the second electrode are flush; and / or at least one of the top section and the bottom section gradually increases its respective radial dimension in a direction from bottom to top.

18. The light emitting diode chip of claim 10, wherein, a gap exists between the pair of light emitting diode units having the first adjacent relationship, the portion of the second electrode (4) is positioned directly below the gap, and a bottom end of a pair of light emitting diode units having a second adjacent relationship is immediately adjacent.

19. The light emitting diode chip of claim 18, wherein, the electrode layer of the pair of light emitting diode units having the second adjacent relationship at least partially obstructs a second electrode between the pair of light emitting diode units in a vertical direction.

20. The light emitting diode chip of any of claims 1-7, wherein, the light emitting diode chip is a micro light emitting diode chip using a micron-scale LED as a light emitting diode.

21. The light emitting diode chip of claim 1, wherein, the insulating layer extends from a sidewall top end of the light emitting body to a sidewall bottom end of the electrode layer in a continuous downward extending trend, so that an outer wall of the insulating layer does not form a step on a complete sidewall of the light emitting diode unit.

22. The light emitting diode chip of claim 1, wherein, an included angle between a main extension direction of any one section of the insulating layer and a vertical plane is less than 30°.

23. The light emitting diode chip of claim 1, wherein, an outer sidewall of the insulating layer includes a section whose main extension direction is a horizontal direction but whose radial extension dimension in the horizontal direction is no more than 100 nm.

24. The light emitting diode chip of claim 1, wherein, characterized in that a maximum horizontal width of the light emitting diode unit is less than or equal to 4 μm.

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