Epitaxial structure with N-type As doped buffer layer on silicon substrate and generation method of epitaxial structure
By introducing an N-type As-doped buffer layer between the silicon substrate and the epitaxial layer, the mismatch problem between the silicon substrate and the epitaxial layer is solved, the crystal quality is improved, the product cost is reduced, and the application range of heavily doped arsenic silicon substrates is expanded.
Patent Information
- Application Number
- CN202511383083.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-26
- Publication Date
- 2026-01-23
AI Technical Summary
Heavy arsenic-doped silicon substrates and thick epitaxial structures suffer from significant differences in thermal expansion coefficients and severe lattice mismatch due to the large differences between the doping concentration of the silicon substrate and the doping concentration of the epitaxial layer. This introduces a large number of defects, mismatches and dislocations, affecting the performance of semiconductor devices.
An N-type As-doped buffer layer is introduced between the silicon substrate and the epitaxial layer. By designing resistivity parameters with gradients, interface defects are reduced and crystal quality is improved.
It effectively solves the mismatch problem between silicon substrate and epitaxial layer, improves the crystal quality of epitaxial layer, reduces product cost, and expands the application range of heavily arsenic-doped silicon substrate.
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Figure CN121398463A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to an epitaxial structure having an N-type As-doped buffer layer on a silicon substrate and a method for generating the same. Background Technology
[0002] Heavy arsenic-doped silicon substrates are a widely used material for the production of semiconductor devices. The technology for producing this material is very mature and inexpensive, and it is compatible with current semiconductor device fabrication technologies.
[0003] Currently, the significant difference in doping concentration between the silicon substrate and the epitaxial layer in heavily doped silicon substrates and thick epitaxial structures leads to large differences in thermal expansion coefficients and severe lattice mismatch. This introduces numerous defects, mismatches, and dislocations into the products. The high dislocation density on the surface turns this region into a non-radiative recombination center, reducing the radiative recombination efficiency in the active region and thus affecting the performance of semiconductor devices. Therefore, this invention grows a buffer layer between the substrate and the epitaxial layer to reduce defect density and improve material quality. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide an epitaxial structure with an N-type As-doped buffer layer on a silicon substrate and a method for generating the same, which reduces lattice mismatch and thermal mismatch, improves the crystal quality of silicon epitaxial materials with different doping types and concentrations grown on the buffer layer, and reduces epitaxial wafer defects.
[0005] The technical solution adopted by the present invention to solve its technical problem is: to provide an epitaxial structure with an N-type As-doped buffer layer on a silicon substrate, comprising a silicon substrate, a buffer layer and an epitaxial layer, wherein the buffer layer and the epitaxial layer are grown sequentially on the silicon substrate;
[0006] The resistivity of the silicon substrate is in the range of 0.0009 ohm·cm to 0.05 ohm·cm, the thickness of the silicon substrate is in the range of 500 to 800 μm, and the silicon substrate is doped with As atoms.
[0007] The resistivity of the buffer layer is in the range of 0.01 ohm·cm to 0.05 ohm·cm, the thickness of the buffer layer is in the range of 0.5 μm to 0.8 μm, and the buffer layer is an N-type As-doped buffer layer.
[0008] The epitaxial layer is doped with Si, and the resistivity of the epitaxial layer is in the range of 0.01 ohm·cm to 200 ohm·cm.
[0009] In this technical solution, by selecting a heavily doped As substrate as the silicon substrate, the overall cost of the product can be reduced and the application range of the heavily doped arsenic silicon substrate can be expanded. At the same time, by using a buffer layer to isolate the silicon substrate and the epitaxial layer, the mismatch problem between the silicon substrate and the epitaxial layer can be effectively solved. Furthermore, by limiting the resistivity parameters of the silicon substrate, the buffer layer and the epitaxial layer, a resistivity gradient design is formed among the three, which enables the buffer layer to reduce interface defects and improve the crystal quality of the epitaxial layer.
[0010] As a supplement to this technical solution, the Si doping concentration in the buffer layer is lower than the Si doping concentration in the silicon substrate. Through a gradient design, the electrical properties and mechanical stress of the two are balanced, providing better growth conditions for the subsequent growth of the epitaxial layer.
[0011] As a supplement to this technical solution, the doping concentration in the silicon substrate is greater than 1×10⁻⁶. 17 / cm 3 .
[0012] As a supplement to this technical solution, the thickness of the epitaxial layer is in the range of 0.5 to 150 μm. By controlling the thickness of the epitaxial layer, the electrical performance of the device can be optimized and the material quality can be improved.
[0013] As a supplement to this technical solution, the silicon substrate is made of a single-crystal silicon wafer with a diameter of 4, 5, 6, 8, 12, or 18 inches.
[0014] A method for generating an epitaxial structure with an N-type As-doped buffer layer on a silicon substrate includes the following steps:
[0015] The process includes the following steps: S1: Selecting a silicon wafer of appropriate size and specifications as the silicon substrate, and doping the silicon substrate with arsenic; S2: Processing the substrate in the chemical vapor deposition chamber, performing a silicon coating technique on the substrate surface to produce a silicon sublayer; S3: Placing the silicon substrate on the substrate using a robotic arm, and simultaneously introducing an arsenic-containing dopant to place the silicon substrate in a gaseous dopant atmosphere, while simultaneously introducing H2 containing trichlorosilane. The silicon substrate is heated to between 1030°C and 1190°C in the H2 atmosphere containing trichlorosilane, forming a buffer layer on the surface of the silicon substrate. The buffer layer is an N-type As-doped buffer layer; S4: Introducing arsine gas to allow the epitaxial layer to grow on the buffer layer.
[0016] In step S1, a silicon substrate of appropriate specifications is selected according to actual needs. In addition to arsenic, the silicon substrate is also doped with phosphorus, antimony and boron to increase the carrier concentration in the silicon substrate and thus reduce the resistivity of the silicon substrate. In step S2, silicon capping technology is performed on the substrate on which the silicon substrate is placed to minimize outward diffusion from the substrate. In step S3, the overall thickness of the buffer layer is controlled by introducing arsenic dopant and H2 containing trichlorosilane to ensure that the thickness of the buffer layer is in the optimal state. The buffer layer is too thick or too thin, which will affect the device performance. In step S4, arsine gas is introduced to ensure the growth of the epitaxial layer.
[0017] When the thickness of the buffer layer is <0.1μm, it is difficult to effectively alleviate doping and lattice mismatch and effectively block the direct contact and diffusion between the heavily doped silicon substrate and the epitaxial layer, resulting in a poor effect on improving the crystal quality of the epitaxial structure; when its thickness is >20μm, the buffer layer is too thick and will affect the overall electrical performance of the structure.
[0018] As a supplement to this technical solution, in step S2, the substrate in the chemical vapor deposition chamber is a high-purity graphite substrate, which needs to be etched with HCl before the silicon capping technology operation.
[0019] As a supplement to this technical solution, in steps S3 and S4, during the growth of the buffer layer and the epitaxial layer, the base used for growth placement is always maintained at a rotation speed of 45 rpm to 55 rpm.
[0020] By providing a rotation during the growth of the buffer layer and the epitaxial layer, the surface of the silicon substrate can be placed in a uniform environment during growth, which refers to the concentration of the reactive gas and the temperature during the reaction process.
[0021] As a supplement to this technical solution, the growth rate of the buffer layer is 0.5 to 5 μm per minute, and the overall thickness of the buffer layer is controlled by controlling the production speed of the buffer layer.
[0022] As a supplement to this technical solution, in step S3, during the growth of the buffer layer, it is necessary to ensure that the internal temperature is between 1100℃ and 1190℃.
[0023] Beneficial Effects: This invention relates to an epitaxial structure with an N-type As-doped buffer layer on a silicon substrate and its generation method. By selecting a heavily As-doped substrate as the silicon substrate, the overall cost of the product can be reduced, and the application range of the heavily As-doped silicon substrate can be expanded. At the same time, by using a buffer layer to isolate the silicon substrate and the epitaxial layer, the mismatch problem between the silicon substrate and the epitaxial layer can be effectively solved. Furthermore, by limiting the resistivity parameters of the silicon substrate, the buffer layer, and the epitaxial layer, a resistivity gradient design is formed among the three, which enables the buffer layer to reduce interface defects and improve the crystal quality of the epitaxial layer. This technical solution reduces lattice mismatch and thermal mismatch, improves the crystal quality of silicon epitaxial materials with different doping types and concentrations grown on the buffer layer, and reduces epitaxial wafer defects. Attached Figure Description
[0024] Figure 1 This is a structural view of the present invention;
[0025] Figure 2 This is a flowchart illustrating the present invention. Detailed Implementation
[0026] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.
[0027] Embodiments of the present invention relate to an epitaxial structure having an N-type As-doped buffer layer on a silicon substrate and a method for forming the same, such as... Figure 1 As shown in Figure 2, the silicon substrate includes a silicon substrate 1, a buffer layer 2, and an epitaxial layer 3, wherein the buffer layer 2 and the epitaxial layer 3 are sequentially grown on the silicon substrate 1.
[0028] The resistivity of the silicon substrate 1 is in the range of 0.0009 ohm·cm to 0.05 ohm·cm, the thickness of the silicon substrate 1 is in the range of 500 to 800 μm, and the silicon substrate 1 is doped with As atoms.
[0029] The resistivity of the buffer layer 2 is in the range of 0.01 ohm·cm to 0.05 ohm·cm, the thickness of the buffer layer 2 is in the range of 0.5 μm to 0.8 μm, and the buffer layer 2 is an N-type As-doped buffer layer.
[0030] The epitaxial layer 3 is doped with Si, and the resistivity of the epitaxial layer 3 is in the range of 0.01 ohm·cm to 200 ohm·cm.
[0031] In this technical solution, by selecting a heavily As-doped substrate as the silicon substrate 1, the overall cost of the product can be reduced and the application range of the heavily As-doped silicon substrate can be expanded. At the same time, by using a buffer layer 2 to isolate the silicon substrate 1 and the epitaxial layer 3, the mismatch problem between the silicon substrate 1 and the epitaxial layer 3 can be effectively solved. Furthermore, by limiting the resistivity parameters of the silicon substrate 1, the buffer layer 2, and the epitaxial layer 3, a resistivity gradient design is formed among the three, which enables the buffer layer 2 to reduce interface defects and improve the crystal quality of the epitaxial layer 3.
[0032] As a supplement to this technical solution, the Si doping concentration in the buffer layer 2 is lower than the Si doping concentration in the silicon substrate 1. Through a gradient design, the electrical properties and mechanical stress of the two are balanced, providing better growth conditions for the subsequent growth of the epitaxial layer 3.
[0033] As a supplement to this technical solution, the thickness of the epitaxial layer 3 is in the range of 0.5 to 150 μm. By controlling the thickness of the epitaxial layer 3, the electrical performance of the device can be optimized and the material quality can be improved.
[0034] As a supplement to this technical solution, the silicon substrate 1 is made of a single-crystal silicon wafer with a diameter of 4, 5, 6, 8, 12, or 18 inches.
[0035] A method for generating an epitaxial structure with an N-type As-doped buffer layer on a silicon substrate includes the following steps:
[0036] The process includes the following steps: S1: Selecting a silicon wafer of appropriate size and specifications as the silicon substrate 1, and doping the silicon substrate 1 with arsenic, phosphorus, antimony and boron elements; S2: Processing the substrate used to place the silicon substrate 1 in the chemical vapor deposition chamber, performing silicon coverage technology on the substrate surface to produce a silicon sublayer on the substrate surface; S3: Placing the silicon substrate 1 on the substrate using a robotic arm, and simultaneously introducing a dopant containing arsenic, so that the silicon substrate 1 is in a gaseous dopant atmosphere, and simultaneously introducing H2 containing trichlorosilane, heating the silicon substrate 1 to between 1030℃ and 1190℃ in the H2 atmosphere containing trichlorosilane, and forming a buffer layer 2 on the surface of the silicon substrate 1, the buffer layer 2 being an N-type As-doped buffer layer; S4: Introducing arsine gas, so that the epitaxial layer 3 can grow on the buffer layer 2.
[0037] In step S1, a silicon substrate 1 of appropriate specifications is selected according to actual needs. Simultaneously, the silicon substrate 1 is doped with arsenic, phosphorus, antimony and boron elements to increase the carrier concentration in the silicon substrate 1, thereby reducing the resistivity of the silicon substrate 1. In step S2, silicon covering technology is performed on the base on which the silicon substrate 1 is placed to minimize outward diffusion from the base. In step S3, the overall thickness of the buffer layer 2 is controlled by introducing arsenic dopant and H2 containing trichlorosilane, so that the thickness of the buffer layer 2 is in the optimal state. If the buffer layer 2 is too thick or too thin, it will affect the device performance. In step S4, arsine gas is introduced to ensure the growth of the epitaxial layer 3.
[0038] When the thickness of buffer layer 2 is <0.1μm, it is difficult to effectively alleviate doping and lattice mismatch and effectively block the direct contact and diffusion between the heavily doped silicon substrate and epitaxial layer 3, resulting in a poor effect on improving the crystal quality of the epitaxial structure; when its thickness is >20μm, the buffer layer is too thick and will affect the overall electrical performance of the structure.
[0039] As a supplement to this technical solution, in step S2, the substrate in the chemical vapor deposition chamber is a high-purity graphite substrate, which needs to be etched with HCl before the silicon capping technology operation.
[0040] As a supplement to this technical solution, in steps S3 and S4, during the growth of buffer layer 2 and epitaxial layer 3, the base used for growth placement is always maintained at a rotation speed of 45 rpm to 55 rpm.
[0041] By providing a rotation during the growth of buffer layer 2 and epitaxial layer 3, the surface of silicon substrate 1 can be in a uniform environment during growth. This uniform environment refers to the concentration of reactive gases and the temperature during the reaction process. At the same time, the rotation operation can also release the internal mechanical stress of buffer layer 2 and epitaxial layer 3, thereby improving the stability of the process.
[0042] As a supplement to this technical solution, the growth rate of the buffer layer 2 is 0.5 to 5 μm per minute. The overall thickness of the buffer layer 2 is controlled by controlling the production rate of the buffer layer 2.
[0043] As a supplement to this technical solution, in step S3, during the growth of buffer layer 2, it is necessary to ensure that the internal temperature is between 1100℃ and 1150℃.
[0044] Example 1
[0045] A heavily doped 12-inch diameter silicon substrate was selected, with As atoms doped at a concentration of 1×10⁻⁶. 18 / cm 3 The resistivity is less than 0.01 ohm·cm, and the substrate has a thickness of 775 μm.
[0046] The growth buffer layer 2 and the epitaxial layer 3 can be manufactured in the chemical vapor deposition chamber itself using a single continuous epitaxial process. The substrate in the chemical vapor deposition chamber is a high-purity graphite substrate, which needs to be etched with HCl gas before the silicon capping technology operation.
[0047] The silicon source in the growth buffer layer 2 is preferably trichlorosilane. Simultaneously, an H2 atmosphere containing trichlorosilane gas is introduced to heat the silicon substrate to 1150°C. The growth rate of the buffer layer 2 is approximately 2 μm per minute. The resistivity of the buffer layer 2 is in the range of 0.01 to 0.05 ohm·cm, and the thickness of the buffer layer 2 is between 0.5 μm and 0.8 μm. Then, the epitaxial layer 3 is grown in a chemical vapor deposition reactor on the buffer layer 2. Arsine gas is introduced during the growth process. The thickness of the epitaxial layer 3 is between 0.5 and 150 μm, and the resistivity of the epitaxial layer 3 is in the range of 0.01 to 200 ohm·cm.
[0048] Example 2
[0049] The difference between this comparative example and Example 1 lies in the growth of a heavily arsenic-doped low-temperature buffer layer and a heavily arsenic-doped high-temperature buffer layer:
[0050] The method for preparing an epitaxial wafer grown on the silicon substrate includes the following steps:
[0051] (1) Prepare and heat-treat the silicon substrate according to the process described in Example 1;
[0052] (2) The heavily arsenic-doped low-temperature buffer layer and the heavily arsenic-doped high-temperature buffer layer were grown according to the process described in Example 1;
[0053] The growth temperature of the heavily arsenic-doped low-temperature buffer layer is 1120℃, while the growth temperature of the heavily arsenic-doped high-temperature buffer layer is 1180℃. By testing the semiconductor devices produced using the above heavily arsenic-doped low-temperature buffer layer process and the heavily arsenic-doped high-temperature buffer layer process, and comparing the parameters with those of the semiconductor device in Example 1, the optimal technical route can be obtained.
[0054] Example 3
[0055] A heavily doped 12-inch diameter silicon substrate was selected, with As atoms doped at a concentration of 1×10⁻⁶. 18 / cm3, resistivity less than 0.01ohm·cm.
[0056] The substrate is placed in the process chamber of the epitaxial equipment, and the temperature in the process chamber is raised to 950℃~1150℃ to process the substrate.
[0057] Based on growth and debugging experience, when the flow rate of the arsine gas used for doping in the epitaxial layer is A, the arsine doping gas in the buffer layer is set to 2A or 3A and is introduced into the process chamber for at least a certain period of time t1, so that the process chamber is in the atmosphere of doped gas during the buffer layer process.
[0058] The arsine doping gas of the buffer layer was set to 2A in the range of 10sccm to 1000sccm, and the time t1 was 30s to 300s; the resistivity and thickness of the buffer layer were measured respectively.
[0059] According to the specifications, epitaxial growth is performed on the buffer layer using TCS and doping gas until the target epitaxial layer is obtained on the silicon substrate.
[0060] Example 4
[0061] A heavily doped 12-inch diameter silicon substrate was selected. The substrate was doped with As atoms with an impurity concentration of 1×10¹⁸ / cm³ and a resistivity of less than 0.01 ohm·cm.
[0062] The substrate is placed in the process chamber of the epitaxial equipment, and the temperature in the process chamber is raised to 950℃~1150℃ to process the substrate.
[0063] Based on growth and debugging experience, when the flow rate of the arsine gas used for doping in the epitaxial layer is A, the arsine doping gas in the buffer layer is set to a maximum flow rate of 2A, which gradually changes to A within a fixed time t1. In this case, the buffer layer has a gradually distributed concentration gradient.
[0064] The arsine doping gas of the buffer layer was set to 2A in the range of 10sccm to 1000sccm, and the time t1 was 30s to 300s; the resistivity and thickness of the buffer layer were measured respectively.
[0065] According to the specifications, epitaxial growth is performed on the buffer layer using TCS and doping gas until the target epitaxial layer is obtained on the silicon substrate.
Claims
1. An epitaxial structure having an N-type As-doped buffer layer on a silicon substrate, characterized in that: It includes a silicon substrate (1), a buffer layer (2) and an epitaxial layer (3), wherein the buffer layer (2) and the epitaxial layer (3) are grown sequentially on the silicon substrate (1); The resistivity of the silicon substrate (1) is in the range of 0.0009 ohm·cm to 0.05 ohm·cm, the thickness of the silicon substrate (1) is in the range of 500 to 800 μm, and the silicon substrate (1) is doped with As atoms. The resistivity of the buffer layer (2) is in the range of 0.01 ohm·cm to 0.05 ohm·cm, the thickness of the buffer layer (2) is in the range of 0.5 μm to 0.8 μm, and the buffer layer (2) is an N-type As-doped buffer layer. The epitaxial layer (3) is doped with Si, and the resistivity of the epitaxial layer (3) is in the range of 0.01 ohm·cm to 200 ohm·cm.
2. The epitaxial structure with an N-type As-doped buffer layer on a silicon substrate according to claim 1, characterized in that: The Si doping concentration in the buffer layer (2) is less than the Si doping concentration in the silicon substrate (1).
3. The epitaxial structure with an N-type As-doped buffer layer on a silicon substrate according to claim 1, characterized in that: The doping concentration in the silicon substrate (1) is greater than 1×10⁻⁶. 17 / cm 3 .
4. The epitaxial structure with an N-type As-doped buffer layer on a silicon substrate according to claim 1, characterized in that: The thickness of the epitaxial layer (3) is in the range of 0.5 μm to 150 μm.
5. An epitaxial structure having an N-type As-doped buffer layer on a silicon substrate according to claim 1, characterized in that: The silicon substrate (1) is made of a single-crystal silicon wafer with a diameter of 4, 5, 6, 8, 12 or 18 inches.
6. A method for generating an epitaxial structure with an N-type As-doped buffer layer on a silicon substrate, characterized in that: Includes the following steps: S1: Select a silicon wafer of appropriate size and specifications as the silicon substrate (1), and the silicon substrate (1) is doped with arsenic. S2: The substrate used to place the silicon substrate (1) in the chemical vapor deposition chamber is processed by performing silicon covering technology on the substrate surface, so that a silicon sublayer is produced on the substrate surface. S3: The silicon substrate (1) is placed on the base by a robotic arm, and an arsenic-containing dopant is introduced at the same time, so that the silicon substrate (1) is in the gaseous dopant. At the same time, H2 containing trichlorosilane is introduced. The silicon substrate (1) is heated to between 1030°C and 1190°C in the H2 atmosphere containing trichlorosilane. A buffer layer (2) will be formed on the surface of the silicon substrate (1). The buffer layer (2) is an N-type As-doped buffer layer. S4: Arsenic gas is introduced so that the epitaxial layer (3) can grow on the buffer layer (2).
7. The method for generating an epitaxial structure with an N-type As-doped buffer layer on a silicon substrate according to claim 5, characterized in that: In step S2, the substrate in the chemical vapor deposition chamber is a high-purity graphite substrate, which needs to be etched with HCl before the silicon capping technology operation.
8. The method for generating an epitaxial structure with an N-type As-doped buffer layer on a silicon substrate according to claim 5, characterized in that: In steps S3 and S4, during the growth of the buffer layer (2) and the epitaxial layer (3), the substrate used for growth placement is always kept at a rotation speed of 45 rpm to 55 rpm.
9. The method for generating an epitaxial structure with an N-type As-doped buffer layer on a silicon substrate according to claim 5, characterized in that: The growth rate of the buffer layer (2) is 0.5 μm to 5 μm per minute.
10. The method for generating an epitaxial structure with an N-type As-doped buffer layer on a silicon substrate according to claim 5, characterized in that: In step S3, when the buffer layer (2) is grown, it is necessary to ensure that the internal temperature is between 1100℃ and 1190℃.