Semiconductor structure, semiconductor unit and forming method thereof

Abstract

The invention discloses a semiconductor structure, a semiconductor unit and a forming method thereof. The semiconductor structure comprises a bottom layer, a support and a semiconductor element. The bottom layer has protrusions. The support is arranged on the bottom layer. The support comprises a joint part, a connecting part and a bearing part. The joint part is connected with the convex part of the bottom layer. The connecting part is connected with the joint part. The bearing part is connected with the connecting part. The semiconductor element is arranged on the bearing part. The semiconductor element exposes the joint portion and the connection portion. A gap is formed between the bottom surface of the support and the top surface of the bottom layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor structures, semiconductor units, and methods of forming the same, and more particularly, to semiconductor structures including supporting members, semiconductor units, and methods of forming the same. BACKGROUND

[0002] With the advancement of technology, various electronic products are developed towards the trend of being light, thin, short, and small. The size of semiconductor elements (e.g., light-emitting diodes (LEDs) or integrated circuits (ICs)) applied in the electronic products is also shrunk, and the related manufacturing process technology (e.g., mass transfer manufacturing process) and cost requirements can become higher.

[0003] Thus, although the existing semiconductor structures, semiconductor units, and methods of forming the same have gradually met their established purposes, they still do not completely meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding semiconductor structures, semiconductor units, and methods of forming the same. SUMMARY

[0004] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a base layer, a supporting member, and a semiconductor element. The base layer has a protruding portion. The supporting member is disposed on the base layer. The supporting member includes a bonding portion, a connecting portion, and a carrying portion. The bonding portion is connected with the protruding portion of the base layer. The connecting portion is connected with the bonding portion. The carrying portion is connected with the connecting portion. The semiconductor element is disposed on the carrying portion. The semiconductor element exposes the bonding portion and the connecting portion. There is a gap between a bottom surface of the supporting member and a top surface of the base layer.

[0005] In some embodiments, a semiconductor unit is provided. The semiconductor unit includes a supporting member and a semiconductor element. The supporting member includes a connecting portion and a carrying portion. The connecting portion has a first side surface. The carrying portion is connected with the connecting portion, and the carrying portion has a second side surface. The semiconductor element is disposed on the carrying portion, and the semiconductor element exposes the connecting portion. A roughness of the first side surface is greater than a roughness of the second side surface.

[0006] In some embodiments, a method of forming a semiconductor structure is provided. The method of forming a semiconductor structure includes providing a first semiconductor layer. An insulating layer is formed on the first semiconductor layer. A semiconductor element is formed on the insulating layer. The insulating layer is patterned to form a supporting member. A portion of the first semiconductor layer is removed to have a gap between a bottom surface of the supporting member and a top surface of the first semiconductor layer.

[0007] The semiconductor structure, the semiconductor unit and the forming method thereof of the present application can be applied in various types of electronic devices. In order to make the features and advantages of the present application more obvious and easy to understand, various embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0008] The idea of the embodiments of the present application can be better understood by the following detailed description with the accompanying drawings. It is worth noting that according to the standard practice in the industry, some features may not be drawn to scale. In fact, in order to be clearly described, the size of different components may be increased or decreased.

[0009] Figures 1 to 4 Cross-sectional schematic diagrams of different stages of the forming method of the semiconductor structure 1 of some embodiments of the present application, respectively;

[0010] Figure 5 Detailed cross-sectional schematic diagrams of the semiconductor structure 1 of some embodiments of the present application;

[0011] Figure 6 Partial top view schematic diagrams of the semiconductor structure 1 of some embodiments of the present application;

[0012] Figure 7 Cross-sectional schematic diagrams of the semiconductor unit 1' of some embodiments of the present application;

[0013] Figure 8 Top view schematic diagrams of the semiconductor unit 1' of some embodiments of the present application;

[0014] Figure 9 Top view schematic diagrams of the semiconductor structure 2 of some embodiments of the present application;

[0015] Figure 10 Top view schematic diagrams of the semiconductor unit 2' of some embodiments of the present application;

[0016] Figures 11 to 16 Cross-sectional schematic diagrams of different stages of the forming method of the semiconductor structure 3 of some embodiments of the present application, respectively;

[0017] Figure 17 Detailed cross-sectional schematic diagrams of the semiconductor structure 3 of some embodiments of the present application;

[0018] Figure 18 Partial top view schematic diagrams of the semiconductor structure 3 of some embodiments of the present application;

[0019] Figure 19 Cross-sectional schematic diagrams of the semiconductor unit 3' of some embodiments of the present application;

[0020] Figure 20 Fig. 2 is a top view schematic of a semiconductor unit 3’ for some embodiments of the present application;

[0021] Figure 21 Fig. 3 is a detailed cross-sectional view schematic of a semiconductor structure 4 for some embodiments of the present application.

[0022] Legend:

[0023] 1, 2, 3, 4: semiconductor structure

[0024] 1’, 2’, 3’: semiconductor unit

[0025] 10: first semiconductor layer

[0026] 10T: top surface

[0027] 12: protrusion

[0028] 13: cavity

[0029] 20: insulating layer

[0030] 21, 21’: support

[0031] 21B, 22B, 24B, 26B: bottom surface

[0032] 22: joint

[0033] 22S, 24S1, 24S1’, 24S2, 26S1, 26S2, 30S, 40S, 54S: side surface

[0034] 24, 24’: connection

[0035] 25: recess

[0036] 25a: point

[0037] 26: bearing

[0038] 26P1, 26P2: part

[0039] 30: second semiconductor layer

[0040] 40: element layer

[0041] 42: contact pad

[0042] 50: carrier plate

[0043] 52: first adhesive layer

[0044] 54: second adhesive layer

[0045] D1: first direction

[0046] D2: Second Direction

[0047] D3: Third direction

[0048] G: Gap

[0049] I-I': line segment

[0050] L22, L24, L26: Length

[0051] S1: First distance

[0052] S2: Second distance

[0053] S3: Third Distance

[0054] T1: First thickness

[0055] T2: Second thickness

[0056] W24, W26, W30, W40, W54: Width Detailed Implementation

[0057] The following provides a detailed description of the semiconductor structures, semiconductor cells, and methods for forming them according to various embodiments of the present invention. It should be understood that the following description provides many different embodiments for implementing various forms of some embodiments of the present invention. The specific elements and arrangements described below are merely for simple and clear description of some embodiments of the present invention. Of course, these are only examples and not for limiting the present invention. Furthermore, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements to clearly describe the present invention. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of the present invention and does not imply any correlation between the different embodiments and / or structures discussed.

[0058] It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in various embodiments to describe the relative relationship of one element to another in the figures. It is understood that if the apparatus in the figures is flipped upside down, the element described as being on the "lower" side will become the element on the "higher" side. Embodiments of the invention may be used in conjunction with the accompanying drawings. Figure 1 It is understood that the accompanying drawings of this invention are also considered part of the disclosure.

[0059] Furthermore, when it is mentioned that a first element is located on or over a second element, it may include situations where the first element and the second element are in direct contact, or situations where the first element and the second element are not in direct contact, that is, situations where there may be one or more other elements between the first element and the second element. However, if the first element is located directly on the second element, it indicates that the first element and the second element are in direct contact.

[0060] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number for that element (or those elements), nor to indicate the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; for example, a first element in the specification may be a second element in the claim.

[0061] In some embodiments of the present invention, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures in direct contact, or to two structures not in direct contact, wherein another structure is disposed between the two structures. Furthermore, these terms regarding connection and bonding may also include cases where both structures are movable or both structures are fixed. In addition, the terms "electrical connection" or "electrical coupling" include any direct and indirect electrical connection means.

[0062] In this document, the terms "approximately," "about," "substantially" and variations thereof, are used to describe values that can not be exact, but that are approximately or substantially the same as a given value. In this context, "about" is intended to convey the approximate nature of the value and is not intended to distinguish between values that are slightly different as a result of, for example, measuring techniques or manufacturing techniques. In this document, the terms "first," "second," "third," etc. are used merely as labels, and are not intended to impose numerical or other order unless specifically stated. Moreover, use of such terms as "first," "second," etc. is not intended to limit the scope of the disclosure to only those claimable variations that can be described by these terms. In this document, the use of "or" as a conjunction is used only to present information found either in the first instance, the second instance, or both instances. Contrary to common linguistic form "either / or," the disjunctive term "or" in this document has the same meaning as the single term "and" in order to avoid the connotation of exclusivity.

[0063] Throughout this specification and claims, certain terms shall be used in a specific manner. It will be understood that those of ordinary skill in the art can refer to the same component by different names. The present document does not intend to distinguish between components that do the same thing but have different names. In the following description and claims, the terms "including," "containing," "having," and the like are open-ended terms that are intended to be interpreted the same as "comprising" and thus should be interpreted to allow for elements, components, etc. that can be additionally included. Thus, when a description in the present document uses terminology "including," "containing," "having," and / or "with," it specifies the presence of stated elements, components, steps, operations, and / or members, but does not preclude the presence or addition of one or more other components, regions, steps, operations, and / or members.

[0064] It is to be understood that the embodiments which follow are by way of example only and that various alterations and modifications will occur to those skilled in the art without departing from the spirit of the application. Any feature in one embodiment can be used in combination with features in another embodiment.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0066] In this invention, the directions are not limited to the three axes of a Cartesian coordinate system such as the X, Y, and Z axes, and can be interpreted in a broader sense. For example, the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following text, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (thickness or depth direction). In some embodiments, the cross-sectional view described herein is a cross-sectional view of the XZ plane, and the top view described herein is a cross-sectional view of the XY plane. In some embodiments, the third direction D3 may be the normal direction of the first semiconductor layer.

[0067] In some embodiments, the phrase "a distance exists between one element and another element" means that the distance exists between the center of one element and the center of another element, or that the distance exists between a boundary of one element and a boundary of another element. The center of the element may be the geometric center of the element.

[0068] In some embodiments, the term "roughness" may refer to arithmetic average roughness, maximum roughness, ten-point average roughness, or roughness calculated in other ways.

[0069] In some embodiments, additional components may be added to the semiconductor structure of the present invention. In some embodiments, some components of the semiconductor structure of the present invention may be replaced or omitted. In some embodiments, additional operational steps may be provided before, during, and / or after the method of manufacturing the semiconductor structure. In some embodiments, some of the described operational steps may be replaced or omitted, and the order of some of the described operational steps is interchangeable. Furthermore, it should be understood that some of the described steps may be replaced or deleted for other embodiments of the method. Moreover, in this invention, the number and dimensions of the elements in the drawings are merely illustrative and are not intended to limit the scope of the invention.

[0070] Reference Figure 1 This is a cross-sectional schematic diagram of different stages of the semiconductor structure formation method according to some embodiments of the present invention. Figure 1As shown, in some embodiments, a first semiconductor layer 10 may be provided. In some embodiments, the first semiconductor layer 10 may include elemental semiconductors, compound semiconductors, alloy semiconductors, the like, or combinations thereof. In some embodiments, the elemental semiconductor may include silicon or germanium. In some embodiments, the compound semiconductor may include III-V group semiconductor materials, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), the like, or combinations thereof. In some embodiments, the compound semiconductor may include silicon carbide. In some embodiments, the alloy semiconductor may include SiGe, the like, or combinations thereof.

[0071] like Figure 1 As shown, in some embodiments, an insulating layer 20 may be formed on the first semiconductor layer 10. In some embodiments, the insulating layer 20 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxynitrides such as silicon oxynitride, or combinations thereof, but the invention is not limited thereto. In some embodiments, the insulating layer 20 may be formed by performing a plasma fabrication process, such as oxygen plasma, on the first semiconductor layer 10. For example, the first semiconductor layer 10 may be silicon, and the insulating layer 20 may be silicon oxide formed by performing an oxygen plasma fabrication process on silicon.

[0072] like Figure 1 As shown, in some embodiments, the insulating layer 20 may have a first thickness T1 in the normal direction (i.e., the third direction D3) of the first semiconductor layer 10. In some embodiments, the first thickness T1 may be 2 μm to 3 μm. For example, the first thickness T1 may be any value or a range of values ​​between 2 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, 2.5 μm, 2.6 μm, 2.7 μm, 2.8 μm, 2.9 μm, and 3 μm, but the present invention is not limited thereto.

[0073] like Figure 1As shown, in some embodiments, a second semiconductor layer 30 can be formed on the insulating layer 20, such that the insulating layer 20 is interposed between the first semiconductor layer 10 and the second semiconductor layer 30. In some embodiments, the material of the second semiconductor layer 30 can be the same as or different from the material of the first semiconductor layer 10. In some embodiments, the second semiconductor layer 30 can comprise a III-V semiconductor material. In some embodiments, the first semiconductor layer 10 and the second semiconductor layer 30 can have the same material, and the insulating layer 20 can serve as a buried insulating layer interposed therebetween. For example, the first semiconductor layer 10 and the second semiconductor layer 30 can both be silicon. In some embodiments, the first semiconductor layer 10, the insulating layer 20, and the second semiconductor layer 30 can collectively serve as a silicon-on-insulator (SOI) structure, although the present disclosure is not limited thereto.

[0074] As Figure 1In some embodiments, as shown, an element layer 40 can be formed on the second semiconductor layer 30. In some embodiments, the element layer 40 can include a conductor material, a semiconductor material, and / or an insulator material, although the application is not limited in this respect. In some embodiments, the conductor material can include a metal, a conductive nitride, a conductive oxide, the like, or a combination thereof, although the application is not limited in this respect. In some embodiments, the metal can be, for example, tin (Sn), copper (Cu), gold (Au), silver (Ag), nickel (Ni), indium (In), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), molybdenum (Mo), titanium (Ti), magnesium (Mg), zinc (Zn), an alloy thereof, or a combination thereof, although the application is not limited in this respect. In some embodiments, the conductive nitride can include titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), the like, or a combination thereof, although the application is not limited in this respect. In some embodiments, the conductive oxide can be a transparent conductive oxide (TCO), and can include indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), the like, or a combination thereof, although the application is not limited in this respect. In some embodiments, the semiconductor material can include a III-V semiconductor material, such as a Group III nitride, a Group III phosphide, a Group III arsenide, the like, or a combination thereof, although the application is not limited in this respect. In some embodiments, the insulator material can include a dielectric oxide, a dielectric nitride, a dielectric oxynitride, the like, or a combination thereof, although the application is not limited in this respect. As Figure 2As shown, in some embodiments, contact pads 42 can be formed on element layer 40. In some embodiments, the material of contact pads 42 can include metal, conductive nitride, conductive oxide, the like, or a combination thereof, although the application is not limited thereto. In some embodiments, the metal can be, for example, tin (Sn), copper (Cu), gold (Au), silver (Ag), nickel (Ni), indium (In), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), molybdenum (Mo), titanium (Ti), magnesium (Mg), zinc (Zn), an alloy thereof, or a combination thereof, although the application is not limited thereto. In some embodiments, the conductive nitride can include titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), the like, or a combination thereof, although the application is not limited thereto. In some embodiments, the conductive oxide can be a transparent conductive oxide (TCO), and can include indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), the like, or a combination thereof, although the application is not limited thereto.

[0075] Referring to Figure 2 FIG. 1 is a cross-sectional schematic diagram of a semiconductor structure, according to some embodiments of the application. As shown, in some embodiments, a semiconductor structure 10 can include an insulating layer 20, a first semiconductor layer 10, an element layer 40, and a second semiconductor layer 30. Figure 1 As shown, in some embodiments, a removal fabrication process is performed to remove a portion of element layer 40 and a portion of second semiconductor layer 30, thereby exposing a top surface of insulating layer 20. In some embodiments, after performing the removal fabrication process, a side surface 30S of second semiconductor layer 30 can be flush with a side surface 40S of element layer 40.

[0076] In some embodiments, the removal fabrication process may include etching or other suitable fabrication processes, but the invention is not limited thereto. In some embodiments, the etching fabrication process may include dry etching, wet etching, or a combination thereof. In some embodiments, dry etching may include plasma etching, plasma-free gas etching, sputter etching, ion milling, or reactive ion etching (RIE). In some embodiments, wet etching may include using an acidic solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed. For example, the element layer 40 and the second semiconductor layer 30 may be removed by performing a plasma fabrication process.

[0077] In some embodiments, the step of removing a portion of the component layer 40 and a portion of the second semiconductor layer 30 may further include removing a portion of the insulating layer 20. In other words, a removal fabrication process is performed to remove a portion of the component layer 40, a portion of the second semiconductor layer 30, and a portion of the insulating layer 20. In some embodiments, the second thickness T2 of the insulating layer 20 exposed to the component layer 40 and the second semiconductor layer 30 may be less than the first thickness T1 of the insulating layer 20 covered by the component layer 40 and the second semiconductor layer 30. In other words, the second thickness T2 of the exposed insulating layer 20 may be less than the first thickness T1 of the insulating layer 20 located below the second semiconductor layer 30.

[0078] In some embodiments, the second thickness T2 can be 1 μm to 2 μm. For example, the second thickness T2 can be any value or a range of values ​​between 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, and 2 μm, but the invention is not limited thereto. Accordingly, when the second thickness T2 is less than 1 μm, the support and reliability of the subsequently formed scaffold will be insufficient. When the second thickness T2 is greater than 2 μm, it will be difficult to perform the subsequent separation fabrication process.

[0079] like Figure 2 and Figure 3 As shown, in some embodiments, the second semiconductor layer 30 and the element layer 40 can together serve as a semiconductor element. Therefore, the semiconductor element can be formed on the insulating layer 20 by sequentially forming the second semiconductor layer 30 and the element layer 40 on the insulating layer 20, and then removing a portion of the element layer 40 and a portion of the second semiconductor layer 30. In some embodiments, the semiconductor element can be an integrated circuit (IC). In other embodiments, the second semiconductor layer 30 can be omitted, allowing the element layer 40 to serve as the semiconductor element.

[0080] Referring to Figure 3 , which are cross-sectional schematic views of different stages of a method of forming a semiconductor structure according to some embodiments of the present application. As shown in Figure 9 , in some embodiments, the insulating layer 20 can be patterned to form a support 21 on the first semiconductor layer 10. In some embodiments, the insulating layer 20 can be patterned by a removal fabrication process. In some embodiments, after the insulating layer 20 is patterned, a portion of the first semiconductor layer 10 is exposed. In some embodiments, the insulating layer 20 can be patterned to form a recess (such as the recess 25 shown later) in the insulating layer 20. Accordingly, since the insulating layer 20 can be a buried insulating layer in an SOI structure, and the support 21 can be formed by patterning the insulating layer 20, i.e., without the need of depositing other materials as the support, the fabrication process steps can be reduced, the fabrication process yield and / or reliability can be improved. Figure 4

[0081] Referring to Figure 4 , which are cross-sectional schematic views of different stages of a method of forming a semiconductor structure 1 according to some embodiments of the present application. As shown in Figure 5 , in some embodiments, a removal fabrication process is performed to remove a portion of the first semiconductor layer 10, such that a portion of the first semiconductor layer 10 is separated from the support 21, thereby obtaining the semiconductor structure 1. Specifically, a portion of the first semiconductor layer 10 under the element layer 40 is removed, such that an adjacent protrusion 12 and a cavity 13 are formed between the first semiconductor layer 10 and the support 21, the protrusion 12 is connected to the support 21, and the cavity 13 overlaps with the element layer 40 in a vertical direction.

[0082] In some embodiments, in a cross-sectional view, the protrusion 12 can have a right trapezoid, an inverted trapezoid, a rectangle, or other similar shapes. In some embodiments, the cavity 13 can include air, inert gas, the like, or a combination thereof, or the cavity 13 can be a vacuum.

[0083] Referring to Figure 5 , which is a detailed cross-sectional schematic view of the semiconductor structure 1 according to some embodiments of the present application. As shown in Figure 5 ​As shown, in some embodiments, the support 21 can be located on the convex portion 12 of the first semiconductor layer 10. In some embodiments, in the first direction D1, the support 21 can include, in sequence, a joint portion 22, a connection portion 24, and a bearing portion 26. In some embodiments, the joint portion 22 is disposed on the convex portion 12 of the first semiconductor layer 10 to connect with the convex portion 12 of the first semiconductor layer 10. In some embodiments, the connection portion 24 connects the joint portion 22 and the bearing portion 26. In some embodiments, the second semiconductor layer 30 and the element layer 40 can be located on the bearing portion 26. In other words, the second semiconductor layer 30 can be located between the bearing portion 26 and the element layer 40. In some embodiments, the second semiconductor layer 30 and the element layer 40 can expose the joint portion 22 and the connection portion 24. In other words, the second semiconductor layer 30 and the element layer 40 can not be located on the joint portion 22 and the connection portion 24.

[0084] As shown, in some embodiments, the support 21 can be located on the convex portion 12 of the first semiconductor layer 10. In some embodiments, in the first direction D1, the support 21 can include, in sequence, a joint portion 22, a connection portion 24, and a bearing portion 26. In some embodiments, the joint portion 22 is disposed on the convex portion 12 of the first semiconductor layer 10 to connect with the convex portion 12 of the first semiconductor layer 10. In some embodiments, the connection portion 24 connects the joint portion 22 and the bearing portion 26. In some embodiments, the second semiconductor layer 30 and the element layer 40 can be located on the bearing portion 26. In other words, the second semiconductor layer 30 can be located between the bearing portion 26 and the element layer 40. In some embodiments, the second semiconductor layer 30 and the element layer 40 can expose the joint portion 22 and the connection portion 24. In other words, the second semiconductor layer 30 and the element layer 40 can not be located on the joint portion 22 and the connection portion 24. Figure 5 As shown, in some embodiments, the bottom surface 24B of the connection portion 24 and the top surface 10T of the first semiconductor layer 10 can have a gap G therebetween, and the bottom surface 26B of the bearing portion 26 and the top surface 10T of the first semiconductor layer 10 can have a gap G therebetween. In some embodiments, in the third direction D3, the depth of the gap G below the bearing portion 26 can be a constant value. In some embodiments, in the third direction D3, the depth of the gap G below the connection portion 24 can gradually decrease along the direction toward the convex portion 12. In some embodiments, the bottom surface 22B of the joint portion 22 is parallel to the top surface 10T of the first semiconductor layer 10. In some embodiments, in a cross-sectional view, the top surface 10T of the first semiconductor layer 10 can be horizontal, U-shaped, V-shaped, or other similar profile.

[0085] As shown, in some embodiments, the support 21 can be located on the convex portion 12 of the first semiconductor layer 10. In some embodiments, in the first direction D1, the support 21 can include, in sequence, a joint portion 22, a connection portion 24, and a bearing portion 26. In some embodiments, the joint portion 22 is disposed on the convex portion 12 of the first semiconductor layer 10 to connect with the convex portion 12 of the first semiconductor layer 10. In some embodiments, the connection portion 24 connects the joint portion 22 and the bearing portion 26. In some embodiments, the second semiconductor layer 30 and the element layer 40 can be located on the bearing portion 26. In other words, the second semiconductor layer 30 can be located between the bearing portion 26 and the element layer 40. In some embodiments, the second semiconductor layer 30 and the element layer 40 can expose the joint portion 22 and the connection portion 24. In other words, the second semiconductor layer 30 and the element layer 40 can not be located on the joint portion 22 and the connection portion 24. Figure 6 As shown, in some embodiments, the second semiconductor layer 30 and the element layer 40 can expose a portion 26P1, 26P2 of the bearing portion 26. In some embodiments, the second thickness T2 of the portion 26P1, 26P2 of the bearing portion 26 exposed by the second semiconductor layer 30 and the element layer 40 can be smaller than the first thickness T1 of other portions of the bearing portion 26 located below the second semiconductor layer 30 and the element layer 40. In some embodiments, in the first direction D1, the second semiconductor layer 30 can have a width W30, the element layer 40 can have a width W40, and the width W30 and the width W40 can be substantially the same. In the first direction D1, the bearing portion 26 can have a width W26, and the width W26 can be greater than the width W30 and the width W40.

[0086] Referring to Figure 5 , which is a partial top view schematic diagram of a semiconductor structure 1 of some embodiments of the present application. In which, Figure 6 the cross-sectional view shown is along Figure 7FIG. 2A is a cross-sectional schematic view of a semiconductor structure 1 taken along a line I-I' of FIG. 1A. In some embodiments, the connecting portion 24 can have side surfaces 24S1, 24S2 opposite to each other in the first direction D1. In some embodiments, the carrier portion 26 can have side surfaces 26S1, 26S2 opposite to each other in the first direction D1. In some embodiments, the side surface 22S of the joint portion 22 is connected to the side surface 24S1 of the connecting portion 24, and the side surface 24S2 of the connecting portion 24 is connected to the side surface 26S1 of the carrier portion 26. In some embodiments, the length L24 of the connecting portion 24 of the support 21 in the second direction D2 can be smaller than the length L22 of the joint portion 22 of the support 21. In some embodiments, the length L24 of the connecting portion 24 of the support 21 in the second direction D2 can be smaller than the length L26 of the carrier portion 26. Accordingly, by adjusting the length of the connecting portion 24, it facilitates the subsequent execution of a separation fabrication process.

[0087] Referring to Figure 8 and Figure 7 which are a cross-sectional schematic view and a top view of a semiconductor unit 1' of some embodiments of the present disclosure, respectively. In some embodiments, a separation fabrication process is performed on the semiconductor structure 1 to form the semiconductor unit 1'. In some embodiments, the separation fabrication process can be a stamp pick up fabrication process. In some embodiments, the stamp can be applied on the semiconductor structure 1 to break the support 21 and pick up the semiconductor unit 1'. Accordingly, a plurality of semiconductor units 1' can be transferred to other carriers with the stamp, thereby achieving mass transfer.

[0088] As shown in Figure 8 and Figure 9 , in some embodiments, a separation fabrication process is performed to separate the joint portion 22 from the connecting portion 24 in the support 21. For example, an external force such as a pressing force is applied to break the joint portion 22 from the connecting portion 24. Accordingly, after the separation fabrication process is performed, the support 21' of the semiconductor unit 1' can include a connecting portion 24' and a carrier portion 26. In some embodiments, after the separation fabrication process is performed, the roughness of the side surface 24S1' of the connecting portion 24 can be greater than the roughness of the side surface 26S2 of the carrier portion 26. In other words, the roughness of one side surface of the support 21' can be greater than the roughness of another side surface of the support 21'.

[0089] Hereinafter, the same or similar reference numerals and descriptions are omitted.

[0090] Referring to Figure 10 and Figure 9 which are a top view of a semiconductor structure 2 and a semiconductor unit 2' of some embodiments of the present disclosure, respectively. The semiconductor structure 2 is subjected to a separation fabrication process to obtain the semiconductor unit 2'.

[0091] As shown in FIG. 1, in some embodiments, the connecting portion 24 can have a recess 25 in a top view. In some embodiments, the recess 25 in the connecting portion 24 can be formed by a step of patterning the insulating layer 20 as shown in FIG. 2. In some embodiments, the recess 25 in the connecting portion 24 can be formed by using a mask with a specific pattern. Accordingly, by providing the recess 25 in the connecting portion 24, the area of the connecting portion 24 can be reduced, so that the separation fabrication process can be easily performed. In detail, the recess 25 can act as a stress concentration in the connecting portion 24, so that the stress release can be facilitated. Figure 3 Figure 10 As shown in FIG. 1, in some embodiments, the connecting portion 24 can have a recess 25 in a top view. In some embodiments, the recess 25 in the connecting portion 24 can be formed by a step of patterning the insulating layer 20 as shown in FIG. 2. In some embodiments, the recess 25 in the connecting portion 24 can be formed by using a mask with a specific pattern. Accordingly, by providing the recess 25 in the connecting portion 24, the area of the connecting portion 24 can be reduced, so that the separation fabrication process can be easily performed. In detail, the recess 25 can act as a stress concentration in the connecting portion 24, so that the stress release can be facilitated.

[0092] In some embodiments, the length L24 of the connecting portion 24 in the second direction D2 can not be a constant value. In some embodiments, the recess 25 can have a V shape, a U shape or other similar profile in a top view. In some embodiments, the first distance S1 between the most concave point 25a of the recess 25 and the side surface 24S1 of the connecting portion 24 can be greater than or equal to the second distance S2 between the most concave point 25a of the recess 25 and the side surface 24S2 of the connecting portion 24. Accordingly, by adjusting the setting position of the most concave point 25a of the recess 25, the separation fabrication process can be more easily performed. Furthermore, by adjusting the setting position of the most concave point 25a of the recess 25, the area of the connecting portion 24' after the separation fabrication process can be reduced, so that the size of the semiconductor unit 2' can be reduced.

[0093] As shown in FIG. 1, in some embodiments, the connecting portion 24 of the semiconductor unit 2' can have a width W24 smaller than the width W24 of the connecting portion 24 of the semiconductor unit 1'. In some embodiments, the width W24 of the connecting portion 24 of the semiconductor unit 2' can be greater than or equal to 0. Figure 11

[0094] Referring to FIG. 4, which is a cross-sectional schematic view of different stages of a method of forming a semiconductor structure according to some embodiments of the present application. As shown in FIG. 4, in some embodiments, a first semiconductor layer 10 is provided, and an insulating layer 20 is formed on the first semiconductor layer 10. Figure 11 Figure 11 As shown in FIG. 4, in some embodiments, a first semiconductor layer 10 is provided, and an insulating layer 20 is formed on the first semiconductor layer 10.

[0095] As shown in FIG. 4, in some embodiments, a first semiconductor layer 10 is provided, and an insulating layer 20 is formed on the first semiconductor layer 10. Figure 11 ​​​As shown, in some embodiments, a carrier plate 50 is provided. In some embodiments, the carrier plate 50 may include silicon, glass, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), the like, or combinations thereof, but the invention is not limited thereto. In some embodiments, a first adhesive layer 52 is formed on the carrier plate 50. In some embodiments, the first adhesive layer 52 may include a pyrolytic adhesive, an ultraviolet (UV) pyrolytic adhesive, a light-to-heat conversion (LTHC) adhesive, other suitable pyrolytic adhesive layers, or combinations thereof, but the invention is not limited thereto.

[0096] like Figure 12 As shown, in some embodiments, an element layer 40 is formed on a first adhesive layer 52. In some embodiments, a contact pad 42 is formed on the element layer 40 before the element layer 40 is formed on the first adhesive layer 52. In some embodiments, the element layer 40 and the contact pad 42 contact the first adhesive layer 52. In some embodiments, the contact pad 42 is embedded in the first adhesive layer 52.

[0097] Reference Figure 12 This is a cross-sectional schematic diagram of different stages of the semiconductor structure formation method according to some embodiments of the present invention. Figure 13 As shown, in some embodiments, a second adhesive layer 54 is formed to bond the element layer 40 to the insulating layer 20. In some embodiments, after the element layer 40 and the insulating layer 20 are bonded, the element layer 40, contact pad 42, and first adhesive layer 52 are embedded in the second adhesive layer 54. In some embodiments, the second adhesive layer 54 contacts the element layer 40, the first adhesive layer 52, and the carrier 50. In some embodiments, the material of the second adhesive layer 54 may be the same as or different from the material of the first adhesive layer 52. In some embodiments, since the element layer 40 may be a semiconductor element, the semiconductor element can be formed on the insulating layer 20 through the second adhesive layer 54. In some embodiments, the semiconductor element may be an integrated circuit (IC) or a light-emitting diode (LED).

[0098] Reference Figure 13 This is a cross-sectional schematic diagram of different stages of the semiconductor structure formation method according to some embodiments of the present invention. Figure 14As shown, in some embodiments, the carrier plate 50 is removed to expose the first adhesive layer 52 and the second adhesive layer 54. In some embodiments, the carrier plate 50 is removed from the first adhesive layer 52 and the second adhesive layer 54 by irradiating the first adhesive layer 52 and the second adhesive layer 54 with a laser having the same wavelength.

[0099] Referring to Figure 14 , which are cross-sectional schematic diagrams of different stages of a method of forming a semiconductor structure of some embodiments of the present application. As Figure 14 shown, in some embodiments, the first adhesive layer 52 and a portion of the second adhesive layer 54 can be removed to pattern the second adhesive layer 54. In some embodiments, patterning the second adhesive layer 54 can expose a top surface of the insulating layer 20. In some embodiments, during performing the patterning of the second adhesive layer 54, a portion of the second adhesive layer 54 located under the element layer 40 can be removed, and a remaining portion of the second adhesive layer 54 located under the element layer 40 can be retained.

[0100] As Figure 2 shown, in some embodiments, the second adhesive layer 54 can be patterned by performing a plasma fabrication process. In some embodiments, the thickness of the insulating layer 20 exposed due to patterning the second adhesive layer 54 can be the same as or different from the thickness before being exposed. For example, when the first adhesive layer 52 and the second adhesive layer 54 are removed using a plasma fabrication process such as an oxygen plasma, the thickness of the insulating layer 20 exposed after removing the second adhesive layer 54 does not change, while when the first adhesive layer 52 and the second adhesive layer 54 are removed using a plasma fabrication process such as a fluorine plasma, the thickness of the insulating layer 20 exposed after removing the second adhesive layer 54 decreases. Thus, similar to Figure 15 shown, the insulating layer 20 covered by the second adhesive layer 54 can have a first thickness T1, the insulating layer 20 exposed by the second adhesive layer 54 can have a second thickness T2, and the first thickness T1 can be greater than the second thickness T2.

[0101] Referring to Figure 15 , which are cross-sectional schematic diagrams of different stages of a method of forming a semiconductor structure of some embodiments of the present application. As Figure 16 shown, in some embodiments, the insulating layer 20 can be patterned to form the support 21.

[0102] Referring to Figure 16 , which are cross-sectional schematic diagrams of different stages of a method of forming a semiconductor structure of some embodiments of the present application. As Figure 17 shown, in some embodiments, a portion of the first semiconductor layer 10 can be removed to have a gap G between the support 21 and a top surface 10T of the first semiconductor layer, thereby obtaining the semiconductor structure 3.

[0103] Referring toFigure 18 and Figure 17 which are detailed cross-sectional and partial top view schematic diagrams of the semiconductor structure 3 of some embodiments of the present application. As shown in Figure 18 and Figure 19 In some embodiments, the second adhesive layer 54 can be located between the load portion 26 of the support 21 and the element layer 40. In some embodiments, in the first direction D1, the width W54 of the second adhesive layer 54 can be smaller than the width W40 of the element layer 40.

[0104] Referring to Figure 20 and Figure 19 which are cross-sectional and top view schematic diagrams of the semiconductor unit 3' of some embodiments of the present application. Therein, a separation fabrication process is performed on the semiconductor structure 3 to obtain the semiconductor unit 3'. As shown in Figure 20 and Figure 21 In some embodiments, the second adhesive layer 54 can be located between the load portion 26 of the support 21 and the element layer 40. In some embodiments, in the first direction D1, a third distance S3 can be present between the side surface 54S of the second adhesive layer 54 and the side surface 40S of the element layer 40. In some embodiments, the third distance S3 can be greater than 0.

[0105] Referring to ​ which is a cross-sectional schematic diagram of the semiconductor structure 4 of some embodiments of the present application. In some embodiments, the contact pad 42 can be located between the element layer 40 and the load portion 26 of the support 21. In some embodiments, the contact pad 42 and the load portion 26 are separated from each other by the second adhesive layer 54. In some embodiments, the contact pad 42 is embedded in the second adhesive layer 54.

[0106] The components of the embodiments of the present application can be arbitrarily mixed and used as long as they do not violate the spirit of the present application or conflict. In addition, the scope of protection of the present application is not limited to the fabrication processes, machines, manufactures, compositions of matter, means, methods, and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the fabrication processes, machines, manufactures, compositions of matter, means, methods, and steps currently or developed in the future from the disclosure of the present application, as long as they can substantially the same function or achieve substantially the same results as in the embodiments described herein. Therefore, the scope of protection of the present application includes the aforementioned fabrication processes, machines, manufactures, compositions of matter, means, methods, and steps. Any embodiment or claim of the present application does not necessarily achieve all the purposes, advantages, and / or features disclosed in the present application.

[0107] The foregoing is considered as merely an illustrative example of the presently preferred embodiments of the application, since modifications and variations can be made to the disclosed embodiments by those of ordinary skill in the art without departing from the spirit or scope of the application. It is intended that the scope of the application encompass such modifications and variations as come within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor structure, comprising: The bottom layer has a convex part; A support frame, disposed on the underlying layer, includes: The joint is connected to the protrusion of the bottom layer; The connecting part is located next to the joint; and The supporting part is located next to the connecting part; and A semiconductor element is disposed on the carrier portion and exposes the junction portion and the connection portion, wherein there is a gap between the carrier portion of the support and the bottom layer.

2. The semiconductor structure of claim 1, wherein the semiconductor element exposes a portion of the carrier portion, and the thickness of the exposed portion of the carrier portion is less than the thickness of the carrier portion located below the semiconductor element.

3. The semiconductor structure as claimed in claim 1, wherein the semiconductor element includes a semiconductor layer and an element layer, the semiconductor layer is disposed between the carrier portion and the element layer, and the bottom layer has the same material as the semiconductor layer.

4. The semiconductor structure of claim 1, wherein, in a top view, the connection portion has a recess located at the edge of the connection portion.

5. The semiconductor structure as described in claim 1, further comprising: An adhesive layer is disposed between the carrier and the semiconductor element.

6. The semiconductor structure of claim 5, wherein the width of the adhesive layer is smaller than the width of the semiconductor element.

7. The semiconductor structure of claim 1, wherein the semiconductor element comprises a III-V group semiconductor material.

8. A semiconductor unit, comprising: The support includes: The connecting portion has a first side surface; and A support portion, located beside the connecting portion, and having a second side surface; and A semiconductor element is disposed on the carrier portion, and the connection portion is exposed. The roughness of the first side surface is greater than the roughness of the second side surface.

9. The semiconductor unit of claim 8, further comprising: An adhesive layer is disposed between the carrier and the semiconductor element, and there is a distance between the side surface of the adhesive layer and the side surface of the semiconductor element.

10. A method for forming a semiconductor structure, comprising: Provide a first semiconductor layer; An insulating layer is formed on the first semiconductor layer; Semiconductor elements are formed on the insulating layer; The insulating layer is patterned to form a support structure; and A portion of the first semiconductor layer is removed to create a gap between the bottom surface of the support and the top surface of the first semiconductor layer.

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