Test structure and test method

Abstract

The invention discloses a test structure and a test method. The test structure comprises a first electric signal loading line which is electrically connected with the drain side of a pull-down transistor of a first subunit region; the second electric signal loading line is electrically connected with the source electrode sides of the transmission gate transistor and the pull-down transistor of the first subunit region; a third electric signal loading line is electrically connected with the drain electrode sides of the transmission gate transistors of the first subunit region and the second subunit region; a fourth electric signal loading line is electrically connected with the drain sides of the pull-up transistors of the first subunit region and the second subunit region; a seventh electric signal loading line is electrically connected with the pull-down transistor of the first subunit region and the substrate side of the transmission gate transistor; an eleventh electrical signal loading line is electrically connected to gate sides of the pull-up transistor and the pull-down transistor of the second sub-unit region and to a source side of the first sub-unit region. The leakage current value of each part of a pull-up transistor, a pull-down transistor and a transmission gate transistor of the test structure can be obtained.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a test structure and a test method. BACKGROUND

[0002] SRAM (Static Random Access Memory) is a kind of static random access semiconductor memory, which can be used to store data and can be written and read.

[0003] 6T SRAM is widely used due to its small static power consumption and strong compatibility with logic operation. 6T SRAM is composed of two inverters (PD and PU) to form a latch circuit, plus two access switches (PG). In the charged state, the two storage will always maintain the initial state, and when the power is cut off, the steady state no longer exists, and the storage information is lost.

[0004] Since SRAM has static nature, its static power consumption is the main source of power consumption, and reducing the static leakage current can effectively reduce the static power consumption.

[0005] However, as the size of SRAM is gradually compressed, the SRAM static leakage current is more and more cannot be ignored, and it is not enough to simply measure the total static leakage current of SRAM. It is also necessary to understand the static leakage proportion of each part of SRAM, so as to improve it. SUMMARY

[0006] The problem solved by the embodiments of the present application is to provide a test structure and a test method to improve the performance of the test structure.

[0007] To solve the above problems, the embodiment of the present application provides a test structure, comprising: a substrate comprising a memory cell region, the memory cell region comprising a first sub-cell region and a second sub-cell region extending along a first direction and adjacent along a second direction, the first direction being perpendicular to the second direction, the first sub-cell region comprising a pass gate transistor, a pull-up transistor and a pull-down transistor, and the second sub-cell region comprising a pass gate transistor, a pull-up transistor and a pull-down transistor; a first electrical signal loading line electrically connected to the drain side of the pull-down transistor of the first sub-cell region; a second electrical signal loading line electrically connected to the source side of the pass gate transistor and the pull-down transistor of the first sub-cell region; a third electrical signal loading line electrically connected to the drain side of the pass gate transistor of the first sub-cell region and the second sub-cell region; a fourth electrical signal loading line electrically connected to the drain side of the pull-up transistor of the first sub-cell region and the second sub-cell region; a fifth electrical signal loading line electrically connected to the gate side of the pass gate transistor and the pull-down transistor of the first sub-cell region, and the source side of the pull-up transistor of the second sub-cell region; a sixth electrical signal loading line electrically connected to the gate side of the pass gate transistor of the first sub-cell region and the second sub-cell region; a seventh electrical signal loading line electrically connected to the substrate side of the pull-down transistor and the pass gate transistor of the first sub-cell region; an eighth electrical signal loading line electrically connected to the substrate side of the pull-down transistor and the pass gate transistor of the second sub-cell region; a ninth electrical signal loading line electrically connected to the source side of the pull-down transistor and the pass gate transistor of the second sub-cell region; a tenth electrical signal loading line electrically connected to the drain side of the pull-down transistor of the second sub-cell region; and an eleventh electrical signal loading line electrically connected to the gate side of the pull-up transistor and the pull-down transistor of the second sub-cell region, and the source side of the first sub-cell region.

[0008] Optionally, the first and second sub-unit regions each comprise: a first active region on the substrate and extending along the first direction and arranged in parallel along the second direction; a second active region on the substrate and extending along the first direction and arranged in parallel along the second direction; a first gate structure across the first and second active regions, the first gate structure and the first active region forming a pull-down transistor, the first gate and the second active region forming a pull-up transistor; a second gate structure across the first active region, the second gate structure and the first active region forming a pass transistor; a first interconnection plug on the substrate at a side of the pull-down transistor and the pass transistor; a second interconnection plug on the substrate at a side of the pull-down transistor different from the first interconnection plug; a third interconnection plug on the substrate at a side of the pass transistor different from the first interconnection plug; a first gate plug on top of the first gate structure and electrically connected with the first gate structure, and the first gate plug being electrically connected with the substrate at a side of the pull-up transistor adjacent to the sub-unit region; a fourth interconnection plug on the substrate at a side of the pull-up transistor different from the first gate plug; a second gate plug on top of the second gate structure and electrically connected with the second gate structure.

[0009] Optionally, the first electrical signal loading line is electrically connected with the second interconnection plug; the second electrical signal loading line is electrically connected with the first interconnection plug; the third electrical signal loading line is electrically connected with the third interconnection plug; the fourth electrical signal loading line is electrically connected with the fourth interconnection plug; the fifth electrical signal loading line is electrically connected with the first gate plug; the sixth electrical signal loading line is electrically connected with the second gate plug; the ninth electrical signal loading line is electrically connected with the first interconnection plug; the tenth electrical signal loading line is electrically connected with the second interconnection plug; the eleventh electrical signal loading line is electrically connected with the first gate plug.

[0010] Optionally, the first and second sub-unit regions each further comprise: a third active region in the substrate at a side of the pull-up transistor, the pull-down transistor and the pass transistor, and the third active region being electrically connected with the substrate at a side of the pull-down transistor and the pass transistor; a fifth interconnection plug on top of the third active region, and the fifth interconnection plug being electrically connected with the third active region.

[0011] Optionally, the seventh electrical signal loading line is on top of the fifth interconnection plug of the first sub-unit region, and the seventh electrical signal loading line is electrically connected with the fifth interconnection plug; the eighth electrical signal loading line is on top of the fifth interconnection plug of the second sub-unit region, and the eighth electrical signal loading line is electrically connected with the fifth interconnection plug.

[0012] Optionally, the test structure further comprises: a fourth active region located in the base of the side of the pull-up transistor; a sixth interconnection plug located on the top of the fourth active region, and the sixth interconnection plug is electrically connected with the fourth active region; and the fourth electrical signal loading line is electrically connected with the sixth interconnection plug.

[0013] Optionally, the base comprises a plurality of memory cell regions.

[0014] Correspondingly, the embodiment of the present application further provides a test method suitable for testing the test structure provided by the embodiment of the present application, and the test method comprises the following steps: loading different test electrical signals on the first electrical signal loading line, the second electrical signal loading line, the third electrical signal loading line, the fourth electrical signal loading line, the fifth electrical signal loading line, the sixth electrical signal loading line, the seventh electrical signal loading line, the eighth electrical signal loading line, the ninth electrical signal loading line, the tenth electrical signal loading line and the eleventh electrical signal loading line; obtaining the leakage currents of the first electrical signal loading line, the second electrical signal loading line, the fifth electrical signal loading line, the seventh electrical signal loading line, the eighth electrical signal loading line, the ninth electrical signal loading line, the tenth electrical signal loading line and the eleventh electrical signal loading line under the test electrical signals; and obtaining the total leakage current of the test structure based on the leakage currents.

[0015] Optionally, the step of loading different test electrical signals on the first electrical signal loading line, the second electrical signal loading line, the third electrical signal loading line, the fourth electrical signal loading line, the fifth electrical signal loading line, the sixth electrical signal loading line, the seventh electrical signal loading line, the eighth electrical signal loading line, the ninth electrical signal loading line, the tenth electrical signal loading line and the eleventh electrical signal loading line comprises the following steps: loading positive voltages on the third electrical signal loading line, the fourth electrical signal loading line, the fifth electrical signal loading line and the ninth electrical signal loading line; and loading zero voltages on the sixth electrical signal loading line, the second electrical signal loading line, the eleventh electrical signal loading line, the eighth electrical signal loading line, the tenth electrical signal loading line, the first electrical signal loading line and the seventh electrical signal loading line.

[0016] Optionally, the step of obtaining the leakage currents of the first electrical signal loading line, the second electrical signal loading line, the fifth electrical signal loading line, the seventh electrical signal loading line, the eighth electrical signal loading line, the ninth electrical signal loading line, the tenth electrical signal loading line and the eleventh electrical signal loading line under the test electrical signals comprises the following step: obtaining the leakage currents of the first electrical signal loading line, the second electrical signal loading line, the seventh electrical signal loading line, the eighth electrical signal loading line, the tenth electrical signal loading line and the eleventh electrical signal loading line.

[0017] Optionally, the step of obtaining the total leakage current of the test structure includes: adding the obtained leakage currents of the first electrical signal loading line, the second electrical signal loading line, the seventh electrical signal loading line, the eighth electrical signal loading line, the tenth electrical signal loading line, and the eleventh electrical signal loading line to obtain the total leakage current of the test structure.

[0018] Optionally, the substrate includes multiple memory cell regions; based on the obtained total leakage current of the test structure, the test method further includes: obtaining the leakage current I = I0 of each memory cell region. 总 / D; where I 总 The value represents the total leakage current of the obtained test structure; D represents the number of memory cell areas.

[0019] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0020] In the test structure provided in this embodiment of the invention, the first electrical signal loading line is electrically connected to the drain side of the pull-down transistor in the first sub-unit region; the second electrical signal loading line is electrically connected to the source side of the transmission gate transistor and the pull-down transistor in the first sub-unit region; the third electrical signal loading line is electrically connected to the drain side of the transmission gate transistor in the first and second sub-unit regions; the fourth electrical signal loading line is electrically connected to the drain side of the pull-up transistor in the first and second sub-unit regions; the fifth electrical signal loading line is electrically connected to the gate side of the transmission gate transistor and the pull-down transistor in the first sub-unit region, and to the source side of the pull-up transistor in the second sub-unit region; the sixth electrical signal loading line is electrically connected to the gate side of the transmission gate transistor in the first and second sub-unit regions; the seventh electrical signal loading line is electrically connected to the substrate side of the pull-down transistor and the transmission gate transistor in the first sub-unit region; the eighth electrical signal loading line is electrically connected to the substrate side of the pull-down transistor and the transmission gate transistor in the second sub-unit region; the ninth electrical signal loading line is electrically connected to the source side of the pull-down transistor and the transmission gate transistor in the second sub-unit region; and the tenth electrical signal loading line is electrically connected to the source side of the pull-down transistor and the transmission gate transistor in the second sub-unit region. The signal loading line is electrically connected to the drain side of the pull-down transistor in the second sub-unit region, and the eleventh signal loading line is electrically connected to the gate side of the pull-up and pull-down transistors in the second sub-unit region, as well as to the source side of the first sub-unit region. That is, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh signal loading lines are not connected to each other. During the subsequent electrical testing of the test structure, different electrical signals can be applied to the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh signal loading lines, thereby obtaining the leakage current values ​​of each part of the pull-up transistor, pull-down transistor, and transmission gate transistor in the test structure, and further improving the performance of the test structure. Attached Figure Description

[0021] Figure 1 This is a circuit diagram corresponding to an embodiment of the test structure of the present invention;

[0022] Figure 2 This is a schematic diagram of an embodiment of the test structure of the present invention;

[0023] Figure 3 This is a flowchart corresponding to one embodiment of the testing method of the present invention. Detailed Implementation

[0024] Currently, the performance of the test structure still needs improvement. Especially in 6TSRAM, when measuring the static leakage current of SRAM, the substrates of PG and PD are connected to 0V, and the substrate of PU is connected to Vdd voltage. Vdd voltage is applied to VDD and BL / BLB terminals, while VSS and WL are connected to 0V. The current received at the VSS terminal is the static leakage current. As the size of SRAM is gradually reduced, the static leakage current of SRAM is becoming increasingly non-negligible. Simply measuring the total static leakage current of an SRAM is not enough; it is also necessary to understand the static leakage current of each part of the SRAM.

[0025] To address the aforementioned technical problems, embodiments of the present invention provide a test structure, comprising: a substrate including a memory cell region, the memory cell region including a first sub-cell region and a second sub-cell region extending along a first direction and adjacent to each other along a second direction, the first direction being perpendicular to the second direction; the first sub-cell region including a transmission gate transistor, a pull-up transistor, and a pull-down transistor; the second sub-cell region including a transmission gate transistor, a pull-up transistor, and a pull-down transistor; a first electrical signal loading line electrically connected to the drain side of the pull-down transistor in the first sub-cell region; a second electrical signal loading line electrically connected to the source side of the transmission gate transistor and the pull-down transistor in the first sub-cell region; a third electrical signal loading line electrically connected to the drain side of the transmission gate transistor in the first and second sub-cell regions; and a fourth electrical signal loading line electrically connected to the drain side of the pull-up transistor in the first and second sub-cell regions. The fifth electrical signal loading line is electrically connected to the gate side of the transmission gate transistor and the pull-down transistor in the first sub-cell region, and to the source side of the pull-up transistor in the second sub-cell region; the sixth electrical signal loading line is electrically connected to the gate side of the transmission gate transistor in the first and second sub-cell regions; the seventh electrical signal loading line is electrically connected to the substrate side of the pull-down transistor and the transmission gate transistor in the first sub-cell region; the eighth electrical signal loading line is electrically connected to the substrate side of the pull-down transistor and the transmission gate transistor in the second sub-cell region; the ninth electrical signal loading line is electrically connected to the source side of the pull-down transistor and the transmission gate transistor in the second sub-cell region; the tenth electrical signal loading line is electrically connected to the drain side of the pull-down transistor in the second sub-cell region; and the eleventh electrical signal loading line is electrically connected to the gate side of the pull-up transistor and the pull-down transistor in the second sub-cell region, and to the source side of the first sub-cell region.

[0026] In the test structure provided by this embodiment of the invention, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh electrical signal loading lines are not connected to each other. During subsequent electrical testing of the test structure, different electrical signals can be applied to the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh electrical signal loading lines, thereby enabling the acquisition of leakage current values ​​for each part of the pull-up transistor, pull-down transistor, and transmission gate transistor in the test structure, and further improving the performance of the test structure.

[0027] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0028] Figure 1 This is a circuit diagram corresponding to an embodiment of the test structure of the present invention; Figure 2 This is a schematic diagram of an embodiment of the test structure of the present invention.

[0029] refer to Figures 1 to 2The test structure includes: a substrate (not shown), including a memory cell region (not labeled), the memory cell region including a first sub-cell region 100A and a second sub-cell region 100B extending along a first direction and adjacent along a second direction, the first direction being perpendicular to the second direction; the first sub-cell region 100A including a transmission gate transistor PG2, a pull-up transistor PU2, and a pull-down transistor PD2, and both the first and second sub-cell regions 100B including a transmission gate transistor PG1, a pull-up transistor PU1, and a pull-down transistor PD1; a first electrical signal is applied. The carrier line VSS2 is electrically connected to the drain side of the pull-down transistor in the first sub-cell region 100A; the second electrical signal loading line N2X is electrically connected to the source side of the transmission gate transistor and the pull-down transistor in the first sub-cell region 100A; the third electrical signal loading line BL / BLB is electrically connected to the drain side of the transmission gate transistor in the first sub-cell region 100A and the second sub-cell region 100B; and the fourth electrical signal loading line VDD is electrically connected to the drain side of the pull-up transistor in the first sub-cell region 100A and the second sub-cell region 100B. The fifth electrical signal loading line N1 is electrically connected to the gate side of the transmission gate transistor and pull-down transistor of the first sub-cell region 100A, and to the source side of the pull-up transistor of the second sub-cell region 100B; the sixth electrical signal loading line WL is electrically connected to the gate side of the transmission gate transistor of the first sub-cell region 100A and the second sub-cell region 100B; the seventh electrical signal loading line VSS2X is electrically connected to the substrate side of the pull-down transistor and transmission gate transistor of the first sub-cell region 100A; the eighth electrical signal loading line VSS1X is electrically connected to... The pull-down transistor and the transmission gate transistor of the second sub-cell region 100B are electrically connected to the substrate side; the ninth electrical signal loading line N1X is electrically connected to the source side of the pull-down transistor and the transmission gate transistor of the second sub-cell region 100B; the tenth electrical signal loading line VSS1 is electrically connected to the drain side of the pull-down transistor of the second sub-cell region 100B; the eleventh electrical signal loading line N2 is electrically connected to the gate side of the pull-up transistor and the pull-down transistor of the second sub-cell region 100B, and to the source side of the first sub-cell region 100A.

[0030] Specifically, the first electrical signal loading line VSS2, the second electrical signal loading line N2X, the third electrical signal loading line BL / BLB, the fourth electrical signal loading line VDD, the fifth electrical signal loading line N1, the sixth electrical signal loading line WL, the seventh electrical signal loading line VSS2X, the eighth electrical signal loading line VSS1X, the ninth electrical signal loading line N1X, the tenth electrical signal loading line VSS1, and the eleventh electrical signal loading line N2 are not connected to each other. During subsequent electrical testing of the test structure, the first electrical signal loading line VSS2, the second electrical signal loading line N2X, the third electrical signal loading line BL / BLB, the fourth electrical signal loading line VDD, the fifth electrical signal loading line N1, the sixth electrical signal loading line WL, the seventh electrical signal loading line VSS2X, the eighth electrical signal loading line VSS1X, the ninth electrical signal loading line N1X, the tenth electrical signal loading line VSS1, and the eleventh electrical signal loading line N2 are not connected to each other. Different electrical signals are applied to the signal loading lines N2X, BL / BLB, VDD, N1, WL, VSS2X, VSS1X, N1X, VSS1, and N2, respectively, thereby enabling the acquisition of leakage current values ​​for various parts of the test structure, including the pull-up transistors, pull-down transistors, and transmission gate transistors, and further improving the performance of the test structure.

[0031] In this embodiment, both the first sub-unit region 100A and the second sub-unit region 100B include: a first active region 100 and a second active region 103, located on the substrate and along the first direction (e.g., Figure 1 Extending along the Y direction (as shown) and along the second direction (as shown) Figure 1 (As shown in the X direction) arranged in parallel; a first gate structure 101, spanning the first active region 100 and the second active region 103, the first gate structure 101 and the first active region 100 form a pull-down transistor, the first gate and the second active region 103 form a pull-up transistor; a second gate structure 102, spanning the first active region 100, the second gate structure 102 and the first active region 100 form a transmission gate transistor; a first interconnect plug 120, located on the substrate adjacent to the pull-down transistor and the transmission gate transistor; a second interconnect plug 190, located adjacent to the first interconnect plug 120. On the substrate of the pull-down transistor on the different side; a third interconnect plug 191, located on the substrate of the transmission gate transistor on the different side from the first interconnect plug 120; a first gate plug 108, located on top of the first gate structure 101 and electrically connected to the first gate structure 101, and the first gate plug 108 is electrically connected to the substrate of the pull-up transistor on the adjacent sub-cell region; a fourth interconnect plug 192, located on the substrate of the pull-up transistor on the different side from the first gate plug; a second gate plug 106, located on top of the second gate structure 102 and electrically connected to the second gate structure 102.

[0032] The substrate provides a process platform for setting up semiconductor structures.

[0033] In this embodiment, the substrate includes a substrate.

[0034] The substrate material is silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0035] In this embodiment, the test structure is an SRAM device, which includes multiple memory cell areas.

[0036] Specifically, in an SRAM device, multiple memory cell regions are arranged in a matrix along a first direction and a second direction.

[0037] It should also be noted that during subsequent electrical testing, the total leakage current of the test structure can be obtained, and then the leakage current of each memory cell area can be obtained based on the number of memory cell areas.

[0038] In this embodiment, the storage cell area includes a first sub-cell area 100A and a second sub-cell area 100B that extend along a first direction and are adjacent to each other along a second direction, wherein the first direction is perpendicular to the second direction.

[0039] Specifically, the first sub-unit region 100A includes a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region, and the second sub-unit region 100B includes a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region.

[0040] Specifically, the transmission gate transistor region is used to form transmission gate transistors, the pull-down transistor region is used to form pull-down transistors, and the pull-up transistor region is used to form pull-up transistors. The transmission gate transistors and pull-down transistors are both N-type transistors, while the pull-up transistors are P-type transistors.

[0041] The first active region 100 is used to provide a conductive channel for pull-down transistors and transmission gate transistors, and the second active region 103 is used to provide a conductive channel for pull-up transistors.

[0042] In this embodiment, both the first active region 100 and the second active region 103 are made of silicon. In other embodiments, the materials of the first active region 100 and the second active region 103 may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth, and the materials of the first active region 100 and the second active region 103 may also be different from the material of the substrate.

[0043] It should be noted that the first gate structure 101 is used to control the opening and closing of the conductive channels of the pull-down transistor and the pull-up transistor, and the second gate structure 102 is used to control the opening and closing of the conductive channel of the transmission gate transistor.

[0044] In this embodiment, both the first gate structure 101 and the second gate structure 102 are metal gate structures. The first gate structure 101 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, and the second gate structure 102 also includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0045] The gate dielectric layer is used for the electrically isolated gate electrode layer and the first active region 100, and for the electrically isolated gate electrode layer and the second active region 103.

[0046] In this embodiment, the material of the gate dielectric layer includes silicon oxide.

[0047] Specifically, the gate electrode layer is used to bring out the electrical properties of the metal gate structure.

[0048] In this embodiment, the gate electrode layer is made of polysilicon. It should be noted that, as an example, the transmission gate transistor and the pull-down transistor share the same first active region 100 to meet the operational requirements of the SRAM device.

[0049] As an example, the pull-down transistor and the pull-up transistor share the first gate structure 101 to meet the operating requirements of the SRAM device.

[0050] In this embodiment, the first interconnect plug 120 is located on the substrate adjacent to the pull-down transistor and the transmission gate transistor (i.e., the source side), the second interconnect plug 190 is located on the substrate on the pull-down transistor side (i.e., the drain side) of the same side as the first interconnect plug 120, and the third interconnect plug 191 is located on the substrate on the transmission gate transistor side (i.e., the drain side) of the same side as the first interconnect plug 120.

[0051] In this embodiment, the fourth interconnect plug 192 is located on the substrate on the pull-up transistor side (i.e., the drain side) on a side different from the first gate plug.

[0052] In this embodiment, the first electrical signal loading line is electrically connected to the second interconnect plug.

[0053] It should be noted that the first electrical signal loading line is the rear section of the metal line located at the top of the second interconnect plug 190 in the first sub-unit area 100A.

[0054] Specifically, such as Figure 1 As shown, the first electrical signal loading line is the VSS2 terminal.

[0055] In this embodiment, the second electrical signal loading line is electrically connected to the first interconnect plug 120.

[0056] It should be noted that the second electrical signal loading line is the rear section of the metal line located at the top of the first interconnect plug 120 in the first sub-unit area.

[0057] Specifically, such as Figure 1 As shown, the second electrical signal loading line is the N2X terminal.

[0058] In this embodiment, the third electrical signal loading line is electrically connected to the third interconnect plug 191.

[0059] It should be noted that the third electrical signal loading line is the rear section of the metal line at the top of the third interconnect plug 191 in the first sub-unit area 100A.

[0060] Specifically, such as Figure 1 As shown, the third electrical signal loading line is the BLB terminal and the BL terminal.

[0061] In this embodiment, the fourth electrical signal loading line is electrically connected to the fourth interconnect plug 192.

[0062] It should be noted that the fourth electrical signal loading line is the rear section of the metal wire located on top of the fourth interconnect plug 192 in the first sub-cell area 100A and the second sub-cell area 100B.

[0063] Specifically, such as Figure 1 As shown, the fourth electrical signal loading line is the VDD terminal.

[0064] In this embodiment, the fifth electrical signal loading line is electrically connected to the first gate plug.

[0065] It should be noted that the fifth electrical signal loading line is the rear section of the metal line located at the top of the first gate plug in the first sub-cell region.

[0066] Specifically, such as Figure 1 As shown, the fifth electrical signal loading line is terminal N1.

[0067] In this embodiment, the sixth electrical signal loading line is electrically connected to the second gate plug.

[0068] It should be noted that the sixth electrical signal loading line is the rear section of the metal line located on top of the second gate plug in the first sub-cell region 100A and the second sub-cell region 100B.

[0069] Specifically, such as Figure 1 As shown, the sixth electrical signal loading line is the WL terminal.

[0070] In this embodiment, the first sub-unit region 100A and the second sub-unit region 100B each include a third active region 130, located in the substrate on the side of the pull-up transistor, pull-down transistor and transmission gate transistor, and the third active region 130 is electrically connected to the substrate side of the pull-down transistor and transmission gate transistor.

[0071] Specifically, the third active region 130 is used to connect to the substrate of the transmission gate transistor and the pull-down transistor, and can obtain the leakage current of the transmission gate transistor and the pull-down transistor on the substrate in the static state during subsequent electrical testing.

[0072] In this embodiment, the first sub-unit region 100A and the second sub-unit region 100B each include a fifth interconnect plug 150, which is located on top of the third active region 130 and is electrically connected to the third active region 130.

[0073] The seventh electrical signal loading line is located on top of the fifth interconnect plug 150 of the first sub-unit area 100A, and the seventh electrical signal loading line is electrically connected to the fifth interconnect plug 150.

[0074] It should be noted that the seventh electrical signal loading line is the rear section of the metal line at the top of the fifth interconnect plug 150 in the first sub-cell area.

[0075] Specifically, such as Figure 1 As shown, the seventh electrical signal loading line is the VSS2X terminal.

[0076] In this embodiment, the test structure further includes an eighth electrical signal loading line, located on top of the fifth interconnect plug 150 of the second sub-unit area 100B, and the eighth electrical signal loading line is electrically connected to the fifth interconnect plug 150.

[0077] It should be noted that the eighth electrical signal loading line is the rear section of the metal line located at the top of the fifth interconnect plug 150 in the second sub-unit area 100B.

[0078] Specifically, such as Figure 1 As shown, the eighth electrical signal loading line is the VSS1X terminal.

[0079] In this embodiment, the ninth electrical signal loading line is electrically connected to the first interconnect plug 120.

[0080] It should be noted that the ninth electrical signal loading line is the rear section of the metal line located at the top of the first interconnect plug 120 in the second sub-unit area 100B.

[0081] Specifically, such as Figure 1 As shown, the ninth electrical signal loading line is the N1X terminal.

[0082] In this embodiment, the tenth electrical signal loading line is electrically connected to the second interconnect plug 190.

[0083] It should be noted that the tenth electrical signal loading line is the rear section of the metal line located at the top of the second interconnect plug 190 in the second sub-unit area 100B.

[0084] Specifically, such asFigure 1 As shown, the tenth electrical signal loading line is the VSS1 terminal.

[0085] In this embodiment, the eleventh electrical signal loading line is electrically connected to the first gate plug 108.

[0086] It should be noted that the eleventh electrical signal loading line is the rear section of the metal line located at the top of the first gate plug 108 in the second sub-cell region 100B.

[0087] Specifically, such as Figure 1 As shown, the eleventh electrical signal loading line is terminal N2.

[0088] In this embodiment, the test structure further includes a fourth active region 140, located in the substrate on the side of the pull-up transistor.

[0089] Specifically, the fourth active region 140 is used to connect to the substrate of the pull-up transistor, and can obtain the leakage current of the substrate of the pull-up transistor in the off state during subsequent electrical testing.

[0090] In this embodiment, the test structure further includes a sixth interconnect plug 160, located at the top of the fourth active region, and the sixth interconnect plug 160 is electrically connected to the fourth active region.

[0091] It should be noted that during the process of setting the fourth electrical signal loading line, the fourth electrical signal loading line is also electrically connected to the sixth interconnect plug 160.

[0092] Specifically, the fourth electrical signal loading line is electrically connected to the sixth interconnect plug 160.

[0093] Accordingly, the present invention also provides a testing method suitable for testing the aforementioned test structure. Figure 1 This is a schematic flowchart corresponding to one embodiment of the testing method of the present invention. The following is in conjunction with the appendix... Figure 1 and 2 The testing methods of this implementation will be described in detail.

[0094] It should be noted that for a detailed description of the aforementioned test structure, please refer to the corresponding description in the preceding sections, which will not be repeated here.

[0095] Reference Figure 3 and 2Step S1: Apply different test electrical signals to the first electrical signal loading line VSS2, the second electrical signal loading line N2X, the third electrical signal loading line BL / BLB, the fourth electrical signal loading line VDD, the fifth electrical signal loading line N1, the sixth electrical signal loading line WL, the seventh electrical signal loading line VSS2X, the eighth electrical signal loading line VSS1X, the ninth electrical signal loading line N1X, the tenth electrical signal loading line VSS1, and the eleventh electrical signal loading line N2.

[0096] Specifically, the first electrical signal loading line VSS2, the second electrical signal loading line N2X, the third electrical signal loading line BL / BLB, the fourth electrical signal loading line VDD, the fifth electrical signal loading line N1, the sixth electrical signal loading line WL, the seventh electrical signal loading line VSS2X, the eighth electrical signal loading line VSS1X, the ninth electrical signal loading line N1X, the tenth electrical signal loading line VSS1, and the eleventh electrical signal loading line N2 are not connected to each other. During subsequent electrical testing of the test structure, the first electrical signal loading line VSS2, the second electrical signal loading line N2X, the third electrical signal loading line BL / BLB, the fourth electrical signal loading line VDD, the fifth electrical signal loading line N1, the sixth electrical signal loading line WL, the seventh electrical signal loading line VSS2X, the eighth electrical signal loading line VSS1X, the ninth electrical signal loading line N1X, the tenth electrical signal loading line VSS1, and the eleventh electrical signal loading line N2 are not connected to each other. Different electrical signals are applied to the signal loading lines N2X, BL / BLB, VDD, N1, WL, VSS2X, VSS1X, N1X, VSS1, and N2, respectively, thereby enabling the acquisition of leakage current values ​​for various parts of the test structure, including the pull-up transistors, pull-down transistors, and transmission gate transistors, and further improving the performance of the test structure.

[0097] In this embodiment, the step of applying different test electrical signals to the first electrical signal loading line VSS2, the second electrical signal loading line N2X, the third electrical signal loading line BL / BLB, the fourth electrical signal loading line VDD, the fifth electrical signal loading line N1, the sixth electrical signal loading line WL, the seventh electrical signal loading line VSS2X, the eighth electrical signal loading line VSS1X, the ninth electrical signal loading line N1X, the tenth electrical signal loading line VSS1, and the eleventh electrical signal loading line N2 includes: applying a positive voltage to the third, fourth, fifth, and ninth electrical signal loading lines; and applying zero voltage to the sixth, second, eleventh, eighth, tenth, first, and seventh electrical signal loading lines.

[0098] Specifically, the positive voltage is 1.2V. In other embodiments, other positive voltage values ​​may be applied as needed.

[0099] Reference Figure 1 and 2Step S2: Obtain the leakage current of the first electrical signal loading line VSS2, the second electrical signal loading line N2X, the fifth electrical signal loading line N1, the seventh electrical signal loading line VSS2X, the eighth electrical signal loading line VSS1X, the ninth electrical signal loading line N1X, the tenth electrical signal loading line VSS1, and the eleventh electrical signal loading line N2 under the test electrical signal.

[0100] In this embodiment, the step of obtaining the leakage current of the first electrical signal loading line VSS2, the second electrical signal loading line N2X, the fifth electrical signal loading line N1, the seventh electrical signal loading line VSS2X, the eighth electrical signal loading line VSS1X, the ninth electrical signal loading line N1X, the tenth electrical signal loading line VSS1, and the eleventh electrical signal loading line N2 under the test electrical signal includes: obtaining the leakage current of the first electrical signal loading line, the second electrical signal loading line, the seventh electrical signal loading line, the eighth electrical signal loading line, the tenth electrical signal loading line, and the eleventh electrical signal loading line.

[0101] Specifically, such as Figure 1 As shown, the leakage current of the eighth electrical signal loading line is I. B PG1 and I B PD1.

[0102] The leakage current of the tenth electrical signal loading line is I off PD1.

[0103] The leakage current of the eleventh electrical signal loading line is I. g PU1 and I off PU2.

[0104] The leakage current of the second electrical signal loading line is I. off PG2.

[0105] The leakage current of the first electrical signal loading line is I. g PD2.

[0106] The leakage current of the seventh electrical signal loading line is I B PG2 and I B PD2.

[0107] Reference Figure 1 and 2 Step S3: Based on the leakage current, obtain the total leakage current of the test structure.

[0108] Specifically, the step of obtaining the total leakage current of the test structure includes: adding the obtained leakage currents of the first electrical signal loading line, the second electrical signal loading line, the seventh electrical signal loading line, the eighth electrical signal loading line, the tenth electrical signal loading line, and the eleventh electrical signal loading line to obtain the total leakage current of the test structure.

[0109] In other words, the total leakage current of the test structure = I off PD1+I g PD2+I off PG2+I g PU1+I off PU1+I B PG1+I B PD1+I B PG2+I B PD2.

[0110] Reference Figure 2 Figure 1 Figure 1 and 2 Step S4: Obtain the leakage current of each memory cell area.

[0111] Specifically, obtain the leakage current I = I in each memory cell area. 总 / D; where I 总 The value represents the total leakage current of the obtained test structure; D represents the number of memory cell areas.

[0112] It should be noted that the number of storage unit areas can be flexibly set according to actual needs.

[0113] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A test structure, characterized in that, include: The substrate includes a memory cell region, the memory cell region including a first sub-cell region and a second sub-cell region extending along a first direction and adjacent along a second direction, the first direction being perpendicular to the second direction, the first sub-cell region including a transmission gate transistor, a pull-up transistor and a pull-down transistor, and the second sub-cell region including a transmission gate transistor, a pull-up transistor and a pull-down transistor; The first electrical signal loading line is electrically connected to the drain side of the pull-down transistor in the first sub-cell region; The second electrical signal loading line is electrically connected to the source side of the transmission gate transistor and the pull-down transistor in the first sub-unit region; The third electrical signal loading line is electrically connected to the drain side of the transmission gate transistor in the first sub-unit region and the second sub-unit region; The fourth electrical signal loading line is electrically connected to the drain side of the pull-up transistors in the first and second sub-cell regions; The fifth electrical signal loading line is electrically connected to the gate side of the transmission gate transistor and the pull-down transistor in the first sub-unit region, and to the source side of the pull-up transistor in the second sub-unit region. The sixth electrical signal loading line is electrically connected to the gate side of the transmission gate transistor in the first and second sub-unit regions; The seventh electrical signal loading line is electrically connected to the substrate side of the pull-down transistor and the transmission gate transistor in the first sub-cell region; The eighth electrical signal loading line is electrically connected to the substrate side of the pull-down transistor and the transmission gate transistor in the second sub-unit region; The ninth electrical signal loading line is electrically connected to the source side of the pull-down transistor and the transmission gate transistor in the second sub-unit region; The tenth electrical signal loading line is electrically connected to the drain side of the pull-down transistor in the second sub-unit region; The eleventh electrical signal loading line is electrically connected to the gate side of the pull-up transistor and pull-down transistor in the second sub-cell region, and to the source side of the first sub-cell region.

2. The test structure as described in claim 1, characterized in that, Both the first sub-unit region and the second sub-unit region include: A first active region is located on the substrate and extends along the first direction and is arranged in parallel along the second direction; The second active region is located on the substrate and extends along the first direction and is arranged in parallel along the second direction; A first gate structure spans the first active region and the second active region. The first gate structure and the first active region form a pull-down transistor, and the first gate and the second active region form a pull-up transistor. A second gate structure spans the first active region, and the second gate structure and the first active region together constitute a transmission gate transistor. The first interconnect plug is located on the substrate adjacent to the pull-down transistor and the transmission gate transistor; The second interconnect plug is located on the substrate on the side of the pull-down transistor, which is different from the first interconnect plug; The third interconnect plug is located on the substrate on the side of the transmission gate transistor, which is different from the first interconnect plug; The first gate plug is located on top of the first gate structure and is electrically connected to the first gate structure, and the first gate plug is electrically connected to the substrate on the side of the pull-up transistor of the adjacent sub-cell region. The fourth interconnect plug is located on the substrate on the side of the pull-up transistor, which is different from the first gate plug; The second gate plug is located on top of the second gate structure and is electrically connected to the second gate structure.

3. The test structure as described in claim 2, characterized in that, The first electrical signal loading line is electrically connected to the second interconnect plug; The second electrical signal loading line is electrically connected to the first interconnect plug; The third electrical signal loading line is electrically connected to the third interconnect plug; The fourth electrical signal loading line is electrically connected to the fourth interconnect plug; The fifth electrical signal loading line is electrically connected to the first gate plug; The sixth electrical signal loading line is electrically connected to the second gate plug; The ninth electrical signal loading line is electrically connected to the first interconnect plug; The tenth electrical signal loading line is electrically connected to the second interconnect plug; The eleventh electrical signal loading line is electrically connected to the first gate plug.

4. The test structure as described in claim 1, characterized in that, The first sub-cell region and the second sub-cell region each include: a third active region located in the substrate of the pull-up transistor, the pull-down transistor and the transmission gate transistor, and the third active region is electrically connected to the substrate side of the pull-down transistor and the transmission gate transistor; The fifth interconnect plug is located on top of the third active region and is electrically connected to the third active region.

5. The test structure as described in claim 4, characterized in that, The seventh electrical signal loading line is located on top of the fifth interconnect plug in the first sub-unit area, and the seventh electrical signal loading line is electrically connected to the fifth interconnect plug. The eighth electrical signal loading line is located on top of the fifth interconnect plug in the second sub-unit area, and the eighth electrical signal loading line is electrically connected to the fifth interconnect plug.

6. The test structure as described in claim 1, characterized in that, The test structure further includes: a fourth active region located in the substrate on the side of the pull-up transistor; The sixth interconnect plug is located at the top of the fourth active region and is electrically connected to the fourth active region; The fourth electrical signal loading line is electrically connected to the sixth interconnect plug.

7. The test structure as described in claim 1, characterized in that, The substrate includes multiple storage cell areas.

8. A testing method, characterized in that, Suitable for testing the test structure according to any one of claims 1 to 7, the test method comprising: Different test electrical signals are applied to the first electrical signal loading line, the second electrical signal loading line, the third electrical signal loading line, the fourth electrical signal loading line, the fifth electrical signal loading line, the sixth electrical signal loading line, the seventh electrical signal loading line, the eighth electrical signal loading line, the ninth electrical signal loading line, the tenth electrical signal loading line, and the eleventh electrical signal loading line; Obtain the leakage current of the first electrical signal loading line, the second electrical signal loading line, the fifth electrical signal loading line, the seventh electrical signal loading line, the eighth electrical signal loading line, the ninth electrical signal loading line, the tenth electrical signal loading line, and the eleventh electrical signal loading line under the test electrical signal; Based on the leakage current, the total leakage current of the test structure is obtained.

9. The test method as described in claim 8, characterized in that, The steps of applying different test electrical signals to the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh electrical signal loading lines include: applying a positive voltage to the third, fourth, fifth, and ninth electrical signal loading lines; and applying zero voltage to the sixth, second, eleventh, eighth, tenth, first, and seventh electrical signal loading lines.

10. The test method as described in claim 9, characterized in that, The step of obtaining the leakage current of the first electrical signal loading line, the second electrical signal loading line, the fifth electrical signal loading line, the seventh electrical signal loading line, the eighth electrical signal loading line, the ninth electrical signal loading line, the tenth electrical signal loading line, and the eleventh electrical signal loading line under the test electrical signal includes: obtaining the leakage current of the first electrical signal loading line, the second electrical signal loading line, the seventh electrical signal loading line, the eighth electrical signal loading line, the tenth electrical signal loading line, and the eleventh electrical signal loading line.

11. The test method as described in claim 8, characterized in that, The step of obtaining the total leakage current of the test structure includes: adding the obtained leakage currents of the first electrical signal loading line, the second electrical signal loading line, the seventh electrical signal loading line, the eighth electrical signal loading line, the tenth electrical signal loading line, and the eleventh electrical signal loading line to obtain the total leakage current of the test structure.

12. The test method as described in claim 8, characterized in that, The substrate includes multiple storage cell areas; After obtaining the total leakage current of the test structure, the test method further includes: obtaining the leakage current I = I0 of each memory cell area. 总 / D; where I 总 The value represents the total leakage current of the obtained test structure; D represents the number of memory cell areas.

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