Manufacturing method of shallow trench isolation structure of memory chip and shallow trench isolation structure
By using a hard mask layer with a thickness ratio of the second silicon oxide layer and the second silicon nitride layer to protect the first silicon nitride layer in the non-volatile flash memory, the problem of voids in the shallow trench isolation structure is solved, improving device quality and the reliability of the memory chip.
Patent Information
- Application Number
- CN202511523472.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-23
- Publication Date
- 2026-01-23
AI Technical Summary
In non-volatile flash memory, voids can easily appear during the fabrication of shallow trench isolation structures, leading to leakage, stress, or thermal stability issues, which can affect the quality of semiconductor devices.
A hard mask layer is formed by setting a second silicon oxide layer and a second silicon nitride layer with a preset thickness ratio on the first silicon nitride layer, and the first silicon nitride layer is protected during the etching process. Then the second silicon oxide layer is removed and silicon oxide is filled to form a shallow trench isolation structure.
It reduces the generation of voids in shallow trench isolation structures, improves device quality and yield, ensures the stability of floating gate thickness, reduces aspect ratio, and enhances the reliability of memory chips.
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Figure CN121398564A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of semiconductor, in particular to a manufacturing method of shallow trench isolation structure of memory chip and shallow trench isolation structure. BACKGROUND
[0002] In the non-volatile flash memory, a storage area and a logic area are provided. The storage area of the non-volatile flash memory is used for storing data, and the logic area of the non-volatile flash memory is used for realizing execution of instructions. In the storage area and the logic area, a shallow trench isolation structure is provided.
[0003] When the shallow trench isolation structure is formed in the non-volatile flash memory, a hard mask layer can be first formed on the substrate, and a shallow trench is etched in the substrate, then a medium is filled in the shallow trench, and finally the wafer surface is planarized. When the non-volatile flash memory is formed, a layer of silicon nitride is formed on the substrate. Since the thickness of the nitride layer is related to the thickness of the floating gate of the memory device in the subsequent storage area, in order to ensure that the silicon nitride layer is not affected during etching, an oxide layer is formed on the silicon nitride layer. Therefore, when the shallow trench is etched on the substrate, a multilayer stack of silicon nitride and silicon oxide is formed on the substrate. When the shallow trench is filled, the shallow trench has a higher aspect ratio than other types of product processes, which easily leads to voids in the filled medium when filling the medium in the shallow trench. Further, the formed semiconductor device has problems such as leakage, stress or thermal stability, which affects the quality of the semiconductor device. SUMMARY
[0004] The purpose of the present application is to provide a manufacturing method of shallow trench isolation structure of memory chip and shallow trench isolation structure, which can solve the problem of voids in the formation of shallow trench isolation structure.
[0005] To solve the above technical problems, the present application is realized by the following technical scheme:
[0006] The present application provides a manufacturing method of shallow trench isolation structure of memory chip, the memory chip comprising a storage area and a logic area, comprising the following steps:
[0007] A silicon substrate is provided, and a first silicon oxide layer and a first silicon nitride layer are sequentially formed on the silicon substrate;
[0008] A second silicon oxide layer and a second silicon nitride layer with a preset thickness ratio are formed on the first silicon nitride layer;
[0009] The second silicon nitride layer, the second silicon oxide layer, the first silicon nitride layer and the first silicon oxide layer are etched with a first mask pattern to form a mask layer with a first mask pattern;
[0010] forming a first blocking layer on the sidewall of the mask layer of the first mask pattern and the surface thereof and the surface of the substrate;
[0011] forming a first shallow trench while consuming the second silicon nitride layer on the storage region by etching the silicon substrate of the storage region by a photolithography and etching process with a second mask pattern;
[0012] forming a second blocking layer on the surface of the silicon substrate of the first shallow trench;
[0013] forming a second shallow trench while consuming the second silicon nitride layer on the logic region by etching the silicon substrate of the logic region by a photolithography and etching process with a third mask pattern;
[0014] wet etching the second blocking layer and the second silicon oxide layer;
[0015] filling silicon oxide in the first shallow trench and the second shallow trench to form a shallow trench isolation structure.
[0016] In an embodiment of the present application, the preset thickness ratio of the second silicon oxide layer and the second silicon nitride layer ranges from 1:15 to 1:25.
[0017] In an embodiment of the present application, the second silicon oxide layer is made by an atomic layer deposition process.
[0018] In an embodiment of the present application, when the silicon substrate and the second silicon nitride layer are etched by a dry etching method, the selectivity etching ratio of the second silicon nitride layer and the silicon substrate ranges from 1:70 to 1:90.
[0019] In an embodiment of the present application, the first blocking layer and the second blocking layer are silicon oxide layers.
[0020] In an embodiment of the present application, the silicon substrate and the second silicon nitride layer are etched by a dry etching method, and the gas of the dry etching method includes octafluorocyclobutane and sulfur hexafluoride, and the flow ratio of the octafluorocyclobutane and the sulfur hexafluoride ranges from 10:1 to 1:1.
[0021] In an embodiment of the present application, the gas of the dry etching method further includes trifluoromethane and hexafluoro-2-butyne.
[0022] In an embodiment of the present application, the first blocking layer and the second blocking layer cover the sidewall of the first silicon nitride layer.
[0023] In an embodiment of the present application, silicon oxide is deposited in the first shallow trench and the second shallow trench by a high aspect ratio process to form a shallow trench isolation structure.
[0024] The application further provides a shallow trench isolation structure formed by the method for manufacturing the shallow trench isolation structure of the memory chip.
[0025] In summary, the method for manufacturing the shallow trench isolation structure of the memory chip and the shallow trench isolation structure have the unexpected effect that the thickness of the floating gate in the formed nonvolatile flash memory is within the set size by setting the second silicon oxide layer on the first silicon nitride layer and the thickness of the second silicon nitride layer and the thickness ratio of the two layers of the hard mask layer, and the second silicon nitride layer is used to protect the first silicon nitride layer in the process of forming the first shallow trench and the second shallow trench. In the process of etching to form the first / second shallow trench, the second silicon nitride layer is consumed. After the first shallow trench and the second shallow trench are manufactured, the second silicon oxide layer is removed, and the first shallow trench and the second shallow trench are filled with silicon oxide. Compared with the manufacturing process of the shallow trench isolation structure in the prior art, the first silicon nitride layer does not need to be made thicker, and the thickness of the first silicon nitride layer is more uniform under the protection of the second oxide layer and the second silicon nitride layer, which will not cause the thickness of the floating gate in the subsequent process of the memory chip to exceed the expected range. By reducing the thickness of the first silicon nitride layer, the aspect ratio of the shallow trench when filling the silicon oxide is also reduced, and the probability of forming a hollow in the shallow trench isolation structure is also reduced. The method for manufacturing the shallow trench isolation structure of the memory chip provided by the application can improve the quality of the formed shallow trench isolation structure, and further improve the yield and reliability of the memory chip. BRIEF DESCRIPTION OF DRAWINGS
[0026] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.
[0027] Figure 1 The structural diagram of forming the first silicon oxide layer and the first silicon nitride layer in an embodiment.
[0028] Figure 2 The structural diagram of forming the second silicon oxide layer in an embodiment.
[0029] Figure 3 The structural diagram of forming the second silicon nitride layer in an embodiment.
[0030] Figure 4 The structural diagram of forming the opening in an embodiment.
[0031] Figure 5 The structural diagram of forming the first barrier layer in an embodiment.
[0032] Figure 6 This is a schematic diagram of the structure forming the first shallow trench in one embodiment.
[0033] Figure 7 This is a schematic diagram of the structure forming the second barrier layer in one embodiment.
[0034] Figure 8 This is a schematic diagram of the structure forming the second shallow trench in one embodiment.
[0035] Figure 9 This is a schematic diagram of a structure in one embodiment where the second silicon oxide layer has been removed.
[0036] Figure 10 This is a schematic diagram of a shallow trench isolation structure in one embodiment.
[0037] Label Explanation:
[0038] 100, Substrate; 101, First silicon oxide layer; 102, First silicon nitride layer; 103, Second silicon oxide layer; 104, Second silicon nitride layer; 105, Opening; 106, First barrier layer; 1071, First shallow trench; 1072, Second shallow trench; 108, Second barrier layer; 109, Silicon oxide; 1091, First shallow trench isolation structure; 1092, Second shallow trench isolation structure. Detailed Implementation
[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0040] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0041] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.
[0042] In semiconductor integrated devices, multiple semiconductor devices are formed on the same silicon substrate. When forming semiconductor devices, shallow trench isolation structures are set between the active regions of adjacent semiconductor devices or between different active regions of the same semiconductor device to isolate the different active regions.
[0043] Please see Figures 1 to 10 As shown, in one embodiment of the present invention, a semiconductor integrated device, such as a non-volatile flash memory (NOR Flash), is provided. The NOR Flash memory includes a storage region and a logic region. The storage region of the NOR Flash memory contains multiple storage devices for storing data. The logic region of the NOR Flash memory contains semiconductor devices such as high-voltage N-Metal-Oxide-Semiconductor (HV NMOS), high-voltage P-channel Metal-Oxide-Semiconductor (HV PMOS), low-voltage N-Metal-Oxide-Semiconductor (LVNMOS), or low-voltage P-channel Metal-Oxide-Semiconductor (LV PMOS) for executing instructions. A first shallow trench 1071 isolation structure 1091 is provided in the storage region of the NOR Flash memory to isolate the active region within the storage region. In the logic region of the non-volatile flash memory, a second shallow trench 1072 isolation structure 1092 is provided to isolate the active area in the logic region. The depth of the first shallow trench isolation structure 1091 is less than the depth of the second shallow trench isolation structure 1092.
[0044] It should be noted that this application does not limit the number and type of shallow trench isolation structures. In other embodiments, in the semiconductor integrated device, a third, fourth, or fifth shallow trench isolation structure of different depths may also be provided.
[0045] Please see Figures 1 to 10 As shown, in one embodiment of the present invention, when forming a non-volatile flash memory using the method for fabricating a shallow trench isolation structure on a silicon substrate 100 provided by the present invention, a first silicon oxide layer 101 and a first silicon nitride layer 102 are first sequentially formed on the silicon substrate 100. Next, a second silicon oxide layer 103 and a second silicon nitride layer 104 with a predetermined thickness ratio are formed on the first silicon nitride layer 102, and the second silicon nitride layer 104, the second silicon oxide layer 103, the first silicon nitride layer 102, and the first silicon oxide layer 101 are etched to form an opening 105 in contact with the surface of the silicon substrate 100. Then, the second silicon nitride layers 104 on both sides of the opening 105 and the silicon substrate 100 at the bottom of the opening 105 are simultaneously etched, consuming the second silicon nitride layers 104 on both sides of the opening 105 while forming a shallow trench in the silicon substrate 100, thereby reducing the aspect ratio of the shallow trench to be filled. Finally, silicon oxide is deposited in the shallow trench to form a shallow trench isolation structure. The method for fabricating a shallow trench isolation structure on a silicon substrate provided in this application can solve the problem of voids easily forming in shallow trench isolation structures.
[0046] For details, please refer to Figure 1 As shown, in one embodiment of the present invention, a silicon substrate 100 is first provided. The silicon substrate 100 can be any applicable semiconductor material, such as sapphire, silicon wafer, silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), or silicon germanium (GeSi) substrates. It also includes a stacked structure composed of these semiconductors, or silicon-on-insulator, silicon-on-insulator stacked, silicon-on-insulator stacked, silicon-on-insulator, and germanium-on-insulator, etc., which can be selected according to the fabrication requirements of the semiconductor device. In this embodiment, the silicon substrate 100 is, for example, a silicon wafer semiconductor substrate. The silicon substrate 100 can be an undoped substrate or a doped substrate, and the thickness of the silicon substrate 100 is not specifically limited, but is selected according to the fabrication requirements.
[0047] Please see Figure 1As shown, in one embodiment of the present invention, before depositing the first silicon nitride layer 102, a first silicon oxide layer 101 is first formed on the silicon substrate 100, and the formed first silicon oxide layer 101 covers the surface of the silicon substrate 100. The first silicon oxide layer 101 is, for example, a dense silicon oxide material, and the first silicon oxide layer 101 can be formed by any one of the following methods: dry oxidation, wet oxidation, or in-situ water vapor growth. The first silicon oxide layer 101 is disposed between the subsequently formed first silicon nitride layer 102 and the silicon substrate 100, and can serve as a buffer layer to improve the stress between the silicon substrate 100 and the subsequently formed first silicon nitride layer 102. In other embodiments, the first silicon nitride layer 102 can also be formed directly on the silicon substrate 100.
[0048] Please see Figure 1 As shown, in one embodiment of the present invention, after forming a first silicon oxide layer 101, a first silicon nitride layer 102 is formed on the first silicon oxide layer 101, and the first silicon nitride layer 102 covers the first silicon oxide layer 101. The first silicon nitride layer 102 is, for example, a silicon nitride layer, and can be formed using methods such as chemical vapor deposition (CVD) or low-pressure chemical vapor deposition (LPCVD). It should be noted that the first silicon nitride layer 102 formed in this application is used as the floating gate of the non-volatile flash memory in subsequent processes. Therefore, during the etching of the silicon substrate 100 to form shallow trenches, it is necessary to protect the first silicon nitride layer 102 from being etched.
[0049] Please see Figures 1 to 2 As shown, in one embodiment of the present invention, after forming a first silicon nitride layer 102, a second silicon oxide layer 103 is formed on the first silicon nitride layer 102, and the second silicon oxide layer 103 covers the first silicon nitride layer 102. The second silicon oxide layer 103 is, for example, a silicon oxide layer, and can be formed on the first silicon nitride layer 102 using deposition methods such as atomic layer deposition (ALD) or chemical vapor deposition as the second silicon oxide layer 103. In this embodiment, to avoid the thickness of the first silicon nitride layer 102 being affected by the shallow trench etching process, a second silicon oxide layer 103 is formed on the first silicon nitride layer 102, which protects the first silicon nitride layer 102 from being affected during the shallow trench etching process. Furthermore, to avoid the thickness of the second silicon oxide layer 103 affecting etching and dielectric deposition, the thickness of the second silicon oxide layer 103 is set to, for example... For example,
[0050] Please see Figures 2 to 3As shown, in one embodiment of the present invention, after forming the second silicon oxide layer 103, a second silicon nitride layer 104 is formed on the second silicon oxide layer 103, and the second silicon nitride layer 104 covers the second silicon oxide layer 103. The second silicon nitride layer 104 can be formed using deposition methods such as chemical vapor deposition or low-pressure chemical vapor deposition. In this embodiment, the preset thickness ratio range of the second silicon nitride layer 104 and the second silicon oxide layer 103 is, for example, 1:15 to 1:25. Therefore, the thickness of the second silicon nitride layer 104 is, for example, [missing information]. Setting a thicker second silicon nitride layer 104 can leave sufficient margin for subsequent synchronous etching of shallow trenches and the second silicon nitride layer 104, so as to ensure that the depth of shallow trenches of different depths formed later meets the requirements.
[0051] Please see Figures 3 to 4 As shown, in one embodiment of the present invention, after forming the second silicon nitride layer 104, the second silicon nitride layer 104, the second silicon oxide layer 103, the first silicon nitride layer 102, and the first silicon oxide layer 101 are sequentially etched according to the first mask pattern to form an opening 105 in contact with the surface of the silicon substrate 100. The remaining second silicon nitride layer 104, the second silicon oxide layer 103, the first silicon nitride layer 102, and the first silicon oxide layer 101 form a mask layer of the first mask pattern. The etching gas mainly includes a mixture of gases containing fluorine, chlorine, oxygen, helium, etc., as well as inert gases (e.g., hydrogen (Ar) and neon (Ne)). When etching each semiconductor layer, the gas ratio can be adjusted according to the material of the semiconductor layer. In this embodiment, since the trench isolation structure widths provided on the storage region and the logic region of the non-volatile flash memory are different, the widths of the openings 105 formed in the storage region and the logic region are different. When forming the openings 105, the openings 105 in the storage region and the logic region can be formed step by step. For example, a photoresist layer is first used to cover the logic region, forming an opening 105 of one width in the memory region. Then, a photoresist layer is used to cover the memory region, forming an opening 105 of another width in the logic region. Each opening 105 defines the location of a shallow trench isolation structure; the opening 105 in the memory region defines the location of a first shallow trench isolation structure 1091, and the opening 105 in the logic region defines the location of a second shallow trench isolation structure 1092.
[0052] Please see Figure 4 As shown, in one embodiment of the present invention, the formed opening 105 is in contact with the surface of the silicon substrate 100. In the actual etching process, a small amount of over-etching can be performed on the silicon substrate 100 to ensure that the opening 105 is in contact with the surface of the silicon substrate 100.
[0053] Please see Figures 4 to 8As shown, in one embodiment of the present invention, after the opening 105 is formed, the second silicon nitride layer 104 on both sides of the opening 105 and the silicon substrate 100 at the bottom of the opening 105 are simultaneously etched, and the second silicon nitride layer 104 on both sides of the opening 105 is consumed while forming a shallow trench in the silicon substrate 100.
[0054] Please see Figures 4 to 8 As shown, in one embodiment of the present invention, the shallow trench includes a first shallow trench 1071 and a second shallow trench 1072. The first shallow trench 1071 is located in the storage region of the non-volatile flash memory, and the second shallow trench 1072 is located in the logic region of the non-volatile flash memory. A second mask pattern can be used for photolithography and etching processes. First, the silicon substrate 100 of the non-volatile flash memory storage region is etched to form the first shallow trench 1071. Then, a third mask pattern is used for photolithography and etching processes to etch the silicon substrate 100 of the non-volatile flash memory logic region to form the second shallow trench 1072. Before simultaneously etching the second silicon nitride layers 104 on both sides of the opening 105 and the silicon substrate 100 at the bottom of the opening 105, a linear barrier layer is formed on the inner wall of the opening 105 to protect the first silicon nitride layer 102 on the sidewall of the opening 105 from damage.
[0055] Please see Figures 5 to 6 As shown, in one embodiment of the present invention, before forming the first shallow trench 1071 in the storage region, a first barrier layer 106 is first formed on the inner wall of the opening 105 to ensure that the first silicon nitride layer 102 is not damaged during etching. Specifically, after thinning the second silicon nitride layer 104, the first barrier layer 106 can be formed using hydrothermal oxidation (HTO), in-situ vapor deposition, or other deposition methods. Forming the first barrier layer 106 can repair the damage to the silicon substrate 100 during etching of the opening 105. Simultaneously, the first barrier layer 106 covers the inner wall of the opening 105 in both the storage and logic regions, as well as the thinned second silicon nitride layer 104. That is, the first barrier layer 106 covers the silicon substrate 100 at the bottom wall of the opening 105 in the storage area and the logic area, the first silicon oxide layer 101, the first silicon nitride layer 102, the second silicon oxide layer 103 and the second silicon nitride layer 104 at the side wall of the opening 105, and can protect the first silicon nitride layer 102 from damage during the etching of the first shallow trench 1071.
[0056] Please see Figures 5 to 6As shown, in one embodiment of the present invention, after forming the first barrier layer 106, the logic region is covered with a second mask pattern, and the second silicon nitride layer 104 on both sides of the opening 105 in the storage region and the silicon substrate 100 at the bottom of the opening 105 are simultaneously etched with the second mask pattern, so as to form a first shallow trench 1071 in the silicon substrate 100 at the bottom of the opening 105 in the storage region while simultaneously etching the second silicon nitride layer 104 on both sides of the opening 105 in the storage region.
[0057] Please combine Figure 5 and Figure 6 As shown, in some embodiments, since the depth of the first shallow trench 1071 is less than the depth of the second shallow trench 1072, a portion of the thickness of the second silicon nitride layer 104 remains on the second silicon oxide layer 103 on both sides of the opening 105 in the storage region when the first shallow trench 1071 is formed. In other embodiments, when the first shallow trench 1071 is formed, the entire thickness of the second silicon nitride layer 104 on both sides of the opening 105 in the storage region can be etched away simultaneously.
[0058] Please see Figures 5 to 6 As shown, in one embodiment of the present invention, a dry etching method is used to simultaneously etch the second silicon nitride layer 104 on both sides of the opening 105 and the silicon substrate 100 at the bottom of the opening 105. The dry etching gas includes octafluorocyclobutane (C4F8) and sulfur hexafluoride (SF6), and the flow ratio of octafluorocyclobutane (C4F8) and sulfur hexafluoride (SF6) is in the range of 10:1 to 1:1. To adjust the flow ratio of the dry etching gas, trifluoromethane (CHF3) and hexafluoro-2-butyne (C4F6) can also be added to the dry etching gas. The selective etching ratio of the second silicon nitride layer 104 and the silicon substrate 100 is in the range of 1:70 to 1:90. During the process of simultaneously etching the second silicon nitride layer 104 on both sides of the opening 105 and the silicon substrate 100 at the bottom of the opening 105, the first barrier layer 106 on the top of the second silicon nitride layer 104 and the first barrier layer 106 on the bottom wall of the opening 105 are also etched away, and the first barrier layer 106 on the side wall of the opening 105 is also thinned during the etching process.
[0059] Please see Figures 6 to 7 As shown, in one embodiment of the present invention, after the first shallow trench 1071 is formed, the first shallow trench 1071 and the first barrier layer 106 on the sidewall of the opening 105 are cleaned to remove etching residue, particulate contamination and the first barrier layer 106 on the sidewall of the opening 105, so as to ensure good adhesion and electrical properties of the subsequent filling material.
[0060] Please see Figures 7 to 8As shown, in one embodiment of the present invention, when forming the second shallow trench 1072 in the storage region, a second barrier layer 108 is formed on the inner wall of the opening 105 to ensure that the first silicon nitride layer 102 is not damaged during etching. Specifically, after forming the first shallow trench 1071, the second barrier layer 108 can be formed using thermal oxidation, in-situ water vapor growth, or other deposition methods. Forming the second barrier layer 108 can repair the damage to the silicon substrate 100 caused by etching the first shallow trench 1071. At the same time, the second barrier layer 108 covers the inner wall of the opening 105 in the storage region and the logic region, the inner wall of the first shallow trench 1071 and the second silicon oxide layer 103 in the storage region, and the thinned second silicon nitride layer 104 in the logic region. Specifically, the first barrier layer 106 covers the silicon substrate 100 exposed by the first shallow trench 1071 in the storage region, the first silicon oxide layer 101, the first silicon nitride layer 102, and the second silicon oxide layer 103 on the sidewall of the opening 105, and simultaneously covers the silicon substrate 100 on the bottom wall of the opening 105 in the logic region, the first silicon oxide layer 101, the first silicon nitride layer 102, the second silicon oxide layer 103, and the second silicon nitride layer 104. This protects the first shallow trench 1071 and the first silicon nitride layer 102 from damage during the etching of the second shallow trench 1072.
[0061] Please see Figures 7 to 8 As shown, in one embodiment of the present invention, after the second barrier layer 108 is formed, the storage area is covered with a third mask pattern, and the second silicon nitride layer 104 on both sides of the opening 105 in the logic area and the silicon substrate 100 at the bottom of the opening 105 are simultaneously etched with the third mask pattern, so as to form a second shallow trench 1072 in the silicon substrate 100 at the bottom of the opening 105 in the logic area while simultaneously etching the second silicon nitride layer 104 on both sides of the opening 105 in the logic area.
[0062] Please combine Figure 7 and Figure 8 As shown, in some embodiments, when forming the second shallow trench 1072, the entire thickness of the second silicon nitride layer 104 on both sides of the opening 105 in the logic region can be etched away simultaneously. In other embodiments, when forming the second shallow trench 1072, a portion of the thickness of the second silicon oxide layer 103 on both sides of the opening 105 in the logic region can be etched away. In still other embodiments, when forming the second shallow trench 1072, a portion of the thickness of the second silicon nitride layer 104 remains on the second silicon oxide layer 103 on both sides of the opening 105 in the logic region.
[0063] Please combine Figures 5 to 8As shown, in one embodiment of the present invention, after forming the first shallow trench 1071 and the second shallow trench 1072, the second silicon nitride layer 104 on the storage region is completely etched away, the second silicon nitride layer 104 on the logic region is completely etched away, and a portion of the thickness of the second silicon oxide layer 103 is etched away. In other embodiments of the present invention, it is only necessary to ensure that the second silicon oxide layer 103 on the storage region and the logic region is not completely etched away; a portion of the thickness of the second silicon oxide layer 103 can be retained, or a portion of the thickness of the second silicon oxide layer 103 and a portion of the thickness of the second silicon nitride layer 104 can be retained.
[0064] Please see Figures 7 to 8 As shown, in one embodiment of the present invention, a dry etching method is used to simultaneously etch the second silicon nitride layer 104 on both sides of the opening 105 and the silicon substrate 100 at the bottom of the opening 105. The dry etching gas includes octafluorocyclobutane (C4F8) and sulfur hexafluoride (SF6), and the flow ratio of octafluorocyclobutane (C4F8) and sulfur hexafluoride (SF6) is in the range of 10:1 to 1:1. To adjust the flow ratio of the dry etching gas, trifluoromethane (CHF3) and hexafluoro-2-butyne (C4F6) can also be added to the dry etching gas. The selective etching ratio of the second silicon nitride layer 104 and the silicon substrate 100 is in the range of 1:70 to 1:90. During the process of simultaneously etching the second silicon nitride layer 104 on both sides of the opening 105 and the silicon substrate 100 at the bottom of the opening 105, the second barrier layer 108 on the top of the second silicon nitride layer 104 and the second barrier layer 108 on the bottom wall of the opening 105 are also etched away, and the second barrier layer 108 on the side wall of the opening 105 is also thinned during the etching process.
[0065] Please see Figures 8 to 9 As shown, in one embodiment of the present invention, after forming the second shallow trench 1072, the remaining second barrier layer 108 is removed first, followed by the removal of the remaining second silicon oxide layer 103 and second silicon nitride layer 104 on the first silicon nitride layer 102. The remaining second barrier layer 108, second silicon oxide layer 103, and second silicon nitride layer 104 can be removed using wet etching. The solution used for wet etching of the second silicon nitride layer 104 is, for example, hot phosphoric acid. The solution used for wet etching of the second barrier layer 108 and second silicon oxide layer 1072 is, for example, BOE (Buffered Oxide Etch) solution. BOE is a mixed solution of hydrofluoric acid (HF) and ammonium fluoride (NH4F). Because the BOE solution has a relatively high selectivity for etching the oxide and nitride layers, removing the second silicon oxide layer 103 and the second barrier layer 108 has almost no effect on the first silicon nitride layer 102, and therefore will not affect the thickness of the subsequently formed floating gate.
[0066] Please see Figures 4 to 9As shown, in one embodiment of the present invention, for ease of description, the recess formed by etching the silicon substrate 100 in the storage region is defined as the first shallow trench 1071, and the recess formed by etching the silicon substrate 100 in the logic region is defined as the second shallow trench 1072. In this embodiment, the depth of the first shallow trench 1071 to be filled is equal to the sum of the depth of the first shallow trench 1071 in the substrate 100, the thickness of the first silicon oxide layer 101, and the thickness of the first silicon nitride layer 102, and the depth of the second shallow trench 1072 to be filled is equal to the sum of the depth of the second shallow trench 1072 in the substrate 100, the thickness of the first silicon oxide layer 101, and the thickness of the first silicon nitride layer 102. In this application, retaining the second silicon oxide layer 103 before forming the shallow trench ensures that the etching process of the shallow trench does not affect the first silicon nitride layer 102, and thus does not affect the thickness of the floating gate of the subsequent non-volatile flash memory. Removing the second silicon nitride layer 104 and the second silicon oxide layer 103 before depositing the medium in the shallow trenches can reduce the depth of the first shallow trench 1071 and the second shallow trench 1072 to be filled, thereby reducing the aspect ratio of the shallow trenches to be filled. Therefore, when forming the shallow trench isolation structure subsequently, the probability of void formation can be greatly reduced, improving the quality of the formed shallow trench isolation structure.
[0067] Please see Figure 9 and Figure 10 As shown, in one embodiment of the present invention, after forming the first shallow trench 1071 and the second shallow trench 1072, silicon oxide 107 is deposited in the shallow trenches and on top of the shallow trenches until the silicon oxide 107 covers the surface of the silicon substrate 100. The present invention does not limit the deposition method of silicon oxide 107. For example, silicon oxide 107 can be deposited by a high aspect ratio process (HARP), that is, by using a thermochemical reaction of ozone and tetraethyl orthosilicate (TEOS) to form the oxide.
[0068] Please see Figure 9 and Figure 10 As shown, in one embodiment of the present invention, after depositing silicon oxide 107, a high-temperature tempering process can be performed, for example, annealing the silicon oxide 107 at 800–1200°C, to increase the density and stress condition of the silicon oxide 107. In this embodiment, the silicon oxide 107 is, for example, silicon oxide with high adaptability to grinding; in other embodiments, the silicon oxide 107 can also be an insulating material such as fluorosilicone glass.
[0069] Please see Figure 9 and Figure 10As shown, in one embodiment of the present invention, silicon oxide 107 in the first shallow trench 1071 forms a first shallow trench isolation structure 1091, and silicon oxide 107 in the second shallow trench 1072 forms a second shallow trench isolation structure 1092. The first shallow trench isolation structure 1091 is located in the storage region of the non-volatile flash memory, and the second shallow trench 1072 is located in the logic region of the non-volatile flash memory.
[0070] Please see Figure 9 and Figure 10 As shown, in one embodiment of the present invention, after etching away the linear oxide layer 104 in the first shallow trench 1071 and the second shallow trench 1072, a pad silicon oxide layer (not shown in the figure) can be formed in the shallow trench first, and then silicon oxide 107 is deposited in the shallow trench and on the top of the shallow trench. In this embodiment, when forming the pad silicon oxide layer, for example, under conditions of 500-650°C and a pressure of 10-20T, oxygen (O2) mixed with a small amount of hydrogen (H2) is introduced. The hydrogen and oxygen form a mixture of water vapor, OH radicals, O radicals, etc. on the silicon surface in the shallow trench, which reacts with the surface of the silicon substrate 100 on the inner wall of the shallow trench to produce silicon oxide, thereby forming a linear pad silicon oxide layer. The pad silicon oxide layer can repair the damage to the surface of the shallow trench edge during etching, and improve the electrical properties and yield of the device.
[0071] Please see Figure 10 As shown, in one embodiment of the present invention, after forming the first shallow trench isolation structure 1091 and the second shallow trench isolation structure 1092, in subsequent processes, the silicon oxide 107 above the first silicon nitride layer 102 can be removed first, the first silicon nitride layer 102 forms a floating gate, and then ion implantation is performed to form a non-volatile flash memory.
[0072] In summary, the present invention provides a method for fabricating a shallow trench isolation structure for a memory chip and the shallow trench isolation structure thereof. The method for fabricating the shallow trench isolation structure for the memory chip includes: providing a silicon substrate; sequentially forming a first silicon oxide layer and a first silicon nitride layer on the silicon substrate; forming a second silicon oxide layer and a second silicon nitride layer with a predetermined thickness ratio on the first silicon nitride layer; etching the second silicon nitride layer, the second silicon oxide layer, the second silicon nitride layer, and the first oxide layer with a first mask pattern to form a mask layer of the first mask pattern; and etching the mask layer sidewalls and its surface of the first mask pattern onto the substrate surface. A first barrier layer of predetermined thickness is formed on the surface. A second mask pattern is used to perform photolithography and etching processes on the silicon substrate of the storage region, forming a first shallow trench while simultaneously consuming the second silicon nitride layer on the storage region. A second barrier layer is formed on the surface of the silicon substrate where the first shallow trench is formed. A third mask pattern is used to perform photolithography and etching processes on the silicon substrate of the logic region, forming a second shallow trench while simultaneously consuming the second silicon nitride layer on the logic region. The second barrier layer and the second silicon oxide layer are wet-etched. Silicon oxide is filled into the first and second shallow trenches to form a shallow trench isolation structure. An unexpected effect is that, to ensure the height of the floating gate in the formed non-volatile flash memory is within a set size, a second silicon oxide layer and a hard mask layer with an adjustable thickness ratio are set on the first silicon nitride layer. During the formation of the first and second shallow trenches, the second silicon nitride layer protects the first silicon nitride layer. The second silicon nitride layer is consumed during the etching process to form the first / second shallow trenches. After fabricating the first and second shallow trenches, the second silicon oxide layer is removed, and then the first and second shallow trenches are filled with silicon oxide. Compared to the existing shallow trench isolation structure fabrication process, the first silicon nitride layer does not need to be made thicker. The thickness of the first silicon nitride layer is also more uniform due to the protection of the second oxide and silicon nitride layers, preventing unexpected variations in the thickness of the floating gate during subsequent memory chip manufacturing processes. Reducing the thickness of the first nitride layer also lowers the aspect ratio of the shallow trenches when filling with silicon oxide, thus reducing the probability of voids in the shallow trench isolation structure. The shallow trench isolation structure fabrication method for memory chips provided by this invention can improve the quality of the formed shallow trench isolation structure, further contributing to improved yield and reliability of memory chips.
[0073] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A method for fabricating a shallow trench isolation structure for a memory chip, the memory chip comprising a storage region and a logic region, characterized in that, Includes the following steps: A silicon substrate is provided, on which a first silicon oxide layer and a first silicon nitride layer are sequentially formed; A second silicon oxide layer and a second silicon nitride layer with a predetermined thickness ratio are formed on the first silicon nitride layer; A mask layer with a first mask pattern is formed by etching the second silicon nitride layer, the second silicon oxide layer, the first silicon nitride layer, and the first silicon oxide layer with a first mask pattern. A first barrier layer is formed on the sidewalls and surface of the mask layer of the first mask pattern and on the surface of the substrate; The silicon substrate of the memory region is etched using a photolithography and etching process with a second mask pattern to form a first shallow trench while consuming the second silicon nitride layer on the memory region. A second barrier layer is formed on the surface of the silicon substrate on which the first shallow trench is formed; The silicon substrate of the logic region is etched using a photolithography and etching process with a third mask pattern to form a second shallow trench while consuming the second silicon nitride layer on the logic region. Wet etching is performed on the second barrier layer and the second silicon oxide layer; Silicon oxide is filled into the first shallow trench and the second shallow trench to form a shallow trench isolation structure.
2. The method for fabricating the shallow trench isolation structure of the memory chip according to claim 1, characterized in that, The preset thickness ratio of the second silicon oxide layer and the second silicon nitride layer is 1:15 to 1:
25.
3. The method for fabricating the shallow trench isolation structure of the memory chip according to claim 1, characterized in that, The second silicon oxide layer is fabricated using atomic layer deposition (ALD) technology.
4. The method for fabricating the shallow trench isolation structure of the memory chip according to claim 1, characterized in that, When the silicon substrate and the second silicon nitride layer are etched using a dry etching method, the selective etching ratio between the second silicon nitride layer and the silicon substrate is in the range of 1:70 to 1:
90.
5. The method for fabricating the shallow trench isolation structure of the memory chip according to claim 1, characterized in that, The first barrier layer and the second barrier layer are silicon oxide layers.
6. The method for fabricating the shallow trench isolation structure of the memory chip according to claim 1, characterized in that, The silicon substrate and the second silicon nitride layer are etched using a dry etching method, and the gases used in the dry etching include octafluorocyclobutane and sulfur hexafluoride, with the flow ratio of octafluorocyclobutane and sulfur hexafluoride ranging from 10:1 to 1:
1.
7. The method for fabricating the shallow trench isolation structure of the memory chip according to claim 1, characterized in that, The gases used in the dry etching process also include trifluoromethane and hexafluoro-2-butyne.
8. The method for fabricating the shallow trench isolation structure of the memory chip according to claim 1, characterized in that, The first barrier layer and the second barrier layer cover the sidewalls of the first silicon nitride layer.
9. The method for fabricating the shallow trench isolation structure of the memory chip according to claim 1, characterized in that, Silicon oxide is deposited in the first and second shallow trenches using a high aspect ratio process to form a shallow trench isolation structure.
10. A shallow trench isolation structure, characterized in that, The shallow trench isolation structure is formed using the fabrication method of the shallow trench isolation structure of the memory chip as described in any one of claims 1 to 9.