Manufacturing method of shallow trench isolation structure of memory chip and shallow trench isolation structure

Abstract

The invention discloses a manufacturing method of a shallow trench isolation structure of a memory chip and the shallow trench isolation structure, and belongs to the technical field of semiconductors, the manufacturing method of the shallow trench isolation structure of the memory chip comprises the following steps: providing a silicon substrate, forming a shallow trench on the silicon substrate, a hard mask layer with a preset thickness formed by sequentially stacking a silicon nitride layer and a silicon oxide layer is formed on the surface of the silicon substrate between the shallow trenches, and first silicon oxide layers are formed on the surfaces of the shallow trenches and the side walls of the hard mask layer; filling a first dielectric layer in the shallow trench; performing wet processing on the silicon oxide layer in the hard mask layer and removing the first dielectric layer; removing the first silicon oxide layer, and filling a second silicon oxide layer in the shallow trench until the second silicon oxide layer is higher than the surface of the silicon nitride; and forming a shallow trench isolation structure. According to the manufacturing method of the shallow trench isolation structure of the memory chip and the shallow trench isolation structure disclosed by the invention, the quality of the formed shallow trench isolation structure can be improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a manufacturing method of a shallow trench isolation structure of a memory chip and the shallow trench isolation structure. BACKGROUND

[0002] In a non-volatile flash memory, a storage area and a logic area are provided. The storage area of the non-volatile flash memory is used for storing data, and the logic area of the non-volatile flash memory is used for implementing execution of instructions. In the storage area and the logic area, a shallow trench isolation structure is provided.

[0003] In the formation of the shallow trench isolation structure in the non-volatile flash memory, a hard mask layer is first formed on a substrate, and a shallow trench is etched in the substrate, then a medium is filled in the shallow trench, and finally the surface of a wafer is planarized. In the formation of the hard mask layer on the substrate, a silicon nitride layer is first formed, and since the thickness of the silicon nitride layer is related to the thickness of a floating gate of a memory device in a subsequent storage area, in order to ensure that the silicon nitride layer is not affected in the etching process, a silicon oxide layer is formed on the silicon nitride layer. Since the hard mask layer formed on the substrate includes the silicon nitride layer and the silicon oxide layer, when the shallow trench is filled, the shallow trench has a relatively high aspect ratio compared with an isolation trench of other products, which easily leads to the occurrence of voids in the filled medium in the shallow trench. Further, the semiconductor device formed has problems such as leakage, stress or thermal stability, which affect the quality of the semiconductor device. SUMMARY

[0004] The present application aims to provide a manufacturing method of a shallow trench isolation structure of a memory chip and the shallow trench isolation structure, which can solve the problem that the shallow trench isolation structure is prone to voids.

[0005] To solve the above technical problems, the present application is implemented by the following technical scheme:

[0006] The present application provides a manufacturing method of a shallow trench isolation structure of a memory chip, the memory chip including a storage area and a logic area, and comprising the following steps:

[0007] A silicon substrate is provided, shallow trenches of the storage area and shallow trenches of the logic area are formed on the silicon substrate, a hard mask layer with a preset thickness of a silicon nitride layer and a silicon oxide layer stacked in sequence is formed on the surface of the silicon substrate between the shallow trenches, a first silicon oxide layer is formed on the surface of the shallow trench of the storage area and the sidewall and surface of the hard mask layer, and the sidewall of the hard mask layer of the logic area is provided with the first silicon oxide layer;

[0008] A first medium layer is filled in the shallow trench with the hard mask layer and the first silicon oxide layer and protrudes from the hard mask layer by a preset thickness, and a flat surface of the first medium layer is formed.

[0009] etching back the first dielectric layer to a surface of the first dielectric layer below the surface of the hard mask layer by a preset distance;

[0010] removing the silicon oxide layer in the hard mask layer by wet etching and then removing the first dielectric layer;

[0011] filling a second silicon oxide layer in the shallow trench above the surface of the silicon nitride after removing the first silicon oxide layer; and

[0012] chemically mechanically polishing the second silicon oxide layer to the surface of the silicon nitride to form a shallow trench isolation structure.

[0013] In an embodiment of the present application, the first dielectric layer is an organic planarization layer.

[0014] In an embodiment of the present application, the etching solution for etching away part of the thickness of the hard mask layer by wet etching is a BOE solution.

[0015] In an embodiment of the present application, the ratio of BOE to DIW in the BOE solution ranges from 1:10 to 1:300.

[0016] In an embodiment of the present application, the etching selectivity ratio of the BOE solution to the oxide layer and the nitride layer ranges from 1:50 to 1:200.

[0017] In an embodiment of the present application, the SPM solution is used to remove the organic planarization layer in the shallow trench.

[0018] In an embodiment of the present application, the ratio of H2SO4 to H2O2 in the SPM solution ranges from 1:2 to 1:10.

[0019] In an embodiment of the present application, the second silicon oxide layer is filled in the shallow trench by using a high aspect ratio process to form a shallow trench isolation structure.

[0020] In an embodiment of the present application, between removing the first silicon oxide layer and filling the second silicon oxide layer, a pad silicon oxide layer is formed on the bottom and sidewall of the shallow trench.

[0021] The present application also provides a shallow trench isolation structure formed by using the method for forming a shallow trench isolation structure of any one of the above storage chips.

[0022] In summary, the application provides a manufacturing method of a shallow trench isolation structure of a memory chip and the shallow trench isolation structure, and the unexpected effect is that: in order to ensure that the height of the floating gate in the formed nonvolatile flash memory is within the set size, the hard mask layer is set as a stacked structure of a silicon nitride layer and a silicon oxide layer with a preset thickness ratio, and the silicon oxide layer is arranged on the surface of the silicon nitride, so as to protect the silicon nitride layer in the process of shallow trench etching and make the thickness of the silicon nitride layer within the control range. In the process of manufacturing the memory chip, the thickness of the silicon nitride as the hard mask layer directly affects the thickness and uniformity of the subsequently manufactured floating gate, and the fluctuation range of the thickness of the floating gate directly affects the yield and stability of the memory chip. After the shallow trench is formed, the organic planarization layer with good fluidity is filled in the trench before the second silicon oxide layer is filled, so as to protect the trench in the subsequent process of etching off the silicon oxide layer on the silicon nitride layer by wet etching. The first silicon oxide layer on the sidewall of the trench with the hard mask layer can isolate the silicon nitride layer in the hard mask layer from the organic planarization medium layer, so as to avoid the influence of the organic planarization medium on the silicon nitride. Since the etching selectivity ratio between the silicon oxide and the silicon nitride is about 80:1 when the buffered hydrofluoric acid solution is used for wet etching of the silicon oxide layer, the silicon nitride layer is almost not affected when the silicon oxide layer is etched. When the second silicon oxide layer is filled in the shallow trench after the silicon oxide layer is removed, the aspect ratio of the shallow trench to be filled can be reduced, and then the probability of forming a cavity when the shallow trench is filled with an insulating medium subsequently can be reduced. Therefore, by using the manufacturing method of the shallow trench isolation structure of the memory chip and the shallow trench isolation structure, the problem that the void is easily formed when the shallow trench isolation structure is formed can be solved, and the quality of the shallow trench isolation structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0024] Figure 1 The structural diagram of forming the hard mask layer and the shallow trench in an embodiment.

[0025] Figure 2 The structural diagram of forming the first medium layer in an embodiment.

[0026] Figure 3 The structural diagram of the etched first medium layer in an embodiment.

[0027] Figure 4 The structural diagram of etching off part of the thickness of the hard mask layer in an embodiment.

[0028] Figure 5A structure diagram for etching away the first silicon oxide layer in an embodiment.

[0029] Figure 6 A structure diagram for forming a shallow trench isolation structure in an embodiment.

[0030] Label explanation:

[0031] 10, hard mask layer; 101, pad oxide layer; 102, silicon nitride layer; 103, silicon oxide layer; 1031, notch; 104, first silicon oxide layer; 1051, first shallow trench; 1052, second shallow trench; 106, first dielectric layer; 107, second silicon oxide layer; 1071, first shallow trench isolation structure; 1072, second shallow trench isolation structure. DETAILED DESCRIPTION

[0032] The embodiments of the present application will be described in detail with specific reference felt to the drawings. Those skilled in the art can easily understand other advantages and effects of the present application from the description of the present application. The present application can also be implemented or applied in other different embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0033] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The shape, number and ratio of the components when actually implemented can be arbitrarily changed, and the layout of the components can be more complex.

[0034] In the present application, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like appear, the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only for description and differentiation purposes, and cannot be understood as indicating or implying relative importance.

[0035] In a semiconductor integrated device, a plurality of semiconductor devices can be formed on the same substrate, and when the semiconductor devices are formed, a shallow trench isolation structure can be provided between active regions of adjacent semiconductor devices or between different active regions of the same semiconductor device to isolate the different active regions.

[0036] Please refer to Figures 1 to 6As shown in the embodiment of the present application, a semiconductor memory chip, such as a non-volatile flash memory (NOR Flash), is provided with a storage area and a logic area. The storage area of the non-volatile flash memory is provided with a plurality of memory devices for storing data. The logic area of the non-volatile flash memory is provided with semiconductor devices, such as a high voltage N-type metal-oxide-semiconductor (HV NMOS), a high voltage positive channel metal-oxide-semiconductor (HV PMOS), a low voltage N-type metal-oxide-semiconductor (LV NMOS), or a low voltage positive channel metal-oxide-semiconductor (LV PMOS), for executing instructions. The storage area of the non-volatile flash memory is provided with a first shallow trench isolation structure 1071 for isolating active regions in the storage area. The logic area of the non-volatile flash memory is provided with a second shallow trench isolation structure 1072 for isolating active regions in the logic area. The depth of the first shallow trench isolation structure 1071 is less than the depth of the second shallow trench isolation structure 1072.

[0037] It should be noted that the present application does not limit the number and type of the shallow trench isolation structures. In other embodiments, the semiconductor integrated device can also be provided with a third shallow trench isolation structure, a fourth shallow trench isolation structure, or a fifth shallow trench isolation structure, etc. with different depths.

[0038] Please refer to Figures 1 to 6 As shown in the embodiment of the present application, when forming a non-volatile flash memory using the method for manufacturing a shallow trench isolation structure of a memory chip provided by the present application, a hard mask layer 10 is first formed on a substrate 100, and the hard mask layer 10 and the substrate 100 are etched in sequence to form a shallow trench in the substrate 100. Then, a portion of the hard mask layer 10 is etched to reduce the aspect ratio of the shallow trench to be filled. Finally, a second silicon oxide layer 107 is deposited in the shallow trench to form a shallow trench isolation structure. The method for manufacturing a shallow trench isolation structure of a memory chip provided by the present application can solve the problem of voids in the shallow trench isolation structure.

[0039] Specifically, please refer to Figure 1As shown in the embodiment of the present application, a silicon substrate 100 is provided first, and the substrate 100 is any applicable semiconductor material, such as sapphire, silicon wafer, silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AIN), indium nitride (InN), or germanium silicon (GeSi), and the like, including a laminated structure of these semiconductors, or silicon on insulator, laminated silicon on insulator, laminated germanium silicon on insulator, germanium silicon on insulator, and germanium on insulator, and the like, which can be selected according to the requirements of the semiconductor device manufacturing.

[0040] Referring to Figure 1 As shown in the embodiment of the present application, a hard mask layer 10 is formed on the substrate 100. When the substrate 100 is etched later, the pattern on the photoresist is first transferred to the hard mask layer 10, and then the pattern is transferred to the substrate 100 through the patterned hard mask layer 10. In the present application, since the semiconductor integrated device to be manufactured is a non-volatile flash memory, the hard mask layer 10 formed on the substrate 100 includes a laminated pad oxide layer 101, silicon nitride layer 102, and silicon oxide layer 103, i.e., the pad oxide layer 101 is disposed on the substrate 100, the silicon nitride layer 102 is disposed on the pad oxide layer 101, and the silicon oxide layer 103 is disposed on the silicon nitride layer 102. In the present application, the hard mask layer 10 formed covers the storage area and the logic area of the non-volatile flash memory.

[0041] Referring to Figure 1 As shown in the embodiment of the present application, when the hard mask layer 10 is formed, the pad oxide layer 101 is first formed on the substrate 100, and the pad oxide layer 101 formed covers the storage area and the logic area of the non-volatile flash memory. The pad oxide layer 101 is, for example, a dense silicon oxide material, and the pad oxide layer 101 can be formed by any one of a dry oxygen oxidation method, a wet oxygen oxidation method, or an in-situ water vapor growth method. The pad oxide layer 101 is disposed between the silicon nitride layer 102 formed later and the substrate 100, and can serve as a buffer layer to improve the stress between the substrate 100 and the silicon nitride layer 102 formed later.

[0042] Referring to Figure 1As shown in the embodiment of the present application, after the pad oxide layer 101 is formed, a silicon nitride layer 102 with a preset thickness is formed on the pad oxide layer 101, and the silicon nitride layer 102 covers the pad oxide layer 101. The silicon nitride layer 102 can be formed by using a low pressure chemical vapor deposition (LPCVD) method or the like. On one hand, the preset thickness of the silicon nitride layer 102 determines the thickness of the floating gate to be formed later. On the other hand, during the process of forming the shallow trench isolation structure later, the silicon nitride layer 102 serves as a mask to protect the substrate 100 from being damaged when the substrate 100 is etched.

[0043] Referring to Figure 1 As shown in the embodiment of the present application, after the silicon nitride layer 102 is formed, a silicon oxide layer 103 is formed on the silicon nitride layer 102, and the silicon oxide layer 103 covers the silicon nitride layer 102. The silicon oxide layer 103 can be formed on the silicon nitride layer 102 by using a thermal oxidation method or a chemical vapor deposition method. In the embodiment, the preset thickness of the silicon nitride layer 102 is critical to the thickness of the floating gate of each semiconductor device to be formed in the subsequent nonvolatile flash memory. In order to avoid the influence of the thickness of the silicon nitride layer 102 on the etching of the shallow trench, a silicon oxide layer 103 is further formed on the silicon nitride layer 102 to protect the silicon nitride layer 102 from being affected during the etching process of the shallow trench. Therefore, in the present application, the pad oxide layer 101, the silicon nitride layer 102 and the silicon oxide layer 103 form a complete hard mask layer 10.

[0044] Referring to Figure 1 As shown in the embodiment of the present application, after the hard mask layer 10 is formed, the hard mask layer 10 and the substrate 100 are etched to form a shallow trench on the substrate 100. In the embodiment, the shallow trench includes a first shallow trench 1051 and a second shallow trench 1052. The first shallow trench 1051 is located in the storage area of the nonvolatile flash memory, and the second shallow trench 1052 is located in the logic area of the nonvolatile flash memory. The substrate 100 in the storage area of the nonvolatile flash memory can be etched first to form the first shallow trench 1051, and then the substrate 100 in the logic area of the nonvolatile flash memory can be etched to form the second shallow trench 1052.

[0045] Referring to Figure 1As shown, in an embodiment of the present application, when forming the shallow trench, first, the first shallow trench 1051 is formed in the non-volatile flash memory storage region. Specifically, when forming the first shallow trench 1051, first, photoresist is coated on the silicon oxide layer 103 by using the spin coating method, and a photoresist pattern is formed by using the photolithography process such as exposure and development, which defines the position for isolating the first shallow trench 1051. Then, the photoresist pattern is transferred to the silicon oxide layer 103, the silicon nitride layer 102 and the pad oxide layer 101 by using the photoresist pattern as a mask to etch the silicon oxide layer 103, the silicon nitride layer 102 and the pad oxide layer 101. That is, an opening is formed in the silicon oxide layer 103, the silicon nitride layer 102 and the pad oxide layer 101 in the non-volatile flash memory storage region, and the opening in the silicon oxide layer 103, the silicon nitride layer 102 and the pad oxide layer 101 in the non-volatile flash memory storage region exposes the position of the first shallow trench 1051. In the process of etching the hard mask layer 10, the etching gas is a mixed gas including fluorine-containing gas, chlorine, oxygen, helium, etc., and inert gas (such as hydrogen Ar, neon Ne) etc. After the photoresist pattern is transferred to the hard mask layer 10, the photoresist pattern is removed by using the organic solvent (such as CLK-888) wet method or the photoresist pattern is removed by using the oxygen plasma ashing process. Then, the silicon oxide layer 103, the silicon nitride layer 102 and the pad oxide layer 101 are used as a mask to etch the substrate 100 in the storage region range by using the reactive ion etching or the plasma etching process, and the first shallow trench 1051 is formed.

[0046] Referring to Figure 1 As shown, in an embodiment of the present application, after the first shallow trench 1051 in the non-volatile flash memory storage region, the second shallow trench 1052 is formed in the non-volatile flash memory logic region. The forming method of the second shallow trench 1052 is the same as the forming method of the first shallow trench 1051. First, photoresist is coated on the silicon oxide layer 103, and a photoresist pattern is formed by using the photolithography process such as exposure and development, which defines the position for isolating the second shallow trench 1052. Then, the photoresist pattern is transferred to the silicon oxide layer 103, the silicon nitride layer 102 and the pad oxide layer 101, that is, an opening is formed in the silicon oxide layer 103, the silicon nitride layer 102 and the pad oxide layer 101 in the non-volatile flash memory logic region, and the opening in the silicon oxide layer 103, the silicon nitride layer 102 and the pad oxide layer 101 in the non-volatile flash memory logic region exposes the position of the second shallow trench 1052. Then, the silicon oxide layer 103, the silicon nitride layer 102 and the pad oxide layer 101 are used as a mask to etch the substrate 100 in the logic region range, and the second shallow trench 1052 is formed.

[0047] Referring to Figure 1As shown, in one embodiment of the present application, in the process of forming the second shallow trench 1052, after forming the opening in the silicon oxide layer 103, the silicon nitride layer 102 and the pad oxide layer 101 in the logic region of the non-volatile flash memory, the first silicon oxide layer 104 is formed on the first shallow trench 1051, the surface of the logic region and the bottom and side walls of the opening in the logic region. The first silicon oxide layer 104 protects the side walls of the first shallow trench 1051 from being damaged when etching the second shallow trench 1052. In addition, the first silicon oxide layer 104 also protects the side walls of the silicon nitride layer 102 and the silicon oxide layer 103 in the opening from being damaged when etching the second shallow trench 1052.

[0048] Referring to Figure 1 As shown, in one embodiment of the present application, when etching the substrate 100 in the logic region to form the second shallow trench 1052, the first silicon oxide layer 104 and part of the silicon oxide layer 103 on the hard mask layer 10 in the logic region are etched away, forming a gap 1031 on the logic region.

[0049] Referring to Figure 1 As shown, in one embodiment of the present application, for the convenience of description, the recess formed by etching the substrate 100 in the storage region is defined as the first shallow trench 1051, and the recess formed by etching the substrate 100 in the logic region is defined as the second shallow trench 1052.

[0050] In one embodiment of the present application, after forming the first shallow trench 1051 in the storage region of the non-volatile flash memory and the second shallow trench 1052 in the logic region of the non-volatile flash memory, the part of the silicon oxide in the hard mask layer 10 in the storage region and the logic region is removed before filling the first shallow trench 1051 and the second shallow trench 1052, reducing the aspect ratio of the filled shallow trench.

[0051] In particular, referring to Figures 1 to 2As shown, in an embodiment of the present application, the first shallow trench 1051 is formed in the storage area of the non-volatile flash memory, and the second shallow trench 1052 is formed in the logic area of the non-volatile flash memory. Then, the first dielectric layer 106 is deposited in the first shallow trench 1051 and the second shallow trench 1052. The first dielectric layer 106 covers the first shallow trench 1051 and the second shallow trench 1052, and is higher than the hard mask layer by a preset height, so as to protect the first shallow trench 1051 and the second shallow trench 1052 from being damaged in the etching process of the hard mask layer 10. Specifically, the first dielectric layer 106 is an organic planarization layer (OPL), and the OPL filled in the first shallow trench 1051 and the second shallow trench 1052 has good fluidity and can be used to fill the shallow trench with large depth-width ratio. The OPL can be specifically an acrylic resin or a polyimide. The first dielectric layer 106 can be formed by spin coating, chemical vapor deposition, plasma enhanced chemical vapor deposition (PECVD), evaporation or chemical solution deposition, which is not limited in the present application. The first silicon oxide layer 104 in the first shallow trench 1051 and the second shallow trench 1052 can better protect the sidewall of the silicon nitride in the hard mask layer 10, so as to avoid damage to the silicon nitride in the hard mask layer 10 when the OPL is used as the first dielectric layer 106.

[0052] Referring to Figures 2 to 3 As shown, in an embodiment of the present application, after the first dielectric layer 106 is formed, the first dielectric layer 106 higher than the surface of the hard mask layer 10 is removed. Specifically, the first dielectric layer 106 can be etched back by using a dry etching method such as reaction ion etching (RIE) or enhanced capacitance coupled plasma (ECCP), so as to etch away the first dielectric layer 106 higher than the surface of the hard mask layer 10, so that the first dielectric layer 106 is lower than the surface of the hard mask layer by a preset distance and is flush with the plane where the notch 1031 is located. At this time, the first dielectric layer 106 fills the first shallow trench 1051 and the second shallow trench 1052, so as to protect the first shallow trench 1051 and the second shallow trench 1052 from being damaged in the etching process of the hard mask layer 10. Meanwhile, the first dielectric layer 106 exposes the hard mask layer 10 and the first silicon oxide layer 104 between the first shallow trench 1051 and the first shallow trench 1051, the hard mask layer 10 and the first silicon oxide layer 104 between the first shallow trench 1051 and the second shallow trench 1052, and the hard mask layer 10 between the second shallow trench 1052 and the second shallow trench 1052, which facilitates the etching of the hard mask layer 10.

[0053] Referring to Figure 3And Figure 4 As shown in the figure, in an embodiment of the present application, after etching away the first dielectric layer 106 above the surface of the hard mask layer 10, the silicon oxide layer 103 in the hard mask layer 10 is etched away to achieve the purpose of etching part of the thickness of the hard mask layer 10. Specifically, the first silicon oxide layer 104 and the silicon oxide layer 103 between the first shallow trench 1051 and the first shallow trench 1051, the first silicon oxide layer 104 and the silicon oxide layer 103 between the first shallow trench 1051 and the second shallow trench 1052, and the silicon oxide layer 103 between the second shallow trench 1052 and the second shallow trench 1052 can be removed by wet etching. The solution for wet etching the silicon oxide layer 103 is, for example, a BOE (Buffered Oxide Etch) solution, and the ratio of BOE to DIW (Deionized Water) in the BOE solution ranges from 1:10 to 1:300. The etching selectivity ratio of the BOE solution to the silicon oxide layer 103 and the silicon nitride layer 102 ranges from 1:50 to 1:200, which is related to the thickness of the silicon oxide layer 103 and the silicon nitride layer 102. Among them, the BOE is a mixed solution of hydrofluoric acid (HF) and ammonium fluoride (NH4F). Since the etching selectivity ratio of the BOE solution to the silicon oxide layer 103 and the silicon nitride layer 102 ranges from 1:50 to 1:200, there is almost no impact on the silicon nitride layer 102 when the silicon oxide layer 103 is etched away, so there is also no impact on the thickness of the floating gate formed subsequently.

[0054] Please refer to Figure 3 And Figure 4 As shown in the figure, in an embodiment of the present application, etching part of the thickness of the hard mask layer 10 includes the silicon oxide layer 103 and the first silicon oxide layer 104 on top of the silicon oxide layer 103, and the silicon oxide layer 103 is completely removed, which reduces the aspect ratio of the first shallow trench and the second shallow trench to be filled, greatly reduces the probability of forming voids during the formation of the shallow trench isolation structure, and improves the quality of the formed shallow trench isolation structure. The silicon oxide layer 103 is retained during the formation of the shallow trench, and the silicon oxide layer 103 is etched away after the formation of the shallow trench, which can ensure that the etching process of the shallow trench has no impact on the silicon nitride layer 102, and thus has no impact on the thickness of the floating gate of the subsequent non-volatile flash memory. At the same time, during the subsequent deposition of the dielectric in the shallow trench, the aspect ratio of the shallow trench to be filled can be reduced, thereby reducing the probability of forming voids during the deposition of the dielectric.

[0055] Please refer to Figure 3 And Figure 4As shown, in one embodiment of the present invention, after etching away a portion of the thickness of the hard mask layer 10, i.e., etching away the silicon oxide layer 103, the first dielectric layer 106 within the first shallow trench 1051 and the second shallow trench 1052 is removed. Specifically, a wet etching method can be used to remove the first dielectric layer 106 within the first shallow trench 1051 and the second shallow trench 1052. The wet etching solution is determined based on the material used for the first dielectric layer 106. In this embodiment, an SPM (Sulfuric Acid / Peroxide Mix) solution can be used for wet etching to remove the first dielectric layer 106 within the shallow trenches, and the H2SO4:H2O2 ratio in the SPM solution is in the range of 1:2 to 1:10.

[0056] Please see Figure 4 and Figure 5 As shown, in one embodiment of the present invention, after etching away the first dielectric layer 106 in the first shallow trench 1051 and the second shallow trench 1052, the first silicon oxide layer 104 in the first shallow trench 1051 and the second shallow trench 1052 is removed. Specifically, a wet etching method can be used to remove the first silicon oxide layer 104 in the first shallow trench 1051 and the second shallow trench 1052. The solution for wet etching the first silicon oxide layer 104 is, for example, a mixed solution of hydrofluoric acid and ammonium fluoride, or a mixed solution of hydrofluoric acid and ethylene glycol.

[0057] Please see Figure 5 and Figure 6 As shown, in one embodiment of the present invention, after etching away the first silicon oxide layer 104 within the first shallow trench 1051 and the second shallow trench 1052, a second silicon oxide layer 107 is deposited within the shallow trenches and on top of the shallow trenches until the second silicon oxide layer 107 covers the surface of the substrate 100. The present invention does not limit the deposition method of the second silicon oxide layer 107; for example, the second silicon oxide layer 107 can be deposited using a high aspect ratio process (HARP), i.e., using a thermochemical reaction of ozone and tetraethyl orthosilicate (TEOS) to form an oxide.

[0058] Please see Figure 5 and Figure 6 As shown, in one embodiment of the present invention, after depositing the second silicon oxide layer 107, a high-temperature tempering process can be performed, for example, annealing the second silicon oxide layer 107 at 800–1200°C, to increase the density and stress condition of the second silicon oxide layer 107. In this embodiment, the second silicon oxide layer 107 is, for example, silicon oxide with high adaptability to grinding; in other embodiments, the second silicon oxide layer 107 can also be an insulating material such as fluorosilicone glass.

[0059] Referring to Figure 6 In one embodiment of the present application, as shown in the figure, the second silicon oxide layer 107 in the first shallow trench 1051 forms the first shallow trench isolation structure 1071, and the second silicon oxide layer 107 in the second shallow trench 1052 forms the second shallow trench isolation structure 1072. The first shallow trench isolation structure 1071 is located in the storage area of the non-volatile flash memory, and the second shallow trench 1052 is located in the logic area of the non-volatile flash memory.

[0060] Referring to Figure 5 and Figure 6 In one embodiment of the present application, after the first silicon oxide layer 104 in the first shallow trench 1051 and the second shallow trench 1052 is etched away, a pad silicon oxide layer (not shown in the figure) can be formed in the shallow trench first, and then the second silicon oxide layer 107 is deposited in the shallow trench until the second silicon oxide layer 107 is higher than the surface of the silicon nitride layer 102. In this embodiment, when the pad silicon oxide layer is formed, for example, under the conditions of 500-650°C and a pressure of 10-20T, oxygen (O2) mixed with a small amount of hydrogen (H2) is introduced, and the hydrogen and oxygen form a mixture of water vapor, OH radicals, O radicals and other substances on the silicon surface in the shallow trench, and react with the surface of the silicon substrate 100 on the inner wall of the shallow trench to produce silicon oxide, thereby forming a linear pad silicon oxide layer. The pad silicon oxide layer can repair the damage to the surface of the shallow trench edge during etching, and improve the electrical properties and yield of the device.

[0061] Referring to Figure 6 In one embodiment of the present application, after the first shallow trench isolation structure 1071 and the second shallow trench isolation structure 1072 are formed, the second silicon oxide layer 107 higher than the silicon nitride layer 102 can be removed using chemical mechanical polishing (CMP) in the subsequent process, so that the second silicon oxide layer 102 is flush with the surface of the silicon nitride layer 102.

[0062] In summary, the application provides a manufacturing method of a shallow trench isolation structure of a memory chip and the shallow trench isolation structure. The manufacturing method comprises the following steps. A silicon substrate is provided. The silicon substrate is formed with shallow trenches in a logic region and shallow trenches in a memory region. A hard mask layer with a preset thickness is formed on the surface of the silicon substrate between the shallow trenches, and the hard mask layer is formed by stacking silicon nitride and silicon oxide in sequence. A first silicon oxide layer is formed on the surface of the shallow trenches in the memory region and the sidewall and surface of the hard mask layer. The sidewall of the hard mask layer in the logic region is provided with the first silicon oxide layer. The shallow trenches with the hard mask layer and the first silicon oxide layer are filled with a first dielectric layer, and the first dielectric layer is higher than the hard mask layer by a preset thickness, so as to form a flat surface of the first dielectric layer. The first dielectric layer is etched back by a preset distance, so that the surface of the first dielectric layer is lower than the surface of the hard mask layer. The silicon oxide layer in the hard mask layer is etched by wet etching, and the first dielectric layer is removed. The first silicon oxide layer is removed, and a second silicon oxide layer is filled in the shallow trenches and is higher than the surface of the silicon nitride. The second silicon oxide layer is polished by chemical mechanical polishing until the surface of the silicon nitride, so as to form the shallow trench isolation structure. The unexpected effect is that, in order to ensure that the height of a floating gate formed in a nonvolatile flash memory is within a set size, the hard mask layer is arranged in a stacked structure of a silicon nitride layer and a silicon oxide layer with a preset thickness ratio, and the silicon oxide layer is arranged on the surface of the silicon nitride layer, so as to protect the silicon nitride layer during the etching of the shallow trench and ensure that the thickness of the silicon nitride layer is within a control range. In the manufacturing process of the memory chip, the thickness of the silicon nitride layer as the hard mask layer directly affects the thickness and uniformity of the subsequently manufactured floating gate, and the fluctuation range of the thickness of the floating gate directly affects the yield and stability of the memory chip. After the shallow trench is formed and before the second silicon oxide layer is filled, an organic planarization layer with good fluidity is filled in the trench, so as to protect the trench during the subsequent process of etching the silicon oxide layer on the silicon nitride layer by wet etching. The first silicon oxide layer on the sidewall of the trench with the hard mask layer can isolate the silicon nitride layer in the hard mask layer from the organic planarization dielectric layer, so as to avoid the influence of the organic planarization dielectric layer on the silicon nitride. Since the etching selectivity ratio between the silicon oxide and the silicon nitride in the buffered hydrofluoric acid solution used for wet etching of the silicon oxide layer is about 80:1, the silicon nitride layer is almost not affected when the silicon oxide layer is etched. When the second silicon oxide layer is filled in the shallow trench after the silicon oxide layer is removed, the aspect ratio of the shallow trench to be filled can be reduced, and the probability of forming a cavity when the shallow trench is filled with an insulating dielectric in the subsequent process can be reduced. Therefore, by using the manufacturing method of the shallow trench isolation structure of the memory chip and the shallow trench isolation structure, the problem that a gap is easily formed when the shallow trench isolation structure is formed can be solved, and the quality of the shallow trench isolation structure is improved.

[0063] The above disclosed embodiments of the present application are only used to help explain the present application. The embodiments do not describe all of the details of the present application, and the present application is not limited to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of the present specification. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well understand and utilize the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for fabricating a shallow trench isolation structure for a memory chip, the memory chip comprising a storage region and a logic region, characterized in that, Includes the following steps: A silicon substrate is provided, on which shallow trenches for storage regions and shallow trenches for logic regions are formed. A hard mask layer consisting of a silicon nitride layer and a silicon oxide layer of a predetermined thickness stacked sequentially is formed on the surface of the silicon substrate between the shallow trenches. A first silicon oxide layer is formed on the surface of the shallow trenches of the storage regions and on the sidewalls and surface of the hard mask layer. The first silicon oxide layer is disposed on the sidewalls of the hard mask layer of the logic regions. A first dielectric layer is filled into the shallow trench containing the hard mask layer and the first silicon oxide layer, and the first dielectric layer is higher than the predetermined thickness of the hard mask layer to form a flat surface of the first dielectric layer. The first dielectric layer is etched back until the surface of the first dielectric layer is lower than the surface of the hard mask layer by a predetermined distance; The silicon oxide layer in the hard mask layer is removed by wet process, and then the first dielectric layer is removed. After removing the first silicon oxide layer, a second silicon oxide layer is filled into the shallow trench until it is higher than the silicon nitride surface; as well as The second silicon oxide layer is chemically and mechanically ground to the surface of the silicon nitride to form a shallow trench isolation structure.

2. The method for fabricating the shallow trench isolation structure of the memory chip according to claim 1, characterized in that, The first dielectric layer is an organic planarization layer.

3. The method for fabricating the shallow trench isolation structure of the memory chip according to claim 2, characterized in that, The etching solution used to wet-etch away a portion of the thickness of the hard mask layer is a BOE solution.

4. The method for fabricating the shallow trench isolation structure of the memory chip according to claim 3, characterized in that, The BOE:DIW ratio in the BOE solution ranges from 1:10 to 1:

300.

5. The method for fabricating the shallow trench isolation structure of the memory chip according to claim 4, characterized in that, The etching selectivity ratio of the BOE solution for the oxide layer and the nitride layer ranges from 1:50 to 1:

200.

6. The method for fabricating a shallow trench isolation structure for a memory chip according to claim 2, characterized in that, The organic planarization layer in the shallow trench is removed using an SPM solution.

7. The method for fabricating the shallow trench isolation structure of the memory chip according to claim 6, characterized in that, The ratio of H2SO4 to H2O2 in the SPM solution is in the range of 1:2 to 1:

10.

8. The method for fabricating a shallow trench isolation structure for a memory chip according to claim 1, characterized in that, A second silicon oxide layer is filled into the shallow trench using a high aspect ratio process to form a shallow trench isolation structure.

9. The method for fabricating a shallow trench isolation structure for a memory chip according to claim 8, characterized in that, Between removing the first oxide layer and filling the second silicon oxide layer, a pad silicon oxide layer is also formed at the bottom and sidewalls of the shallow trench.

10. A shallow trench isolation structure, characterized in that, The shallow trench isolation structure is formed using the fabrication method of the shallow trench isolation structure of the memory chip as described in any one of claims 1 to 9.

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